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Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * pata_oldpiix.c - Intel PATA/SATA controllers
3 *
4 * (C) 2005 Red Hat <alan@redhat.com>
5 *
6 * Some parts based on ata_piix.c by Jeff Garzik and others.
7 *
8 * Early PIIX differs significantly from the later PIIX as it lacks
9 * SITRE and the slave timing registers. This means that you have to
10 * set timing per channel, or be clever. Libata tells us whenever it
11 * does drive selection and we use this to reload the timings.
12 *
13 * Because of these behaviour differences PIIX gets its own driver module.
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/blkdev.h>
21#include <linux/delay.h>
22#include <linux/device.h>
23#include <scsi/scsi_host.h>
24#include <linux/libata.h>
25#include <linux/ata.h>
26
27#define DRV_NAME "pata_oldpiix"
Jeff Garzika0fcdc02007-03-09 07:24:15 -050028#define DRV_VERSION "0.5.5"
Jeff Garzik669a5db2006-08-29 18:12:40 -040029
30/**
31 * oldpiix_pre_reset - probe begin
Tejun Heocc0680a2007-08-06 18:36:23 +090032 * @link: ATA link
Tejun Heod4b2bab2007-02-02 16:50:52 +090033 * @deadline: deadline jiffies for the operation
Jeff Garzik669a5db2006-08-29 18:12:40 -040034 *
35 * Set up cable type and use generic probe init
36 */
37
Tejun Heocc0680a2007-08-06 18:36:23 +090038static int oldpiix_pre_reset(struct ata_link *link, unsigned long deadline)
Jeff Garzik669a5db2006-08-29 18:12:40 -040039{
Tejun Heocc0680a2007-08-06 18:36:23 +090040 struct ata_port *ap = link->ap;
Jeff Garzik669a5db2006-08-29 18:12:40 -040041 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
42 static const struct pci_bits oldpiix_enable_bits[] = {
43 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
44 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
45 };
46
Alan Coxc9619222006-09-26 17:53:38 +010047 if (!pci_test_config_bits(pdev, &oldpiix_enable_bits[ap->port_no]))
48 return -ENOENT;
Tejun Heod4b2bab2007-02-02 16:50:52 +090049
Tejun Heocc0680a2007-08-06 18:36:23 +090050 return ata_std_prereset(link, deadline);
Jeff Garzik669a5db2006-08-29 18:12:40 -040051}
52
53/**
54 * oldpiix_pata_error_handler - Probe specified port on PATA host controller
55 * @ap: Port to probe
56 * @classes:
57 *
58 * LOCKING:
59 * None (inherited from caller).
60 */
61
62static void oldpiix_pata_error_handler(struct ata_port *ap)
63{
64 ata_bmdma_drive_eh(ap, oldpiix_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
65}
66
67/**
68 * oldpiix_set_piomode - Initialize host controller PATA PIO timings
69 * @ap: Port whose timings we are configuring
Jeff Garzika0fcdc02007-03-09 07:24:15 -050070 * @adev: Device whose timings we are configuring
Jeff Garzik669a5db2006-08-29 18:12:40 -040071 *
72 * Set PIO mode for device, in host controller PCI config space.
73 *
74 * LOCKING:
75 * None (inherited from caller).
76 */
77
78static void oldpiix_set_piomode (struct ata_port *ap, struct ata_device *adev)
79{
80 unsigned int pio = adev->pio_mode - XFER_PIO_0;
81 struct pci_dev *dev = to_pci_dev(ap->host->dev);
82 unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;
83 u16 idetm_data;
84 int control = 0;
85
86 /*
87 * See Intel Document 298600-004 for the timing programing rules
88 * for PIIX/ICH. Note that the early PIIX does not have the slave
89 * timing port at 0x44.
90 */
91
92 static const /* ISP RTC */
93 u8 timings[][2] = { { 0, 0 },
94 { 0, 0 },
95 { 1, 0 },
96 { 2, 1 },
97 { 2, 3 }, };
98
Sergei Shtylyov409ba472007-02-05 19:45:38 +030099 if (pio > 1)
100 control |= 1; /* TIME */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400101 if (ata_pio_need_iordy(adev))
Sergei Shtylyov409ba472007-02-05 19:45:38 +0300102 control |= 2; /* IE */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400103
Sergei Shtylyov409ba472007-02-05 19:45:38 +0300104 /* Intel specifies that the prefetch/posting is for disk only */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400105 if (adev->class == ATA_DEV_ATA)
Sergei Shtylyov409ba472007-02-05 19:45:38 +0300106 control |= 4; /* PPE */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400107
108 pci_read_config_word(dev, idetm_port, &idetm_data);
109
Sergei Shtylyov409ba472007-02-05 19:45:38 +0300110 /*
111 * Set PPE, IE and TIME as appropriate.
112 * Clear the other drive's timing bits.
113 */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400114 if (adev->devno == 0) {
115 idetm_data &= 0xCCE0;
116 idetm_data |= control;
117 } else {
118 idetm_data &= 0xCC0E;
119 idetm_data |= (control << 4);
120 }
121 idetm_data |= (timings[pio][0] << 12) |
122 (timings[pio][1] << 8);
123 pci_write_config_word(dev, idetm_port, idetm_data);
124
125 /* Track which port is configured */
126 ap->private_data = adev;
127}
128
129/**
130 * oldpiix_set_dmamode - Initialize host controller PATA DMA timings
131 * @ap: Port whose timings we are configuring
132 * @adev: Device to program
133 * @isich: True if the device is an ICH and has IOCFG registers
134 *
135 * Set MWDMA mode for device, in host controller PCI config space.
136 *
137 * LOCKING:
138 * None (inherited from caller).
139 */
140
141static void oldpiix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
142{
143 struct pci_dev *dev = to_pci_dev(ap->host->dev);
144 u8 idetm_port = ap->port_no ? 0x42 : 0x40;
145 u16 idetm_data;
146
147 static const /* ISP RTC */
148 u8 timings[][2] = { { 0, 0 },
149 { 0, 0 },
150 { 1, 0 },
151 { 2, 1 },
152 { 2, 3 }, };
153
154 /*
155 * MWDMA is driven by the PIO timings. We must also enable
156 * IORDY unconditionally along with TIME1. PPE has already
157 * been set when the PIO timing was set.
158 */
159
160 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
161 unsigned int control;
162 const unsigned int needed_pio[3] = {
163 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
164 };
165 int pio = needed_pio[mwdma] - XFER_PIO_0;
166
167 pci_read_config_word(dev, idetm_port, &idetm_data);
168
169 control = 3; /* IORDY|TIME0 */
170 /* Intel specifies that the PPE functionality is for disk only */
171 if (adev->class == ATA_DEV_ATA)
172 control |= 4; /* PPE enable */
173
174 /* If the drive MWDMA is faster than it can do PIO then
175 we must force PIO into PIO0 */
176
177 if (adev->pio_mode < needed_pio[mwdma])
178 /* Enable DMA timing only */
179 control |= 8; /* PIO cycles in PIO0 */
180
181 /* Mask out the relevant control and timing bits we will load. Also
182 clear the other drive TIME register as a precaution */
183 if (adev->devno == 0) {
184 idetm_data &= 0xCCE0;
185 idetm_data |= control;
186 } else {
187 idetm_data &= 0xCC0E;
188 idetm_data |= (control << 4);
189 }
190 idetm_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
191 pci_write_config_word(dev, idetm_port, idetm_data);
192
193 /* Track which port is configured */
194 ap->private_data = adev;
195}
196
197/**
198 * oldpiix_qc_issue_prot - command issue
199 * @qc: command pending
200 *
201 * Called when the libata layer is about to issue a command. We wrap
202 * this interface so that we can load the correct ATA timings if
Robert P. J. Day3a4fa0a2007-10-19 23:10:43 +0200203 * necessary. Our logic also clears TIME0/TIME1 for the other device so
Jeff Garzik669a5db2006-08-29 18:12:40 -0400204 * that, even if we get this wrong, cycles to the other device will
205 * be made PIO0.
206 */
207
208static unsigned int oldpiix_qc_issue_prot(struct ata_queued_cmd *qc)
209{
210 struct ata_port *ap = qc->ap;
211 struct ata_device *adev = qc->dev;
212
213 if (adev != ap->private_data) {
Alanb7939b12007-02-20 17:47:37 +0000214 oldpiix_set_piomode(ap, adev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400215 if (adev->dma_mode)
216 oldpiix_set_dmamode(ap, adev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400217 }
218 return ata_qc_issue_prot(qc);
219}
220
221
222static struct scsi_host_template oldpiix_sht = {
223 .module = THIS_MODULE,
224 .name = DRV_NAME,
225 .ioctl = ata_scsi_ioctl,
226 .queuecommand = ata_scsi_queuecmd,
227 .can_queue = ATA_DEF_QUEUE,
228 .this_id = ATA_SHT_THIS_ID,
229 .sg_tablesize = LIBATA_MAX_PRD,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400230 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
231 .emulated = ATA_SHT_EMULATED,
232 .use_clustering = ATA_SHT_USE_CLUSTERING,
233 .proc_name = DRV_NAME,
234 .dma_boundary = ATA_DMA_BOUNDARY,
235 .slave_configure = ata_scsi_slave_config,
Tejun Heoafdfe892006-11-29 11:26:47 +0900236 .slave_destroy = ata_scsi_slave_destroy,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400237 .bios_param = ata_std_bios_param,
238};
239
240static const struct ata_port_operations oldpiix_pata_ops = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400241 .set_piomode = oldpiix_set_piomode,
242 .set_dmamode = oldpiix_set_dmamode,
243 .mode_filter = ata_pci_default_filter,
244
245 .tf_load = ata_tf_load,
246 .tf_read = ata_tf_read,
247 .check_status = ata_check_status,
248 .exec_command = ata_exec_command,
249 .dev_select = ata_std_dev_select,
250
251 .freeze = ata_bmdma_freeze,
252 .thaw = ata_bmdma_thaw,
253 .error_handler = oldpiix_pata_error_handler,
254 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500255 .cable_detect = ata_cable_40wire,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400256
257 .bmdma_setup = ata_bmdma_setup,
258 .bmdma_start = ata_bmdma_start,
259 .bmdma_stop = ata_bmdma_stop,
260 .bmdma_status = ata_bmdma_status,
261 .qc_prep = ata_qc_prep,
262 .qc_issue = oldpiix_qc_issue_prot,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900263 .data_xfer = ata_data_xfer,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400264
265 .irq_handler = ata_interrupt,
266 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900267 .irq_on = ata_irq_on,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400268
Alan Cox81ad1832007-08-22 22:55:41 +0100269 .port_start = ata_sff_port_start,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400270};
271
272
273/**
274 * oldpiix_init_one - Register PIIX ATA PCI device with kernel services
275 * @pdev: PCI device to register
276 * @ent: Entry in oldpiix_pci_tbl matching with @pdev
277 *
278 * Called from kernel PCI layer. We probe for combined mode (sigh),
279 * and then hand over control to libata, for it to do the rest.
280 *
281 * LOCKING:
282 * Inherited from PCI layer (may sleep).
283 *
284 * RETURNS:
285 * Zero on success, or -ERRNO value.
286 */
287
288static int oldpiix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
289{
290 static int printed_version;
Tejun Heo1626aeb2007-05-04 12:43:58 +0200291 static const struct ata_port_info info = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400292 .sht = &oldpiix_sht,
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400293 .flags = ATA_FLAG_SLAVE_POSS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400294 .pio_mask = 0x1f, /* pio0-4 */
295 .mwdma_mask = 0x07, /* mwdma1-2 */
296 .port_ops = &oldpiix_pata_ops,
297 };
Tejun Heo1626aeb2007-05-04 12:43:58 +0200298 const struct ata_port_info *ppi[] = { &info, NULL };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400299
300 if (!printed_version++)
301 dev_printk(KERN_DEBUG, &pdev->dev,
302 "version " DRV_VERSION "\n");
303
Tejun Heo1626aeb2007-05-04 12:43:58 +0200304 return ata_pci_init_one(pdev, ppi);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400305}
306
307static const struct pci_device_id oldpiix_pci_tbl[] = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400308 { PCI_VDEVICE(INTEL, 0x1230), },
309
Jeff Garzik669a5db2006-08-29 18:12:40 -0400310 { } /* terminate list */
311};
312
313static struct pci_driver oldpiix_pci_driver = {
314 .name = DRV_NAME,
315 .id_table = oldpiix_pci_tbl,
316 .probe = oldpiix_init_one,
317 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900318#ifdef CONFIG_PM
Alan30ced0f2006-11-22 16:57:36 +0000319 .suspend = ata_pci_device_suspend,
320 .resume = ata_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900321#endif
Jeff Garzik669a5db2006-08-29 18:12:40 -0400322};
323
324static int __init oldpiix_init(void)
325{
326 return pci_register_driver(&oldpiix_pci_driver);
327}
328
329static void __exit oldpiix_exit(void)
330{
331 pci_unregister_driver(&oldpiix_pci_driver);
332}
333
Jeff Garzik669a5db2006-08-29 18:12:40 -0400334module_init(oldpiix_init);
335module_exit(oldpiix_exit);
336
337MODULE_AUTHOR("Alan Cox");
338MODULE_DESCRIPTION("SCSI low-level driver for early PIIX series controllers");
339MODULE_LICENSE("GPL");
340MODULE_DEVICE_TABLE(pci, oldpiix_pci_tbl);
341MODULE_VERSION(DRV_VERSION);
342