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Mark Brownbe2de992011-05-10 15:42:08 +02001/*
Mark Brownb3748dd2009-06-15 11:23:20 +01002 * Copyright 2009 Wolfson Microelectronics plc
3 *
4 * S3C64xx CPUfreq Support
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
Mark Browna6a43412011-12-05 18:22:01 +000011#define pr_fmt(fmt) "cpufreq: " fmt
12
Mark Brownb3748dd2009-06-15 11:23:20 +010013#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/init.h>
16#include <linux/cpufreq.h>
17#include <linux/clk.h>
18#include <linux/err.h>
19#include <linux/regulator/consumer.h>
Mark Browna6ee8772011-07-29 16:19:26 +010020#include <linux/module.h>
Mark Brownb3748dd2009-06-15 11:23:20 +010021
Mark Brownb3748dd2009-06-15 11:23:20 +010022static struct regulator *vddarm;
Mark Brown43f10692009-11-03 14:42:11 +000023static unsigned long regulator_latency;
Mark Brownb3748dd2009-06-15 11:23:20 +010024
25#ifdef CONFIG_CPU_S3C6410
26struct s3c64xx_dvfs {
27 unsigned int vddarm_min;
28 unsigned int vddarm_max;
29};
30
31static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
Mark Browne9c08f02009-11-03 14:42:12 +000032 [0] = { 1000000, 1150000 },
33 [1] = { 1050000, 1150000 },
34 [2] = { 1100000, 1150000 },
35 [3] = { 1200000, 1350000 },
Mark Brownc6e2d682011-06-08 14:49:15 +010036 [4] = { 1300000, 1350000 },
Mark Brownb3748dd2009-06-15 11:23:20 +010037};
38
39static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
Viresh Kumar7f4b0462014-03-28 19:11:47 +053040 { 0, 0, 66000 },
41 { 0, 0, 100000 },
42 { 0, 0, 133000 },
43 { 0, 1, 200000 },
44 { 0, 1, 222000 },
45 { 0, 1, 266000 },
46 { 0, 2, 333000 },
47 { 0, 2, 400000 },
48 { 0, 2, 532000 },
49 { 0, 2, 533000 },
50 { 0, 3, 667000 },
51 { 0, 4, 800000 },
52 { 0, 0, CPUFREQ_TABLE_END },
Mark Brownb3748dd2009-06-15 11:23:20 +010053};
54#endif
55
Mark Brownb3748dd2009-06-15 11:23:20 +010056static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
Viresh Kumar9c0ebcf2013-10-25 19:45:48 +053057 unsigned int index)
Mark Brownb3748dd2009-06-15 11:23:20 +010058{
Mark Brownb3748dd2009-06-15 11:23:20 +010059 struct s3c64xx_dvfs *dvfs;
Viresh Kumard4019f02013-08-14 19:38:24 +053060 unsigned int old_freq, new_freq;
61 int ret;
Mark Brownb3748dd2009-06-15 11:23:20 +010062
Viresh Kumar652ed952014-01-09 20:38:43 +053063 old_freq = clk_get_rate(policy->clk) / 1000;
Viresh Kumard4019f02013-08-14 19:38:24 +053064 new_freq = s3c64xx_freq_table[index].frequency;
Viresh Kumar9c0ebcf2013-10-25 19:45:48 +053065 dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[index].driver_data];
Mark Brownb3748dd2009-06-15 11:23:20 +010066
Mark Brownb3748dd2009-06-15 11:23:20 +010067#ifdef CONFIG_REGULATOR
Viresh Kumard4019f02013-08-14 19:38:24 +053068 if (vddarm && new_freq > old_freq) {
Mark Brownb3748dd2009-06-15 11:23:20 +010069 ret = regulator_set_voltage(vddarm,
70 dvfs->vddarm_min,
71 dvfs->vddarm_max);
72 if (ret != 0) {
Mark Browna6a43412011-12-05 18:22:01 +000073 pr_err("Failed to set VDDARM for %dkHz: %d\n",
Viresh Kumard4019f02013-08-14 19:38:24 +053074 new_freq, ret);
75 return ret;
Mark Brownb3748dd2009-06-15 11:23:20 +010076 }
77 }
78#endif
79
Viresh Kumar652ed952014-01-09 20:38:43 +053080 ret = clk_set_rate(policy->clk, new_freq * 1000);
Mark Brownb3748dd2009-06-15 11:23:20 +010081 if (ret < 0) {
Mark Browna6a43412011-12-05 18:22:01 +000082 pr_err("Failed to set rate %dkHz: %d\n",
Viresh Kumard4019f02013-08-14 19:38:24 +053083 new_freq, ret);
84 return ret;
Mark Brownb3748dd2009-06-15 11:23:20 +010085 }
86
87#ifdef CONFIG_REGULATOR
Viresh Kumard4019f02013-08-14 19:38:24 +053088 if (vddarm && new_freq < old_freq) {
Mark Brownb3748dd2009-06-15 11:23:20 +010089 ret = regulator_set_voltage(vddarm,
90 dvfs->vddarm_min,
91 dvfs->vddarm_max);
92 if (ret != 0) {
Mark Browna6a43412011-12-05 18:22:01 +000093 pr_err("Failed to set VDDARM for %dkHz: %d\n",
Viresh Kumard4019f02013-08-14 19:38:24 +053094 new_freq, ret);
Viresh Kumar652ed952014-01-09 20:38:43 +053095 if (clk_set_rate(policy->clk, old_freq * 1000) < 0)
Viresh Kumard4019f02013-08-14 19:38:24 +053096 pr_err("Failed to restore original clock rate\n");
97
98 return ret;
Mark Brownb3748dd2009-06-15 11:23:20 +010099 }
100 }
101#endif
102
Mark Browna6a43412011-12-05 18:22:01 +0000103 pr_debug("Set actual frequency %lukHz\n",
Viresh Kumar652ed952014-01-09 20:38:43 +0530104 clk_get_rate(policy->clk) / 1000);
Mark Brownb3748dd2009-06-15 11:23:20 +0100105
106 return 0;
Mark Brownb3748dd2009-06-15 11:23:20 +0100107}
108
109#ifdef CONFIG_REGULATOR
Mark Brown43f10692009-11-03 14:42:11 +0000110static void __init s3c64xx_cpufreq_config_regulator(void)
Mark Brownb3748dd2009-06-15 11:23:20 +0100111{
112 int count, v, i, found;
113 struct cpufreq_frequency_table *freq;
114 struct s3c64xx_dvfs *dvfs;
115
116 count = regulator_count_voltages(vddarm);
117 if (count < 0) {
Mark Browna6a43412011-12-05 18:22:01 +0000118 pr_err("Unable to check supported voltages\n");
Mark Brownb3748dd2009-06-15 11:23:20 +0100119 }
120
Stratos Karafotis041526f2014-04-25 23:15:38 +0300121 if (!count)
122 goto out;
Mark Brownb3748dd2009-06-15 11:23:20 +0100123
Stratos Karafotis041526f2014-04-25 23:15:38 +0300124 cpufreq_for_each_valid_entry(freq, s3c64xx_freq_table) {
Charles Keepax0e824432013-10-14 19:36:47 +0100125 dvfs = &s3c64xx_dvfs_table[freq->driver_data];
Mark Brownb3748dd2009-06-15 11:23:20 +0100126 found = 0;
127
128 for (i = 0; i < count; i++) {
129 v = regulator_list_voltage(vddarm, i);
130 if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max)
131 found = 1;
132 }
133
134 if (!found) {
Mark Browna6a43412011-12-05 18:22:01 +0000135 pr_debug("%dkHz unsupported by regulator\n",
Mark Brownb3748dd2009-06-15 11:23:20 +0100136 freq->frequency);
137 freq->frequency = CPUFREQ_ENTRY_INVALID;
138 }
Mark Brownb3748dd2009-06-15 11:23:20 +0100139 }
Mark Brown43f10692009-11-03 14:42:11 +0000140
Stratos Karafotis041526f2014-04-25 23:15:38 +0300141out:
Mark Brown43f10692009-11-03 14:42:11 +0000142 /* Guess based on having to do an I2C/SPI write; in future we
143 * will be able to query the regulator performance here. */
144 regulator_latency = 1 * 1000 * 1000;
Mark Brownb3748dd2009-06-15 11:23:20 +0100145}
146#endif
147
Mark Brown6d0de152011-03-11 16:10:03 +0900148static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
Mark Brownb3748dd2009-06-15 11:23:20 +0100149{
150 int ret;
151 struct cpufreq_frequency_table *freq;
152
153 if (policy->cpu != 0)
154 return -EINVAL;
155
156 if (s3c64xx_freq_table == NULL) {
Mark Browna6a43412011-12-05 18:22:01 +0000157 pr_err("No frequency information for this CPU\n");
Mark Brownb3748dd2009-06-15 11:23:20 +0100158 return -ENODEV;
159 }
160
Viresh Kumar652ed952014-01-09 20:38:43 +0530161 policy->clk = clk_get(NULL, "armclk");
162 if (IS_ERR(policy->clk)) {
Mark Browna6a43412011-12-05 18:22:01 +0000163 pr_err("Unable to obtain ARMCLK: %ld\n",
Viresh Kumar652ed952014-01-09 20:38:43 +0530164 PTR_ERR(policy->clk));
165 return PTR_ERR(policy->clk);
Mark Brownb3748dd2009-06-15 11:23:20 +0100166 }
167
168#ifdef CONFIG_REGULATOR
169 vddarm = regulator_get(NULL, "vddarm");
170 if (IS_ERR(vddarm)) {
171 ret = PTR_ERR(vddarm);
Mark Browna6a43412011-12-05 18:22:01 +0000172 pr_err("Failed to obtain VDDARM: %d\n", ret);
173 pr_err("Only frequency scaling available\n");
Mark Brownb3748dd2009-06-15 11:23:20 +0100174 vddarm = NULL;
175 } else {
Mark Brown43f10692009-11-03 14:42:11 +0000176 s3c64xx_cpufreq_config_regulator();
Mark Brownb3748dd2009-06-15 11:23:20 +0100177 }
178#endif
179
Stratos Karafotis041526f2014-04-25 23:15:38 +0300180 cpufreq_for_each_entry(freq, s3c64xx_freq_table) {
Mark Brownb3748dd2009-06-15 11:23:20 +0100181 unsigned long r;
182
183 /* Check for frequencies we can generate */
Viresh Kumar652ed952014-01-09 20:38:43 +0530184 r = clk_round_rate(policy->clk, freq->frequency * 1000);
Mark Brownb3748dd2009-06-15 11:23:20 +0100185 r /= 1000;
Mark Brown383af9c2009-11-03 14:42:07 +0000186 if (r != freq->frequency) {
Mark Browna6a43412011-12-05 18:22:01 +0000187 pr_debug("%dkHz unsupported by clock\n",
Mark Brown383af9c2009-11-03 14:42:07 +0000188 freq->frequency);
Mark Brownb3748dd2009-06-15 11:23:20 +0100189 freq->frequency = CPUFREQ_ENTRY_INVALID;
Mark Brown383af9c2009-11-03 14:42:07 +0000190 }
Mark Brownb3748dd2009-06-15 11:23:20 +0100191
192 /* If we have no regulator then assume startup
193 * frequency is the maximum we can support. */
Viresh Kumar652ed952014-01-09 20:38:43 +0530194 if (!vddarm && freq->frequency > clk_get_rate(policy->clk) / 1000)
Mark Brownb3748dd2009-06-15 11:23:20 +0100195 freq->frequency = CPUFREQ_ENTRY_INVALID;
Mark Brownb3748dd2009-06-15 11:23:20 +0100196 }
197
Mark Brown43f10692009-11-03 14:42:11 +0000198 /* Datasheet says PLL stabalisation time (if we were to use
199 * the PLLs, which we don't currently) is ~300us worst case,
200 * but add some fudge.
201 */
Viresh Kumara307a1e2013-10-03 20:29:22 +0530202 ret = cpufreq_generic_init(policy, s3c64xx_freq_table,
203 (500 * 1000) + regulator_latency);
Mark Brownb3748dd2009-06-15 11:23:20 +0100204 if (ret != 0) {
Mark Browna6a43412011-12-05 18:22:01 +0000205 pr_err("Failed to configure frequency table: %d\n",
Mark Brownb3748dd2009-06-15 11:23:20 +0100206 ret);
207 regulator_put(vddarm);
Viresh Kumar652ed952014-01-09 20:38:43 +0530208 clk_put(policy->clk);
Mark Brownb3748dd2009-06-15 11:23:20 +0100209 }
210
211 return ret;
212}
213
214static struct cpufreq_driver s3c64xx_cpufreq_driver = {
Viresh Kumarae6b4272013-12-03 11:20:45 +0530215 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
Viresh Kumare96a4102013-10-03 20:28:21 +0530216 .verify = cpufreq_generic_frequency_table_verify,
Viresh Kumar9c0ebcf2013-10-25 19:45:48 +0530217 .target_index = s3c64xx_cpufreq_set_target,
Viresh Kumar652ed952014-01-09 20:38:43 +0530218 .get = cpufreq_generic_get,
Mark Brownb3748dd2009-06-15 11:23:20 +0100219 .init = s3c64xx_cpufreq_driver_init,
220 .name = "s3c",
221};
222
223static int __init s3c64xx_cpufreq_init(void)
224{
225 return cpufreq_register_driver(&s3c64xx_cpufreq_driver);
226}
227module_init(s3c64xx_cpufreq_init);