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Zhang Wei173acc72008-03-01 07:42:48 -07001/*
Forrest Shif3c677b2010-12-09 16:14:04 +08002 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
Zhang Wei173acc72008-03-01 07:42:48 -07003 *
4 * Author:
5 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007
6 * Ebony Zhu <ebony.zhu@freescale.com>, May 2007
7 *
8 * This is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 */
14#ifndef __DMA_FSLDMA_H
15#define __DMA_FSLDMA_H
16
17#include <linux/device.h>
18#include <linux/dmapool.h>
19#include <linux/dmaengine.h>
20
21/* Define data structures needed by Freescale
22 * MPC8540 and MPC8349 DMA controller.
23 */
24#define FSL_DMA_MR_CS 0x00000001
25#define FSL_DMA_MR_CC 0x00000002
26#define FSL_DMA_MR_CA 0x00000008
27#define FSL_DMA_MR_EIE 0x00000040
28#define FSL_DMA_MR_XFE 0x00000020
29#define FSL_DMA_MR_EOLNIE 0x00000100
30#define FSL_DMA_MR_EOLSIE 0x00000080
31#define FSL_DMA_MR_EOSIE 0x00000200
32#define FSL_DMA_MR_CDSM 0x00000010
33#define FSL_DMA_MR_CTM 0x00000004
34#define FSL_DMA_MR_EMP_EN 0x00200000
35#define FSL_DMA_MR_EMS_EN 0x00040000
36#define FSL_DMA_MR_DAHE 0x00002000
37#define FSL_DMA_MR_SAHE 0x00001000
38
Forrest Shif3c677b2010-12-09 16:14:04 +080039/*
40 * Bandwidth/pause control determines how many bytes a given
41 * channel is allowed to transfer before the DMA engine pauses
42 * the current channel and switches to the next channel
43 */
Hongbo Zhang0ca583a2014-01-16 14:10:53 +080044#define FSL_DMA_MR_BWC 0x0A000000
Forrest Shif3c677b2010-12-09 16:14:04 +080045
Zhang Wei173acc72008-03-01 07:42:48 -070046/* Special MR definition for MPC8349 */
47#define FSL_DMA_MR_EOTIE 0x00000080
Ira W. Snydera7aea372009-04-23 16:17:54 -070048#define FSL_DMA_MR_PRC_RM 0x00000800
Zhang Wei173acc72008-03-01 07:42:48 -070049
50#define FSL_DMA_SR_CH 0x00000020
Zhang Weif79abb62008-03-18 18:45:00 -070051#define FSL_DMA_SR_PE 0x00000010
Zhang Wei173acc72008-03-01 07:42:48 -070052#define FSL_DMA_SR_CB 0x00000004
53#define FSL_DMA_SR_TE 0x00000080
54#define FSL_DMA_SR_EOSI 0x00000002
55#define FSL_DMA_SR_EOLSI 0x00000001
56#define FSL_DMA_SR_EOCDI 0x00000001
57#define FSL_DMA_SR_EOLNI 0x00000008
58
59#define FSL_DMA_SATR_SBPATMU 0x20000000
60#define FSL_DMA_SATR_STRANSINT_RIO 0x00c00000
61#define FSL_DMA_SATR_SREADTYPE_SNOOP_READ 0x00050000
62#define FSL_DMA_SATR_SREADTYPE_BP_IORH 0x00020000
63#define FSL_DMA_SATR_SREADTYPE_BP_NREAD 0x00040000
64#define FSL_DMA_SATR_SREADTYPE_BP_MREAD 0x00070000
65
66#define FSL_DMA_DATR_DBPATMU 0x20000000
67#define FSL_DMA_DATR_DTRANSINT_RIO 0x00c00000
68#define FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE 0x00050000
69#define FSL_DMA_DATR_DWRITETYPE_BP_FLUSH 0x00010000
70
71#define FSL_DMA_EOL ((u64)0x1)
72#define FSL_DMA_SNEN ((u64)0x10)
73#define FSL_DMA_EOSIE 0x8
74#define FSL_DMA_NLDA_MASK (~(u64)0x1f)
75
76#define FSL_DMA_BCR_MAX_CNT 0x03ffffffu
77
78#define FSL_DMA_DGSR_TE 0x80
79#define FSL_DMA_DGSR_CH 0x20
80#define FSL_DMA_DGSR_PE 0x10
81#define FSL_DMA_DGSR_EOLNI 0x08
82#define FSL_DMA_DGSR_CB 0x04
83#define FSL_DMA_DGSR_EOSI 0x02
84#define FSL_DMA_DGSR_EOLSI 0x01
85
Al Viroa4e6d5d2008-03-29 03:10:18 +000086typedef u64 __bitwise v64;
87typedef u32 __bitwise v32;
88
Zhang Wei173acc72008-03-01 07:42:48 -070089struct fsl_dma_ld_hw {
Al Viroa4e6d5d2008-03-29 03:10:18 +000090 v64 src_addr;
91 v64 dst_addr;
92 v64 next_ln_addr;
93 v32 count;
94 v32 reserve;
Zhang Wei173acc72008-03-01 07:42:48 -070095} __attribute__((aligned(32)));
96
97struct fsl_desc_sw {
98 struct fsl_dma_ld_hw hw;
99 struct list_head node;
Dan Williamseda34232009-09-08 17:53:02 -0700100 struct list_head tx_list;
Zhang Wei173acc72008-03-01 07:42:48 -0700101 struct dma_async_tx_descriptor async_tx;
Zhang Wei173acc72008-03-01 07:42:48 -0700102} __attribute__((aligned(32)));
103
Ira Snydera4f56d42010-01-06 13:34:01 +0000104struct fsldma_chan_regs {
Ira Snyder31f43062011-03-03 07:54:57 +0000105 u32 mr; /* 0x00 - Mode Register */
106 u32 sr; /* 0x04 - Status Register */
Al Viroa4e6d5d2008-03-29 03:10:18 +0000107 u64 cdar; /* 0x08 - Current descriptor address register */
108 u64 sar; /* 0x10 - Source Address Register */
109 u64 dar; /* 0x18 - Destination Address Register */
110 u32 bcr; /* 0x20 - Byte Count Register */
111 u64 ndar; /* 0x24 - Next Descriptor Address Register */
Zhang Wei173acc72008-03-01 07:42:48 -0700112};
113
Ira Snydera4f56d42010-01-06 13:34:01 +0000114struct fsldma_chan;
Hongbo Zhang8de7a7d2013-09-26 17:33:43 +0800115#define FSL_DMA_MAX_CHANS_PER_DEVICE 8
Zhang Wei173acc72008-03-01 07:42:48 -0700116
Ira Snydera4f56d42010-01-06 13:34:01 +0000117struct fsldma_device {
Ira Snydere7a29152010-01-06 13:34:03 +0000118 void __iomem *regs; /* DGSR register base */
Zhang Wei173acc72008-03-01 07:42:48 -0700119 struct device *dev;
120 struct dma_device common;
Ira Snydera4f56d42010-01-06 13:34:01 +0000121 struct fsldma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE];
Zhang Wei173acc72008-03-01 07:42:48 -0700122 u32 feature; /* The same as DMA channels */
Timur Tabi77cd62e2008-09-26 17:00:11 -0700123 int irq; /* Channel IRQ */
Zhang Wei173acc72008-03-01 07:42:48 -0700124};
125
Ira Snydera4f56d42010-01-06 13:34:01 +0000126/* Define macros for fsldma_chan->feature property */
Zhang Wei173acc72008-03-01 07:42:48 -0700127#define FSL_DMA_LITTLE_ENDIAN 0x00000000
128#define FSL_DMA_BIG_ENDIAN 0x00000001
129
130#define FSL_DMA_IP_MASK 0x00000ff0
131#define FSL_DMA_IP_85XX 0x00000010
132#define FSL_DMA_IP_83XX 0x00000020
133
134#define FSL_DMA_CHAN_PAUSE_EXT 0x00001000
135#define FSL_DMA_CHAN_START_EXT 0x00002000
136
Ira Snydera4f56d42010-01-06 13:34:01 +0000137struct fsldma_chan {
Ira Snyderb1584712011-03-03 07:54:55 +0000138 char name[8]; /* Channel name */
Ira Snydere7a29152010-01-06 13:34:03 +0000139 struct fsldma_chan_regs __iomem *regs;
Zhang Wei173acc72008-03-01 07:42:48 -0700140 spinlock_t desc_lock; /* Descriptor operation lock */
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000141 struct list_head ld_pending; /* Link descriptors queue */
142 struct list_head ld_running; /* Link descriptors queue */
Zhang Wei173acc72008-03-01 07:42:48 -0700143 struct dma_chan common; /* DMA common channel */
144 struct dma_pool *desc_pool; /* Descriptors pool */
145 struct device *dev; /* Channel device */
Zhang Wei173acc72008-03-01 07:42:48 -0700146 int irq; /* Channel IRQ */
147 int id; /* Raw id of this channel */
148 struct tasklet_struct tasklet;
149 u32 feature;
Ira Snyderf04cd402011-03-03 07:54:58 +0000150 bool idle; /* DMA controller is idle */
Zhang Wei173acc72008-03-01 07:42:48 -0700151
Ira Snydera4f56d42010-01-06 13:34:01 +0000152 void (*toggle_ext_pause)(struct fsldma_chan *fsl_chan, int enable);
153 void (*toggle_ext_start)(struct fsldma_chan *fsl_chan, int enable);
154 void (*set_src_loop_size)(struct fsldma_chan *fsl_chan, int size);
Ira Snyder738f5f72010-01-06 13:34:02 +0000155 void (*set_dst_loop_size)(struct fsldma_chan *fsl_chan, int size);
Ira Snydera4f56d42010-01-06 13:34:01 +0000156 void (*set_request_count)(struct fsldma_chan *fsl_chan, int size);
Zhang Wei173acc72008-03-01 07:42:48 -0700157};
158
Ira Snydera4f56d42010-01-06 13:34:01 +0000159#define to_fsl_chan(chan) container_of(chan, struct fsldma_chan, common)
Zhang Wei173acc72008-03-01 07:42:48 -0700160#define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node)
161#define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx)
162
163#ifndef __powerpc64__
164static u64 in_be64(const u64 __iomem *addr)
165{
Al Viroa4e6d5d2008-03-29 03:10:18 +0000166 return ((u64)in_be32((u32 __iomem *)addr) << 32) |
167 (in_be32((u32 __iomem *)addr + 1));
Zhang Wei173acc72008-03-01 07:42:48 -0700168}
169
170static void out_be64(u64 __iomem *addr, u64 val)
171{
Al Viroa4e6d5d2008-03-29 03:10:18 +0000172 out_be32((u32 __iomem *)addr, val >> 32);
173 out_be32((u32 __iomem *)addr + 1, (u32)val);
Zhang Wei173acc72008-03-01 07:42:48 -0700174}
175
176/* There is no asm instructions for 64 bits reverse loads and stores */
177static u64 in_le64(const u64 __iomem *addr)
178{
Al Viroa4e6d5d2008-03-29 03:10:18 +0000179 return ((u64)in_le32((u32 __iomem *)addr + 1) << 32) |
180 (in_le32((u32 __iomem *)addr));
Zhang Wei173acc72008-03-01 07:42:48 -0700181}
182
183static void out_le64(u64 __iomem *addr, u64 val)
184{
Al Viroa4e6d5d2008-03-29 03:10:18 +0000185 out_le32((u32 __iomem *)addr + 1, val >> 32);
186 out_le32((u32 __iomem *)addr, (u32)val);
Zhang Wei173acc72008-03-01 07:42:48 -0700187}
188#endif
189
190#define DMA_IN(fsl_chan, addr, width) \
191 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
192 in_be##width(addr) : in_le##width(addr))
193#define DMA_OUT(fsl_chan, addr, val, width) \
194 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
195 out_be##width(addr, val) : out_le##width(addr, val))
196
197#define DMA_TO_CPU(fsl_chan, d, width) \
198 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
Al Viroa4e6d5d2008-03-29 03:10:18 +0000199 be##width##_to_cpu((__force __be##width)(v##width)d) : \
200 le##width##_to_cpu((__force __le##width)(v##width)d))
Zhang Wei173acc72008-03-01 07:42:48 -0700201#define CPU_TO_DMA(fsl_chan, c, width) \
202 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
Al Viroa4e6d5d2008-03-29 03:10:18 +0000203 (__force v##width)cpu_to_be##width(c) : \
204 (__force v##width)cpu_to_le##width(c))
Zhang Wei173acc72008-03-01 07:42:48 -0700205
206#endif /* __DMA_FSLDMA_H */