Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/common/gic.c |
| 3 | * |
| 4 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * Interrupt architecture for the GIC: |
| 11 | * |
| 12 | * o There is one Interrupt Distributor, which receives interrupts |
| 13 | * from system devices and sends them to the Interrupt Controllers. |
| 14 | * |
| 15 | * o There is one CPU Interface per CPU, which sends interrupts sent |
| 16 | * by the Distributor, and interrupts generated locally, to the |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 17 | * associated CPU. The base address of the CPU interface is usually |
| 18 | * aliased so that the same address points to different chips depending |
| 19 | * on the CPU it is accessed from. |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 20 | * |
| 21 | * Note that IRQs 0-31 are special - they are local to each CPU. |
| 22 | * As such, the enable set/clear, pending set/clear and active bit |
| 23 | * registers are banked per-cpu for these sources. |
| 24 | */ |
| 25 | #include <linux/init.h> |
| 26 | #include <linux/kernel.h> |
| 27 | #include <linux/list.h> |
| 28 | #include <linux/smp.h> |
Catalin Marinas | dcb86e8 | 2005-08-31 21:45:14 +0100 | [diff] [blame] | 29 | #include <linux/cpumask.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 30 | #include <linux/io.h> |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 31 | |
| 32 | #include <asm/irq.h> |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 33 | #include <asm/mach/irq.h> |
| 34 | #include <asm/hardware/gic.h> |
| 35 | |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 36 | static DEFINE_SPINLOCK(irq_controller_lock); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 37 | |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 38 | struct gic_chip_data { |
| 39 | unsigned int irq_offset; |
| 40 | void __iomem *dist_base; |
| 41 | void __iomem *cpu_base; |
| 42 | }; |
| 43 | |
| 44 | #ifndef MAX_GIC_NR |
| 45 | #define MAX_GIC_NR 1 |
| 46 | #endif |
| 47 | |
| 48 | static struct gic_chip_data gic_data[MAX_GIC_NR]; |
| 49 | |
| 50 | static inline void __iomem *gic_dist_base(unsigned int irq) |
| 51 | { |
| 52 | struct gic_chip_data *gic_data = get_irq_chip_data(irq); |
| 53 | return gic_data->dist_base; |
| 54 | } |
| 55 | |
| 56 | static inline void __iomem *gic_cpu_base(unsigned int irq) |
| 57 | { |
| 58 | struct gic_chip_data *gic_data = get_irq_chip_data(irq); |
| 59 | return gic_data->cpu_base; |
| 60 | } |
| 61 | |
| 62 | static inline unsigned int gic_irq(unsigned int irq) |
| 63 | { |
| 64 | struct gic_chip_data *gic_data = get_irq_chip_data(irq); |
| 65 | return irq - gic_data->irq_offset; |
| 66 | } |
| 67 | |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 68 | /* |
| 69 | * Routines to acknowledge, disable and enable interrupts |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 70 | */ |
| 71 | static void gic_ack_irq(unsigned int irq) |
| 72 | { |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 73 | |
| 74 | spin_lock(&irq_controller_lock); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 75 | writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI); |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 76 | spin_unlock(&irq_controller_lock); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 77 | } |
| 78 | |
| 79 | static void gic_mask_irq(unsigned int irq) |
| 80 | { |
| 81 | u32 mask = 1 << (irq % 32); |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 82 | |
| 83 | spin_lock(&irq_controller_lock); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 84 | writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4); |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 85 | spin_unlock(&irq_controller_lock); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 86 | } |
| 87 | |
| 88 | static void gic_unmask_irq(unsigned int irq) |
| 89 | { |
| 90 | u32 mask = 1 << (irq % 32); |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 91 | |
| 92 | spin_lock(&irq_controller_lock); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 93 | writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_SET + (gic_irq(irq) / 32) * 4); |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 94 | spin_unlock(&irq_controller_lock); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 95 | } |
| 96 | |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 97 | static int gic_set_type(unsigned int irq, unsigned int type) |
| 98 | { |
| 99 | void __iomem *base = gic_dist_base(irq); |
| 100 | unsigned int gicirq = gic_irq(irq); |
| 101 | u32 enablemask = 1 << (gicirq % 32); |
| 102 | u32 enableoff = (gicirq / 32) * 4; |
| 103 | u32 confmask = 0x2 << ((gicirq % 16) * 2); |
| 104 | u32 confoff = (gicirq / 16) * 4; |
| 105 | bool enabled = false; |
| 106 | u32 val; |
| 107 | |
| 108 | /* Interrupt configuration for SGIs can't be changed */ |
| 109 | if (gicirq < 16) |
| 110 | return -EINVAL; |
| 111 | |
| 112 | if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) |
| 113 | return -EINVAL; |
| 114 | |
| 115 | spin_lock(&irq_controller_lock); |
| 116 | |
| 117 | val = readl(base + GIC_DIST_CONFIG + confoff); |
| 118 | if (type == IRQ_TYPE_LEVEL_HIGH) |
| 119 | val &= ~confmask; |
| 120 | else if (type == IRQ_TYPE_EDGE_RISING) |
| 121 | val |= confmask; |
| 122 | |
| 123 | /* |
| 124 | * As recommended by the spec, disable the interrupt before changing |
| 125 | * the configuration |
| 126 | */ |
| 127 | if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { |
| 128 | writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); |
| 129 | enabled = true; |
| 130 | } |
| 131 | |
| 132 | writel(val, base + GIC_DIST_CONFIG + confoff); |
| 133 | |
| 134 | if (enabled) |
| 135 | writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); |
| 136 | |
| 137 | spin_unlock(&irq_controller_lock); |
| 138 | |
| 139 | return 0; |
| 140 | } |
| 141 | |
Catalin Marinas | a06f546 | 2005-09-30 16:07:05 +0100 | [diff] [blame] | 142 | #ifdef CONFIG_SMP |
Yinghai Lu | d5dedd4 | 2009-04-27 17:59:21 -0700 | [diff] [blame] | 143 | static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 144 | { |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 145 | void __iomem *reg = gic_dist_base(irq) + GIC_DIST_TARGET + (gic_irq(irq) & ~3); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 146 | unsigned int shift = (irq % 4) * 8; |
Rusty Russell | 0de2652 | 2008-12-13 21:20:26 +1030 | [diff] [blame] | 147 | unsigned int cpu = cpumask_first(mask_val); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 148 | u32 val; |
Chao Xie | 8750750 | 2010-12-06 07:01:10 +0100 | [diff] [blame] | 149 | struct irq_desc *desc; |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 150 | |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 151 | spin_lock(&irq_controller_lock); |
Chao Xie | 8750750 | 2010-12-06 07:01:10 +0100 | [diff] [blame] | 152 | desc = irq_to_desc(irq); |
| 153 | if (desc == NULL) { |
| 154 | spin_unlock(&irq_controller_lock); |
| 155 | return -EINVAL; |
| 156 | } |
| 157 | desc->node = cpu; |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 158 | val = readl(reg) & ~(0xff << shift); |
| 159 | val |= 1 << (cpu + shift); |
| 160 | writel(val, reg); |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 161 | spin_unlock(&irq_controller_lock); |
Yinghai Lu | d5dedd4 | 2009-04-27 17:59:21 -0700 | [diff] [blame] | 162 | |
| 163 | return 0; |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 164 | } |
Catalin Marinas | a06f546 | 2005-09-30 16:07:05 +0100 | [diff] [blame] | 165 | #endif |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 166 | |
Russell King | 0f347bb | 2007-05-17 10:11:34 +0100 | [diff] [blame] | 167 | static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 168 | { |
| 169 | struct gic_chip_data *chip_data = get_irq_data(irq); |
| 170 | struct irq_chip *chip = get_irq_chip(irq); |
Russell King | 0f347bb | 2007-05-17 10:11:34 +0100 | [diff] [blame] | 171 | unsigned int cascade_irq, gic_irq; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 172 | unsigned long status; |
| 173 | |
| 174 | /* primary controller ack'ing */ |
| 175 | chip->ack(irq); |
| 176 | |
| 177 | spin_lock(&irq_controller_lock); |
| 178 | status = readl(chip_data->cpu_base + GIC_CPU_INTACK); |
| 179 | spin_unlock(&irq_controller_lock); |
| 180 | |
Russell King | 0f347bb | 2007-05-17 10:11:34 +0100 | [diff] [blame] | 181 | gic_irq = (status & 0x3ff); |
| 182 | if (gic_irq == 1023) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 183 | goto out; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 184 | |
Russell King | 0f347bb | 2007-05-17 10:11:34 +0100 | [diff] [blame] | 185 | cascade_irq = gic_irq + chip_data->irq_offset; |
| 186 | if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS)) |
| 187 | do_bad_IRQ(cascade_irq, desc); |
| 188 | else |
| 189 | generic_handle_irq(cascade_irq); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 190 | |
| 191 | out: |
| 192 | /* primary controller unmasking */ |
| 193 | chip->unmask(irq); |
| 194 | } |
| 195 | |
David Brownell | 38c677c | 2006-08-01 22:26:25 +0100 | [diff] [blame] | 196 | static struct irq_chip gic_chip = { |
| 197 | .name = "GIC", |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 198 | .ack = gic_ack_irq, |
| 199 | .mask = gic_mask_irq, |
| 200 | .unmask = gic_unmask_irq, |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 201 | .set_type = gic_set_type, |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 202 | #ifdef CONFIG_SMP |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 203 | .set_affinity = gic_set_cpu, |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 204 | #endif |
| 205 | }; |
| 206 | |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 207 | void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) |
| 208 | { |
| 209 | if (gic_nr >= MAX_GIC_NR) |
| 210 | BUG(); |
| 211 | if (set_irq_data(irq, &gic_data[gic_nr]) != 0) |
| 212 | BUG(); |
| 213 | set_irq_chained_handler(irq, gic_handle_cascade_irq); |
| 214 | } |
| 215 | |
Russell King | b580b89 | 2010-12-04 15:55:14 +0000 | [diff] [blame^] | 216 | static void __init gic_dist_init(unsigned int gic_nr, void __iomem *base, |
| 217 | unsigned int irq_start) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 218 | { |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 219 | unsigned int gic_irqs, irq_limit, i; |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 220 | u32 cpumask = 1 << smp_processor_id(); |
| 221 | |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 222 | if (gic_nr >= MAX_GIC_NR) |
| 223 | BUG(); |
| 224 | |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 225 | cpumask |= cpumask << 8; |
| 226 | cpumask |= cpumask << 16; |
| 227 | |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 228 | gic_data[gic_nr].dist_base = base; |
| 229 | gic_data[gic_nr].irq_offset = (irq_start - 1) & ~31; |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 230 | |
| 231 | writel(0, base + GIC_DIST_CTRL); |
| 232 | |
| 233 | /* |
| 234 | * Find out how many interrupts are supported. |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 235 | * The GIC only supports up to 1020 interrupt sources. |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 236 | */ |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 237 | gic_irqs = readl(base + GIC_DIST_CTR) & 0x1f; |
| 238 | gic_irqs = (gic_irqs + 1) * 32; |
| 239 | if (gic_irqs > 1020) |
| 240 | gic_irqs = 1020; |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 241 | |
| 242 | /* |
| 243 | * Set all global interrupts to be level triggered, active low. |
| 244 | */ |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 245 | for (i = 32; i < gic_irqs; i += 16) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 246 | writel(0, base + GIC_DIST_CONFIG + i * 4 / 16); |
| 247 | |
| 248 | /* |
| 249 | * Set all global interrupts to this CPU only. |
| 250 | */ |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 251 | for (i = 32; i < gic_irqs; i += 4) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 252 | writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); |
| 253 | |
| 254 | /* |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 255 | * Set priority on all global interrupts. |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 256 | */ |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 257 | for (i = 32; i < gic_irqs; i += 4) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 258 | writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); |
| 259 | |
| 260 | /* |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 261 | * Disable all interrupts. Leave the PPI and SGIs alone |
| 262 | * as these enables are banked registers. |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 263 | */ |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 264 | for (i = 32; i < gic_irqs; i += 32) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 265 | writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); |
| 266 | |
| 267 | /* |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 268 | * Limit number of interrupts registered to the platform maximum |
| 269 | */ |
| 270 | irq_limit = gic_data[gic_nr].irq_offset + gic_irqs; |
| 271 | if (WARN_ON(irq_limit > NR_IRQS)) |
| 272 | irq_limit = NR_IRQS; |
| 273 | |
| 274 | /* |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 275 | * Setup the Linux IRQ subsystem. |
| 276 | */ |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 277 | for (i = irq_start; i < irq_limit; i++) { |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 278 | set_irq_chip(i, &gic_chip); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 279 | set_irq_chip_data(i, &gic_data[gic_nr]); |
Russell King | 10dd5ce | 2006-11-23 11:41:32 +0000 | [diff] [blame] | 280 | set_irq_handler(i, handle_level_irq); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 281 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
| 282 | } |
| 283 | |
| 284 | writel(1, base + GIC_DIST_CTRL); |
| 285 | } |
| 286 | |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 287 | void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 288 | { |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 289 | void __iomem *dist_base; |
| 290 | int i; |
| 291 | |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 292 | if (gic_nr >= MAX_GIC_NR) |
| 293 | BUG(); |
| 294 | |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 295 | dist_base = gic_data[gic_nr].dist_base; |
| 296 | BUG_ON(!dist_base); |
| 297 | |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 298 | gic_data[gic_nr].cpu_base = base; |
| 299 | |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 300 | /* |
| 301 | * Deal with the banked PPI and SGI interrupts - disable all |
| 302 | * PPI interrupts, ensure all SGI interrupts are enabled. |
| 303 | */ |
| 304 | writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); |
| 305 | writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); |
| 306 | |
| 307 | /* |
| 308 | * Set priority on PPI and SGI interrupts |
| 309 | */ |
| 310 | for (i = 0; i < 32; i += 4) |
| 311 | writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); |
| 312 | |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 313 | writel(0xf0, base + GIC_CPU_PRIMASK); |
| 314 | writel(1, base + GIC_CPU_CTRL); |
| 315 | } |
| 316 | |
Russell King | b580b89 | 2010-12-04 15:55:14 +0000 | [diff] [blame^] | 317 | void __init gic_init(unsigned int gic_nr, unsigned int irq_start, |
| 318 | void __iomem *dist_base, void __iomem *cpu_base) |
| 319 | { |
| 320 | gic_dist_init(gic_nr, dist_base, irq_start); |
| 321 | gic_cpu_init(gic_nr, cpu_base); |
| 322 | } |
| 323 | |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 324 | #ifdef CONFIG_SMP |
Russell King | 8266810 | 2009-05-17 16:20:18 +0100 | [diff] [blame] | 325 | void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 326 | { |
Russell King | 8266810 | 2009-05-17 16:20:18 +0100 | [diff] [blame] | 327 | unsigned long map = *cpus_addr(*mask); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 328 | |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 329 | /* this always happens on GIC0 */ |
| 330 | writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 331 | } |
| 332 | #endif |