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Felipe Balbi550a7372008-07-24 12:27:36 +03001/*
2 * MUSB OTG driver - support for Mentor's DMA controller
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2007 by Texas Instruments
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
33#include <linux/device.h>
34#include <linux/interrupt.h>
35#include <linux/platform_device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090036#include <linux/slab.h>
Felipe Balbi550a7372008-07-24 12:27:36 +030037#include "musb_core.h"
Bryan Wu6995eb62008-12-02 21:33:47 +020038#include "musbhsdma.h"
Felipe Balbi550a7372008-07-24 12:27:36 +030039
40static int dma_controller_start(struct dma_controller *c)
41{
42 /* nothing to do */
43 return 0;
44}
45
Felipe Balbi458e6a52008-09-11 11:53:24 +030046static void dma_channel_release(struct dma_channel *channel);
Felipe Balbi550a7372008-07-24 12:27:36 +030047
48static int dma_controller_stop(struct dma_controller *c)
49{
Felipe Balbi458e6a52008-09-11 11:53:24 +030050 struct musb_dma_controller *controller = container_of(c,
51 struct musb_dma_controller, controller);
52 struct musb *musb = controller->private_data;
53 struct dma_channel *channel;
54 u8 bit;
Felipe Balbi550a7372008-07-24 12:27:36 +030055
Felipe Balbi458e6a52008-09-11 11:53:24 +030056 if (controller->used_channels != 0) {
Felipe Balbi550a7372008-07-24 12:27:36 +030057 dev_err(musb->controller,
58 "Stopping DMA controller while channel active\n");
59
Felipe Balbi458e6a52008-09-11 11:53:24 +030060 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
61 if (controller->used_channels & (1 << bit)) {
62 channel = &controller->channel[bit].channel;
63 dma_channel_release(channel);
Felipe Balbi550a7372008-07-24 12:27:36 +030064
Felipe Balbi458e6a52008-09-11 11:53:24 +030065 if (!controller->used_channels)
Felipe Balbi550a7372008-07-24 12:27:36 +030066 break;
67 }
68 }
69 }
Felipe Balbi458e6a52008-09-11 11:53:24 +030070
Felipe Balbi550a7372008-07-24 12:27:36 +030071 return 0;
72}
73
74static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
75 struct musb_hw_ep *hw_ep, u8 transmit)
76{
Felipe Balbi458e6a52008-09-11 11:53:24 +030077 struct musb_dma_controller *controller = container_of(c,
78 struct musb_dma_controller, controller);
79 struct musb_dma_channel *musb_channel = NULL;
80 struct dma_channel *channel = NULL;
81 u8 bit;
Felipe Balbi550a7372008-07-24 12:27:36 +030082
Felipe Balbi458e6a52008-09-11 11:53:24 +030083 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
84 if (!(controller->used_channels & (1 << bit))) {
85 controller->used_channels |= (1 << bit);
86 musb_channel = &(controller->channel[bit]);
87 musb_channel->controller = controller;
88 musb_channel->idx = bit;
89 musb_channel->epnum = hw_ep->epnum;
90 musb_channel->transmit = transmit;
91 channel = &(musb_channel->channel);
92 channel->private_data = musb_channel;
93 channel->status = MUSB_DMA_STATUS_FREE;
Anil Shetty6587cc02010-09-24 13:44:05 +030094 channel->max_len = 0x100000;
Felipe Balbi550a7372008-07-24 12:27:36 +030095 /* Tx => mode 1; Rx => mode 0 */
Felipe Balbi458e6a52008-09-11 11:53:24 +030096 channel->desired_mode = transmit;
97 channel->actual_len = 0;
Felipe Balbi550a7372008-07-24 12:27:36 +030098 break;
99 }
100 }
Felipe Balbi458e6a52008-09-11 11:53:24 +0300101
102 return channel;
Felipe Balbi550a7372008-07-24 12:27:36 +0300103}
104
Felipe Balbi458e6a52008-09-11 11:53:24 +0300105static void dma_channel_release(struct dma_channel *channel)
Felipe Balbi550a7372008-07-24 12:27:36 +0300106{
Felipe Balbi458e6a52008-09-11 11:53:24 +0300107 struct musb_dma_channel *musb_channel = channel->private_data;
Felipe Balbi550a7372008-07-24 12:27:36 +0300108
Felipe Balbi458e6a52008-09-11 11:53:24 +0300109 channel->actual_len = 0;
110 musb_channel->start_addr = 0;
111 musb_channel->len = 0;
Felipe Balbi550a7372008-07-24 12:27:36 +0300112
Felipe Balbi458e6a52008-09-11 11:53:24 +0300113 musb_channel->controller->used_channels &=
114 ~(1 << musb_channel->idx);
Felipe Balbi550a7372008-07-24 12:27:36 +0300115
Felipe Balbi458e6a52008-09-11 11:53:24 +0300116 channel->status = MUSB_DMA_STATUS_UNKNOWN;
Felipe Balbi550a7372008-07-24 12:27:36 +0300117}
118
Felipe Balbi458e6a52008-09-11 11:53:24 +0300119static void configure_channel(struct dma_channel *channel,
Felipe Balbi550a7372008-07-24 12:27:36 +0300120 u16 packet_sz, u8 mode,
121 dma_addr_t dma_addr, u32 len)
122{
Felipe Balbi458e6a52008-09-11 11:53:24 +0300123 struct musb_dma_channel *musb_channel = channel->private_data;
124 struct musb_dma_controller *controller = musb_channel->controller;
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300125 struct musb *musb = controller->private_data;
Felipe Balbi458e6a52008-09-11 11:53:24 +0300126 void __iomem *mbase = controller->base;
127 u8 bchannel = musb_channel->idx;
Felipe Balbi550a7372008-07-24 12:27:36 +0300128 u16 csr = 0;
129
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300130 dev_dbg(musb->controller, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
Felipe Balbi458e6a52008-09-11 11:53:24 +0300131 channel, packet_sz, dma_addr, len, mode);
Felipe Balbi550a7372008-07-24 12:27:36 +0300132
133 if (mode) {
134 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
135 BUG_ON(len < packet_sz);
Felipe Balbi550a7372008-07-24 12:27:36 +0300136 }
Hema HKc0f1f8e2010-06-24 23:07:09 +0530137 csr |= MUSB_HSDMA_BURSTMODE_INCR16
138 << MUSB_HSDMA_BURSTMODE_SHIFT;
Felipe Balbi550a7372008-07-24 12:27:36 +0300139
Felipe Balbi458e6a52008-09-11 11:53:24 +0300140 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
Felipe Balbi550a7372008-07-24 12:27:36 +0300141 | (1 << MUSB_HSDMA_ENABLE_SHIFT)
142 | (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
Felipe Balbi458e6a52008-09-11 11:53:24 +0300143 | (musb_channel->transmit
Felipe Balbi550a7372008-07-24 12:27:36 +0300144 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
145 : 0);
146
147 /* address/count */
Bryan Wu6995eb62008-12-02 21:33:47 +0200148 musb_write_hsdma_addr(mbase, bchannel, dma_addr);
149 musb_write_hsdma_count(mbase, bchannel, len);
Felipe Balbi550a7372008-07-24 12:27:36 +0300150
151 /* control (this should start things) */
152 musb_writew(mbase,
Felipe Balbi458e6a52008-09-11 11:53:24 +0300153 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
Felipe Balbi550a7372008-07-24 12:27:36 +0300154 csr);
155}
156
Felipe Balbi458e6a52008-09-11 11:53:24 +0300157static int dma_channel_program(struct dma_channel *channel,
Felipe Balbi550a7372008-07-24 12:27:36 +0300158 u16 packet_sz, u8 mode,
159 dma_addr_t dma_addr, u32 len)
160{
Felipe Balbi458e6a52008-09-11 11:53:24 +0300161 struct musb_dma_channel *musb_channel = channel->private_data;
Anand Gadiyar6e16edf2010-11-08 00:20:30 -0600162 struct musb_dma_controller *controller = musb_channel->controller;
163 struct musb *musb = controller->private_data;
Felipe Balbi550a7372008-07-24 12:27:36 +0300164
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300165 dev_dbg(musb->controller, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
Felipe Balbi458e6a52008-09-11 11:53:24 +0300166 musb_channel->epnum,
167 musb_channel->transmit ? "Tx" : "Rx",
Felipe Balbi550a7372008-07-24 12:27:36 +0300168 packet_sz, dma_addr, len, mode);
169
Felipe Balbi458e6a52008-09-11 11:53:24 +0300170 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
171 channel->status == MUSB_DMA_STATUS_BUSY);
Felipe Balbi550a7372008-07-24 12:27:36 +0300172
Mike Frysinger13254302011-03-30 22:48:54 -0400173 /* Let targets check/tweak the arguments */
174 if (musb->ops->adjust_channel_params) {
175 int ret = musb->ops->adjust_channel_params(channel,
176 packet_sz, &mode, &dma_addr, &len);
177 if (ret)
178 return ret;
179 }
180
Anand Gadiyar6e16edf2010-11-08 00:20:30 -0600181 /*
182 * The DMA engine in RTL1.8 and above cannot handle
183 * DMA addresses that are not aligned to a 4 byte boundary.
184 * It ends up masking the last two bits of the address
185 * programmed in DMA_ADDR.
186 *
187 * Fail such DMA transfers, so that the backup PIO mode
188 * can carry out the transfer
189 */
190 if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4))
191 return false;
192
Felipe Balbi458e6a52008-09-11 11:53:24 +0300193 channel->actual_len = 0;
194 musb_channel->start_addr = dma_addr;
195 musb_channel->len = len;
196 musb_channel->max_packet_sz = packet_sz;
197 channel->status = MUSB_DMA_STATUS_BUSY;
Felipe Balbi550a7372008-07-24 12:27:36 +0300198
Anand Gadiyar8ca47c82010-07-08 16:34:55 +0530199 configure_channel(channel, packet_sz, mode, dma_addr, len);
Felipe Balbi550a7372008-07-24 12:27:36 +0300200
201 return true;
202}
203
Felipe Balbi458e6a52008-09-11 11:53:24 +0300204static int dma_channel_abort(struct dma_channel *channel)
Felipe Balbi550a7372008-07-24 12:27:36 +0300205{
Felipe Balbi458e6a52008-09-11 11:53:24 +0300206 struct musb_dma_channel *musb_channel = channel->private_data;
207 void __iomem *mbase = musb_channel->controller->base;
208
209 u8 bchannel = musb_channel->idx;
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700210 int offset;
Felipe Balbi550a7372008-07-24 12:27:36 +0300211 u16 csr;
212
Felipe Balbi458e6a52008-09-11 11:53:24 +0300213 if (channel->status == MUSB_DMA_STATUS_BUSY) {
214 if (musb_channel->transmit) {
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700215 offset = MUSB_EP_OFFSET(musb_channel->epnum,
216 MUSB_TXCSR);
Felipe Balbi550a7372008-07-24 12:27:36 +0300217
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700218 /*
219 * The programming guide says that we must clear
220 * the DMAENAB bit before the DMAMODE bit...
221 */
222 csr = musb_readw(mbase, offset);
223 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
224 musb_writew(mbase, offset, csr);
225 csr &= ~MUSB_TXCSR_DMAMODE;
226 musb_writew(mbase, offset, csr);
Felipe Balbi550a7372008-07-24 12:27:36 +0300227 } else {
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700228 offset = MUSB_EP_OFFSET(musb_channel->epnum,
229 MUSB_RXCSR);
230
231 csr = musb_readw(mbase, offset);
Felipe Balbi550a7372008-07-24 12:27:36 +0300232 csr &= ~(MUSB_RXCSR_AUTOCLEAR |
233 MUSB_RXCSR_DMAENAB |
234 MUSB_RXCSR_DMAMODE);
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700235 musb_writew(mbase, offset, csr);
Felipe Balbi550a7372008-07-24 12:27:36 +0300236 }
237
238 musb_writew(mbase,
Felipe Balbi458e6a52008-09-11 11:53:24 +0300239 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
Felipe Balbi550a7372008-07-24 12:27:36 +0300240 0);
Bryan Wu6995eb62008-12-02 21:33:47 +0200241 musb_write_hsdma_addr(mbase, bchannel, 0);
242 musb_write_hsdma_count(mbase, bchannel, 0);
Felipe Balbi458e6a52008-09-11 11:53:24 +0300243 channel->status = MUSB_DMA_STATUS_FREE;
Felipe Balbi550a7372008-07-24 12:27:36 +0300244 }
Felipe Balbi458e6a52008-09-11 11:53:24 +0300245
Felipe Balbi550a7372008-07-24 12:27:36 +0300246 return 0;
247}
248
249static irqreturn_t dma_controller_irq(int irq, void *private_data)
250{
Felipe Balbi458e6a52008-09-11 11:53:24 +0300251 struct musb_dma_controller *controller = private_data;
252 struct musb *musb = controller->private_data;
253 struct musb_dma_channel *musb_channel;
254 struct dma_channel *channel;
255
256 void __iomem *mbase = controller->base;
257
Felipe Balbi550a7372008-07-24 12:27:36 +0300258 irqreturn_t retval = IRQ_NONE;
Felipe Balbi458e6a52008-09-11 11:53:24 +0300259
Felipe Balbi550a7372008-07-24 12:27:36 +0300260 unsigned long flags;
261
Felipe Balbi458e6a52008-09-11 11:53:24 +0300262 u8 bchannel;
263 u8 int_hsdma;
264
Anand Gadiyarf933a0c2009-12-28 13:40:36 +0200265 u32 addr, count;
Felipe Balbi458e6a52008-09-11 11:53:24 +0300266 u16 csr;
267
Felipe Balbi550a7372008-07-24 12:27:36 +0300268 spin_lock_irqsave(&musb->lock, flags);
269
270 int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
Felipe Balbi550a7372008-07-24 12:27:36 +0300271
Cliff Cai6bd03e72009-11-16 16:19:26 +0530272#ifdef CONFIG_BLACKFIN
273 /* Clear DMA interrupt flags */
274 musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
275#endif
276
Anand Gadiyarf933a0c2009-12-28 13:40:36 +0200277 if (!int_hsdma) {
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300278 dev_dbg(musb->controller, "spurious DMA irq\n");
Anand Gadiyarf933a0c2009-12-28 13:40:36 +0200279
280 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
281 musb_channel = (struct musb_dma_channel *)
282 &(controller->channel[bchannel]);
283 channel = &musb_channel->channel;
284 if (channel->status == MUSB_DMA_STATUS_BUSY) {
285 count = musb_read_hsdma_count(mbase, bchannel);
286
287 if (count == 0)
288 int_hsdma |= (1 << bchannel);
289 }
290 }
291
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300292 dev_dbg(musb->controller, "int_hsdma = 0x%x\n", int_hsdma);
Anand Gadiyarf933a0c2009-12-28 13:40:36 +0200293
294 if (!int_hsdma)
295 goto done;
296 }
297
Felipe Balbi458e6a52008-09-11 11:53:24 +0300298 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
299 if (int_hsdma & (1 << bchannel)) {
300 musb_channel = (struct musb_dma_channel *)
301 &(controller->channel[bchannel]);
302 channel = &musb_channel->channel;
Felipe Balbi550a7372008-07-24 12:27:36 +0300303
304 csr = musb_readw(mbase,
Felipe Balbi458e6a52008-09-11 11:53:24 +0300305 MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
Felipe Balbi550a7372008-07-24 12:27:36 +0300306 MUSB_HSDMA_CONTROL));
307
Felipe Balbi458e6a52008-09-11 11:53:24 +0300308 if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
309 musb_channel->channel.status =
Felipe Balbi550a7372008-07-24 12:27:36 +0300310 MUSB_DMA_STATUS_BUS_ABORT;
Felipe Balbi458e6a52008-09-11 11:53:24 +0300311 } else {
Felipe Balbi550a7372008-07-24 12:27:36 +0300312 u8 devctl;
313
Bryan Wu6995eb62008-12-02 21:33:47 +0200314 addr = musb_read_hsdma_addr(mbase,
315 bchannel);
Felipe Balbi458e6a52008-09-11 11:53:24 +0300316 channel->actual_len = addr
317 - musb_channel->start_addr;
Felipe Balbi550a7372008-07-24 12:27:36 +0300318
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300319 dev_dbg(musb->controller, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n",
Felipe Balbi458e6a52008-09-11 11:53:24 +0300320 channel, musb_channel->start_addr,
321 addr, channel->actual_len,
322 musb_channel->len,
323 (channel->actual_len
324 < musb_channel->len) ?
Felipe Balbi550a7372008-07-24 12:27:36 +0300325 "=> reconfig 0" : "=> complete");
326
327 devctl = musb_readb(mbase, MUSB_DEVCTL);
328
Felipe Balbi458e6a52008-09-11 11:53:24 +0300329 channel->status = MUSB_DMA_STATUS_FREE;
Felipe Balbi550a7372008-07-24 12:27:36 +0300330
331 /* completed */
332 if ((devctl & MUSB_DEVCTL_HM)
Felipe Balbi458e6a52008-09-11 11:53:24 +0300333 && (musb_channel->transmit)
334 && ((channel->desired_mode == 0)
335 || (channel->actual_len &
336 (musb_channel->max_packet_sz - 1)))
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700337 ) {
338 u8 epnum = musb_channel->epnum;
339 int offset = MUSB_EP_OFFSET(epnum,
340 MUSB_TXCSR);
341 u16 txcsr;
342
343 /*
344 * The programming guide says that we
345 * must clear DMAENAB before DMAMODE.
346 */
347 musb_ep_select(mbase, epnum);
348 txcsr = musb_readw(mbase, offset);
349 txcsr &= ~(MUSB_TXCSR_DMAENAB
350 | MUSB_TXCSR_AUTOSET);
351 musb_writew(mbase, offset, txcsr);
Felipe Balbi550a7372008-07-24 12:27:36 +0300352 /* Send out the packet */
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700353 txcsr &= ~MUSB_TXCSR_DMAMODE;
354 txcsr |= MUSB_TXCSR_TXPKTRDY;
355 musb_writew(mbase, offset, txcsr);
Felipe Balbi458e6a52008-09-11 11:53:24 +0300356 }
Sergei Shtylyovc7bbc052009-03-26 18:26:40 -0700357 musb_dma_completion(musb, musb_channel->epnum,
358 musb_channel->transmit);
Felipe Balbi550a7372008-07-24 12:27:36 +0300359 }
360 }
361 }
Bryan Wu6995eb62008-12-02 21:33:47 +0200362
Felipe Balbi550a7372008-07-24 12:27:36 +0300363 retval = IRQ_HANDLED;
364done:
365 spin_unlock_irqrestore(&musb->lock, flags);
366 return retval;
367}
368
369void dma_controller_destroy(struct dma_controller *c)
370{
Felipe Balbi458e6a52008-09-11 11:53:24 +0300371 struct musb_dma_controller *controller = container_of(c,
372 struct musb_dma_controller, controller);
Felipe Balbi550a7372008-07-24 12:27:36 +0300373
Felipe Balbi550a7372008-07-24 12:27:36 +0300374 if (!controller)
375 return;
376
377 if (controller->irq)
378 free_irq(controller->irq, c);
379
380 kfree(controller);
381}
382
383struct dma_controller *__init
Felipe Balbi458e6a52008-09-11 11:53:24 +0300384dma_controller_create(struct musb *musb, void __iomem *base)
Felipe Balbi550a7372008-07-24 12:27:36 +0300385{
386 struct musb_dma_controller *controller;
387 struct device *dev = musb->controller;
388 struct platform_device *pdev = to_platform_device(dev);
Hema Kalliguddifcf173e2010-09-29 11:26:39 -0500389 int irq = platform_get_irq_byname(pdev, "dma");
Felipe Balbi550a7372008-07-24 12:27:36 +0300390
391 if (irq == 0) {
392 dev_err(dev, "No DMA interrupt line!\n");
393 return NULL;
394 }
395
Felipe Balbi458e6a52008-09-11 11:53:24 +0300396 controller = kzalloc(sizeof(*controller), GFP_KERNEL);
Felipe Balbi550a7372008-07-24 12:27:36 +0300397 if (!controller)
398 return NULL;
399
Felipe Balbi458e6a52008-09-11 11:53:24 +0300400 controller->channel_count = MUSB_HSDMA_CHANNELS;
401 controller->private_data = musb;
402 controller->base = base;
Felipe Balbi550a7372008-07-24 12:27:36 +0300403
Felipe Balbi458e6a52008-09-11 11:53:24 +0300404 controller->controller.start = dma_controller_start;
405 controller->controller.stop = dma_controller_stop;
406 controller->controller.channel_alloc = dma_channel_allocate;
407 controller->controller.channel_release = dma_channel_release;
408 controller->controller.channel_program = dma_channel_program;
409 controller->controller.channel_abort = dma_channel_abort;
Felipe Balbi550a7372008-07-24 12:27:36 +0300410
Yong Zhangb5dd18d2011-09-07 16:10:52 +0800411 if (request_irq(irq, dma_controller_irq, 0,
Kay Sievers427c4f32008-11-07 01:52:53 +0100412 dev_name(musb->controller), &controller->controller)) {
Felipe Balbi550a7372008-07-24 12:27:36 +0300413 dev_err(dev, "request_irq %d failed!\n", irq);
Felipe Balbi458e6a52008-09-11 11:53:24 +0300414 dma_controller_destroy(&controller->controller);
415
Felipe Balbi550a7372008-07-24 12:27:36 +0300416 return NULL;
417 }
418
419 controller->irq = irq;
420
Felipe Balbi458e6a52008-09-11 11:53:24 +0300421 return &controller->controller;
Felipe Balbi550a7372008-07-24 12:27:36 +0300422}