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Sascha Haueraecfbdb2012-09-21 10:07:49 +02001/*
2 * Copyright 2005-2009 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU Lesser General
5 * Public License. You may obtain a copy of the GNU Lesser General
6 * Public License Version 2.1 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/lgpl-license.html
9 * http://www.gnu.org/copyleft/lgpl.html
10 */
11
12#ifndef __DRM_IPU_H__
13#define __DRM_IPU_H__
14
15#include <linux/types.h>
16#include <linux/videodev2.h>
17#include <linux/bitmap.h>
18#include <linux/fb.h>
Steve Longerbeam2ffd48f2014-08-19 10:52:40 -070019#include <media/v4l2-mediabus.h>
Jiada Wang6541d712014-12-18 18:00:20 -080020#include <video/videomode.h>
Sascha Haueraecfbdb2012-09-21 10:07:49 +020021
22struct ipu_soc;
23
24enum ipuv3_type {
25 IPUV3EX,
26 IPUV3M,
27 IPUV3H,
28};
29
Philipp Zabel7f4392a2014-02-25 12:43:41 +010030#define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
31
Sascha Haueraecfbdb2012-09-21 10:07:49 +020032/*
33 * Bitfield of Display Interface signal polarities.
34 */
35struct ipu_di_signal_cfg {
Sascha Haueraecfbdb2012-09-21 10:07:49 +020036 unsigned data_pol:1; /* true = inverted */
37 unsigned clk_pol:1; /* true = rising edge */
38 unsigned enable_pol:1;
Sascha Haueraecfbdb2012-09-21 10:07:49 +020039
Steve Longerbeamb6835a72014-12-18 18:00:25 -080040 struct videomode mode;
41
Sascha Haueraecfbdb2012-09-21 10:07:49 +020042 u32 pixel_fmt;
Sascha Haueraecfbdb2012-09-21 10:07:49 +020043 u32 v_to_h_sync;
Steve Longerbeamb6835a72014-12-18 18:00:25 -080044
Sascha Haueraecfbdb2012-09-21 10:07:49 +020045#define IPU_DI_CLKMODE_SYNC (1 << 0)
46#define IPU_DI_CLKMODE_EXT (1 << 1)
47 unsigned long clkflags;
Philipp Zabel2ea42602013-04-08 18:04:35 +020048
49 u8 hsync_pin;
50 u8 vsync_pin;
Sascha Haueraecfbdb2012-09-21 10:07:49 +020051};
52
Steve Longerbeam2ffd48f2014-08-19 10:52:40 -070053/*
54 * Enumeration of CSI destinations
55 */
56enum ipu_csi_dest {
57 IPU_CSI_DEST_IDMAC, /* to memory via SMFC */
58 IPU_CSI_DEST_IC, /* to Image Converter */
59 IPU_CSI_DEST_VDIC, /* to VDIC */
60};
61
Steve Longerbeam1aa8ea02014-08-11 13:04:50 +020062/*
63 * Enumeration of IPU rotation modes
64 */
65enum ipu_rotate_mode {
66 IPU_ROTATE_NONE = 0,
67 IPU_ROTATE_VERT_FLIP,
68 IPU_ROTATE_HORIZ_FLIP,
69 IPU_ROTATE_180,
70 IPU_ROTATE_90_RIGHT,
71 IPU_ROTATE_90_RIGHT_VFLIP,
72 IPU_ROTATE_90_RIGHT_HFLIP,
73 IPU_ROTATE_90_LEFT,
74};
75
Sascha Haueraecfbdb2012-09-21 10:07:49 +020076enum ipu_color_space {
77 IPUV3_COLORSPACE_RGB,
78 IPUV3_COLORSPACE_YUV,
79 IPUV3_COLORSPACE_UNKNOWN,
80};
81
82struct ipuv3_channel;
83
84enum ipu_channel_irq {
85 IPU_IRQ_EOF = 0,
86 IPU_IRQ_NFACK = 64,
87 IPU_IRQ_NFB4EOF = 128,
88 IPU_IRQ_EOS = 192,
89};
90
Steve Longerbeama4cd8f22014-06-25 18:05:39 -070091/*
92 * Enumeration of IDMAC channels
93 */
94#define IPUV3_CHANNEL_CSI0 0
95#define IPUV3_CHANNEL_CSI1 1
96#define IPUV3_CHANNEL_CSI2 2
97#define IPUV3_CHANNEL_CSI3 3
98#define IPUV3_CHANNEL_VDI_MEM_IC_VF 5
99#define IPUV3_CHANNEL_MEM_IC_PP 11
100#define IPUV3_CHANNEL_MEM_IC_PRP_VF 12
101#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF 14
102#define IPUV3_CHANNEL_G_MEM_IC_PP 15
103#define IPUV3_CHANNEL_IC_PRP_ENC_MEM 20
104#define IPUV3_CHANNEL_IC_PRP_VF_MEM 21
105#define IPUV3_CHANNEL_IC_PP_MEM 22
106#define IPUV3_CHANNEL_MEM_BG_SYNC 23
107#define IPUV3_CHANNEL_MEM_BG_ASYNC 24
108#define IPUV3_CHANNEL_MEM_FG_SYNC 27
109#define IPUV3_CHANNEL_MEM_DC_SYNC 28
110#define IPUV3_CHANNEL_MEM_FG_ASYNC 29
111#define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA 31
112#define IPUV3_CHANNEL_MEM_DC_ASYNC 41
113#define IPUV3_CHANNEL_MEM_ROT_ENC 45
114#define IPUV3_CHANNEL_MEM_ROT_VF 46
115#define IPUV3_CHANNEL_MEM_ROT_PP 47
116#define IPUV3_CHANNEL_ROT_ENC_MEM 48
117#define IPUV3_CHANNEL_ROT_VF_MEM 49
118#define IPUV3_CHANNEL_ROT_PP_MEM 50
119#define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 51
120
Philipp Zabel861a50c2014-04-14 23:53:16 +0200121int ipu_map_irq(struct ipu_soc *ipu, int irq);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200122int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
123 enum ipu_channel_irq irq);
124
125#define IPU_IRQ_DP_SF_START (448 + 2)
126#define IPU_IRQ_DP_SF_END (448 + 3)
127#define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END,
128#define IPU_IRQ_DC_FC_0 (448 + 8)
129#define IPU_IRQ_DC_FC_1 (448 + 9)
130#define IPU_IRQ_DC_FC_2 (448 + 10)
131#define IPU_IRQ_DC_FC_3 (448 + 11)
132#define IPU_IRQ_DC_FC_4 (448 + 12)
133#define IPU_IRQ_DC_FC_6 (448 + 13)
134#define IPU_IRQ_VSYNC_PRE_0 (448 + 14)
135#define IPU_IRQ_VSYNC_PRE_1 (448 + 15)
136
137/*
Steve Longerbeamba079752014-06-25 18:05:30 -0700138 * IPU Common functions
139 */
140void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2);
141void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi);
Steve Longerbeam3feb0492014-06-25 18:05:55 -0700142void ipu_dump(struct ipu_soc *ipu);
Steve Longerbeamba079752014-06-25 18:05:30 -0700143
144/*
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200145 * IPU Image DMA Controller (idmac) functions
146 */
147struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
148void ipu_idmac_put(struct ipuv3_channel *);
149
150int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
151int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
Steve Longerbeam2bcf5772014-06-25 18:05:44 -0700152void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable);
Steve Longerbeam4fd1a072014-06-25 18:05:45 -0700153int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts);
Sascha Hauerfb822a32013-10-10 16:18:41 +0200154int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200155
156void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
157 bool doublebuffer);
Philipp Zabele9046092012-05-16 17:28:29 +0200158int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
Steve Longerbeamaa52f572014-06-25 18:05:40 -0700159bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200160void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
Steve Longerbeambce6f082014-06-25 18:05:41 -0700161void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200162
163/*
Steve Longerbeam7d2691d2014-06-25 18:05:47 -0700164 * IPU Channel Parameter Memory (cpmem) functions
165 */
166struct ipu_rgb {
167 struct fb_bitfield red;
168 struct fb_bitfield green;
169 struct fb_bitfield blue;
170 struct fb_bitfield transp;
171 int bits_per_pixel;
172};
173
174struct ipu_image {
175 struct v4l2_pix_format pix;
176 struct v4l2_rect rect;
Steve Longerbeam2094b602014-06-25 18:05:52 -0700177 dma_addr_t phys0;
178 dma_addr_t phys1;
Steve Longerbeam7d2691d2014-06-25 18:05:47 -0700179};
180
181void ipu_cpmem_zero(struct ipuv3_channel *ch);
182void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
183void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
184void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
185void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
186void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
Steve Longerbeam555f0e62014-06-25 18:05:50 -0700187void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
Steve Longerbeam7d2691d2014-06-25 18:05:47 -0700188void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
Steve Longerbeam9b9da0b2014-06-25 18:05:49 -0700189void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch);
Steve Longerbeamc42d37ca2014-06-25 18:05:51 -0700190void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
191 enum ipu_rotate_mode rot);
Steve Longerbeam7d2691d2014-06-25 18:05:47 -0700192int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
193 const struct ipu_rgb *rgb);
194int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
195void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
196void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
197 u32 pixel_format, int stride,
198 int u_offset, int v_offset);
199void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
200 u32 pixel_format, int stride, int height);
201int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
202int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image);
Steve Longerbeam60c04452014-06-25 18:05:54 -0700203void ipu_cpmem_dump(struct ipuv3_channel *ch);
Steve Longerbeam7d2691d2014-06-25 18:05:47 -0700204
205/*
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200206 * IPU Display Controller (dc) functions
207 */
208struct ipu_dc;
209struct ipu_di;
210struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
211void ipu_dc_put(struct ipu_dc *dc);
212int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
213 u32 pixel_fmt, u32 width);
Philipp Zabel1e6d4862014-04-14 23:53:23 +0200214void ipu_dc_enable(struct ipu_soc *ipu);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200215void ipu_dc_enable_channel(struct ipu_dc *dc);
216void ipu_dc_disable_channel(struct ipu_dc *dc);
Philipp Zabel1e6d4862014-04-14 23:53:23 +0200217void ipu_dc_disable(struct ipu_soc *ipu);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200218
219/*
220 * IPU Display Interface (di) functions
221 */
222struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
223void ipu_di_put(struct ipu_di *);
224int ipu_di_disable(struct ipu_di *);
225int ipu_di_enable(struct ipu_di *);
226int ipu_di_get_num(struct ipu_di *);
Jiada Wang6541d712014-12-18 18:00:20 -0800227int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200228int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
229
230/*
231 * IPU Display Multi FIFO Controller (dmfc) functions
232 */
233struct dmfc_channel;
234int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
235void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
236int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
237 unsigned long bandwidth_mbs, int burstsize);
238void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc);
239int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width);
240struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
241void ipu_dmfc_put(struct dmfc_channel *dmfc);
242
243/*
244 * IPU Display Processor (dp) functions
245 */
246#define IPU_DP_FLOW_SYNC_BG 0
247#define IPU_DP_FLOW_SYNC_FG 1
248#define IPU_DP_FLOW_ASYNC0_BG 2
249#define IPU_DP_FLOW_ASYNC0_FG 3
250#define IPU_DP_FLOW_ASYNC1_BG 4
251#define IPU_DP_FLOW_ASYNC1_FG 5
252
253struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
254void ipu_dp_put(struct ipu_dp *);
Philipp Zabel285bbb02014-04-14 23:53:20 +0200255int ipu_dp_enable(struct ipu_soc *ipu);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200256int ipu_dp_enable_channel(struct ipu_dp *dp);
257void ipu_dp_disable_channel(struct ipu_dp *dp);
Philipp Zabel285bbb02014-04-14 23:53:20 +0200258void ipu_dp_disable(struct ipu_soc *ipu);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200259int ipu_dp_setup_channel(struct ipu_dp *dp,
260 enum ipu_color_space in, enum ipu_color_space out);
261int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
262int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
263 bool bg_chan);
264
Philipp Zabel35de9252012-05-09 16:59:01 +0200265/*
Philipp Zabel3f5a8a92012-05-22 17:08:48 +0200266 * IPU CMOS Sensor Interface (csi) functions
267 */
Steve Longerbeam2ffd48f2014-08-19 10:52:40 -0700268struct ipu_csi;
269int ipu_csi_init_interface(struct ipu_csi *csi,
270 struct v4l2_mbus_config *mbus_cfg,
271 struct v4l2_mbus_framefmt *mbus_fmt);
272bool ipu_csi_is_interlaced(struct ipu_csi *csi);
273void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w);
274void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w);
275void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
276 u32 r_value, u32 g_value, u32 b_value,
277 u32 pix_clk);
278int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
279 struct v4l2_mbus_framefmt *mbus_fmt);
280int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
281 u32 max_ratio, u32 id);
282int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest);
283int ipu_csi_enable(struct ipu_csi *csi);
284int ipu_csi_disable(struct ipu_csi *csi);
285struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id);
286void ipu_csi_put(struct ipu_csi *csi);
287void ipu_csi_dump(struct ipu_csi *csi);
Philipp Zabel3f5a8a92012-05-22 17:08:48 +0200288
289/*
Steve Longerbeam1aa8ea02014-08-11 13:04:50 +0200290 * IPU Image Converter (ic) functions
291 */
292enum ipu_ic_task {
293 IC_TASK_ENCODER,
294 IC_TASK_VIEWFINDER,
295 IC_TASK_POST_PROCESSOR,
296 IC_NUM_TASKS,
297};
298
299struct ipu_ic;
300int ipu_ic_task_init(struct ipu_ic *ic,
301 int in_width, int in_height,
302 int out_width, int out_height,
303 enum ipu_color_space in_cs,
304 enum ipu_color_space out_cs);
305int ipu_ic_task_graphics_init(struct ipu_ic *ic,
306 enum ipu_color_space in_g_cs,
307 bool galpha_en, u32 galpha,
308 bool colorkey_en, u32 colorkey);
309void ipu_ic_task_enable(struct ipu_ic *ic);
310void ipu_ic_task_disable(struct ipu_ic *ic);
311int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
312 u32 width, u32 height, int burst_size,
313 enum ipu_rotate_mode rot);
314int ipu_ic_enable(struct ipu_ic *ic);
315int ipu_ic_disable(struct ipu_ic *ic);
316struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task);
317void ipu_ic_put(struct ipu_ic *ic);
318void ipu_ic_dump(struct ipu_ic *ic);
319
320/*
Philipp Zabel35de9252012-05-09 16:59:01 +0200321 * IPU Sensor Multiple FIFO Controller (SMFC) functions
322 */
Steve Longerbeam7fafa8f2014-06-25 18:05:34 -0700323struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno);
324void ipu_smfc_put(struct ipu_smfc *smfc);
325int ipu_smfc_enable(struct ipu_smfc *smfc);
326int ipu_smfc_disable(struct ipu_smfc *smfc);
327int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id);
328int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize);
Steve Longerbeama2be35e2014-06-25 18:05:35 -0700329int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level);
Philipp Zabel35de9252012-05-09 16:59:01 +0200330
Philipp Zabel7cb17792013-10-10 16:18:38 +0200331enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200332enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
Steve Longerbeamae0e9702014-06-25 18:05:36 -0700333enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code);
Steve Longerbeam6930afd2014-06-25 18:05:43 -0700334int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat);
Steve Longerbeam4cea9402014-06-25 18:05:38 -0700335bool ipu_pixelformat_is_planar(u32 pixelformat);
Steve Longerbeamf835f382014-06-25 18:05:37 -0700336int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
337 bool hflip, bool vflip);
338int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
339 bool hflip, bool vflip);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200340
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200341struct ipu_client_platformdata {
Philipp Zabeld6ca8ca2012-05-23 17:08:19 +0200342 int csi;
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200343 int di;
344 int dc;
345 int dp;
346 int dmfc;
347 int dma[2];
348};
349
350#endif /* __DRM_IPU_H__ */