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gerrit-public.fairphone.software / kernel / msm-4.9 / b7099c498b6cf9f53bb392f7b0087ad212299707 / . / drivers / pinctrl / sh-pfc / pfc-r8a7740.c
blob: f17a39ad77a2554249c6bbb72f7358b05f2b1dfd [file] [log] [blame]
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of the
10 * License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21#include <linux/kernel.h>
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]22#include <mach/r8a7740.h>
23#include <mach/irqs.h>
24
Laurent Pinchartc3323802012-12-15 23:51:55 +0100[diff] [blame]25#include "sh_pfc.h"
26
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]27#define CPU_ALL_PORT(fn, pfx, sfx) \
28 PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
29 PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \
30 PORT_10(fn, pfx##20, sfx), \
31 PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx)
32
Bastian Hecht09bbc1f2013-04-09 10:48:50 +0000[diff] [blame]33#define IRQC_PIN_MUX(irq, pin) \
34static const unsigned int intc_irq##irq##_pins[] = { \
35 pin, \
36}; \
37static const unsigned int intc_irq##irq##_mux[] = { \
38 IRQ##irq##_MARK, \
39}
40
41#define IRQC_PINS_MUX(irq, idx, pin) \
42static const unsigned int intc_irq##irq##_##idx##_pins[] = { \
43 pin, \
44}; \
45static const unsigned int intc_irq##irq##_##idx##_mux[] = { \
46 IRQ##irq##_PORT##pin##_MARK, \
47}
48
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]49enum {
50 PINMUX_RESERVED = 0,
51
52 /* PORT0_DATA -> PORT211_DATA */
53 PINMUX_DATA_BEGIN,
54 PORT_ALL(DATA),
55 PINMUX_DATA_END,
56
57 /* PORT0_IN -> PORT211_IN */
58 PINMUX_INPUT_BEGIN,
59 PORT_ALL(IN),
60 PINMUX_INPUT_END,
61
62 /* PORT0_IN_PU -> PORT211_IN_PU */
63 PINMUX_INPUT_PULLUP_BEGIN,
64 PORT_ALL(IN_PU),
65 PINMUX_INPUT_PULLUP_END,
66
67 /* PORT0_IN_PD -> PORT211_IN_PD */
68 PINMUX_INPUT_PULLDOWN_BEGIN,
69 PORT_ALL(IN_PD),
70 PINMUX_INPUT_PULLDOWN_END,
71
72 /* PORT0_OUT -> PORT211_OUT */
73 PINMUX_OUTPUT_BEGIN,
74 PORT_ALL(OUT),
75 PINMUX_OUTPUT_END,
76
77 PINMUX_FUNCTION_BEGIN,
78 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */
79 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */
80 PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */
81 PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */
82 PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */
83 PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */
84 PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */
85 PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */
86 PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */
87 PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */
88
89 MSEL1CR_31_0, MSEL1CR_31_1,
90 MSEL1CR_30_0, MSEL1CR_30_1,
91 MSEL1CR_29_0, MSEL1CR_29_1,
92 MSEL1CR_28_0, MSEL1CR_28_1,
93 MSEL1CR_27_0, MSEL1CR_27_1,
94 MSEL1CR_26_0, MSEL1CR_26_1,
95 MSEL1CR_16_0, MSEL1CR_16_1,
96 MSEL1CR_15_0, MSEL1CR_15_1,
97 MSEL1CR_14_0, MSEL1CR_14_1,
98 MSEL1CR_13_0, MSEL1CR_13_1,
99 MSEL1CR_12_0, MSEL1CR_12_1,
100 MSEL1CR_9_0, MSEL1CR_9_1,
101 MSEL1CR_7_0, MSEL1CR_7_1,
102 MSEL1CR_6_0, MSEL1CR_6_1,
103 MSEL1CR_5_0, MSEL1CR_5_1,
104 MSEL1CR_4_0, MSEL1CR_4_1,
105 MSEL1CR_3_0, MSEL1CR_3_1,
106 MSEL1CR_2_0, MSEL1CR_2_1,
107 MSEL1CR_0_0, MSEL1CR_0_1,
108
109 MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */
110 MSEL3CR_6_0, MSEL3CR_6_1,
111
112 MSEL4CR_19_0, MSEL4CR_19_1,
113 MSEL4CR_18_0, MSEL4CR_18_1,
114 MSEL4CR_15_0, MSEL4CR_15_1,
115 MSEL4CR_10_0, MSEL4CR_10_1,
116 MSEL4CR_6_0, MSEL4CR_6_1,
117 MSEL4CR_4_0, MSEL4CR_4_1,
118 MSEL4CR_1_0, MSEL4CR_1_1,
119
120 MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */
121 MSEL5CR_30_0, MSEL5CR_30_1,
122 MSEL5CR_29_0, MSEL5CR_29_1,
123 MSEL5CR_27_0, MSEL5CR_27_1,
124 MSEL5CR_25_0, MSEL5CR_25_1,
125 MSEL5CR_23_0, MSEL5CR_23_1,
126 MSEL5CR_21_0, MSEL5CR_21_1,
127 MSEL5CR_19_0, MSEL5CR_19_1,
128 MSEL5CR_17_0, MSEL5CR_17_1,
129 MSEL5CR_15_0, MSEL5CR_15_1,
130 MSEL5CR_14_0, MSEL5CR_14_1,
131 MSEL5CR_13_0, MSEL5CR_13_1,
132 MSEL5CR_12_0, MSEL5CR_12_1,
133 MSEL5CR_11_0, MSEL5CR_11_1,
134 MSEL5CR_10_0, MSEL5CR_10_1,
135 MSEL5CR_8_0, MSEL5CR_8_1,
136 MSEL5CR_7_0, MSEL5CR_7_1,
137 MSEL5CR_6_0, MSEL5CR_6_1,
138 MSEL5CR_5_0, MSEL5CR_5_1,
139 MSEL5CR_4_0, MSEL5CR_4_1,
140 MSEL5CR_3_0, MSEL5CR_3_1,
141 MSEL5CR_2_0, MSEL5CR_2_1,
142 MSEL5CR_0_0, MSEL5CR_0_1,
143 PINMUX_FUNCTION_END,
144
145 PINMUX_MARK_BEGIN,
146
147 /* IRQ */
148 IRQ0_PORT2_MARK, IRQ0_PORT13_MARK,
149 IRQ1_MARK,
150 IRQ2_PORT11_MARK, IRQ2_PORT12_MARK,
151 IRQ3_PORT10_MARK, IRQ3_PORT14_MARK,
152 IRQ4_PORT15_MARK, IRQ4_PORT172_MARK,
153 IRQ5_PORT0_MARK, IRQ5_PORT1_MARK,
154 IRQ6_PORT121_MARK, IRQ6_PORT173_MARK,
155 IRQ7_PORT120_MARK, IRQ7_PORT209_MARK,
156 IRQ8_MARK,
157 IRQ9_PORT118_MARK, IRQ9_PORT210_MARK,
158 IRQ10_MARK,
159 IRQ11_MARK,
160 IRQ12_PORT42_MARK, IRQ12_PORT97_MARK,
161 IRQ13_PORT64_MARK, IRQ13_PORT98_MARK,
162 IRQ14_PORT63_MARK, IRQ14_PORT99_MARK,
163 IRQ15_PORT62_MARK, IRQ15_PORT100_MARK,
164 IRQ16_PORT68_MARK, IRQ16_PORT211_MARK,
165 IRQ17_MARK,
166 IRQ18_MARK,
167 IRQ19_MARK,
168 IRQ20_MARK,
169 IRQ21_MARK,
170 IRQ22_MARK,
171 IRQ23_MARK,
172 IRQ24_MARK,
173 IRQ25_MARK,
174 IRQ26_PORT58_MARK, IRQ26_PORT81_MARK,
175 IRQ27_PORT57_MARK, IRQ27_PORT168_MARK,
176 IRQ28_PORT56_MARK, IRQ28_PORT169_MARK,
177 IRQ29_PORT50_MARK, IRQ29_PORT170_MARK,
178 IRQ30_PORT49_MARK, IRQ30_PORT171_MARK,
179 IRQ31_PORT41_MARK, IRQ31_PORT167_MARK,
180
181 /* Function */
182
183 /* DBGT */
184 DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK,
185 DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK,
186 DBGMD21_MARK,
187
188 /* FSI-A */
189 FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */
190 FSIAISLD_PORT5_MARK,
191 FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */
192 FSIASPDIF_PORT18_MARK,
193 FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
194 FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK,
195 FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
196
197 /* FSI-B */
198 FSIBCK_MARK,
199
200 /* FMSI */
201 FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
202 FMSISLD_PORT6_MARK,
203 FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK,
204 FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK,
205 FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK,
206
207 /* SCIFA0 */
208 SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK,
209 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
210
211 /* SCIFA1 */
212 SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK,
213 SCIFA1_TXD_MARK, SCIFA1_RTS_MARK,
214
215 /* SCIFA2 */
216 SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
217 SCIFA2_SCK_PORT199_MARK,
218 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
219 SCIFA2_CTS_MARK, SCIFA2_RTS_MARK,
220
221 /* SCIFA3 */
222 SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
223 SCIFA3_SCK_PORT116_MARK,
224 SCIFA3_CTS_PORT117_MARK,
225 SCIFA3_RXD_PORT174_MARK,
226 SCIFA3_TXD_PORT175_MARK,
227
228 SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
229 SCIFA3_SCK_PORT158_MARK,
230 SCIFA3_CTS_PORT162_MARK,
231 SCIFA3_RXD_PORT159_MARK,
232 SCIFA3_TXD_PORT160_MARK,
233
234 /* SCIFA4 */
235 SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
236 SCIFA4_TXD_PORT13_MARK,
237
238 SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
239 SCIFA4_TXD_PORT203_MARK,
240
241 SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
242 SCIFA4_TXD_PORT93_MARK,
243
244 SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
245 SCIFA4_SCK_PORT205_MARK,
246
247 /* SCIFA5 */
248 SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
249 SCIFA5_RXD_PORT10_MARK,
250
251 SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
252 SCIFA5_TXD_PORT208_MARK,
253
254 SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
255 SCIFA5_RXD_PORT92_MARK,
256
257 SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
258 SCIFA5_SCK_PORT206_MARK,
259
260 /* SCIFA6 */
261 SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
262
263 /* SCIFA7 */
264 SCIFA7_TXD_MARK, SCIFA7_RXD_MARK,
265
266 /* SCIFAB */
267 SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
268 SCIFB_RXD_PORT191_MARK,
269 SCIFB_TXD_PORT192_MARK,
270 SCIFB_RTS_PORT186_MARK,
271 SCIFB_CTS_PORT187_MARK,
272
273 SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
274 SCIFB_RXD_PORT3_MARK,
275 SCIFB_TXD_PORT4_MARK,
276 SCIFB_RTS_PORT172_MARK,
277 SCIFB_CTS_PORT173_MARK,
278
279 /* LCD0 */
280 LCDC0_SELECT_MARK,
281
282 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
283 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
284 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
285 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
286 LCD0_D16_MARK, LCD0_D17_MARK,
287 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
288 LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */
289 LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
290 LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */
291 LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */
292
293 LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
294 LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK,
295 LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK,
296 LCD0_LCLK_PORT165_MARK,
297
298 LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
299 LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK,
300 LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK,
301 LCD0_LCLK_PORT102_MARK,
302
303 /* LCD1 */
304 LCDC1_SELECT_MARK,
305
306 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
307 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
308 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
309 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
310 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
311 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
312 LCD1_DON_MARK, LCD1_VCPWC_MARK,
313 LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
314
315 LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */
316 LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
317 LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */
318 LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */
319
320 /* RSPI */
321 RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK,
322 RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK,
323 RSPI_MISO_A_MARK,
324
325 /* VIO CKO */
326 VIO_CKO1_MARK, /* needs fixup */
327 VIO_CKO2_MARK,
328 VIO_CKO_1_MARK,
329 VIO_CKO_MARK,
330
331 /* VIO0 */
332 VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
333 VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
334 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
335 VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK,
336 VIO0_FIELD_MARK,
337
338 VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
339 VIO0_D14_PORT25_MARK,
340 VIO0_D15_PORT24_MARK,
341
342 VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
343 VIO0_D14_PORT95_MARK,
344 VIO0_D15_PORT96_MARK,
345
346 /* VIO1 */
347 VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
348 VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
349 VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK,
350
351 /* TPU0 */
352 TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK,
353 TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
354 TPU0TO2_PORT202_MARK,
355
356 /* SSP1 0 */
357 STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
358 STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
359 STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK,
360
361 /* SSP1 1 */
362 STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
363 STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
364 STP1_IPSYNC_MARK,
365
366 STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
367 STP1_IPEN_PORT187_MARK,
368
369 STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
370 STP1_IPEN_PORT193_MARK,
371
372 /* SIM */
373 SIM_RST_MARK, SIM_CLK_MARK,
374 SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */
375 SIM_D_PORT199_MARK,
376
377 /* SDHI0 */
378 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
379 SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK,
380
381 /* SDHI1 */
382 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
383 SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK,
384
385 /* SDHI2 */
386 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
387 SDHI2_CLK_MARK, SDHI2_CMD_MARK,
388
389 SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
390 SDHI2_WP_PORT25_MARK,
391
392 SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
393 SDHI2_CD_PORT202_MARK,
394
395 /* MSIOF2 */
396 MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK,
397 MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK,
398 MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK,
399 MSIOF2_RSCK_MARK,
400
401 /* KEYSC */
402 KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
403 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
404 KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
405
406 KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
407 KEYIN1_PORT44_MARK,
408 KEYIN2_PORT45_MARK,
409 KEYIN3_PORT46_MARK,
410
411 KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
412 KEYIN1_PORT57_MARK,
413 KEYIN2_PORT56_MARK,
414 KEYIN3_PORT55_MARK,
415
416 /* VOU */
417 DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK,
418 DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK,
419 DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK,
420 DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK,
421 DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK,
422
423 /* MEMC */
424 MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK,
425 MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK,
426 MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK,
427 MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
428 MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK,
429
430 MEMC_CS1_MARK, /* MSEL4CR_6_0 */
431 MEMC_ADV_MARK,
432 MEMC_WAIT_MARK,
433 MEMC_BUSCLK_MARK,
434
435 MEMC_A1_MARK, /* MSEL4CR_6_1 */
436 MEMC_DREQ0_MARK,
437 MEMC_DREQ1_MARK,
438 MEMC_A0_MARK,
439
440 /* MMC */
441 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK,
442 MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK,
443 MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK,
444 MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */
445
446 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK,
447 MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK,
448 MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK,
449 MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */
450
451 /* MSIOF0 */
452 MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK,
453 MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK,
454 MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK,
455 MSIOF0_TSYNC_MARK,
456
457 /* MSIOF1 */
458 MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK,
459 MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
460
461 MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK,
462 MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK,
463 MSIOF1_TSYNC_PORT120_MARK,
464 MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */
465
466 MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK,
467 MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK,
468 MSIOF1_RXD_PORT75_MARK,
469 MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */
470
471 /* GPIO */
472 GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK,
473
474 /* USB0 */
475 USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK,
476
477 /* USB1 */
478 USB1_OCI_MARK, USB1_PPON_MARK,
479
480 /* BBIF1 */
481 BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK,
482 BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
483 BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK,
484
485 /* BBIF2 */
486 BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
487 BBIF2_RXD2_PORT60_MARK,
488 BBIF2_TSYNC2_PORT6_MARK,
489 BBIF2_TSCK2_PORT59_MARK,
490
491 BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
492 BBIF2_TXD2_PORT183_MARK,
493 BBIF2_TSCK2_PORT89_MARK,
494 BBIF2_TSYNC2_PORT184_MARK,
495
496 /* BSC / FLCTL / PCMCIA */
497 CS0_MARK, CS2_MARK, CS4_MARK,
498 CS5B_MARK, CS6A_MARK,
499 CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
500 CS5A_PORT19_MARK,
501 IOIS16_MARK, /* ? */
502
503 A0_MARK, A1_MARK, A2_MARK, A3_MARK,
504 A4_FOE_MARK, /* share with FLCTL */
505 A5_FCDE_MARK, /* share with FLCTL */
506 A6_MARK, A7_MARK, A8_MARK, A9_MARK,
507 A10_MARK, A11_MARK, A12_MARK, A13_MARK,
508 A14_MARK, A15_MARK, A16_MARK, A17_MARK,
509 A18_MARK, A19_MARK, A20_MARK, A21_MARK,
510 A22_MARK, A23_MARK, A24_MARK, A25_MARK,
511 A26_MARK,
512
513 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */
514 D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */
515 D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */
516 D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
517 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
518 D15_NAF15_MARK, /* share with FLCTL */
519 D16_MARK, D17_MARK, D18_MARK, D19_MARK,
520 D20_MARK, D21_MARK, D22_MARK, D23_MARK,
521 D24_MARK, D25_MARK, D26_MARK, D27_MARK,
522 D28_MARK, D29_MARK, D30_MARK, D31_MARK,
523
524 WE0_FWE_MARK, /* share with FLCTL */
525 WE1_MARK,
526 WE2_ICIORD_MARK, /* share with PCMCIA */
527 WE3_ICIOWR_MARK, /* share with PCMCIA */
528 CKO_MARK, BS_MARK, RDWR_MARK,
529 RD_FSC_MARK, /* share with FLCTL */
530 WAIT_PORT177_MARK, /* WAIT Port 90/177 */
531 WAIT_PORT90_MARK,
532
533 FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */
534
535 /* IRDA */
536 IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK,
537
538 /* ATAPI */
539 IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK,
540 IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK,
541 IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK,
542 IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK,
543 IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK,
544 IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK,
545 IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK,
546 IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK,
547
548 /* RMII */
549 RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK,
550 RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK,
551 RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK,
552 RMII_REF50CK_MARK, /* for RMII */
553 RMII_REF125CK_MARK, /* for GMII */
554
555 /* GEther */
556 ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK,
557 ET_ETXD2_MARK, ET_ETXD3_MARK,
558 ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */
559 ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */
560 ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK,
561 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
562 ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */
563 ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */
564 ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK,
565 ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK,
566
567 /* DMA0 */
568 DREQ0_MARK, DACK0_MARK,
569
570 /* DMA1 */
571 DREQ1_MARK, DACK1_MARK,
572
573 /* SYSC */
574 RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK,
575
576 /* IRREM */
577 IROUT_MARK,
578
579 /* SDENC */
580 SDENC_CPG_MARK, SDENC_DV_CLKI_MARK,
581
582 /* HDMI */
583 HDMI_HPD_MARK, HDMI_CEC_MARK,
584
585 /* DEBUG */
586 EDEBGREQ_PULLUP_MARK, /* for JTAG */
587 EDEBGREQ_PULLDOWN_MARK,
588
589 TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
590 TRACEAUD_FROM_LCDC0_MARK,
591 TRACEAUD_FROM_MEMC_MARK,
592
593 PINMUX_MARK_END,
594};
595
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]596static const pinmux_enum_t pinmux_data[] = {
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]597 /* specify valid pin states for each pin in GPIO mode */
598
599 /* I/O and Pull U/D */
600 PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1),
601 PORT_DATA_IO_PD(2), PORT_DATA_IO_PD(3),
602 PORT_DATA_IO_PD(4), PORT_DATA_IO_PD(5),
603 PORT_DATA_IO_PD(6), PORT_DATA_IO(7),
604 PORT_DATA_IO(8), PORT_DATA_IO(9),
605
606 PORT_DATA_IO_PD(10), PORT_DATA_IO_PD(11),
607 PORT_DATA_IO_PD(12), PORT_DATA_IO_PU_PD(13),
608 PORT_DATA_IO_PD(14), PORT_DATA_IO_PD(15),
609 PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17),
610 PORT_DATA_IO(18), PORT_DATA_IO_PU(19),
611
612 PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PD(21),
613 PORT_DATA_IO_PU_PD(22), PORT_DATA_IO(23),
614 PORT_DATA_IO_PU(24), PORT_DATA_IO_PU(25),
615 PORT_DATA_IO_PU(26), PORT_DATA_IO_PU(27),
616 PORT_DATA_IO_PU(28), PORT_DATA_IO_PU(29),
617
618 PORT_DATA_IO_PU(30), PORT_DATA_IO_PD(31),
619 PORT_DATA_IO_PD(32), PORT_DATA_IO_PD(33),
620 PORT_DATA_IO_PD(34), PORT_DATA_IO_PU(35),
621 PORT_DATA_IO_PU(36), PORT_DATA_IO_PD(37),
622 PORT_DATA_IO_PU(38), PORT_DATA_IO_PD(39),
623
624 PORT_DATA_IO_PU_PD(40), PORT_DATA_IO_PD(41),
625 PORT_DATA_IO_PD(42), PORT_DATA_IO_PU_PD(43),
626 PORT_DATA_IO_PU_PD(44), PORT_DATA_IO_PU_PD(45),
627 PORT_DATA_IO_PU_PD(46), PORT_DATA_IO_PU_PD(47),
628 PORT_DATA_IO_PU_PD(48), PORT_DATA_IO_PU_PD(49),
629
630 PORT_DATA_IO_PU_PD(50), PORT_DATA_IO_PD(51),
631 PORT_DATA_IO_PD(52), PORT_DATA_IO_PD(53),
632 PORT_DATA_IO_PD(54), PORT_DATA_IO_PU_PD(55),
633 PORT_DATA_IO_PU_PD(56), PORT_DATA_IO_PU_PD(57),
634 PORT_DATA_IO_PU_PD(58), PORT_DATA_IO_PU_PD(59),
635
636 PORT_DATA_IO_PU_PD(60), PORT_DATA_IO_PD(61),
637 PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63),
638 PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65),
639 PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
640 PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
641
642 PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
643 PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73),
644 PORT_DATA_IO_PU_PD(74), PORT_DATA_IO_PU_PD(75),
645 PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
646 PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
647
648 PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
649 PORT_DATA_IO(82), PORT_DATA_IO_PU_PD(83),
650 PORT_DATA_IO(84), PORT_DATA_IO_PD(85),
651 PORT_DATA_IO_PD(86), PORT_DATA_IO_PD(87),
652 PORT_DATA_IO_PD(88), PORT_DATA_IO_PD(89),
653
654 PORT_DATA_IO_PD(90), PORT_DATA_IO_PU_PD(91),
655 PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93),
656 PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95),
657 PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97),
658 PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99),
659
660 PORT_DATA_IO_PU_PD(100), PORT_DATA_IO(101),
661 PORT_DATA_IO_PU(102), PORT_DATA_IO_PU_PD(103),
662 PORT_DATA_IO_PU(104), PORT_DATA_IO_PU(105),
663 PORT_DATA_IO_PU_PD(106), PORT_DATA_IO(107),
664 PORT_DATA_IO(108), PORT_DATA_IO(109),
665
666 PORT_DATA_IO(110), PORT_DATA_IO(111),
667 PORT_DATA_IO(112), PORT_DATA_IO(113),
668 PORT_DATA_IO_PU_PD(114), PORT_DATA_IO(115),
669 PORT_DATA_IO_PD(116), PORT_DATA_IO_PD(117),
670 PORT_DATA_IO_PD(118), PORT_DATA_IO_PD(119),
671
672 PORT_DATA_IO_PD(120), PORT_DATA_IO_PD(121),
673 PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123),
674 PORT_DATA_IO_PD(124), PORT_DATA_IO(125),
675 PORT_DATA_IO(126), PORT_DATA_IO(127),
676 PORT_DATA_IO(128), PORT_DATA_IO(129),
677
678 PORT_DATA_IO(130), PORT_DATA_IO(131),
679 PORT_DATA_IO(132), PORT_DATA_IO(133),
680 PORT_DATA_IO(134), PORT_DATA_IO(135),
681 PORT_DATA_IO(136), PORT_DATA_IO(137),
682 PORT_DATA_IO(138), PORT_DATA_IO(139),
683
684 PORT_DATA_IO(140), PORT_DATA_IO(141),
685 PORT_DATA_IO_PU(142), PORT_DATA_IO_PU(143),
686 PORT_DATA_IO_PU(144), PORT_DATA_IO_PU(145),
687 PORT_DATA_IO_PU(146), PORT_DATA_IO_PU(147),
688 PORT_DATA_IO_PU(148), PORT_DATA_IO_PU(149),
689
690 PORT_DATA_IO_PU(150), PORT_DATA_IO_PU(151),
691 PORT_DATA_IO_PU(152), PORT_DATA_IO_PU(153),
692 PORT_DATA_IO_PU(154), PORT_DATA_IO_PU(155),
693 PORT_DATA_IO_PU(156), PORT_DATA_IO_PU(157),
694 PORT_DATA_IO_PD(158), PORT_DATA_IO_PD(159),
695
696 PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PD(161),
697 PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163),
698 PORT_DATA_IO_PD(164), PORT_DATA_IO_PD(165),
699 PORT_DATA_IO_PU(166), PORT_DATA_IO_PU(167),
700 PORT_DATA_IO_PU(168), PORT_DATA_IO_PU(169),
701
702 PORT_DATA_IO_PU(170), PORT_DATA_IO_PU(171),
703 PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173),
704 PORT_DATA_IO_PD(174), PORT_DATA_IO_PD(175),
705 PORT_DATA_IO_PU(176), PORT_DATA_IO_PU_PD(177),
706 PORT_DATA_IO_PU(178), PORT_DATA_IO_PD(179),
707
708 PORT_DATA_IO_PD(180), PORT_DATA_IO_PU(181),
709 PORT_DATA_IO_PU(182), PORT_DATA_IO(183),
710 PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185),
711 PORT_DATA_IO_PD(186), PORT_DATA_IO_PD(187),
712 PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189),
713
714 PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191),
715 PORT_DATA_IO_PD(192), PORT_DATA_IO_PU_PD(193),
716 PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PD(195),
717 PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PD(197),
718 PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199),
719
720 PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU(201),
721 PORT_DATA_IO_PU_PD(202), PORT_DATA_IO(203),
722 PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
723 PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207),
724 PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PD(209),
725
726 PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
727
728 /* Port0 */
729 PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
730 PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0),
731 PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3),
732 PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0),
733 PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6),
734 PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7),
735 PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0),
736
737 /* Port1 */
738 PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1),
739 PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0),
740 PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3),
741 PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0),
742 PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6),
743 PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7),
744 PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1),
745
746 /* Port2 */
747 PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1),
748 PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1),
749 PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0),
750 PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7),
751 PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1),
752
753 /* Port3 */
754 PINMUX_DATA(DBGMD21_MARK, PORT3_FN1),
755 PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1),
756 PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0),
757 PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7),
758
759 /* Port4 */
760 PINMUX_DATA(DBGMD20_MARK, PORT4_FN1),
761 PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1),
762 PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0),
763 PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7),
764
765 /* Port5 */
766 PINMUX_DATA(DBGMD11_MARK, PORT5_FN1),
767 PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0),
768 PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1),
769 PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6),
770 PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7),
771
772 /* Port6 */
773 PINMUX_DATA(DBGMD10_MARK, PORT6_FN1),
774 PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0),
775 PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1),
776 PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6),
777 PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7),
778
779 /* Port7 */
780 PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1),
781
782 /* Port8 */
783 PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1),
784
785 /* Port9 */
786 PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1),
787 PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0),
788
789 /* Port10 */
790 PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1),
791 PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0, MSEL5CR_15_0),
792 PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0),
793
794 /* Port11 */
795 PINMUX_DATA(FSIACK_MARK, PORT11_FN1),
796 PINMUX_DATA(FSIBCK_MARK, PORT11_FN2),
797 PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0),
798
799 /* Port12 */
800 PINMUX_DATA(FSIAILR_MARK, PORT12_FN1),
801 PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
802 PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6),
803 PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7),
804 PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1),
805
806 /* Port13 */
807 PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1),
808 PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
809 PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7),
810 PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0),
811
812 /* Port14 */
813 PINMUX_DATA(FMSOILR_MARK, PORT14_FN1),
814 PINMUX_DATA(FMSIILR_MARK, PORT14_FN2),
815 PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3),
816 PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7),
817 PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1),
818
819 /* Port15 */
820 PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1),
821 PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2),
822 PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3),
823 PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7),
824 PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0),
825
826 /* Port16 */
827 PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1),
828 PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2),
829
830 /* Port17 */
831 PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1),
832 PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2),
833
834 /* Port18 */
835 PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1),
836 PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1),
837
838 /* Port19 */
839 PINMUX_DATA(FMSICK_MARK, PORT19_FN1),
840 PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1),
841 PINMUX_DATA(IRQ10_MARK, PORT19_FN0),
842
843 /* Port20 */
844 PINMUX_DATA(FMSOCK_MARK, PORT20_FN1),
845 PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0, MSEL5CR_14_0),
846 PINMUX_DATA(IRQ1_MARK, PORT20_FN0),
847
848 /* Port21 */
849 PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1),
850 PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0),
851 PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4),
852 PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5),
853 PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6),
854 PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7),
855
856 /* Port22 */
857 PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0),
858 PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0),
859 PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1),
860
861 /* Port23 */
862 PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1),
863 PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0),
864 PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4),
865 PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5),
866 PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6),
867 PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7),
868
869 /* Port24 */
870 PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0),
871 PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5),
872 PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6),
873 PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0),
874
875 /* Port25 */
876 PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0),
877 PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5),
878 PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6),
879 PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0),
880
881 /* Port26 */
882 PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0),
883 PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5),
884 PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6),
885
886 /* Port27 - Port39 Function */
887 PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1),
888 PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1),
889 PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1),
890 PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1),
891 PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1),
892 PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1),
893 PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1),
894 PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1),
895 PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1),
896 PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1),
897 PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1),
898 PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1),
899 PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1),
900
901 /* Port38 IRQ */
902 PINMUX_DATA(IRQ25_MARK, PORT38_FN0),
903
904 /* Port40 */
905 PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0),
906 PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6),
907 PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7),
908
909 /* Port41 */
910 PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1),
911 PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2),
912 PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1),
913
914 /* Port42 */
915 PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1),
916 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2),
917 PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1),
918
919 /* Port43 */
920 PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1),
921 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2),
922 PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0),
923 PINMUX_DATA(DV_D15_MARK, PORT43_FN6),
924
925 /* Port44 */
926 PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1),
927 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2),
928 PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0),
929 PINMUX_DATA(DV_D14_MARK, PORT44_FN6),
930
931 /* Port45 */
932 PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1),
933 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2),
934 PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0),
935 PINMUX_DATA(DV_D13_MARK, PORT45_FN6),
936
937 /* Port46 */
938 PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1),
939 PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0),
940 PINMUX_DATA(DV_D12_MARK, PORT46_FN6),
941
942 /* Port47 */
943 PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1),
944 PINMUX_DATA(KEYIN4_MARK, PORT47_FN3),
945 PINMUX_DATA(DV_D11_MARK, PORT47_FN6),
946
947 /* Port48 */
948 PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1),
949 PINMUX_DATA(KEYIN5_MARK, PORT48_FN3),
950 PINMUX_DATA(DV_D10_MARK, PORT48_FN6),
951
952 /* Port49 */
953 PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1),
954 PINMUX_DATA(KEYIN6_MARK, PORT49_FN3),
955 PINMUX_DATA(DV_D9_MARK, PORT49_FN6),
956 PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1),
957
958 /* Port50 */
959 PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1),
960 PINMUX_DATA(KEYIN7_MARK, PORT50_FN3),
961 PINMUX_DATA(DV_D8_MARK, PORT50_FN6),
962 PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1),
963
964 /* Port51 */
965 PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1),
966 PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3),
967 PINMUX_DATA(DV_D7_MARK, PORT51_FN6),
968
969 /* Port52 */
970 PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1),
971 PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3),
972 PINMUX_DATA(DV_D6_MARK, PORT52_FN6),
973
974 /* Port53 */
975 PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1),
976 PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3),
977 PINMUX_DATA(DV_D5_MARK, PORT53_FN6),
978
979 /* Port54 */
980 PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1),
981 PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3),
982 PINMUX_DATA(DV_D4_MARK, PORT54_FN6),
983
984 /* Port55 */
985 PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1),
986 PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3),
987 PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1),
988 PINMUX_DATA(DV_D3_MARK, PORT55_FN6),
989
990 /* Port56 */
991 PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1),
992 PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3),
993 PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1),
994 PINMUX_DATA(DV_D2_MARK, PORT56_FN6),
995 PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1),
996
997 /* Port57 */
998 PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1),
999 PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3),
1000 PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1),
1001 PINMUX_DATA(DV_D1_MARK, PORT57_FN6),
1002 PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1),
1003
1004 /* Port58 */
1005 PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1),
1006 PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3),
1007 PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1),
1008 PINMUX_DATA(DV_D0_MARK, PORT58_FN6),
1009 PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1),
1010
1011 /* Port59 */
1012 PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1),
1013 PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0),
1014 PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6),
1015
1016 /* Port60 */
1017 PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1),
1018 PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0),
1019 PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6),
1020
1021 /* Port61 */
1022 PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1),
1023 PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2),
1024
1025 /* Port62 */
1026 PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1),
1027 PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4),
1028 PINMUX_DATA(DV_CLK_MARK, PORT62_FN6),
1029 PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1),
1030
1031 /* Port63 */
1032 PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1),
1033 PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6),
1034 PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1),
1035
1036 /* Port64 */
1037 PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1),
1038 PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4),
1039 PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6),
1040 PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1),
1041
1042 /* Port65 */
1043 PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1),
1044 PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2),
1045 PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4),
1046
1047 /* Port66 */
1048 PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1),
1049 PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0),
1050 PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0),
1051 PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6),
1052
1053 /* Port67 - Port73 Function1 */
1054 PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1),
1055 PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1),
1056 PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1),
1057 PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1),
1058 PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1),
1059 PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1),
1060 PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1),
1061
1062 /* Port67 - Port73 Function2 */
1063 PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1),
1064 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2),
1065 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2),
1066 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2),
1067 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2),
1068 PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1),
1069 PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1),
1070
1071 /* Port67 - Port73 Function4 */
1072 PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0),
1073 PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0),
1074 PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0),
1075 PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0),
1076 PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0),
1077 PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0),
1078 PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0),
1079
1080 /* Port67 - Port73 Function6 */
1081 PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6),
1082 PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6),
1083 PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6),
1084 PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6),
1085 PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6),
1086 PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6),
1087 PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6),
1088
1089 /* Port67 - Port71 IRQ */
1090 PINMUX_DATA(IRQ20_MARK, PORT67_FN0),
1091 PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0),
1092 PINMUX_DATA(IRQ17_MARK, PORT69_FN0),
1093 PINMUX_DATA(IRQ18_MARK, PORT70_FN0),
1094 PINMUX_DATA(IRQ19_MARK, PORT71_FN0),
1095
1096 /* Port74 */
1097 PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1),
1098 PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1),
1099 PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0),
1100 PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6),
1101 PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7),
1102
1103 /* Port75 */
1104 PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1),
1105 PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1),
1106 PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0),
1107 PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6),
1108 PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7),
1109
1110 /* Port76 - Port80 Function */
1111 PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1),
1112 PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1),
1113 PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1),
1114 PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1),
1115 PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1),
1116
1117 /* Port81 */
1118 PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1),
1119 PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0),
1120
1121 /* Port82 - Port88 Function */
1122 PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1),
1123 PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1),
1124 PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1),
1125 PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1),
1126 PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1),
1127 PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1),
1128 PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1),
1129
1130 /* Port89 */
1131 PINMUX_DATA(DREQ0_MARK, PORT89_FN1),
1132 PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1),
1133 PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6),
1134
1135 /* Port90 */
1136 PINMUX_DATA(DACK0_MARK, PORT90_FN1),
1137 PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1),
1138 PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6),
1139 PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1),
1140
1141 /* Port91 */
1142 PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1),
1143 PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2),
1144 PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1145 PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7),
1146
1147 /* Port92 */
1148 PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1),
1149 PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2),
1150 PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1151 PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6),
1152 PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7),
1153
1154 /* Port93 */
1155 PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1),
1156 PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2),
1157 PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1158 PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6),
1159 PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7),
1160
1161 /* Port94 */
1162 PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1),
1163 PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2),
1164 PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1165 PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6),
1166 PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7),
1167
1168 /* Port95 */
1169 PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0),
1170 PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1),
1171
1172 PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2),
1173 PINMUX_DATA(SIM_RST_MARK, PORT95_FN4),
1174 PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1),
1175 PINMUX_DATA(IRQ22_MARK, PORT95_FN0),
1176
1177 /* Port96 */
1178 PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0),
1179 PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1),
1180
1181 PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2),
1182 PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4),
1183 PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1),
1184 PINMUX_DATA(IRQ23_MARK, PORT96_FN0),
1185
1186 /* Port97 */
1187 PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1),
1188 PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2),
1189 PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6),
1190 PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7),
1191 PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0),
1192
1193 /* Port98 */
1194 PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1),
1195 PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2),
1196 PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7),
1197 PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0),
1198
1199 /* Port99 */
1200 PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1),
1201 PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2),
1202 PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6),
1203 PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7),
1204 PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0),
1205
1206 /* Port100 */
1207 PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1),
1208 PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2),
1209 PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7),
1210 PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0),
1211
1212 /* Port101 */
1213 PINMUX_DATA(FCE0_MARK, PORT101_FN1),
1214
1215 /* Port102 */
1216 PINMUX_DATA(FRB_MARK, PORT102_FN1),
1217 PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0),
1218
1219 /* Port103 */
1220 PINMUX_DATA(CS5B_MARK, PORT103_FN1),
1221 PINMUX_DATA(FCE1_MARK, PORT103_FN2),
1222 PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1),
1223
1224 /* Port104 */
1225 PINMUX_DATA(CS6A_MARK, PORT104_FN1),
1226 PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1),
1227 PINMUX_DATA(IRQ11_MARK, PORT104_FN0),
1228
1229 /* Port105 */
1230 PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0),
1231 PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0),
1232
1233 /* Port106 */
1234 PINMUX_DATA(IOIS16_MARK, PORT106_FN1),
1235 PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6),
1236
1237 /* Port107 - Port115 Function */
1238 PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1),
1239 PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1),
1240 PINMUX_DATA(CS0_MARK, PORT109_FN1),
1241 PINMUX_DATA(CS2_MARK, PORT110_FN1),
1242 PINMUX_DATA(CS4_MARK, PORT111_FN1),
1243 PINMUX_DATA(WE1_MARK, PORT112_FN1),
1244 PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1),
1245 PINMUX_DATA(RDWR_MARK, PORT114_FN1),
1246 PINMUX_DATA(RD_FSC_MARK, PORT115_FN1),
1247
1248 /* Port116 */
1249 PINMUX_DATA(A25_MARK, PORT116_FN1),
1250 PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2),
1251 PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0),
1252 PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0),
1253 PINMUX_DATA(GPO1_MARK, PORT116_FN5),
1254
1255 /* Port117 */
1256 PINMUX_DATA(A24_MARK, PORT117_FN1),
1257 PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2),
1258 PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0),
1259 PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0),
1260 PINMUX_DATA(GPO0_MARK, PORT117_FN5),
1261
1262 /* Port118 */
1263 PINMUX_DATA(A23_MARK, PORT118_FN1),
1264 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2),
1265 PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0),
1266 PINMUX_DATA(GPI1_MARK, PORT118_FN5),
1267 PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0),
1268
1269 /* Port119 */
1270 PINMUX_DATA(A22_MARK, PORT119_FN1),
1271 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2),
1272 PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0),
1273 PINMUX_DATA(GPI0_MARK, PORT119_FN5),
1274 PINMUX_DATA(IRQ8_MARK, PORT119_FN0),
1275
1276 /* Port120 */
1277 PINMUX_DATA(A21_MARK, PORT120_FN1),
1278 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2),
1279 PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0),
1280 PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_1),
1281
1282 /* Port121 */
1283 PINMUX_DATA(A20_MARK, PORT121_FN1),
1284 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2),
1285 PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0),
1286 PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0),
1287
1288 /* Port122 */
1289 PINMUX_DATA(A19_MARK, PORT122_FN1),
1290 PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2),
1291
1292 /* Port123 */
1293 PINMUX_DATA(A18_MARK, PORT123_FN1),
1294 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2),
1295
1296 /* Port124 */
1297 PINMUX_DATA(A17_MARK, PORT124_FN1),
1298 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2),
1299
1300 /* Port125 - Port141 Function */
1301 PINMUX_DATA(A16_MARK, PORT125_FN1),
1302 PINMUX_DATA(A15_MARK, PORT126_FN1),
1303 PINMUX_DATA(A14_MARK, PORT127_FN1),
1304 PINMUX_DATA(A13_MARK, PORT128_FN1),
1305 PINMUX_DATA(A12_MARK, PORT129_FN1),
1306 PINMUX_DATA(A11_MARK, PORT130_FN1),
1307 PINMUX_DATA(A10_MARK, PORT131_FN1),
1308 PINMUX_DATA(A9_MARK, PORT132_FN1),
1309 PINMUX_DATA(A8_MARK, PORT133_FN1),
1310 PINMUX_DATA(A7_MARK, PORT134_FN1),
1311 PINMUX_DATA(A6_MARK, PORT135_FN1),
1312 PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1),
1313 PINMUX_DATA(A4_FOE_MARK, PORT137_FN1),
1314 PINMUX_DATA(A3_MARK, PORT138_FN1),
1315 PINMUX_DATA(A2_MARK, PORT139_FN1),
1316 PINMUX_DATA(A1_MARK, PORT140_FN1),
1317 PINMUX_DATA(CKO_MARK, PORT141_FN1),
1318
1319 /* Port142 - Port157 Function1 */
1320 PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1),
1321 PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1),
1322 PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1),
1323 PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1),
1324 PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1),
1325 PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1),
1326 PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1),
1327 PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1),
1328 PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1),
1329 PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1),
1330 PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1),
1331 PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1),
1332 PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1),
1333 PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1),
1334 PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1),
1335 PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1),
1336
1337 /* Port142 - Port149 Function3 */
1338 PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1),
1339 PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1),
1340 PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1),
1341 PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1),
1342 PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1),
1343 PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1),
1344 PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1),
1345 PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1),
1346
1347 /* Port158 */
1348 PINMUX_DATA(D31_MARK, PORT158_FN1),
1349 PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1),
1350 PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3),
1351 PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1),
1352 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5),
1353 PINMUX_DATA(IDE_D15_MARK, PORT158_FN6),
1354
1355 /* Port159 */
1356 PINMUX_DATA(D30_MARK, PORT159_FN1),
1357 PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1),
1358 PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3),
1359 PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1),
1360 PINMUX_DATA(IDE_D14_MARK, PORT159_FN6),
1361
1362 /* Port160 */
1363 PINMUX_DATA(D29_MARK, PORT160_FN1),
1364 PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1),
1365 PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1),
1366 PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5),
1367 PINMUX_DATA(IDE_D13_MARK, PORT160_FN6),
1368
1369 /* Port161 */
1370 PINMUX_DATA(D28_MARK, PORT161_FN1),
1371 PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1),
1372 PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3),
1373 PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1),
1374 PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5),
1375 PINMUX_DATA(IDE_D12_MARK, PORT161_FN6),
1376
1377 /* Port162 */
1378 PINMUX_DATA(D27_MARK, PORT162_FN1),
1379 PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1),
1380 PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1),
1381 PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5),
1382 PINMUX_DATA(IDE_D11_MARK, PORT162_FN6),
1383
1384 /* Port163 */
1385 PINMUX_DATA(D26_MARK, PORT163_FN1),
1386 PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2),
1387 PINMUX_DATA(ET_COL_MARK, PORT163_FN3),
1388 PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1),
1389 PINMUX_DATA(IROUT_MARK, PORT163_FN5),
1390 PINMUX_DATA(IDE_D10_MARK, PORT163_FN6),
1391
1392 /* Port164 */
1393 PINMUX_DATA(D25_MARK, PORT164_FN1),
1394 PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2),
1395 PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3),
1396 PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4),
1397 PINMUX_DATA(IDE_D9_MARK, PORT164_FN6),
1398
1399 /* Port165 */
1400 PINMUX_DATA(D24_MARK, PORT165_FN1),
1401 PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2),
1402 PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1),
1403 PINMUX_DATA(IDE_D8_MARK, PORT165_FN6),
1404
1405 /* Port166 - Port171 Function1 */
1406 PINMUX_DATA(D21_MARK, PORT166_FN1),
1407 PINMUX_DATA(D20_MARK, PORT167_FN1),
1408 PINMUX_DATA(D19_MARK, PORT168_FN1),
1409 PINMUX_DATA(D18_MARK, PORT169_FN1),
1410 PINMUX_DATA(D17_MARK, PORT170_FN1),
1411 PINMUX_DATA(D16_MARK, PORT171_FN1),
1412
1413 /* Port166 - Port171 Function3 */
1414 PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3),
1415 PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3),
1416 PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3),
1417 PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3),
1418 PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3),
1419 PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3),
1420
1421 /* Port166 - Port171 Function6 */
1422 PINMUX_DATA(IDE_D5_MARK, PORT166_FN6),
1423 PINMUX_DATA(IDE_D4_MARK, PORT167_FN6),
1424 PINMUX_DATA(IDE_D3_MARK, PORT168_FN6),
1425 PINMUX_DATA(IDE_D2_MARK, PORT169_FN6),
1426 PINMUX_DATA(IDE_D1_MARK, PORT170_FN6),
1427 PINMUX_DATA(IDE_D0_MARK, PORT171_FN6),
1428
1429 /* Port167 - Port171 IRQ */
1430 PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0),
1431 PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0),
1432 PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0),
1433 PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0),
1434 PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0),
1435
1436 /* Port172 */
1437 PINMUX_DATA(D23_MARK, PORT172_FN1),
1438 PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1),
1439 PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3),
1440 PINMUX_DATA(IDE_D7_MARK, PORT172_FN6),
1441 PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1),
1442
1443 /* Port173 */
1444 PINMUX_DATA(D22_MARK, PORT173_FN1),
1445 PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1),
1446 PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3),
1447 PINMUX_DATA(IDE_D6_MARK, PORT173_FN6),
1448 PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1),
1449
1450 /* Port174 */
1451 PINMUX_DATA(A26_MARK, PORT174_FN1),
1452 PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2),
1453 PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3),
1454 PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0),
1455
1456 /* Port175 */
1457 PINMUX_DATA(A0_MARK, PORT175_FN1),
1458 PINMUX_DATA(BS_MARK, PORT175_FN2),
1459 PINMUX_DATA(ET_WOL_MARK, PORT175_FN3),
1460 PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0),
1461
1462 /* Port176 */
1463 PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3),
1464
1465 /* Port177 */
1466 PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0),
1467 PINMUX_DATA(ET_LINK_MARK, PORT177_FN3),
1468 PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6),
1469 PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1),
1470
1471 /* Port178 */
1472 PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1),
1473 PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5),
1474 PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6),
1475
1476 /* Port179 */
1477 PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1),
1478 PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5),
1479 PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6),
1480
1481 /* Port180 */
1482 PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1),
1483 PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4),
1484 PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5),
1485 PINMUX_DATA(IDE_INT_MARK, PORT180_FN6),
1486 PINMUX_DATA(IRQ24_MARK, PORT180_FN0),
1487
1488 /* Port181 */
1489 PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1),
1490 PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5),
1491 PINMUX_DATA(IDE_RST_MARK, PORT181_FN6),
1492
1493 /* Port182 */
1494 PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1),
1495 PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5),
1496 PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6),
1497
1498 /* Port183 */
1499 PINMUX_DATA(DREQ1_MARK, PORT183_FN1),
1500 PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1),
1501 PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3),
1502
1503 /* Port184 */
1504 PINMUX_DATA(DACK1_MARK, PORT184_FN1),
1505 PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1),
1506 PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3),
1507
1508 /* Port185 - Port192 Function1 */
1509 PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1),
1510 PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0),
1511 PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0),
1512 PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1),
1513 PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0),
1514 PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0),
1515 PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0),
1516
1517 /* Port185 - Port192 Function3 */
1518 PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3),
1519 PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3),
1520 PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3),
1521 PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3),
1522 PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3),
1523 PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3),
1524 PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3),
1525 PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3),
1526
1527 /* Port185 - Port192 Function6 */
1528 PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6),
1529 PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0),
1530 PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0),
1531 PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6),
1532 PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6),
1533 PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6),
1534 PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6),
1535 PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6),
1536
1537 /* Port193 */
1538 PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1),
1539 PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3),
1540 PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1), /* ? */
1541 PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7),
1542
1543 /* Port194 */
1544 PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1),
1545 PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3),
1546 PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1), /* ? */
1547 PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7),
1548
1549 /* Port195 */
1550 PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1),
1551 PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3),
1552 PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6),
1553 PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7),
1554
1555 /* Port196 */
1556 PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1),
1557 PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3),
1558 PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6),
1559 PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7),
1560
1561 /* Port197 */
1562 PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1),
1563 PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5),
1564 PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6),
1565 PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7),
1566
1567 /* Port198 */
1568 PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1),
1569 PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5),
1570 PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6),
1571 PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7),
1572
1573 /* Port199 */
1574 PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1),
1575 PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1),
1576 PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3),
1577 PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1),
1578 PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6),
1579 PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7),
1580
1581 /* Port200 */
1582 PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1),
1583 PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2),
1584 PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3),
1585 PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6),
1586 PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7),
1587
1588 /* Port201 */
1589 PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0),
1590 PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1),
1591
1592 PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2),
1593 PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3),
1594 PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6),
1595 PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7),
1596
1597 /* Port202 */
1598 PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0),
1599 PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1),
1600
1601 PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1),
1602 PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3),
1603 PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1),
1604 PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6),
1605 PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1),
1606 PINMUX_DATA(IRQ21_MARK, PORT202_FN0),
1607
1608 /* Port203 - Port208 Function1 */
1609 PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1),
1610 PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1),
1611 PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1),
1612 PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1),
1613 PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1),
1614 PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1),
1615
1616 /* Port203 - Port208 Function3 */
1617 PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3),
1618 PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3),
1619 PINMUX_DATA(ET_CRS_MARK, PORT205_FN3),
1620 PINMUX_DATA(ET_MDC_MARK, PORT206_FN3),
1621 PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3),
1622 PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3),
1623
1624 /* Port203 - Port208 Function6 */
1625 PINMUX_DATA(IDE_A2_MARK, PORT203_FN6),
1626 PINMUX_DATA(IDE_A1_MARK, PORT204_FN6),
1627 PINMUX_DATA(IDE_A0_MARK, PORT205_FN6),
1628 PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6),
1629 PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6),
1630 PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6),
1631
1632 /* Port203 - Port208 Function7 */
1633 PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1634 PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1635 PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1),
1636 PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1),
1637 PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1638 PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1639
1640 /* Port209 */
1641 PINMUX_DATA(VBUS_MARK, PORT209_FN1),
1642 PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_0),
1643
1644 /* Port210 */
1645 PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1),
1646 PINMUX_DATA(HDMI_HPD_MARK, PORT210_FN1),
1647
1648 /* Port211 */
1649 PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
1650 PINMUX_DATA(HDMI_CEC_MARK, PORT211_FN1),
1651
1652 /* LCDC select */
1653 PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0),
1654 PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1),
1655
1656 /* SDENC */
1657 PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
1658 PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
1659
1660 /* SYSC */
1661 PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0),
1662 PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1),
1663
1664 /* DEBUG */
1665 PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0),
1666 PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1),
1667
1668 PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0),
1669 PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1),
1670 PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
1671};
1672
Laurent Pincharta3db40a62013-01-02 14:53:37 +0100[diff] [blame]1673static struct sh_pfc_pin pinmux_pins[] = {
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]1674 GPIO_PORT_ALL(),
Laurent Pincharta373ed02012-11-29 13:24:07 +0100[diff] [blame]1675};
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]1676
Laurent Pinchartb7099c42013-04-18 01:04:30 +0200[diff] [blame^]1677/* - BSC -------------------------------------------------------------------- */
1678static const unsigned int bsc_data8_pins[] = {
1679 /* D[0:7] */
1680 157, 156, 155, 154, 153, 152, 151, 150,
1681};
1682static const unsigned int bsc_data8_mux[] = {
1683 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1684 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1685};
1686static const unsigned int bsc_data16_pins[] = {
1687 /* D[0:15] */
1688 157, 156, 155, 154, 153, 152, 151, 150,
1689 149, 148, 147, 146, 145, 144, 143, 142,
1690};
1691static const unsigned int bsc_data16_mux[] = {
1692 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1693 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1694 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1695 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1696};
1697static const unsigned int bsc_data32_pins[] = {
1698 /* D[0:31] */
1699 157, 156, 155, 154, 153, 152, 151, 150,
1700 149, 148, 147, 146, 145, 144, 143, 142,
1701 171, 170, 169, 168, 167, 166, 173, 172,
1702 165, 164, 163, 162, 161, 160, 159, 158,
1703};
1704static const unsigned int bsc_data32_mux[] = {
1705 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1706 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1707 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1708 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1709 D16_MARK, D17_MARK, D18_MARK, D19_MARK,
1710 D20_MARK, D21_MARK, D22_MARK, D23_MARK,
1711 D24_MARK, D25_MARK, D26_MARK, D27_MARK,
1712 D28_MARK, D29_MARK, D30_MARK, D31_MARK,
1713};
1714static const unsigned int bsc_cs0_pins[] = {
1715 /* CS */
1716 109,
1717};
1718static const unsigned int bsc_cs0_mux[] = {
1719 CS0_MARK,
1720};
1721static const unsigned int bsc_cs2_pins[] = {
1722 /* CS */
1723 110,
1724};
1725static const unsigned int bsc_cs2_mux[] = {
1726 CS2_MARK,
1727};
1728static const unsigned int bsc_cs4_pins[] = {
1729 /* CS */
1730 111,
1731};
1732static const unsigned int bsc_cs4_mux[] = {
1733 CS4_MARK,
1734};
1735static const unsigned int bsc_cs5a_0_pins[] = {
1736 /* CS */
1737 105,
1738};
1739static const unsigned int bsc_cs5a_0_mux[] = {
1740 CS5A_PORT105_MARK,
1741};
1742static const unsigned int bsc_cs5a_1_pins[] = {
1743 /* CS */
1744 19,
1745};
1746static const unsigned int bsc_cs5a_1_mux[] = {
1747 CS5A_PORT19_MARK,
1748};
1749static const unsigned int bsc_cs5b_pins[] = {
1750 /* CS */
1751 103,
1752};
1753static const unsigned int bsc_cs5b_mux[] = {
1754 CS5B_MARK,
1755};
1756static const unsigned int bsc_cs6a_pins[] = {
1757 /* CS */
1758 104,
1759};
1760static const unsigned int bsc_cs6a_mux[] = {
1761 CS6A_MARK,
1762};
1763static const unsigned int bsc_rd_we8_pins[] = {
1764 /* RD, WE[0] */
1765 115, 113,
1766};
1767static const unsigned int bsc_rd_we8_mux[] = {
1768 RD_FSC_MARK, WE0_FWE_MARK,
1769};
1770static const unsigned int bsc_rd_we16_pins[] = {
1771 /* RD, WE[0:1] */
1772 115, 113, 112,
1773};
1774static const unsigned int bsc_rd_we16_mux[] = {
1775 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
1776};
1777static const unsigned int bsc_rd_we32_pins[] = {
1778 /* RD, WE[0:3] */
1779 115, 113, 112, 108, 107,
1780};
1781static const unsigned int bsc_rd_we32_mux[] = {
1782 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
1783};
1784static const unsigned int bsc_bs_pins[] = {
1785 /* BS */
1786 175,
1787};
1788static const unsigned int bsc_bs_mux[] = {
1789 BS_MARK,
1790};
1791static const unsigned int bsc_rdwr_pins[] = {
1792 /* RDWR */
1793 114,
1794};
1795static const unsigned int bsc_rdwr_mux[] = {
1796 RDWR_MARK,
1797};
Bastian Hecht09bbc1f2013-04-09 10:48:50 +0000[diff] [blame]1798/* - INTC ------------------------------------------------------------------- */
1799IRQC_PINS_MUX(0, 0, 2);
1800IRQC_PINS_MUX(0, 1, 13);
1801IRQC_PIN_MUX(1, 20);
1802IRQC_PINS_MUX(2, 0, 11);
1803IRQC_PINS_MUX(2, 1, 12);
1804IRQC_PINS_MUX(3, 0, 10);
1805IRQC_PINS_MUX(3, 1, 14);
1806IRQC_PINS_MUX(4, 0, 15);
1807IRQC_PINS_MUX(4, 1, 172);
1808IRQC_PINS_MUX(5, 0, 0);
1809IRQC_PINS_MUX(5, 1, 1);
1810IRQC_PINS_MUX(6, 0, 121);
1811IRQC_PINS_MUX(6, 1, 173);
1812IRQC_PINS_MUX(7, 0, 120);
1813IRQC_PINS_MUX(7, 1, 209);
1814IRQC_PIN_MUX(8, 119);
1815IRQC_PINS_MUX(9, 0, 118);
1816IRQC_PINS_MUX(9, 1, 210);
1817IRQC_PIN_MUX(10, 19);
1818IRQC_PIN_MUX(11, 104);
1819IRQC_PINS_MUX(12, 0, 42);
1820IRQC_PINS_MUX(12, 1, 97);
1821IRQC_PINS_MUX(13, 0, 64);
1822IRQC_PINS_MUX(13, 1, 98);
1823IRQC_PINS_MUX(14, 0, 63);
1824IRQC_PINS_MUX(14, 1, 99);
1825IRQC_PINS_MUX(15, 0, 62);
1826IRQC_PINS_MUX(15, 1, 100);
1827IRQC_PINS_MUX(16, 0, 68);
1828IRQC_PINS_MUX(16, 1, 211);
1829IRQC_PIN_MUX(17, 69);
1830IRQC_PIN_MUX(18, 70);
1831IRQC_PIN_MUX(19, 71);
1832IRQC_PIN_MUX(20, 67);
1833IRQC_PIN_MUX(21, 202);
1834IRQC_PIN_MUX(22, 95);
1835IRQC_PIN_MUX(23, 96);
1836IRQC_PIN_MUX(24, 180);
1837IRQC_PIN_MUX(25, 38);
1838IRQC_PINS_MUX(26, 0, 58);
1839IRQC_PINS_MUX(26, 1, 81);
1840IRQC_PINS_MUX(27, 0, 57);
1841IRQC_PINS_MUX(27, 1, 168);
1842IRQC_PINS_MUX(28, 0, 56);
1843IRQC_PINS_MUX(28, 1, 169);
1844IRQC_PINS_MUX(29, 0, 50);
1845IRQC_PINS_MUX(29, 1, 170);
1846IRQC_PINS_MUX(30, 0, 49);
1847IRQC_PINS_MUX(30, 1, 171);
1848IRQC_PINS_MUX(31, 0, 41);
1849IRQC_PINS_MUX(31, 1, 167);
1850
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]1851/* - LCD0 ------------------------------------------------------------------- */
1852static const unsigned int lcd0_data8_pins[] = {
1853 /* D[0:7] */
1854 58, 57, 56, 55, 54, 53, 52, 51,
1855};
1856static const unsigned int lcd0_data8_mux[] = {
1857 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1858 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1859};
1860static const unsigned int lcd0_data9_pins[] = {
1861 /* D[0:8] */
1862 58, 57, 56, 55, 54, 53, 52, 51,
1863 50,
1864};
1865static const unsigned int lcd0_data9_mux[] = {
1866 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1867 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1868 LCD0_D8_MARK,
1869};
1870static const unsigned int lcd0_data12_pins[] = {
1871 /* D[0:11] */
1872 58, 57, 56, 55, 54, 53, 52, 51,
1873 50, 49, 48, 47,
1874};
1875static const unsigned int lcd0_data12_mux[] = {
1876 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1877 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1878 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
1879};
1880static const unsigned int lcd0_data16_pins[] = {
1881 /* D[0:15] */
1882 58, 57, 56, 55, 54, 53, 52, 51,
1883 50, 49, 48, 47, 46, 45, 44, 43,
1884};
1885static const unsigned int lcd0_data16_mux[] = {
1886 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1887 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1888 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
1889 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
1890};
1891static const unsigned int lcd0_data18_pins[] = {
1892 /* D[0:17] */
1893 58, 57, 56, 55, 54, 53, 52, 51,
1894 50, 49, 48, 47, 46, 45, 44, 43,
1895 42, 41,
1896};
1897static const unsigned int lcd0_data18_mux[] = {
1898 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1899 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1900 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
1901 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
1902 LCD0_D16_MARK, LCD0_D17_MARK,
1903};
1904static const unsigned int lcd0_data24_0_pins[] = {
1905 /* D[0:23] */
1906 58, 57, 56, 55, 54, 53, 52, 51,
1907 50, 49, 48, 47, 46, 45, 44, 43,
1908 42, 41, 40, 4, 3, 2, 0, 1,
1909};
1910static const unsigned int lcd0_data24_0_mux[] = {
1911 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1912 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1913 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
1914 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
1915 LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK,
1916 LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK,
1917 LCD0_D23_PORT1_MARK,
1918};
1919static const unsigned int lcd0_data24_1_pins[] = {
1920 /* D[0:23] */
1921 58, 57, 56, 55, 54, 53, 52, 51,
1922 50, 49, 48, 47, 46, 45, 44, 43,
1923 42, 41, 163, 162, 161, 158, 160, 159,
1924};
1925static const unsigned int lcd0_data24_1_mux[] = {
1926 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1927 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1928 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
1929 LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
1930 LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
1931 LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,
1932};
1933static const unsigned int lcd0_display_pins[] = {
1934 /* DON, VCPWC, VEPWC */
1935 61, 59, 60,
1936};
1937static const unsigned int lcd0_display_mux[] = {
1938 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
1939};
1940static const unsigned int lcd0_lclk_0_pins[] = {
1941 /* LCLK */
1942 102,
1943};
1944static const unsigned int lcd0_lclk_0_mux[] = {
1945 LCD0_LCLK_PORT102_MARK,
1946};
1947static const unsigned int lcd0_lclk_1_pins[] = {
1948 /* LCLK */
1949 165,
1950};
1951static const unsigned int lcd0_lclk_1_mux[] = {
1952 LCD0_LCLK_PORT165_MARK,
1953};
1954static const unsigned int lcd0_sync_pins[] = {
1955 /* VSYN, HSYN, DCK, DISP */
1956 63, 64, 62, 65,
1957};
1958static const unsigned int lcd0_sync_mux[] = {
1959 LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK,
1960};
1961static const unsigned int lcd0_sys_pins[] = {
1962 /* CS, WR, RD, RS */
1963 64, 62, 164, 65,
1964};
1965static const unsigned int lcd0_sys_mux[] = {
1966 LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
1967};
1968/* - LCD1 ------------------------------------------------------------------- */
1969static const unsigned int lcd1_data8_pins[] = {
1970 /* D[0:7] */
1971 4, 3, 2, 1, 0, 91, 92, 23,
1972};
1973static const unsigned int lcd1_data8_mux[] = {
1974 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
1975 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
1976};
1977static const unsigned int lcd1_data9_pins[] = {
1978 /* D[0:8] */
1979 4, 3, 2, 1, 0, 91, 92, 23,
1980 93,
1981};
1982static const unsigned int lcd1_data9_mux[] = {
1983 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
1984 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
1985 LCD1_D8_MARK,
1986};
1987static const unsigned int lcd1_data12_pins[] = {
1988 /* D[0:12] */
1989 4, 3, 2, 1, 0, 91, 92, 23,
1990 93, 94, 21, 201,
1991};
1992static const unsigned int lcd1_data12_mux[] = {
1993 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
1994 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
1995 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
1996};
1997static const unsigned int lcd1_data16_pins[] = {
1998 /* D[0:15] */
1999 4, 3, 2, 1, 0, 91, 92, 23,
2000 93, 94, 21, 201, 200, 199, 196, 195,
2001};
2002static const unsigned int lcd1_data16_mux[] = {
2003 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2004 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2005 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2006 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2007};
2008static const unsigned int lcd1_data18_pins[] = {
2009 /* D[0:17] */
2010 4, 3, 2, 1, 0, 91, 92, 23,
2011 93, 94, 21, 201, 200, 199, 196, 195,
2012 194, 193,
2013};
2014static const unsigned int lcd1_data18_mux[] = {
2015 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2016 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2017 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2018 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2019 LCD1_D16_MARK, LCD1_D17_MARK,
2020};
2021static const unsigned int lcd1_data24_pins[] = {
2022 /* D[0:23] */
2023 4, 3, 2, 1, 0, 91, 92, 23,
2024 93, 94, 21, 201, 200, 199, 196, 195,
2025 194, 193, 198, 197, 75, 74, 15, 14,
2026};
2027static const unsigned int lcd1_data24_mux[] = {
2028 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2029 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2030 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2031 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2032 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
2033 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
2034};
2035static const unsigned int lcd1_display_pins[] = {
2036 /* DON, VCPWC, VEPWC */
2037 100, 5, 6,
2038};
2039static const unsigned int lcd1_display_mux[] = {
2040 LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK,
2041};
2042static const unsigned int lcd1_lclk_pins[] = {
2043 /* LCLK */
2044 40,
2045};
2046static const unsigned int lcd1_lclk_mux[] = {
2047 LCD1_LCLK_MARK,
2048};
2049static const unsigned int lcd1_sync_pins[] = {
2050 /* VSYN, HSYN, DCK, DISP */
2051 98, 97, 99, 12,
2052};
2053static const unsigned int lcd1_sync_mux[] = {
2054 LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK,
2055};
2056static const unsigned int lcd1_sys_pins[] = {
2057 /* CS, WR, RD, RS */
2058 97, 99, 13, 12,
2059};
2060static const unsigned int lcd1_sys_mux[] = {
2061 LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
2062};
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]2063/* - MMCIF ------------------------------------------------------------------ */
2064static const unsigned int mmc0_data1_0_pins[] = {
2065 /* D[0] */
2066 68,
2067};
2068static const unsigned int mmc0_data1_0_mux[] = {
2069 MMC0_D0_PORT68_MARK,
2070};
2071static const unsigned int mmc0_data4_0_pins[] = {
2072 /* D[0:3] */
2073 68, 69, 70, 71,
2074};
2075static const unsigned int mmc0_data4_0_mux[] = {
2076 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
2077};
2078static const unsigned int mmc0_data8_0_pins[] = {
2079 /* D[0:7] */
2080 68, 69, 70, 71, 72, 73, 74, 75,
2081};
2082static const unsigned int mmc0_data8_0_mux[] = {
2083 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
2084 MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
2085};
2086static const unsigned int mmc0_ctrl_0_pins[] = {
2087 /* CMD, CLK */
2088 67, 66,
2089};
2090static const unsigned int mmc0_ctrl_0_mux[] = {
2091 MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
2092};
2093
2094static const unsigned int mmc0_data1_1_pins[] = {
2095 /* D[0] */
2096 149,
2097};
2098static const unsigned int mmc0_data1_1_mux[] = {
2099 MMC1_D0_PORT149_MARK,
2100};
2101static const unsigned int mmc0_data4_1_pins[] = {
2102 /* D[0:3] */
2103 149, 148, 147, 146,
2104};
2105static const unsigned int mmc0_data4_1_mux[] = {
2106 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
2107};
2108static const unsigned int mmc0_data8_1_pins[] = {
2109 /* D[0:7] */
2110 149, 148, 147, 146, 145, 144, 143, 142,
2111};
2112static const unsigned int mmc0_data8_1_mux[] = {
2113 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
2114 MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
2115};
2116static const unsigned int mmc0_ctrl_1_pins[] = {
2117 /* CMD, CLK */
2118 104, 103,
2119};
2120static const unsigned int mmc0_ctrl_1_mux[] = {
2121 MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
2122};
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]2123/* - SCIFA0 ----------------------------------------------------------------- */
2124static const unsigned int scifa0_data_pins[] = {
2125 /* RXD, TXD */
2126 197, 198,
2127};
2128static const unsigned int scifa0_data_mux[] = {
2129 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2130};
2131static const unsigned int scifa0_clk_pins[] = {
2132 /* SCK */
2133 188,
2134};
2135static const unsigned int scifa0_clk_mux[] = {
2136 SCIFA0_SCK_MARK,
2137};
2138static const unsigned int scifa0_ctrl_pins[] = {
2139 /* RTS, CTS */
2140 194, 193,
2141};
2142static const unsigned int scifa0_ctrl_mux[] = {
2143 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
2144};
Bastian Hecht8fbfdbb2013-04-17 10:34:01 +0000[diff] [blame]2145/* - SCIFA1 ----------------------------------------------------------------- */
2146static const unsigned int scifa1_data_pins[] = {
2147 /* RXD, TXD */
2148 195, 196,
2149};
2150static const unsigned int scifa1_data_mux[] = {
2151 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2152};
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]2153static const unsigned int scifa1_clk_pins[] = {
2154 /* SCK */
2155 185,
2156};
2157static const unsigned int scifa1_clk_mux[] = {
2158 SCIFA1_SCK_MARK,
2159};
2160static const unsigned int scifa1_ctrl_pins[] = {
2161 /* RTS, CTS */
2162 23, 21,
2163};
2164static const unsigned int scifa1_ctrl_mux[] = {
2165 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
2166};
2167/* - SCIFA2 ----------------------------------------------------------------- */
2168static const unsigned int scifa2_data_pins[] = {
2169 /* RXD, TXD */
2170 200, 201,
2171};
2172static const unsigned int scifa2_data_mux[] = {
2173 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2174};
2175static const unsigned int scifa2_clk_0_pins[] = {
2176 /* SCK */
2177 22,
2178};
2179static const unsigned int scifa2_clk_0_mux[] = {
2180 SCIFA2_SCK_PORT22_MARK,
2181};
2182static const unsigned int scifa2_clk_1_pins[] = {
2183 /* SCK */
2184 199,
2185};
2186static const unsigned int scifa2_clk_1_mux[] = {
2187 SCIFA2_SCK_PORT199_MARK,
2188};
2189static const unsigned int scifa2_ctrl_pins[] = {
2190 /* RTS, CTS */
2191 96, 95,
2192};
2193static const unsigned int scifa2_ctrl_mux[] = {
2194 SCIFA2_RTS_MARK, SCIFA2_CTS_MARK,
2195};
2196/* - SCIFA3 ----------------------------------------------------------------- */
2197static const unsigned int scifa3_data_0_pins[] = {
2198 /* RXD, TXD */
2199 174, 175,
2200};
2201static const unsigned int scifa3_data_0_mux[] = {
2202 SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK,
2203};
2204static const unsigned int scifa3_clk_0_pins[] = {
2205 /* SCK */
2206 116,
2207};
2208static const unsigned int scifa3_clk_0_mux[] = {
2209 SCIFA3_SCK_PORT116_MARK,
2210};
2211static const unsigned int scifa3_ctrl_0_pins[] = {
2212 /* RTS, CTS */
2213 105, 117,
2214};
2215static const unsigned int scifa3_ctrl_0_mux[] = {
2216 SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK,
2217};
2218static const unsigned int scifa3_data_1_pins[] = {
2219 /* RXD, TXD */
2220 159, 160,
2221};
2222static const unsigned int scifa3_data_1_mux[] = {
2223 SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK,
2224};
2225static const unsigned int scifa3_clk_1_pins[] = {
2226 /* SCK */
2227 158,
2228};
2229static const unsigned int scifa3_clk_1_mux[] = {
2230 SCIFA3_SCK_PORT158_MARK,
2231};
2232static const unsigned int scifa3_ctrl_1_pins[] = {
2233 /* RTS, CTS */
2234 161, 162,
2235};
2236static const unsigned int scifa3_ctrl_1_mux[] = {
2237 SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK,
2238};
2239/* - SCIFA4 ----------------------------------------------------------------- */
2240static const unsigned int scifa4_data_0_pins[] = {
2241 /* RXD, TXD */
2242 12, 13,
2243};
2244static const unsigned int scifa4_data_0_mux[] = {
2245 SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK,
2246};
2247static const unsigned int scifa4_data_1_pins[] = {
2248 /* RXD, TXD */
2249 204, 203,
2250};
2251static const unsigned int scifa4_data_1_mux[] = {
2252 SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK,
2253};
2254static const unsigned int scifa4_data_2_pins[] = {
2255 /* RXD, TXD */
2256 94, 93,
2257};
2258static const unsigned int scifa4_data_2_mux[] = {
2259 SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK,
2260};
2261static const unsigned int scifa4_clk_0_pins[] = {
2262 /* SCK */
2263 21,
2264};
2265static const unsigned int scifa4_clk_0_mux[] = {
2266 SCIFA4_SCK_PORT21_MARK,
2267};
2268static const unsigned int scifa4_clk_1_pins[] = {
2269 /* SCK */
2270 205,
2271};
2272static const unsigned int scifa4_clk_1_mux[] = {
2273 SCIFA4_SCK_PORT205_MARK,
2274};
2275/* - SCIFA5 ----------------------------------------------------------------- */
2276static const unsigned int scifa5_data_0_pins[] = {
2277 /* RXD, TXD */
2278 10, 20,
2279};
2280static const unsigned int scifa5_data_0_mux[] = {
2281 SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK,
2282};
2283static const unsigned int scifa5_data_1_pins[] = {
2284 /* RXD, TXD */
2285 207, 208,
2286};
2287static const unsigned int scifa5_data_1_mux[] = {
2288 SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK,
2289};
2290static const unsigned int scifa5_data_2_pins[] = {
2291 /* RXD, TXD */
2292 92, 91,
2293};
2294static const unsigned int scifa5_data_2_mux[] = {
2295 SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK,
2296};
2297static const unsigned int scifa5_clk_0_pins[] = {
2298 /* SCK */
2299 23,
2300};
2301static const unsigned int scifa5_clk_0_mux[] = {
2302 SCIFA5_SCK_PORT23_MARK,
2303};
2304static const unsigned int scifa5_clk_1_pins[] = {
2305 /* SCK */
2306 206,
2307};
2308static const unsigned int scifa5_clk_1_mux[] = {
2309 SCIFA5_SCK_PORT206_MARK,
2310};
2311/* - SCIFA6 ----------------------------------------------------------------- */
2312static const unsigned int scifa6_data_pins[] = {
2313 /* RXD, TXD */
2314 25, 26,
2315};
2316static const unsigned int scifa6_data_mux[] = {
2317 SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
2318};
2319static const unsigned int scifa6_clk_pins[] = {
2320 /* SCK */
2321 24,
2322};
2323static const unsigned int scifa6_clk_mux[] = {
2324 SCIFA6_SCK_MARK,
2325};
2326/* - SCIFA7 ----------------------------------------------------------------- */
2327static const unsigned int scifa7_data_pins[] = {
2328 /* RXD, TXD */
2329 0, 1,
2330};
2331static const unsigned int scifa7_data_mux[] = {
2332 SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2333};
2334/* - SCIFB ------------------------------------------------------------------ */
2335static const unsigned int scifb_data_0_pins[] = {
2336 /* RXD, TXD */
2337 191, 192,
2338};
2339static const unsigned int scifb_data_0_mux[] = {
2340 SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK,
2341};
2342static const unsigned int scifb_clk_0_pins[] = {
2343 /* SCK */
2344 190,
2345};
2346static const unsigned int scifb_clk_0_mux[] = {
2347 SCIFB_SCK_PORT190_MARK,
2348};
2349static const unsigned int scifb_ctrl_0_pins[] = {
2350 /* RTS, CTS */
2351 186, 187,
2352};
2353static const unsigned int scifb_ctrl_0_mux[] = {
2354 SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK,
2355};
2356static const unsigned int scifb_data_1_pins[] = {
2357 /* RXD, TXD */
2358 3, 4,
2359};
2360static const unsigned int scifb_data_1_mux[] = {
2361 SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK,
2362};
2363static const unsigned int scifb_clk_1_pins[] = {
2364 /* SCK */
2365 2,
2366};
2367static const unsigned int scifb_clk_1_mux[] = {
2368 SCIFB_SCK_PORT2_MARK,
2369};
2370static const unsigned int scifb_ctrl_1_pins[] = {
2371 /* RTS, CTS */
2372 172, 173,
2373};
2374static const unsigned int scifb_ctrl_1_mux[] = {
2375 SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
2376};
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]2377/* - SDHI0 ------------------------------------------------------------------ */
2378static const unsigned int sdhi0_data1_pins[] = {
2379 /* D0 */
2380 77,
2381};
2382static const unsigned int sdhi0_data1_mux[] = {
2383 SDHI0_D0_MARK,
2384};
2385static const unsigned int sdhi0_data4_pins[] = {
2386 /* D[0:3] */
2387 77, 78, 79, 80,
2388};
2389static const unsigned int sdhi0_data4_mux[] = {
2390 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
2391};
2392static const unsigned int sdhi0_ctrl_pins[] = {
2393 /* CMD, CLK */
2394 76, 82,
2395};
2396static const unsigned int sdhi0_ctrl_mux[] = {
2397 SDHI0_CMD_MARK, SDHI0_CLK_MARK,
2398};
2399static const unsigned int sdhi0_cd_pins[] = {
2400 /* CD */
2401 81,
2402};
2403static const unsigned int sdhi0_cd_mux[] = {
2404 SDHI0_CD_MARK,
2405};
2406static const unsigned int sdhi0_wp_pins[] = {
2407 /* WP */
2408 83,
2409};
2410static const unsigned int sdhi0_wp_mux[] = {
2411 SDHI0_WP_MARK,
2412};
2413/* - SDHI1 ------------------------------------------------------------------ */
2414static const unsigned int sdhi1_data1_pins[] = {
2415 /* D0 */
2416 68,
2417};
2418static const unsigned int sdhi1_data1_mux[] = {
2419 SDHI1_D0_MARK,
2420};
2421static const unsigned int sdhi1_data4_pins[] = {
2422 /* D[0:3] */
2423 68, 69, 70, 71,
2424};
2425static const unsigned int sdhi1_data4_mux[] = {
2426 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
2427};
2428static const unsigned int sdhi1_ctrl_pins[] = {
2429 /* CMD, CLK */
2430 67, 66,
2431};
2432static const unsigned int sdhi1_ctrl_mux[] = {
2433 SDHI1_CMD_MARK, SDHI1_CLK_MARK,
2434};
2435static const unsigned int sdhi1_cd_pins[] = {
2436 /* CD */
2437 72,
2438};
2439static const unsigned int sdhi1_cd_mux[] = {
2440 SDHI1_CD_MARK,
2441};
2442static const unsigned int sdhi1_wp_pins[] = {
2443 /* WP */
2444 73,
2445};
2446static const unsigned int sdhi1_wp_mux[] = {
2447 SDHI1_WP_MARK,
2448};
2449/* - SDHI2 ------------------------------------------------------------------ */
2450static const unsigned int sdhi2_data1_pins[] = {
2451 /* D0 */
2452 205,
2453};
2454static const unsigned int sdhi2_data1_mux[] = {
2455 SDHI2_D0_MARK,
2456};
2457static const unsigned int sdhi2_data4_pins[] = {
2458 /* D[0:3] */
2459 205, 206, 207, 208,
2460};
2461static const unsigned int sdhi2_data4_mux[] = {
2462 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
2463};
2464static const unsigned int sdhi2_ctrl_pins[] = {
2465 /* CMD, CLK */
2466 204, 203,
2467};
2468static const unsigned int sdhi2_ctrl_mux[] = {
2469 SDHI2_CMD_MARK, SDHI2_CLK_MARK,
2470};
2471static const unsigned int sdhi2_cd_0_pins[] = {
2472 /* CD */
2473 202,
2474};
2475static const unsigned int sdhi2_cd_0_mux[] = {
2476 SDHI2_CD_PORT202_MARK,
2477};
2478static const unsigned int sdhi2_wp_0_pins[] = {
2479 /* WP */
2480 177,
2481};
2482static const unsigned int sdhi2_wp_0_mux[] = {
2483 SDHI2_WP_PORT177_MARK,
2484};
2485static const unsigned int sdhi2_cd_1_pins[] = {
2486 /* CD */
2487 24,
2488};
2489static const unsigned int sdhi2_cd_1_mux[] = {
2490 SDHI2_CD_PORT24_MARK,
2491};
2492static const unsigned int sdhi2_wp_1_pins[] = {
2493 /* WP */
2494 25,
2495};
2496static const unsigned int sdhi2_wp_1_mux[] = {
2497 SDHI2_WP_PORT25_MARK,
2498};
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]2499
2500static const struct sh_pfc_pin_group pinmux_groups[] = {
Laurent Pinchartb7099c42013-04-18 01:04:30 +0200[diff] [blame^]2501 SH_PFC_PIN_GROUP(bsc_data8),
2502 SH_PFC_PIN_GROUP(bsc_data16),
2503 SH_PFC_PIN_GROUP(bsc_data32),
2504 SH_PFC_PIN_GROUP(bsc_cs0),
2505 SH_PFC_PIN_GROUP(bsc_cs2),
2506 SH_PFC_PIN_GROUP(bsc_cs4),
2507 SH_PFC_PIN_GROUP(bsc_cs5a_0),
2508 SH_PFC_PIN_GROUP(bsc_cs5a_1),
2509 SH_PFC_PIN_GROUP(bsc_cs5b),
2510 SH_PFC_PIN_GROUP(bsc_cs6a),
2511 SH_PFC_PIN_GROUP(bsc_rd_we8),
2512 SH_PFC_PIN_GROUP(bsc_rd_we16),
2513 SH_PFC_PIN_GROUP(bsc_rd_we32),
2514 SH_PFC_PIN_GROUP(bsc_bs),
2515 SH_PFC_PIN_GROUP(bsc_rdwr),
Bastian Hecht09bbc1f2013-04-09 10:48:50 +0000[diff] [blame]2516 SH_PFC_PIN_GROUP(intc_irq0_0),
2517 SH_PFC_PIN_GROUP(intc_irq0_1),
2518 SH_PFC_PIN_GROUP(intc_irq1),
2519 SH_PFC_PIN_GROUP(intc_irq2_0),
2520 SH_PFC_PIN_GROUP(intc_irq2_1),
2521 SH_PFC_PIN_GROUP(intc_irq3_0),
2522 SH_PFC_PIN_GROUP(intc_irq3_1),
2523 SH_PFC_PIN_GROUP(intc_irq4_0),
2524 SH_PFC_PIN_GROUP(intc_irq4_1),
2525 SH_PFC_PIN_GROUP(intc_irq5_0),
2526 SH_PFC_PIN_GROUP(intc_irq5_1),
2527 SH_PFC_PIN_GROUP(intc_irq6_0),
2528 SH_PFC_PIN_GROUP(intc_irq6_1),
2529 SH_PFC_PIN_GROUP(intc_irq7_0),
2530 SH_PFC_PIN_GROUP(intc_irq7_1),
2531 SH_PFC_PIN_GROUP(intc_irq8),
2532 SH_PFC_PIN_GROUP(intc_irq9_0),
2533 SH_PFC_PIN_GROUP(intc_irq9_1),
2534 SH_PFC_PIN_GROUP(intc_irq10),
2535 SH_PFC_PIN_GROUP(intc_irq11),
2536 SH_PFC_PIN_GROUP(intc_irq12_0),
2537 SH_PFC_PIN_GROUP(intc_irq12_1),
2538 SH_PFC_PIN_GROUP(intc_irq13_0),
2539 SH_PFC_PIN_GROUP(intc_irq13_1),
2540 SH_PFC_PIN_GROUP(intc_irq14_0),
2541 SH_PFC_PIN_GROUP(intc_irq14_1),
2542 SH_PFC_PIN_GROUP(intc_irq15_0),
2543 SH_PFC_PIN_GROUP(intc_irq15_1),
2544 SH_PFC_PIN_GROUP(intc_irq16_0),
2545 SH_PFC_PIN_GROUP(intc_irq16_1),
2546 SH_PFC_PIN_GROUP(intc_irq17),
2547 SH_PFC_PIN_GROUP(intc_irq18),
2548 SH_PFC_PIN_GROUP(intc_irq19),
2549 SH_PFC_PIN_GROUP(intc_irq20),
2550 SH_PFC_PIN_GROUP(intc_irq21),
2551 SH_PFC_PIN_GROUP(intc_irq22),
2552 SH_PFC_PIN_GROUP(intc_irq23),
2553 SH_PFC_PIN_GROUP(intc_irq24),
2554 SH_PFC_PIN_GROUP(intc_irq25),
2555 SH_PFC_PIN_GROUP(intc_irq26_0),
2556 SH_PFC_PIN_GROUP(intc_irq26_1),
2557 SH_PFC_PIN_GROUP(intc_irq27_0),
2558 SH_PFC_PIN_GROUP(intc_irq27_1),
2559 SH_PFC_PIN_GROUP(intc_irq28_0),
2560 SH_PFC_PIN_GROUP(intc_irq28_1),
2561 SH_PFC_PIN_GROUP(intc_irq29_0),
2562 SH_PFC_PIN_GROUP(intc_irq29_1),
2563 SH_PFC_PIN_GROUP(intc_irq30_0),
2564 SH_PFC_PIN_GROUP(intc_irq30_1),
2565 SH_PFC_PIN_GROUP(intc_irq31_0),
2566 SH_PFC_PIN_GROUP(intc_irq31_1),
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]2567 SH_PFC_PIN_GROUP(lcd0_data8),
2568 SH_PFC_PIN_GROUP(lcd0_data9),
2569 SH_PFC_PIN_GROUP(lcd0_data12),
2570 SH_PFC_PIN_GROUP(lcd0_data16),
2571 SH_PFC_PIN_GROUP(lcd0_data18),
2572 SH_PFC_PIN_GROUP(lcd0_data24_0),
2573 SH_PFC_PIN_GROUP(lcd0_data24_1),
2574 SH_PFC_PIN_GROUP(lcd0_display),
2575 SH_PFC_PIN_GROUP(lcd0_lclk_0),
2576 SH_PFC_PIN_GROUP(lcd0_lclk_1),
2577 SH_PFC_PIN_GROUP(lcd0_sync),
2578 SH_PFC_PIN_GROUP(lcd0_sys),
2579 SH_PFC_PIN_GROUP(lcd1_data8),
2580 SH_PFC_PIN_GROUP(lcd1_data9),
2581 SH_PFC_PIN_GROUP(lcd1_data12),
2582 SH_PFC_PIN_GROUP(lcd1_data16),
2583 SH_PFC_PIN_GROUP(lcd1_data18),
2584 SH_PFC_PIN_GROUP(lcd1_data24),
2585 SH_PFC_PIN_GROUP(lcd1_display),
2586 SH_PFC_PIN_GROUP(lcd1_lclk),
2587 SH_PFC_PIN_GROUP(lcd1_sync),
2588 SH_PFC_PIN_GROUP(lcd1_sys),
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]2589 SH_PFC_PIN_GROUP(mmc0_data1_0),
2590 SH_PFC_PIN_GROUP(mmc0_data4_0),
2591 SH_PFC_PIN_GROUP(mmc0_data8_0),
2592 SH_PFC_PIN_GROUP(mmc0_ctrl_0),
2593 SH_PFC_PIN_GROUP(mmc0_data1_1),
2594 SH_PFC_PIN_GROUP(mmc0_data4_1),
2595 SH_PFC_PIN_GROUP(mmc0_data8_1),
2596 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]2597 SH_PFC_PIN_GROUP(scifa0_data),
2598 SH_PFC_PIN_GROUP(scifa0_clk),
2599 SH_PFC_PIN_GROUP(scifa0_ctrl),
Bastian Hecht8fbfdbb2013-04-17 10:34:01 +0000[diff] [blame]2600 SH_PFC_PIN_GROUP(scifa1_data),
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]2601 SH_PFC_PIN_GROUP(scifa1_clk),
2602 SH_PFC_PIN_GROUP(scifa1_ctrl),
2603 SH_PFC_PIN_GROUP(scifa2_data),
2604 SH_PFC_PIN_GROUP(scifa2_clk_0),
2605 SH_PFC_PIN_GROUP(scifa2_clk_1),
2606 SH_PFC_PIN_GROUP(scifa2_ctrl),
2607 SH_PFC_PIN_GROUP(scifa3_data_0),
2608 SH_PFC_PIN_GROUP(scifa3_clk_0),
2609 SH_PFC_PIN_GROUP(scifa3_ctrl_0),
2610 SH_PFC_PIN_GROUP(scifa3_data_1),
2611 SH_PFC_PIN_GROUP(scifa3_clk_1),
2612 SH_PFC_PIN_GROUP(scifa3_ctrl_1),
2613 SH_PFC_PIN_GROUP(scifa4_data_0),
2614 SH_PFC_PIN_GROUP(scifa4_data_1),
2615 SH_PFC_PIN_GROUP(scifa4_data_2),
2616 SH_PFC_PIN_GROUP(scifa4_clk_0),
2617 SH_PFC_PIN_GROUP(scifa4_clk_1),
2618 SH_PFC_PIN_GROUP(scifa5_data_0),
2619 SH_PFC_PIN_GROUP(scifa5_data_1),
2620 SH_PFC_PIN_GROUP(scifa5_data_2),
2621 SH_PFC_PIN_GROUP(scifa5_clk_0),
2622 SH_PFC_PIN_GROUP(scifa5_clk_1),
2623 SH_PFC_PIN_GROUP(scifa6_data),
2624 SH_PFC_PIN_GROUP(scifa6_clk),
2625 SH_PFC_PIN_GROUP(scifa7_data),
2626 SH_PFC_PIN_GROUP(scifb_data_0),
2627 SH_PFC_PIN_GROUP(scifb_clk_0),
2628 SH_PFC_PIN_GROUP(scifb_ctrl_0),
2629 SH_PFC_PIN_GROUP(scifb_data_1),
2630 SH_PFC_PIN_GROUP(scifb_clk_1),
2631 SH_PFC_PIN_GROUP(scifb_ctrl_1),
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]2632 SH_PFC_PIN_GROUP(sdhi0_data1),
2633 SH_PFC_PIN_GROUP(sdhi0_data4),
2634 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2635 SH_PFC_PIN_GROUP(sdhi0_cd),
2636 SH_PFC_PIN_GROUP(sdhi0_wp),
2637 SH_PFC_PIN_GROUP(sdhi1_data1),
2638 SH_PFC_PIN_GROUP(sdhi1_data4),
2639 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2640 SH_PFC_PIN_GROUP(sdhi1_cd),
2641 SH_PFC_PIN_GROUP(sdhi1_wp),
2642 SH_PFC_PIN_GROUP(sdhi2_data1),
2643 SH_PFC_PIN_GROUP(sdhi2_data4),
2644 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2645 SH_PFC_PIN_GROUP(sdhi2_cd_0),
2646 SH_PFC_PIN_GROUP(sdhi2_wp_0),
2647 SH_PFC_PIN_GROUP(sdhi2_cd_1),
2648 SH_PFC_PIN_GROUP(sdhi2_wp_1),
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]2649};
2650
Laurent Pinchartb7099c42013-04-18 01:04:30 +0200[diff] [blame^]2651static const char * const bsc_groups[] = {
2652 "bsc_data8",
2653 "bsc_data16",
2654 "bsc_data32",
2655 "bsc_cs0",
2656 "bsc_cs2",
2657 "bsc_cs4",
2658 "bsc_cs5a_0",
2659 "bsc_cs5a_1",
2660 "bsc_cs5b",
2661 "bsc_cs6a",
2662 "bsc_rd_we8",
2663 "bsc_rd_we16",
2664 "bsc_rd_we32",
2665 "bsc_bs",
2666 "bsc_rdwr",
2667};
2668
Bastian Hecht09bbc1f2013-04-09 10:48:50 +0000[diff] [blame]2669static const char * const intc_groups[] = {
2670 "intc_irq0_0",
2671 "intc_irq0_1",
2672 "intc_irq1",
2673 "intc_irq2_0",
2674 "intc_irq2_1",
2675 "intc_irq3_0",
2676 "intc_irq3_1",
2677 "intc_irq4_0",
2678 "intc_irq4_1",
2679 "intc_irq5_0",
2680 "intc_irq5_1",
2681 "intc_irq6_0",
2682 "intc_irq6_1",
2683 "intc_irq7_0",
2684 "intc_irq7_1",
2685 "intc_irq8",
2686 "intc_irq9_0",
2687 "intc_irq9_1",
2688 "intc_irq10",
2689 "intc_irq11",
2690 "intc_irq12_0",
2691 "intc_irq12_1",
2692 "intc_irq13_0",
2693 "intc_irq13_1",
2694 "intc_irq14_0",
2695 "intc_irq14_1",
2696 "intc_irq15_0",
2697 "intc_irq15_1",
2698 "intc_irq16_0",
2699 "intc_irq16_1",
2700 "intc_irq17",
2701 "intc_irq18",
2702 "intc_irq19",
2703 "intc_irq20",
2704 "intc_irq21",
2705 "intc_irq22",
2706 "intc_irq23",
2707 "intc_irq24",
2708 "intc_irq25",
2709 "intc_irq26_0",
2710 "intc_irq26_1",
2711 "intc_irq27_0",
2712 "intc_irq27_1",
2713 "intc_irq28_0",
2714 "intc_irq28_1",
2715 "intc_irq29_0",
2716 "intc_irq29_1",
2717 "intc_irq30_0",
2718 "intc_irq30_1",
2719 "intc_irq31_0",
2720 "intc_irq31_1",
2721};
2722
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]2723static const char * const lcd0_groups[] = {
2724 "lcd0_data8",
2725 "lcd0_data9",
2726 "lcd0_data12",
2727 "lcd0_data16",
2728 "lcd0_data18",
2729 "lcd0_data24_0",
2730 "lcd0_data24_1",
2731 "lcd0_display",
2732 "lcd0_lclk_0",
2733 "lcd0_lclk_1",
2734 "lcd0_sync",
2735 "lcd0_sys",
2736};
2737
2738static const char * const lcd1_groups[] = {
2739 "lcd1_data8",
2740 "lcd1_data9",
2741 "lcd1_data12",
2742 "lcd1_data16",
2743 "lcd1_data18",
2744 "lcd1_data24",
2745 "lcd1_display",
2746 "lcd1_lclk",
2747 "lcd1_sync",
2748 "lcd1_sys",
2749};
2750
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]2751static const char * const mmc0_groups[] = {
2752 "mmc0_data1_0",
2753 "mmc0_data4_0",
2754 "mmc0_data8_0",
2755 "mmc0_ctrl_0",
2756 "mmc0_data1_1",
2757 "mmc0_data4_1",
2758 "mmc0_data8_1",
2759 "mmc0_ctrl_1",
2760};
2761
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]2762static const char * const scifa0_groups[] = {
2763 "scifa0_data",
2764 "scifa0_clk",
2765 "scifa0_ctrl",
2766};
2767
Bastian Hecht8fbfdbb2013-04-17 10:34:01 +0000[diff] [blame]2768static const char * const scifa1_groups[] = {
2769 "scifa1_data",
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]2770 "scifa1_clk",
2771 "scifa1_ctrl",
2772};
2773
2774static const char * const scifa2_groups[] = {
2775 "scifa2_data",
2776 "scifa2_clk_0",
2777 "scifa2_clk_1",
2778 "scifa2_ctrl",
2779};
2780
2781static const char * const scifa3_groups[] = {
2782 "scifa3_data_0",
2783 "scifa3_clk_0",
2784 "scifa3_ctrl_0",
2785 "scifa3_data_1",
2786 "scifa3_clk_1",
2787 "scifa3_ctrl_1",
2788};
2789
2790static const char * const scifa4_groups[] = {
2791 "scifa4_data_0",
2792 "scifa4_data_1",
2793 "scifa4_data_2",
2794 "scifa4_clk_0",
2795 "scifa4_clk_1",
2796};
2797
2798static const char * const scifa5_groups[] = {
2799 "scifa5_data_0",
2800 "scifa5_data_1",
2801 "scifa5_data_2",
2802 "scifa5_clk_0",
2803 "scifa5_clk_1",
2804};
2805
2806static const char * const scifa6_groups[] = {
2807 "scifa6_data",
2808 "scifa6_clk",
2809};
2810
2811static const char * const scifa7_groups[] = {
2812 "scifa7_data",
2813};
2814
2815static const char * const scifb_groups[] = {
2816 "scifb_data_0",
2817 "scifb_clk_0",
2818 "scifb_ctrl_0",
2819 "scifb_data_1",
2820 "scifb_clk_1",
2821 "scifb_ctrl_1",
Bastian Hecht8fbfdbb2013-04-17 10:34:01 +0000[diff] [blame]2822};
2823
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]2824static const char * const sdhi0_groups[] = {
2825 "sdhi0_data1",
2826 "sdhi0_data4",
2827 "sdhi0_ctrl",
2828 "sdhi0_cd",
2829 "sdhi0_wp",
2830};
2831
2832static const char * const sdhi1_groups[] = {
2833 "sdhi1_data1",
2834 "sdhi1_data4",
2835 "sdhi1_ctrl",
2836 "sdhi1_cd",
2837 "sdhi1_wp",
2838};
2839
2840static const char * const sdhi2_groups[] = {
2841 "sdhi2_data1",
2842 "sdhi2_data4",
2843 "sdhi2_ctrl",
2844 "sdhi2_cd_0",
2845 "sdhi2_wp_0",
2846 "sdhi2_cd_1",
2847 "sdhi2_wp_1",
2848};
2849
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]2850static const struct sh_pfc_function pinmux_functions[] = {
Laurent Pinchartb7099c42013-04-18 01:04:30 +0200[diff] [blame^]2851 SH_PFC_FUNCTION(bsc),
Laurent Pinchartd0316962013-04-18 10:54:18 +0200[diff] [blame]2852 SH_PFC_FUNCTION(intc),
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]2853 SH_PFC_FUNCTION(lcd0),
2854 SH_PFC_FUNCTION(lcd1),
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]2855 SH_PFC_FUNCTION(mmc0),
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]2856 SH_PFC_FUNCTION(scifa0),
Bastian Hecht8fbfdbb2013-04-17 10:34:01 +0000[diff] [blame]2857 SH_PFC_FUNCTION(scifa1),
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]2858 SH_PFC_FUNCTION(scifa2),
2859 SH_PFC_FUNCTION(scifa3),
2860 SH_PFC_FUNCTION(scifa4),
2861 SH_PFC_FUNCTION(scifa5),
2862 SH_PFC_FUNCTION(scifa6),
2863 SH_PFC_FUNCTION(scifa7),
2864 SH_PFC_FUNCTION(scifb),
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]2865 SH_PFC_FUNCTION(sdhi0),
2866 SH_PFC_FUNCTION(sdhi1),
2867 SH_PFC_FUNCTION(sdhi2),
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]2868};
2869
Laurent Pincharta373ed02012-11-29 13:24:07 +0100[diff] [blame]2870#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
2871
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]2872static const struct pinmux_func pinmux_func_gpios[] = {
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]2873 /* IRQ */
2874 GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13),
2875 GPIO_FN(IRQ1),
2876 GPIO_FN(IRQ2_PORT11), GPIO_FN(IRQ2_PORT12),
2877 GPIO_FN(IRQ3_PORT10), GPIO_FN(IRQ3_PORT14),
2878 GPIO_FN(IRQ4_PORT15), GPIO_FN(IRQ4_PORT172),
2879 GPIO_FN(IRQ5_PORT0), GPIO_FN(IRQ5_PORT1),
2880 GPIO_FN(IRQ6_PORT121), GPIO_FN(IRQ6_PORT173),
2881 GPIO_FN(IRQ7_PORT120), GPIO_FN(IRQ7_PORT209),
2882 GPIO_FN(IRQ8),
2883 GPIO_FN(IRQ9_PORT118), GPIO_FN(IRQ9_PORT210),
2884 GPIO_FN(IRQ10),
2885 GPIO_FN(IRQ11),
2886 GPIO_FN(IRQ12_PORT42), GPIO_FN(IRQ12_PORT97),
2887 GPIO_FN(IRQ13_PORT64), GPIO_FN(IRQ13_PORT98),
2888 GPIO_FN(IRQ14_PORT63), GPIO_FN(IRQ14_PORT99),
2889 GPIO_FN(IRQ15_PORT62), GPIO_FN(IRQ15_PORT100),
2890 GPIO_FN(IRQ16_PORT68), GPIO_FN(IRQ16_PORT211),
2891 GPIO_FN(IRQ17),
2892 GPIO_FN(IRQ18),
2893 GPIO_FN(IRQ19),
2894 GPIO_FN(IRQ20),
2895 GPIO_FN(IRQ21),
2896 GPIO_FN(IRQ22),
2897 GPIO_FN(IRQ23),
2898 GPIO_FN(IRQ24),
2899 GPIO_FN(IRQ25),
2900 GPIO_FN(IRQ26_PORT58), GPIO_FN(IRQ26_PORT81),
2901 GPIO_FN(IRQ27_PORT57), GPIO_FN(IRQ27_PORT168),
2902 GPIO_FN(IRQ28_PORT56), GPIO_FN(IRQ28_PORT169),
2903 GPIO_FN(IRQ29_PORT50), GPIO_FN(IRQ29_PORT170),
2904 GPIO_FN(IRQ30_PORT49), GPIO_FN(IRQ30_PORT171),
2905 GPIO_FN(IRQ31_PORT41), GPIO_FN(IRQ31_PORT167),
2906
2907 /* Function */
2908
2909 /* DBGT */
2910 GPIO_FN(DBGMDT2), GPIO_FN(DBGMDT1), GPIO_FN(DBGMDT0),
2911 GPIO_FN(DBGMD10), GPIO_FN(DBGMD11), GPIO_FN(DBGMD20),
2912 GPIO_FN(DBGMD21),
2913
2914 /* FSI-A */
2915 GPIO_FN(FSIAISLD_PORT0), /* FSIAISLD Port 0/5 */
2916 GPIO_FN(FSIAISLD_PORT5),
2917 GPIO_FN(FSIASPDIF_PORT9), /* FSIASPDIF Port 9/18 */
2918 GPIO_FN(FSIASPDIF_PORT18),
2919 GPIO_FN(FSIAOSLD1), GPIO_FN(FSIAOSLD2), GPIO_FN(FSIAOLR),
2920 GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), GPIO_FN(FSIAOMC),
2921 GPIO_FN(FSIACK), GPIO_FN(FSIAILR), GPIO_FN(FSIAIBT),
2922
2923 /* FSI-B */
2924 GPIO_FN(FSIBCK),
2925
2926 /* FMSI */
2927 GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */
2928 GPIO_FN(FMSISLD_PORT6),
2929 GPIO_FN(FMSIILR), GPIO_FN(FMSIIBT), GPIO_FN(FMSIOLR),
2930 GPIO_FN(FMSIOBT), GPIO_FN(FMSICK), GPIO_FN(FMSOILR),
2931 GPIO_FN(FMSOIBT), GPIO_FN(FMSOOLR), GPIO_FN(FMSOOBT),
2932 GPIO_FN(FMSOSLD), GPIO_FN(FMSOCK),
2933
2934 /* SCIFA0 */
2935 GPIO_FN(SCIFA0_SCK), GPIO_FN(SCIFA0_CTS), GPIO_FN(SCIFA0_RTS),
2936 GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_TXD),
2937
2938 /* SCIFA1 */
2939 GPIO_FN(SCIFA1_CTS), GPIO_FN(SCIFA1_SCK),
2940 GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RTS),
2941
2942 /* SCIFA2 */
2943 GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */
2944 GPIO_FN(SCIFA2_SCK_PORT199),
2945 GPIO_FN(SCIFA2_RXD), GPIO_FN(SCIFA2_TXD),
2946 GPIO_FN(SCIFA2_CTS), GPIO_FN(SCIFA2_RTS),
2947
2948 /* SCIFA3 */
2949 GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */
2950 GPIO_FN(SCIFA3_SCK_PORT116),
2951 GPIO_FN(SCIFA3_CTS_PORT117),
2952 GPIO_FN(SCIFA3_RXD_PORT174),
2953 GPIO_FN(SCIFA3_TXD_PORT175),
2954
2955 GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */
2956 GPIO_FN(SCIFA3_SCK_PORT158),
2957 GPIO_FN(SCIFA3_CTS_PORT162),
2958 GPIO_FN(SCIFA3_RXD_PORT159),
2959 GPIO_FN(SCIFA3_TXD_PORT160),
2960
2961 /* SCIFA4 */
2962 GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */
2963 GPIO_FN(SCIFA4_TXD_PORT13),
2964
2965 GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */
2966 GPIO_FN(SCIFA4_TXD_PORT203),
2967
2968 GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */
2969 GPIO_FN(SCIFA4_TXD_PORT93),
2970
2971 GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */
2972 GPIO_FN(SCIFA4_SCK_PORT205),
2973
2974 /* SCIFA5 */
2975 GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */
2976 GPIO_FN(SCIFA5_RXD_PORT10),
2977
2978 GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */
2979 GPIO_FN(SCIFA5_TXD_PORT208),
2980
2981 GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */
2982 GPIO_FN(SCIFA5_RXD_PORT92),
2983
2984 GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */
2985 GPIO_FN(SCIFA5_SCK_PORT206),
2986
2987 /* SCIFA6 */
2988 GPIO_FN(SCIFA6_SCK), GPIO_FN(SCIFA6_RXD), GPIO_FN(SCIFA6_TXD),
2989
2990 /* SCIFA7 */
2991 GPIO_FN(SCIFA7_TXD), GPIO_FN(SCIFA7_RXD),
2992
2993 /* SCIFAB */
2994 GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */
2995 GPIO_FN(SCIFB_RXD_PORT191),
2996 GPIO_FN(SCIFB_TXD_PORT192),
2997 GPIO_FN(SCIFB_RTS_PORT186),
2998 GPIO_FN(SCIFB_CTS_PORT187),
2999
3000 GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */
3001 GPIO_FN(SCIFB_RXD_PORT3),
3002 GPIO_FN(SCIFB_TXD_PORT4),
3003 GPIO_FN(SCIFB_RTS_PORT172),
3004 GPIO_FN(SCIFB_CTS_PORT173),
3005
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3006 /* RSPI */
3007 GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A),
3008 GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A),
3009 GPIO_FN(RSPI_MISO_A),
3010
3011 /* VIO CKO */
3012 GPIO_FN(VIO_CKO1),
3013 GPIO_FN(VIO_CKO2),
3014 GPIO_FN(VIO_CKO_1),
3015 GPIO_FN(VIO_CKO),
3016
3017 /* VIO0 */
3018 GPIO_FN(VIO0_D0), GPIO_FN(VIO0_D1), GPIO_FN(VIO0_D2),
3019 GPIO_FN(VIO0_D3), GPIO_FN(VIO0_D4), GPIO_FN(VIO0_D5),
3020 GPIO_FN(VIO0_D6), GPIO_FN(VIO0_D7), GPIO_FN(VIO0_D8),
3021 GPIO_FN(VIO0_D9), GPIO_FN(VIO0_D10), GPIO_FN(VIO0_D11),
3022 GPIO_FN(VIO0_D12), GPIO_FN(VIO0_VD), GPIO_FN(VIO0_HD),
3023 GPIO_FN(VIO0_CLK), GPIO_FN(VIO0_FIELD),
3024
3025 GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */
3026 GPIO_FN(VIO0_D14_PORT25),
3027 GPIO_FN(VIO0_D15_PORT24),
3028
3029 GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */
3030 GPIO_FN(VIO0_D14_PORT95),
3031 GPIO_FN(VIO0_D15_PORT96),
3032
3033 /* VIO1 */
3034 GPIO_FN(VIO1_D0), GPIO_FN(VIO1_D1), GPIO_FN(VIO1_D2),
3035 GPIO_FN(VIO1_D3), GPIO_FN(VIO1_D4), GPIO_FN(VIO1_D5),
3036 GPIO_FN(VIO1_D6), GPIO_FN(VIO1_D7), GPIO_FN(VIO1_VD),
3037 GPIO_FN(VIO1_HD), GPIO_FN(VIO1_CLK), GPIO_FN(VIO1_FIELD),
3038
3039 /* TPU0 */
3040 GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO3),
3041 GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */
3042 GPIO_FN(TPU0TO2_PORT202),
3043
3044 /* SSP1 0 */
3045 GPIO_FN(STP0_IPD0), GPIO_FN(STP0_IPD1), GPIO_FN(STP0_IPD2),
3046 GPIO_FN(STP0_IPD3), GPIO_FN(STP0_IPD4), GPIO_FN(STP0_IPD5),
3047 GPIO_FN(STP0_IPD6), GPIO_FN(STP0_IPD7), GPIO_FN(STP0_IPEN),
3048 GPIO_FN(STP0_IPCLK), GPIO_FN(STP0_IPSYNC),
3049
3050 /* SSP1 1 */
3051 GPIO_FN(STP1_IPD1), GPIO_FN(STP1_IPD2), GPIO_FN(STP1_IPD3),
3052 GPIO_FN(STP1_IPD4), GPIO_FN(STP1_IPD5), GPIO_FN(STP1_IPD6),
3053 GPIO_FN(STP1_IPD7), GPIO_FN(STP1_IPCLK), GPIO_FN(STP1_IPSYNC),
3054
3055 GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */
3056 GPIO_FN(STP1_IPEN_PORT187),
3057
3058 GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */
3059 GPIO_FN(STP1_IPEN_PORT193),
3060
3061 /* SIM */
3062 GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK),
3063 GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */
3064 GPIO_FN(SIM_D_PORT199),
3065
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3066 /* MSIOF2 */
3067 GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK),
3068 GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1),
3069 GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_MCK0), GPIO_FN(MSIOF2_RSYNC),
3070 GPIO_FN(MSIOF2_RSCK),
3071
3072 /* KEYSC */
3073 GPIO_FN(KEYIN4), GPIO_FN(KEYIN5),
3074 GPIO_FN(KEYIN6), GPIO_FN(KEYIN7),
3075 GPIO_FN(KEYOUT0), GPIO_FN(KEYOUT1), GPIO_FN(KEYOUT2),
3076 GPIO_FN(KEYOUT3), GPIO_FN(KEYOUT4), GPIO_FN(KEYOUT5),
3077 GPIO_FN(KEYOUT6), GPIO_FN(KEYOUT7),
3078
3079 GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */
3080 GPIO_FN(KEYIN1_PORT44),
3081 GPIO_FN(KEYIN2_PORT45),
3082 GPIO_FN(KEYIN3_PORT46),
3083
3084 GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */
3085 GPIO_FN(KEYIN1_PORT57),
3086 GPIO_FN(KEYIN2_PORT56),
3087 GPIO_FN(KEYIN3_PORT55),
3088
3089 /* VOU */
3090 GPIO_FN(DV_D0), GPIO_FN(DV_D1), GPIO_FN(DV_D2),
3091 GPIO_FN(DV_D3), GPIO_FN(DV_D4), GPIO_FN(DV_D5),
3092 GPIO_FN(DV_D6), GPIO_FN(DV_D7), GPIO_FN(DV_D8),
3093 GPIO_FN(DV_D9), GPIO_FN(DV_D10), GPIO_FN(DV_D11),
3094 GPIO_FN(DV_D12), GPIO_FN(DV_D13), GPIO_FN(DV_D14),
3095 GPIO_FN(DV_D15), GPIO_FN(DV_CLK),
3096 GPIO_FN(DV_VSYNC), GPIO_FN(DV_HSYNC),
3097
3098 /* MEMC */
3099 GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2),
3100 GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5),
3101 GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8),
3102 GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11),
3103 GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14),
3104 GPIO_FN(MEMC_AD15), GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_INT),
3105 GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_NOE), GPIO_FN(MEMC_CS1),
3106 GPIO_FN(MEMC_A1), GPIO_FN(MEMC_ADV), GPIO_FN(MEMC_DREQ0),
3107 GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK),
3108 GPIO_FN(MEMC_A0),
3109
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3110 /* MSIOF0 */
3111 GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD),
3112 GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1),
3113 GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_TSCK),
3114 GPIO_FN(MSIOF0_TSYNC),
3115
3116 /* MSIOF1 */
3117 GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC),
3118 GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1),
3119
3120 GPIO_FN(MSIOF1_SS2_PORT116), GPIO_FN(MSIOF1_SS1_PORT117),
3121 GPIO_FN(MSIOF1_RXD_PORT118), GPIO_FN(MSIOF1_TXD_PORT119),
3122 GPIO_FN(MSIOF1_TSYNC_PORT120),
3123 GPIO_FN(MSIOF1_TSCK_PORT121), /* MSEL4CR_10_0 */
3124
3125 GPIO_FN(MSIOF1_SS1_PORT67), GPIO_FN(MSIOF1_TSCK_PORT72),
3126 GPIO_FN(MSIOF1_TSYNC_PORT73), GPIO_FN(MSIOF1_TXD_PORT74),
3127 GPIO_FN(MSIOF1_RXD_PORT75),
3128 GPIO_FN(MSIOF1_SS2_PORT202), /* MSEL4CR_10_1 */
3129
3130 /* GPIO */
3131 GPIO_FN(GPO0), GPIO_FN(GPI0),
3132 GPIO_FN(GPO1), GPIO_FN(GPI1),
3133
3134 /* USB0 */
3135 GPIO_FN(USB0_OCI), GPIO_FN(USB0_PPON), GPIO_FN(VBUS),
3136
3137 /* USB1 */
3138 GPIO_FN(USB1_OCI), GPIO_FN(USB1_PPON),
3139
3140 /* BBIF1 */
3141 GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_TSYNC),
3142 GPIO_FN(BBIF1_TSCK), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC),
3143 GPIO_FN(BBIF1_FLOW), GPIO_FN(BBIF1_RX_FLOW_N),
3144
3145 /* BBIF2 */
3146 GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */
3147 GPIO_FN(BBIF2_RXD2_PORT60),
3148 GPIO_FN(BBIF2_TSYNC2_PORT6),
3149 GPIO_FN(BBIF2_TSCK2_PORT59),
3150
3151 GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */
3152 GPIO_FN(BBIF2_TXD2_PORT183),
3153 GPIO_FN(BBIF2_TSCK2_PORT89),
3154 GPIO_FN(BBIF2_TSYNC2_PORT184),
3155
3156 /* BSC / FLCTL / PCMCIA */
3157 GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4),
3158 GPIO_FN(CS5B), GPIO_FN(CS6A),
3159 GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */
3160 GPIO_FN(CS5A_PORT19),
3161 GPIO_FN(IOIS16), /* ? */
3162
3163 GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3),
3164 GPIO_FN(A4_FOE), GPIO_FN(A5_FCDE), /* share with FLCTL */
3165 GPIO_FN(A6), GPIO_FN(A7), GPIO_FN(A8), GPIO_FN(A9),
3166 GPIO_FN(A10), GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13),
3167 GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), GPIO_FN(A17),
3168 GPIO_FN(A18), GPIO_FN(A19), GPIO_FN(A20), GPIO_FN(A21),
3169 GPIO_FN(A22), GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25),
3170 GPIO_FN(A26),
3171
3172 GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), /* share with FLCTL */
3173 GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), /* share with FLCTL */
3174 GPIO_FN(D4_NAF4), GPIO_FN(D5_NAF5), /* share with FLCTL */
3175 GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), /* share with FLCTL */
3176 GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), /* share with FLCTL */
3177 GPIO_FN(D10_NAF10), GPIO_FN(D11_NAF11), /* share with FLCTL */
3178 GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), /* share with FLCTL */
3179 GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), /* share with FLCTL */
3180 GPIO_FN(D16), GPIO_FN(D17), GPIO_FN(D18), GPIO_FN(D19),
3181 GPIO_FN(D20), GPIO_FN(D21), GPIO_FN(D22), GPIO_FN(D23),
3182 GPIO_FN(D24), GPIO_FN(D25), GPIO_FN(D26), GPIO_FN(D27),
3183 GPIO_FN(D28), GPIO_FN(D29), GPIO_FN(D30), GPIO_FN(D31),
3184
3185 GPIO_FN(WE0_FWE), /* share with FLCTL */
3186 GPIO_FN(WE1),
3187 GPIO_FN(WE2_ICIORD), /* share with PCMCIA */
3188 GPIO_FN(WE3_ICIOWR), /* share with PCMCIA */
3189 GPIO_FN(CKO), GPIO_FN(BS), GPIO_FN(RDWR),
3190 GPIO_FN(RD_FSC), /* share with FLCTL */
3191 GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */
3192 GPIO_FN(WAIT_PORT90),
3193
3194 GPIO_FN(FCE0), GPIO_FN(FCE1), GPIO_FN(FRB), /* FLCTL */
3195
3196 /* IRDA */
3197 GPIO_FN(IRDA_FIRSEL), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_OUT),
3198
3199 /* ATAPI */
3200 GPIO_FN(IDE_D0), GPIO_FN(IDE_D1), GPIO_FN(IDE_D2),
3201 GPIO_FN(IDE_D3), GPIO_FN(IDE_D4), GPIO_FN(IDE_D5),
3202 GPIO_FN(IDE_D6), GPIO_FN(IDE_D7), GPIO_FN(IDE_D8),
3203 GPIO_FN(IDE_D9), GPIO_FN(IDE_D10), GPIO_FN(IDE_D11),
3204 GPIO_FN(IDE_D12), GPIO_FN(IDE_D13), GPIO_FN(IDE_D14),
3205 GPIO_FN(IDE_D15), GPIO_FN(IDE_A0), GPIO_FN(IDE_A1),
3206 GPIO_FN(IDE_A2), GPIO_FN(IDE_CS0), GPIO_FN(IDE_CS1),
3207 GPIO_FN(IDE_IOWR), GPIO_FN(IDE_IORD), GPIO_FN(IDE_IORDY),
3208 GPIO_FN(IDE_INT), GPIO_FN(IDE_RST), GPIO_FN(IDE_DIRECTION),
3209 GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK), GPIO_FN(IDE_IODREQ),
3210
3211 /* RMII */
3212 GPIO_FN(RMII_CRS_DV), GPIO_FN(RMII_RX_ER), GPIO_FN(RMII_RXD0),
3213 GPIO_FN(RMII_RXD1), GPIO_FN(RMII_TX_EN), GPIO_FN(RMII_TXD0),
3214 GPIO_FN(RMII_MDC), GPIO_FN(RMII_TXD1), GPIO_FN(RMII_MDIO),
3215 GPIO_FN(RMII_REF50CK), GPIO_FN(RMII_REF125CK), /* for GMII */
3216
3217 /* GEther */
3218 GPIO_FN(ET_TX_CLK), GPIO_FN(ET_TX_EN), GPIO_FN(ET_ETXD0),
3219 GPIO_FN(ET_ETXD1), GPIO_FN(ET_ETXD2), GPIO_FN(ET_ETXD3),
3220 GPIO_FN(ET_ETXD4), GPIO_FN(ET_ETXD5), /* for GEther */
3221 GPIO_FN(ET_ETXD6), GPIO_FN(ET_ETXD7), /* for GEther */
3222 GPIO_FN(ET_COL), GPIO_FN(ET_TX_ER), GPIO_FN(ET_RX_CLK),
3223 GPIO_FN(ET_RX_DV), GPIO_FN(ET_ERXD0), GPIO_FN(ET_ERXD1),
3224 GPIO_FN(ET_ERXD2), GPIO_FN(ET_ERXD3),
3225 GPIO_FN(ET_ERXD4), GPIO_FN(ET_ERXD5), /* for GEther */
3226 GPIO_FN(ET_ERXD6), GPIO_FN(ET_ERXD7), /* for GEther */
3227 GPIO_FN(ET_RX_ER), GPIO_FN(ET_CRS), GPIO_FN(ET_MDC),
3228 GPIO_FN(ET_MDIO), GPIO_FN(ET_LINK), GPIO_FN(ET_PHY_INT),
3229 GPIO_FN(ET_WOL), GPIO_FN(ET_GTX_CLK),
3230
3231 /* DMA0 */
3232 GPIO_FN(DREQ0), GPIO_FN(DACK0),
3233
3234 /* DMA1 */
3235 GPIO_FN(DREQ1), GPIO_FN(DACK1),
3236
3237 /* SYSC */
3238 GPIO_FN(RESETOUTS),
3239
3240 /* IRREM */
3241 GPIO_FN(IROUT),
3242
3243 /* LCDC */
3244 GPIO_FN(LCDC0_SELECT),
3245 GPIO_FN(LCDC1_SELECT),
3246
3247 /* SDENC */
3248 GPIO_FN(SDENC_CPG),
3249 GPIO_FN(SDENC_DV_CLKI),
3250
3251 /* HDMI */
3252 GPIO_FN(HDMI_HPD),
3253 GPIO_FN(HDMI_CEC),
3254
3255 /* SYSC */
3256 GPIO_FN(RESETP_PULLUP),
3257 GPIO_FN(RESETP_PLAIN),
3258
3259 /* DEBUG */
3260 GPIO_FN(EDEBGREQ_PULLDOWN),
3261 GPIO_FN(EDEBGREQ_PULLUP),
3262
3263 GPIO_FN(TRACEAUD_FROM_VIO),
3264 GPIO_FN(TRACEAUD_FROM_LCDC0),
3265 GPIO_FN(TRACEAUD_FROM_MEMC),
3266};
3267
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3268static const struct pinmux_cfg_reg pinmux_config_regs[] = {
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3269 PORTCR(0, 0xe6050000), /* PORT0CR */
3270 PORTCR(1, 0xe6050001), /* PORT1CR */
3271 PORTCR(2, 0xe6050002), /* PORT2CR */
3272 PORTCR(3, 0xe6050003), /* PORT3CR */
3273 PORTCR(4, 0xe6050004), /* PORT4CR */
3274 PORTCR(5, 0xe6050005), /* PORT5CR */
3275 PORTCR(6, 0xe6050006), /* PORT6CR */
3276 PORTCR(7, 0xe6050007), /* PORT7CR */
3277 PORTCR(8, 0xe6050008), /* PORT8CR */
3278 PORTCR(9, 0xe6050009), /* PORT9CR */
3279 PORTCR(10, 0xe605000a), /* PORT10CR */
3280 PORTCR(11, 0xe605000b), /* PORT11CR */
3281 PORTCR(12, 0xe605000c), /* PORT12CR */
3282 PORTCR(13, 0xe605000d), /* PORT13CR */
3283 PORTCR(14, 0xe605000e), /* PORT14CR */
3284 PORTCR(15, 0xe605000f), /* PORT15CR */
3285 PORTCR(16, 0xe6050010), /* PORT16CR */
3286 PORTCR(17, 0xe6050011), /* PORT17CR */
3287 PORTCR(18, 0xe6050012), /* PORT18CR */
3288 PORTCR(19, 0xe6050013), /* PORT19CR */
3289 PORTCR(20, 0xe6050014), /* PORT20CR */
3290 PORTCR(21, 0xe6050015), /* PORT21CR */
3291 PORTCR(22, 0xe6050016), /* PORT22CR */
3292 PORTCR(23, 0xe6050017), /* PORT23CR */
3293 PORTCR(24, 0xe6050018), /* PORT24CR */
3294 PORTCR(25, 0xe6050019), /* PORT25CR */
3295 PORTCR(26, 0xe605001a), /* PORT26CR */
3296 PORTCR(27, 0xe605001b), /* PORT27CR */
3297 PORTCR(28, 0xe605001c), /* PORT28CR */
3298 PORTCR(29, 0xe605001d), /* PORT29CR */
3299 PORTCR(30, 0xe605001e), /* PORT30CR */
3300 PORTCR(31, 0xe605001f), /* PORT31CR */
3301 PORTCR(32, 0xe6050020), /* PORT32CR */
3302 PORTCR(33, 0xe6050021), /* PORT33CR */
3303 PORTCR(34, 0xe6050022), /* PORT34CR */
3304 PORTCR(35, 0xe6050023), /* PORT35CR */
3305 PORTCR(36, 0xe6050024), /* PORT36CR */
3306 PORTCR(37, 0xe6050025), /* PORT37CR */
3307 PORTCR(38, 0xe6050026), /* PORT38CR */
3308 PORTCR(39, 0xe6050027), /* PORT39CR */
3309 PORTCR(40, 0xe6050028), /* PORT40CR */
3310 PORTCR(41, 0xe6050029), /* PORT41CR */
3311 PORTCR(42, 0xe605002a), /* PORT42CR */
3312 PORTCR(43, 0xe605002b), /* PORT43CR */
3313 PORTCR(44, 0xe605002c), /* PORT44CR */
3314 PORTCR(45, 0xe605002d), /* PORT45CR */
3315 PORTCR(46, 0xe605002e), /* PORT46CR */
3316 PORTCR(47, 0xe605002f), /* PORT47CR */
3317 PORTCR(48, 0xe6050030), /* PORT48CR */
3318 PORTCR(49, 0xe6050031), /* PORT49CR */
3319 PORTCR(50, 0xe6050032), /* PORT50CR */
3320 PORTCR(51, 0xe6050033), /* PORT51CR */
3321 PORTCR(52, 0xe6050034), /* PORT52CR */
3322 PORTCR(53, 0xe6050035), /* PORT53CR */
3323 PORTCR(54, 0xe6050036), /* PORT54CR */
3324 PORTCR(55, 0xe6050037), /* PORT55CR */
3325 PORTCR(56, 0xe6050038), /* PORT56CR */
3326 PORTCR(57, 0xe6050039), /* PORT57CR */
3327 PORTCR(58, 0xe605003a), /* PORT58CR */
3328 PORTCR(59, 0xe605003b), /* PORT59CR */
3329 PORTCR(60, 0xe605003c), /* PORT60CR */
3330 PORTCR(61, 0xe605003d), /* PORT61CR */
3331 PORTCR(62, 0xe605003e), /* PORT62CR */
3332 PORTCR(63, 0xe605003f), /* PORT63CR */
3333 PORTCR(64, 0xe6050040), /* PORT64CR */
3334 PORTCR(65, 0xe6050041), /* PORT65CR */
3335 PORTCR(66, 0xe6050042), /* PORT66CR */
3336 PORTCR(67, 0xe6050043), /* PORT67CR */
3337 PORTCR(68, 0xe6050044), /* PORT68CR */
3338 PORTCR(69, 0xe6050045), /* PORT69CR */
3339 PORTCR(70, 0xe6050046), /* PORT70CR */
3340 PORTCR(71, 0xe6050047), /* PORT71CR */
3341 PORTCR(72, 0xe6050048), /* PORT72CR */
3342 PORTCR(73, 0xe6050049), /* PORT73CR */
3343 PORTCR(74, 0xe605004a), /* PORT74CR */
3344 PORTCR(75, 0xe605004b), /* PORT75CR */
3345 PORTCR(76, 0xe605004c), /* PORT76CR */
3346 PORTCR(77, 0xe605004d), /* PORT77CR */
3347 PORTCR(78, 0xe605004e), /* PORT78CR */
3348 PORTCR(79, 0xe605004f), /* PORT79CR */
3349 PORTCR(80, 0xe6050050), /* PORT80CR */
3350 PORTCR(81, 0xe6050051), /* PORT81CR */
3351 PORTCR(82, 0xe6050052), /* PORT82CR */
3352 PORTCR(83, 0xe6050053), /* PORT83CR */
3353
3354 PORTCR(84, 0xe6051054), /* PORT84CR */
3355 PORTCR(85, 0xe6051055), /* PORT85CR */
3356 PORTCR(86, 0xe6051056), /* PORT86CR */
3357 PORTCR(87, 0xe6051057), /* PORT87CR */
3358 PORTCR(88, 0xe6051058), /* PORT88CR */
3359 PORTCR(89, 0xe6051059), /* PORT89CR */
3360 PORTCR(90, 0xe605105a), /* PORT90CR */
3361 PORTCR(91, 0xe605105b), /* PORT91CR */
3362 PORTCR(92, 0xe605105c), /* PORT92CR */
3363 PORTCR(93, 0xe605105d), /* PORT93CR */
3364 PORTCR(94, 0xe605105e), /* PORT94CR */
3365 PORTCR(95, 0xe605105f), /* PORT95CR */
3366 PORTCR(96, 0xe6051060), /* PORT96CR */
3367 PORTCR(97, 0xe6051061), /* PORT97CR */
3368 PORTCR(98, 0xe6051062), /* PORT98CR */
3369 PORTCR(99, 0xe6051063), /* PORT99CR */
3370 PORTCR(100, 0xe6051064), /* PORT100CR */
3371 PORTCR(101, 0xe6051065), /* PORT101CR */
3372 PORTCR(102, 0xe6051066), /* PORT102CR */
3373 PORTCR(103, 0xe6051067), /* PORT103CR */
3374 PORTCR(104, 0xe6051068), /* PORT104CR */
3375 PORTCR(105, 0xe6051069), /* PORT105CR */
3376 PORTCR(106, 0xe605106a), /* PORT106CR */
3377 PORTCR(107, 0xe605106b), /* PORT107CR */
3378 PORTCR(108, 0xe605106c), /* PORT108CR */
3379 PORTCR(109, 0xe605106d), /* PORT109CR */
3380 PORTCR(110, 0xe605106e), /* PORT110CR */
3381 PORTCR(111, 0xe605106f), /* PORT111CR */
3382 PORTCR(112, 0xe6051070), /* PORT112CR */
3383 PORTCR(113, 0xe6051071), /* PORT113CR */
3384 PORTCR(114, 0xe6051072), /* PORT114CR */
3385
3386 PORTCR(115, 0xe6052073), /* PORT115CR */
3387 PORTCR(116, 0xe6052074), /* PORT116CR */
3388 PORTCR(117, 0xe6052075), /* PORT117CR */
3389 PORTCR(118, 0xe6052076), /* PORT118CR */
3390 PORTCR(119, 0xe6052077), /* PORT119CR */
3391 PORTCR(120, 0xe6052078), /* PORT120CR */
3392 PORTCR(121, 0xe6052079), /* PORT121CR */
3393 PORTCR(122, 0xe605207a), /* PORT122CR */
3394 PORTCR(123, 0xe605207b), /* PORT123CR */
3395 PORTCR(124, 0xe605207c), /* PORT124CR */
3396 PORTCR(125, 0xe605207d), /* PORT125CR */
3397 PORTCR(126, 0xe605207e), /* PORT126CR */
3398 PORTCR(127, 0xe605207f), /* PORT127CR */
3399 PORTCR(128, 0xe6052080), /* PORT128CR */
3400 PORTCR(129, 0xe6052081), /* PORT129CR */
3401 PORTCR(130, 0xe6052082), /* PORT130CR */
3402 PORTCR(131, 0xe6052083), /* PORT131CR */
3403 PORTCR(132, 0xe6052084), /* PORT132CR */
3404 PORTCR(133, 0xe6052085), /* PORT133CR */
3405 PORTCR(134, 0xe6052086), /* PORT134CR */
3406 PORTCR(135, 0xe6052087), /* PORT135CR */
3407 PORTCR(136, 0xe6052088), /* PORT136CR */
3408 PORTCR(137, 0xe6052089), /* PORT137CR */
3409 PORTCR(138, 0xe605208a), /* PORT138CR */
3410 PORTCR(139, 0xe605208b), /* PORT139CR */
3411 PORTCR(140, 0xe605208c), /* PORT140CR */
3412 PORTCR(141, 0xe605208d), /* PORT141CR */
3413 PORTCR(142, 0xe605208e), /* PORT142CR */
3414 PORTCR(143, 0xe605208f), /* PORT143CR */
3415 PORTCR(144, 0xe6052090), /* PORT144CR */
3416 PORTCR(145, 0xe6052091), /* PORT145CR */
3417 PORTCR(146, 0xe6052092), /* PORT146CR */
3418 PORTCR(147, 0xe6052093), /* PORT147CR */
3419 PORTCR(148, 0xe6052094), /* PORT148CR */
3420 PORTCR(149, 0xe6052095), /* PORT149CR */
3421 PORTCR(150, 0xe6052096), /* PORT150CR */
3422 PORTCR(151, 0xe6052097), /* PORT151CR */
3423 PORTCR(152, 0xe6052098), /* PORT152CR */
3424 PORTCR(153, 0xe6052099), /* PORT153CR */
3425 PORTCR(154, 0xe605209a), /* PORT154CR */
3426 PORTCR(155, 0xe605209b), /* PORT155CR */
3427 PORTCR(156, 0xe605209c), /* PORT156CR */
3428 PORTCR(157, 0xe605209d), /* PORT157CR */
3429 PORTCR(158, 0xe605209e), /* PORT158CR */
3430 PORTCR(159, 0xe605209f), /* PORT159CR */
3431 PORTCR(160, 0xe60520a0), /* PORT160CR */
3432 PORTCR(161, 0xe60520a1), /* PORT161CR */
3433 PORTCR(162, 0xe60520a2), /* PORT162CR */
3434 PORTCR(163, 0xe60520a3), /* PORT163CR */
3435 PORTCR(164, 0xe60520a4), /* PORT164CR */
3436 PORTCR(165, 0xe60520a5), /* PORT165CR */
3437 PORTCR(166, 0xe60520a6), /* PORT166CR */
3438 PORTCR(167, 0xe60520a7), /* PORT167CR */
3439 PORTCR(168, 0xe60520a8), /* PORT168CR */
3440 PORTCR(169, 0xe60520a9), /* PORT169CR */
3441 PORTCR(170, 0xe60520aa), /* PORT170CR */
3442 PORTCR(171, 0xe60520ab), /* PORT171CR */
3443 PORTCR(172, 0xe60520ac), /* PORT172CR */
3444 PORTCR(173, 0xe60520ad), /* PORT173CR */
3445 PORTCR(174, 0xe60520ae), /* PORT174CR */
3446 PORTCR(175, 0xe60520af), /* PORT175CR */
3447 PORTCR(176, 0xe60520b0), /* PORT176CR */
3448 PORTCR(177, 0xe60520b1), /* PORT177CR */
3449 PORTCR(178, 0xe60520b2), /* PORT178CR */
3450 PORTCR(179, 0xe60520b3), /* PORT179CR */
3451 PORTCR(180, 0xe60520b4), /* PORT180CR */
3452 PORTCR(181, 0xe60520b5), /* PORT181CR */
3453 PORTCR(182, 0xe60520b6), /* PORT182CR */
3454 PORTCR(183, 0xe60520b7), /* PORT183CR */
3455 PORTCR(184, 0xe60520b8), /* PORT184CR */
3456 PORTCR(185, 0xe60520b9), /* PORT185CR */
3457 PORTCR(186, 0xe60520ba), /* PORT186CR */
3458 PORTCR(187, 0xe60520bb), /* PORT187CR */
3459 PORTCR(188, 0xe60520bc), /* PORT188CR */
3460 PORTCR(189, 0xe60520bd), /* PORT189CR */
3461 PORTCR(190, 0xe60520be), /* PORT190CR */
3462 PORTCR(191, 0xe60520bf), /* PORT191CR */
3463 PORTCR(192, 0xe60520c0), /* PORT192CR */
3464 PORTCR(193, 0xe60520c1), /* PORT193CR */
3465 PORTCR(194, 0xe60520c2), /* PORT194CR */
3466 PORTCR(195, 0xe60520c3), /* PORT195CR */
3467 PORTCR(196, 0xe60520c4), /* PORT196CR */
3468 PORTCR(197, 0xe60520c5), /* PORT197CR */
3469 PORTCR(198, 0xe60520c6), /* PORT198CR */
3470 PORTCR(199, 0xe60520c7), /* PORT199CR */
3471 PORTCR(200, 0xe60520c8), /* PORT200CR */
3472 PORTCR(201, 0xe60520c9), /* PORT201CR */
3473 PORTCR(202, 0xe60520ca), /* PORT202CR */
3474 PORTCR(203, 0xe60520cb), /* PORT203CR */
3475 PORTCR(204, 0xe60520cc), /* PORT204CR */
3476 PORTCR(205, 0xe60520cd), /* PORT205CR */
3477 PORTCR(206, 0xe60520ce), /* PORT206CR */
3478 PORTCR(207, 0xe60520cf), /* PORT207CR */
3479 PORTCR(208, 0xe60520d0), /* PORT208CR */
3480 PORTCR(209, 0xe60520d1), /* PORT209CR */
3481
3482 PORTCR(210, 0xe60530d2), /* PORT210CR */
3483 PORTCR(211, 0xe60530d3), /* PORT211CR */
3484
3485 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
3486 MSEL1CR_31_0, MSEL1CR_31_1,
3487 MSEL1CR_30_0, MSEL1CR_30_1,
3488 MSEL1CR_29_0, MSEL1CR_29_1,
3489 MSEL1CR_28_0, MSEL1CR_28_1,
3490 MSEL1CR_27_0, MSEL1CR_27_1,
3491 MSEL1CR_26_0, MSEL1CR_26_1,
3492 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3493 0, 0, 0, 0, 0, 0, 0, 0,
3494 MSEL1CR_16_0, MSEL1CR_16_1,
3495 MSEL1CR_15_0, MSEL1CR_15_1,
3496 MSEL1CR_14_0, MSEL1CR_14_1,
3497 MSEL1CR_13_0, MSEL1CR_13_1,
3498 MSEL1CR_12_0, MSEL1CR_12_1,
3499 0, 0, 0, 0,
3500 MSEL1CR_9_0, MSEL1CR_9_1,
3501 0, 0,
3502 MSEL1CR_7_0, MSEL1CR_7_1,
3503 MSEL1CR_6_0, MSEL1CR_6_1,
3504 MSEL1CR_5_0, MSEL1CR_5_1,
3505 MSEL1CR_4_0, MSEL1CR_4_1,
3506 MSEL1CR_3_0, MSEL1CR_3_1,
3507 MSEL1CR_2_0, MSEL1CR_2_1,
3508 0, 0,
3509 MSEL1CR_0_0, MSEL1CR_0_1,
3510 }
3511 },
3512 { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
3513 0, 0, 0, 0, 0, 0, 0, 0,
3514 0, 0, 0, 0, 0, 0, 0, 0,
3515 0, 0, 0, 0, 0, 0, 0, 0,
3516 0, 0, 0, 0, 0, 0, 0, 0,
3517 MSEL3CR_15_0, MSEL3CR_15_1,
3518 0, 0, 0, 0, 0, 0, 0, 0,
3519 0, 0, 0, 0, 0, 0, 0, 0,
3520 MSEL3CR_6_0, MSEL3CR_6_1,
3521 0, 0, 0, 0, 0, 0, 0, 0,
3522 0, 0, 0, 0,
3523 }
3524 },
3525 { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
3526 0, 0, 0, 0, 0, 0, 0, 0,
3527 0, 0, 0, 0, 0, 0, 0, 0,
3528 0, 0, 0, 0, 0, 0, 0, 0,
3529 MSEL4CR_19_0, MSEL4CR_19_1,
3530 MSEL4CR_18_0, MSEL4CR_18_1,
3531 0, 0, 0, 0,
3532 MSEL4CR_15_0, MSEL4CR_15_1,
3533 0, 0, 0, 0, 0, 0, 0, 0,
3534 MSEL4CR_10_0, MSEL4CR_10_1,
3535 0, 0, 0, 0, 0, 0,
3536 MSEL4CR_6_0, MSEL4CR_6_1,
3537 0, 0,
3538 MSEL4CR_4_0, MSEL4CR_4_1,
3539 0, 0, 0, 0,
3540 MSEL4CR_1_0, MSEL4CR_1_1,
3541 0, 0,
3542 }
3543 },
3544 { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
3545 MSEL5CR_31_0, MSEL5CR_31_1,
3546 MSEL5CR_30_0, MSEL5CR_30_1,
3547 MSEL5CR_29_0, MSEL5CR_29_1,
3548 0, 0,
3549 MSEL5CR_27_0, MSEL5CR_27_1,
3550 0, 0,
3551 MSEL5CR_25_0, MSEL5CR_25_1,
3552 0, 0,
3553 MSEL5CR_23_0, MSEL5CR_23_1,
3554 0, 0,
3555 MSEL5CR_21_0, MSEL5CR_21_1,
3556 0, 0,
3557 MSEL5CR_19_0, MSEL5CR_19_1,
3558 0, 0,
3559 MSEL5CR_17_0, MSEL5CR_17_1,
3560 0, 0,
3561 MSEL5CR_15_0, MSEL5CR_15_1,
3562 MSEL5CR_14_0, MSEL5CR_14_1,
3563 MSEL5CR_13_0, MSEL5CR_13_1,
3564 MSEL5CR_12_0, MSEL5CR_12_1,
3565 MSEL5CR_11_0, MSEL5CR_11_1,
3566 MSEL5CR_10_0, MSEL5CR_10_1,
3567 0, 0,
3568 MSEL5CR_8_0, MSEL5CR_8_1,
3569 MSEL5CR_7_0, MSEL5CR_7_1,
3570 MSEL5CR_6_0, MSEL5CR_6_1,
3571 MSEL5CR_5_0, MSEL5CR_5_1,
3572 MSEL5CR_4_0, MSEL5CR_4_1,
3573 MSEL5CR_3_0, MSEL5CR_3_1,
3574 MSEL5CR_2_0, MSEL5CR_2_1,
3575 0, 0,
3576 MSEL5CR_0_0, MSEL5CR_0_1,
3577 }
3578 },
3579 { },
3580};
3581
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3582static const struct pinmux_data_reg pinmux_data_regs[] = {
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3583 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
3584 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
3585 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
3586 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
3587 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
3588 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
3589 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
3590 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
3591 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
3592 },
3593 { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
3594 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
3595 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
3596 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
3597 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
3598 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
3599 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
3600 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
3601 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
3602 },
3603 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
3604 0, 0, 0, 0,
3605 0, 0, 0, 0,
3606 0, 0, 0, 0,
3607 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
3608 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
3609 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
3610 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
3611 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
3612 },
3613 { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
3614 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
3615 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
3616 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
3617 0, 0, 0, 0,
3618 0, 0, 0, 0,
3619 0, 0, 0, 0,
3620 0, 0, 0, 0,
3621 0, 0, 0, 0 }
3622 },
3623 { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
3624 0, 0, 0, 0,
3625 0, 0, 0, 0,
3626 0, 0, 0, 0,
3627 0, PORT114_DATA, PORT113_DATA, PORT112_DATA,
3628 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
3629 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
3630 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
3631 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
3632 },
3633 { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
3634 PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
3635 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
3636 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
3637 PORT115_DATA, 0, 0, 0,
3638 0, 0, 0, 0,
3639 0, 0, 0, 0,
3640 0, 0, 0, 0,
3641 0, 0, 0, 0 }
3642 },
3643 { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
3644 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
3645 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
3646 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
3647 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
3648 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
3649 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
3650 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
3651 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
3652 },
3653 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
3654 PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
3655 PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
3656 PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
3657 PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
3658 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
3659 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
3660 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
3661 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
3662 },
3663 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
3664 0, 0, 0, 0,
3665 0, 0, 0, 0,
3666 0, 0, 0, 0,
3667 0, 0, PORT209_DATA, PORT208_DATA,
3668 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
3669 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
3670 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
3671 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
3672 },
3673 { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
3674 0, 0, 0, 0,
3675 0, 0, 0, 0,
3676 0, 0, 0, 0,
3677 PORT211_DATA, PORT210_DATA, 0, 0,
3678 0, 0, 0, 0,
3679 0, 0, 0, 0,
3680 0, 0, 0, 0,
3681 0, 0, 0, 0 }
3682 },
3683 { },
3684};
3685
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3686static const struct pinmux_irq pinmux_irqs[] = {
Bastian Hecht0b7d7822013-03-27 14:54:04 +0100[diff] [blame]3687 PINMUX_IRQ(irq_pin(0), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */
3688 PINMUX_IRQ(irq_pin(1), GPIO_PORT20), /* IRQ1A */
3689 PINMUX_IRQ(irq_pin(2), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */
3690 PINMUX_IRQ(irq_pin(3), GPIO_PORT10, GPIO_PORT14), /* IRQ3A */
3691 PINMUX_IRQ(irq_pin(4), GPIO_PORT15, GPIO_PORT172),/* IRQ4A */
3692 PINMUX_IRQ(irq_pin(5), GPIO_PORT0, GPIO_PORT1), /* IRQ5A */
3693 PINMUX_IRQ(irq_pin(6), GPIO_PORT121, GPIO_PORT173),/* IRQ6A */
3694 PINMUX_IRQ(irq_pin(7), GPIO_PORT120, GPIO_PORT209),/* IRQ7A */
3695 PINMUX_IRQ(irq_pin(8), GPIO_PORT119), /* IRQ8A */
3696 PINMUX_IRQ(irq_pin(9), GPIO_PORT118, GPIO_PORT210),/* IRQ9A */
3697 PINMUX_IRQ(irq_pin(10), GPIO_PORT19), /* IRQ10A */
3698 PINMUX_IRQ(irq_pin(11), GPIO_PORT104), /* IRQ11A */
3699 PINMUX_IRQ(irq_pin(12), GPIO_PORT42, GPIO_PORT97), /* IRQ12A */
3700 PINMUX_IRQ(irq_pin(13), GPIO_PORT64, GPIO_PORT98), /* IRQ13A */
3701 PINMUX_IRQ(irq_pin(14), GPIO_PORT63, GPIO_PORT99), /* IRQ14A */
3702 PINMUX_IRQ(irq_pin(15), GPIO_PORT62, GPIO_PORT100),/* IRQ15A */
3703 PINMUX_IRQ(irq_pin(16), GPIO_PORT68, GPIO_PORT211),/* IRQ16A */
3704 PINMUX_IRQ(irq_pin(17), GPIO_PORT69), /* IRQ17A */
3705 PINMUX_IRQ(irq_pin(18), GPIO_PORT70), /* IRQ18A */
3706 PINMUX_IRQ(irq_pin(19), GPIO_PORT71), /* IRQ19A */
3707 PINMUX_IRQ(irq_pin(20), GPIO_PORT67), /* IRQ20A */
3708 PINMUX_IRQ(irq_pin(21), GPIO_PORT202), /* IRQ21A */
3709 PINMUX_IRQ(irq_pin(22), GPIO_PORT95), /* IRQ22A */
3710 PINMUX_IRQ(irq_pin(23), GPIO_PORT96), /* IRQ23A */
3711 PINMUX_IRQ(irq_pin(24), GPIO_PORT180), /* IRQ24A */
3712 PINMUX_IRQ(irq_pin(25), GPIO_PORT38), /* IRQ25A */
3713 PINMUX_IRQ(irq_pin(26), GPIO_PORT58, GPIO_PORT81), /* IRQ26A */
3714 PINMUX_IRQ(irq_pin(27), GPIO_PORT57, GPIO_PORT168),/* IRQ27A */
3715 PINMUX_IRQ(irq_pin(28), GPIO_PORT56, GPIO_PORT169),/* IRQ28A */
3716 PINMUX_IRQ(irq_pin(29), GPIO_PORT50, GPIO_PORT170),/* IRQ29A */
3717 PINMUX_IRQ(irq_pin(30), GPIO_PORT49, GPIO_PORT171),/* IRQ30A */
3718 PINMUX_IRQ(irq_pin(31), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3719};
3720
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3721const struct sh_pfc_soc_info r8a7740_pinmux_info = {
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3722 .name = "r8a7740_pfc",
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3723 .input = { PINMUX_INPUT_BEGIN,
3724 PINMUX_INPUT_END },
3725 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
3726 PINMUX_INPUT_PULLUP_END },
3727 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN,
3728 PINMUX_INPUT_PULLDOWN_END },
3729 .output = { PINMUX_OUTPUT_BEGIN,
3730 PINMUX_OUTPUT_END },
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3731 .function = { PINMUX_FUNCTION_BEGIN,
3732 PINMUX_FUNCTION_END },
3733
Laurent Pincharta373ed02012-11-29 13:24:07 +0100[diff] [blame]3734 .pins = pinmux_pins,
3735 .nr_pins = ARRAY_SIZE(pinmux_pins),
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]3736 .groups = pinmux_groups,
3737 .nr_groups = ARRAY_SIZE(pinmux_groups),
3738 .functions = pinmux_functions,
3739 .nr_functions = ARRAY_SIZE(pinmux_functions),
3740
Laurent Pincharta373ed02012-11-29 13:24:07 +0100[diff] [blame]3741 .func_gpios = pinmux_func_gpios,
3742 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
Laurent Pinchartd7a7ca52012-11-28 17:51:00 +0100[diff] [blame]3743
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3744 .cfg_regs = pinmux_config_regs,
3745 .data_regs = pinmux_data_regs,
3746
3747 .gpio_data = pinmux_data,
3748 .gpio_data_size = ARRAY_SIZE(pinmux_data),
3749
3750 .gpio_irq = pinmux_irqs,
3751 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
3752};