blob: b3ac5c2e12dcc5db23dc98e05f0de08f185bbd08 [file] [log] [blame]
John Linnb85a3ef2011-06-20 11:47:27 -06001/*
2 * This file contains common code that is intended to be used across
3 * boards so that it's not replicated.
4 *
5 * Copyright (C) 2011 Xilinx
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/cpumask.h>
20#include <linux/platform_device.h>
21#include <linux/clk.h>
22#include <linux/of_irq.h>
23#include <linux/of_platform.h>
24
25#include <asm/mach/map.h>
26#include <asm/page.h>
27#include <asm/hardware/gic.h>
28#include <asm/hardware/cache-l2x0.h>
29
30#include <mach/zynq_soc.h>
31#include <mach/clkdev.h>
32#include "common.h"
33
34static struct of_device_id zynq_of_bus_ids[] __initdata = {
35 { .compatible = "simple-bus", },
36 {}
37};
38
39/**
40 * xilinx_init_machine() - System specific initialization, intended to be
41 * called from board specific initialization.
42 */
43void __init xilinx_init_machine(void)
44{
45#ifdef CONFIG_CACHE_L2X0
46 /*
47 * 64KB way size, 8-way associativity, parity disabled
48 */
49 l2x0_init(PL310_L2CC_BASE, 0x02060000, 0xF0F0FFFF);
50#endif
51
52 of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL);
53}
54
55/**
56 * xilinx_irq_init() - Interrupt controller initialization for the GIC.
57 */
58void __init xilinx_irq_init(void)
59{
60 gic_init(0, 29, SCU_GIC_DIST_BASE, SCU_GIC_CPU_BASE);
61}
62
63/* The minimum devices needed to be mapped before the VM system is up and
64 * running include the GIC, UART and Timer Counter.
65 */
66
67static struct map_desc io_desc[] __initdata = {
68 {
69 .virtual = TTC0_VIRT,
70 .pfn = __phys_to_pfn(TTC0_PHYS),
71 .length = SZ_4K,
72 .type = MT_DEVICE,
73 }, {
74 .virtual = SCU_PERIPH_VIRT,
75 .pfn = __phys_to_pfn(SCU_PERIPH_PHYS),
76 .length = SZ_8K,
77 .type = MT_DEVICE,
78 }, {
79 .virtual = PL310_L2CC_VIRT,
80 .pfn = __phys_to_pfn(PL310_L2CC_PHYS),
81 .length = SZ_4K,
82 .type = MT_DEVICE,
83 },
84
85#ifdef CONFIG_DEBUG_LL
86 {
87 .virtual = UART0_VIRT,
88 .pfn = __phys_to_pfn(UART0_PHYS),
89 .length = SZ_4K,
90 .type = MT_DEVICE,
91 },
92#endif
93
94};
95
96/**
97 * xilinx_map_io() - Create memory mappings needed for early I/O.
98 */
99void __init xilinx_map_io(void)
100{
101 iotable_init(io_desc, ARRAY_SIZE(io_desc));
102}