blob: ca8c965179b13a05f308e5bae65d7efc1ff798fc [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * pata_mpiix.c - Intel MPIIX PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * The MPIIX is different enough to the PIIX4 and friends that we give it
7 * a separate driver. The old ide/pci code handles this by just not tuning
8 * MPIIX at all.
9 *
10 * The MPIIX also differs in another important way from the majority of PIIX
11 * devices. The chip is a bridge (pardon the pun) between the old world of
12 * ISA IDE and PCI IDE. Although the ATA timings are PCI configured the actual
13 * IDE controller is not decoded in PCI space and the chip does not claim to
14 * be IDE class PCI. This requires slightly non-standard probe logic compared
15 * with PCI IDE and also that we do not disable the device when our driver is
16 * unloaded (as it has many other functions).
17 *
18 * The driver conciously keeps this logic internally to avoid pushing quirky
19 * PATA history into the clean libata layer.
20 *
Alan Coxc9619222006-09-26 17:53:38 +010021 * Thinkpad specific note: If you boot an MPIIX using a thinkpad with a PCMCIA
Jeff Garzik669a5db2006-08-29 18:12:40 -040022 * hard disk present this driver will not detect it. This is not a bug. In this
23 * configuration the secondary port of the MPIIX is disabled and the addresses
24 * are decoded by the PCMCIA bridge and therefore are for a generic IDE driver
25 * to operate.
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/init.h>
32#include <linux/blkdev.h>
33#include <linux/delay.h>
34#include <scsi/scsi_host.h>
35#include <linux/libata.h>
36
37#define DRV_NAME "pata_mpiix"
Sergei Shtylyov92ae7842007-02-05 21:08:55 +030038#define DRV_VERSION "0.7.5"
Jeff Garzik669a5db2006-08-29 18:12:40 -040039
40enum {
41 IDETIM = 0x6C, /* IDE control register */
42 IORDY = (1 << 1),
43 PPE = (1 << 2),
44 FTIM = (1 << 0),
45 ENABLED = (1 << 15),
46 SECONDARY = (1 << 14)
47};
48
49static int mpiix_pre_reset(struct ata_port *ap)
50{
51 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Sergei Shtylyov92ae7842007-02-05 21:08:55 +030052 static const struct pci_bits mpiix_enable_bits = { 0x6D, 1, 0x80, 0x80 };
Jeff Garzik669a5db2006-08-29 18:12:40 -040053
Sergei Shtylyov92ae7842007-02-05 21:08:55 +030054 if (!pci_test_config_bits(pdev, &mpiix_enable_bits))
Alan Coxc9619222006-09-26 17:53:38 +010055 return -ENOENT;
Jeff Garzik669a5db2006-08-29 18:12:40 -040056 ap->cbl = ATA_CBL_PATA40;
57 return ata_std_prereset(ap);
58}
59
60/**
61 * mpiix_error_handler - probe reset
62 * @ap: ATA port
63 *
64 * Perform the ATA probe and bus reset sequence plus specific handling
65 * for this hardware. The MPIIX has the enable bits in a different place
66 * to PIIX4 and friends. As a pure PIO device it has no cable detect
67 */
68
69static void mpiix_error_handler(struct ata_port *ap)
70{
71 ata_bmdma_drive_eh(ap, mpiix_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
72}
73
74/**
75 * mpiix_set_piomode - set initial PIO mode data
76 * @ap: ATA interface
77 * @adev: ATA device
78 *
79 * Called to do the PIO mode setup. The MPIIX allows us to program the
Sergei Shtylyov7b4f1a12007-02-05 20:24:57 +030080 * IORDY sample point (2-5 clocks), recovery (1-4 clocks) and whether
81 * prefetching or IORDY are used.
Jeff Garzik669a5db2006-08-29 18:12:40 -040082 *
83 * This would get very ugly because we can only program timing for one
84 * device at a time, the other gets PIO0. Fortunately libata calls
85 * our qc_issue_prot command before a command is issued so we can
86 * flip the timings back and forth to reduce the pain.
87 */
88
89static void mpiix_set_piomode(struct ata_port *ap, struct ata_device *adev)
90{
91 int control = 0;
92 int pio = adev->pio_mode - XFER_PIO_0;
93 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
94 u16 idetim;
95 static const /* ISP RTC */
96 u8 timings[][2] = { { 0, 0 },
97 { 0, 0 },
98 { 1, 0 },
99 { 2, 1 },
100 { 2, 3 }, };
101
102 pci_read_config_word(pdev, IDETIM, &idetim);
Sergei Shtylyov7b4f1a12007-02-05 20:24:57 +0300103
104 /* Mask the IORDY/TIME/PPE for this device */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400105 if (adev->class == ATA_DEV_ATA)
Sergei Shtylyov7b4f1a12007-02-05 20:24:57 +0300106 control |= PPE; /* Enable prefetch/posting for disk */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400107 if (ata_pio_need_iordy(adev))
Sergei Shtylyov7b4f1a12007-02-05 20:24:57 +0300108 control |= IORDY;
109 if (pio > 1)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400110 control |= FTIM; /* This drive is on the fast timing bank */
111
112 /* Mask out timing and clear both TIME bank selects */
113 idetim &= 0xCCEE;
Sergei Shtylyov7b4f1a12007-02-05 20:24:57 +0300114 idetim &= ~(0x07 << (4 * adev->devno));
115 idetim |= control << (4 * adev->devno);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400116
117 idetim |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
118 pci_write_config_word(pdev, IDETIM, idetim);
119
120 /* We use ap->private_data as a pointer to the device currently
121 loaded for timing */
122 ap->private_data = adev;
123}
124
125/**
126 * mpiix_qc_issue_prot - command issue
127 * @qc: command pending
128 *
129 * Called when the libata layer is about to issue a command. We wrap
130 * this interface so that we can load the correct ATA timings if
131 * neccessary. Our logic also clears TIME0/TIME1 for the other device so
132 * that, even if we get this wrong, cycles to the other device will
133 * be made PIO0.
134 */
135
136static unsigned int mpiix_qc_issue_prot(struct ata_queued_cmd *qc)
137{
138 struct ata_port *ap = qc->ap;
139 struct ata_device *adev = qc->dev;
140
141 /* If modes have been configured and the channel data is not loaded
142 then load it. We have to check if pio_mode is set as the core code
143 does not set adev->pio_mode to XFER_PIO_0 while probing as would be
144 logical */
145
146 if (adev->pio_mode && adev != ap->private_data)
147 mpiix_set_piomode(ap, adev);
148
149 return ata_qc_issue_prot(qc);
150}
151
152static struct scsi_host_template mpiix_sht = {
153 .module = THIS_MODULE,
154 .name = DRV_NAME,
155 .ioctl = ata_scsi_ioctl,
156 .queuecommand = ata_scsi_queuecmd,
157 .can_queue = ATA_DEF_QUEUE,
158 .this_id = ATA_SHT_THIS_ID,
159 .sg_tablesize = LIBATA_MAX_PRD,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400160 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
161 .emulated = ATA_SHT_EMULATED,
162 .use_clustering = ATA_SHT_USE_CLUSTERING,
163 .proc_name = DRV_NAME,
164 .dma_boundary = ATA_DMA_BOUNDARY,
165 .slave_configure = ata_scsi_slave_config,
Tejun Heoafdfe892006-11-29 11:26:47 +0900166 .slave_destroy = ata_scsi_slave_destroy,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400167 .bios_param = ata_std_bios_param,
Alan30ced0f2006-11-22 16:57:36 +0000168 .resume = ata_scsi_device_resume,
169 .suspend = ata_scsi_device_suspend,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400170};
171
172static struct ata_port_operations mpiix_port_ops = {
173 .port_disable = ata_port_disable,
174 .set_piomode = mpiix_set_piomode,
175
176 .tf_load = ata_tf_load,
177 .tf_read = ata_tf_read,
178 .check_status = ata_check_status,
179 .exec_command = ata_exec_command,
180 .dev_select = ata_std_dev_select,
181
182 .freeze = ata_bmdma_freeze,
183 .thaw = ata_bmdma_thaw,
184 .error_handler = mpiix_error_handler,
185 .post_internal_cmd = ata_bmdma_post_internal_cmd,
186
187 .qc_prep = ata_qc_prep,
188 .qc_issue = mpiix_qc_issue_prot,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900189 .data_xfer = ata_data_xfer,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400190
191 .irq_handler = ata_interrupt,
192 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900193 .irq_on = ata_irq_on,
194 .irq_ack = ata_irq_ack,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400195
196 .port_start = ata_port_start,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400197};
198
199static int mpiix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
200{
201 /* Single threaded by the PCI probe logic */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900202 static struct ata_probe_ent probe;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400203 static int printed_version;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900204 void __iomem *cmd_addr, *ctl_addr;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400205 u16 idetim;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900206 int irq;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400207
208 if (!printed_version++)
209 dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
210
211 /* MPIIX has many functions which can be turned on or off according
212 to other devices present. Make sure IDE is enabled before we try
213 and use it */
214
215 pci_read_config_word(dev, IDETIM, &idetim);
216 if (!(idetim & ENABLED))
217 return -ENODEV;
218
Sergei Shtylyov92ae7842007-02-05 21:08:55 +0300219 /* See if it's primary or secondary channel... */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900220 if (!(idetim & SECONDARY)) {
221 irq = 14;
222 cmd_addr = devm_ioport_map(&dev->dev, 0x1F0, 8);
223 ctl_addr = devm_ioport_map(&dev->dev, 0x3F6, 1);
224 } else {
225 irq = 15;
226 cmd_addr = devm_ioport_map(&dev->dev, 0x170, 8);
227 ctl_addr = devm_ioport_map(&dev->dev, 0x376, 1);
228 }
229
230 if (!cmd_addr || !ctl_addr)
231 return -ENOMEM;
232
Jeff Garzik669a5db2006-08-29 18:12:40 -0400233 /* We do our own plumbing to avoid leaking special cases for whacko
234 ancient hardware into the core code. There are two issues to
235 worry about. #1 The chip is a bridge so if in legacy mode and
236 without BARs set fools the setup. #2 If you pci_disable_device
237 the MPIIX your box goes castors up */
238
Tejun Heo0d5ff562007-02-01 15:06:36 +0900239 INIT_LIST_HEAD(&probe.node);
240 probe.dev = pci_dev_to_dev(dev);
241 probe.port_ops = &mpiix_port_ops;
242 probe.sht = &mpiix_sht;
243 probe.pio_mask = 0x1F;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900244 probe.irq_flags = SA_SHIRQ;
245 probe.port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST;
246 probe.n_ports = 1;
Sergei Shtylyov92ae7842007-02-05 21:08:55 +0300247
248 probe.irq = irq;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900249 probe.port[0].cmd_addr = cmd_addr;
250 probe.port[0].ctl_addr = ctl_addr;
251 probe.port[0].altstatus_addr = ctl_addr;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400252
253 /* Let libata fill in the port details */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900254 ata_std_ports(&probe.port[0]);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400255
256 /* Now add the port that is active */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900257 if (ata_device_add(&probe))
Jeff Garzik669a5db2006-08-29 18:12:40 -0400258 return 0;
259 return -ENODEV;
260}
261
Jeff Garzik669a5db2006-08-29 18:12:40 -0400262static const struct pci_device_id mpiix[] = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400263 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), },
264
265 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400266};
267
268static struct pci_driver mpiix_pci_driver = {
269 .name = DRV_NAME,
270 .id_table = mpiix,
271 .probe = mpiix_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900272 .remove = ata_pci_remove_one,
Alan30ced0f2006-11-22 16:57:36 +0000273 .suspend = ata_pci_device_suspend,
274 .resume = ata_pci_device_resume,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400275};
276
277static int __init mpiix_init(void)
278{
279 return pci_register_driver(&mpiix_pci_driver);
280}
281
Jeff Garzik669a5db2006-08-29 18:12:40 -0400282static void __exit mpiix_exit(void)
283{
284 pci_unregister_driver(&mpiix_pci_driver);
285}
286
Jeff Garzik669a5db2006-08-29 18:12:40 -0400287MODULE_AUTHOR("Alan Cox");
288MODULE_DESCRIPTION("low-level driver for Intel MPIIX");
289MODULE_LICENSE("GPL");
290MODULE_DEVICE_TABLE(pci, mpiix);
291MODULE_VERSION(DRV_VERSION);
292
293module_init(mpiix_init);
294module_exit(mpiix_exit);