Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / b970b41ea68ace17f389c8387c1df4a86aa039a0 / . / arch / m68k / coldfire / m525x.c
blob: 3d8583e2187c5bf135685cf5a325852e721823e1 [file] [log] [blame]
Steven King04e037a2012-06-05 08:23:08 -0700[diff] [blame]1/***************************************************************************/
2
3/*
Greg Ungererece9ae62014-08-19 11:55:24 +1000[diff] [blame]4 * 525x.c -- platform support for ColdFire 525x based boards
Steven King04e037a2012-06-05 08:23:08 -0700[diff] [blame]5 *
6 * Copyright (C) 2012, Steven King <sfking@fdwdc.com>
7 */
8
9/***************************************************************************/
10
11#include <linux/kernel.h>
12#include <linux/param.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <asm/machdep.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
Greg Ungerer5847c472012-07-13 15:59:26 +1000[diff] [blame]19#include <asm/mcfclk.h>
20
21/***************************************************************************/
22
23DEFINE_CLK(pll, "pll.0", MCF_CLK);
24DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
25DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
26DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
27DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
28DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
Steven King74859522014-05-14 10:06:29 -0700[diff] [blame]29DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
Greg Ungerer5847c472012-07-13 15:59:26 +1000[diff] [blame]30
31struct clk *mcf_clks[] = {
32 &clk_pll,
33 &clk_sys,
34 &clk_mcftmr0,
35 &clk_mcftmr1,
36 &clk_mcfuart0,
37 &clk_mcfuart1,
Steven King74859522014-05-14 10:06:29 -0700[diff] [blame]38 &clk_mcfqspi0,
Greg Ungerer5847c472012-07-13 15:59:26 +1000[diff] [blame]39 NULL
40};
Steven King04e037a2012-06-05 08:23:08 -0700[diff] [blame]41
42/***************************************************************************/
43
44static void __init m525x_qspi_init(void)
45{
46#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
47 /* set the GPIO function for the qspi cs gpios */
48 /* FIXME: replace with pinmux/pinctl support */
49 u32 f = readl(MCFSIM2_GPIOFUNC);
50 f |= (1 << MCFQSPI_CS2) | (1 << MCFQSPI_CS1) | (1 << MCFQSPI_CS0);
51 writel(f, MCFSIM2_GPIOFUNC);
52
53 /* QSPI irq setup */
54 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
Greg Ungererc986a3d2012-08-17 16:48:16 +1000[diff] [blame]55 MCFSIM_QSPIICR);
Steven King04e037a2012-06-05 08:23:08 -0700[diff] [blame]56 mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
57#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
58}
59
60static void __init m525x_i2c_init(void)
61{
62#if IS_ENABLED(CONFIG_I2C_COLDFIRE)
63 u32 r;
64
65 /* first I2C controller uses regular irq setup */
66 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
Greg Ungererc986a3d2012-08-17 16:48:16 +1000[diff] [blame]67 MCFSIM_I2CICR);
Steven King04e037a2012-06-05 08:23:08 -0700[diff] [blame]68 mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
69
70 /* second I2C controller is completely different */
71 r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
72 r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
73 r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
74 writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
75#endif /* IS_ENABLED(CONFIG_I2C_COLDFIRE) */
76}
77
78/***************************************************************************/
79
80void __init config_BSP(char *commandp, int size)
81{
82 mach_sched_init = hw_timer_init;
83
84 m525x_qspi_init();
85 m525x_i2c_init();
86}
87
88/***************************************************************************/