Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1 | /* |
| 2 | * DMA driver for Xilinx Video DMA Engine |
| 3 | * |
| 4 | * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved. |
| 5 | * |
| 6 | * Based on the Freescale DMA driver. |
| 7 | * |
| 8 | * Description: |
| 9 | * The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP |
| 10 | * core that provides high-bandwidth direct memory access between memory |
| 11 | * and AXI4-Stream type video target peripherals. The core provides efficient |
| 12 | * two dimensional DMA operations with independent asynchronous read (S2MM) |
| 13 | * and write (MM2S) channel operation. It can be configured to have either |
| 14 | * one channel or two channels. If configured as two channels, one is to |
| 15 | * transmit to the video device (MM2S) and another is to receive from the |
| 16 | * video device (S2MM). Initialization, status, interrupt and management |
| 17 | * registers are accessed through an AXI4-Lite slave interface. |
| 18 | * |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 19 | * The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core that |
| 20 | * provides high-bandwidth one dimensional direct memory access between memory |
| 21 | * and AXI4-Stream target peripherals. It supports one receive and one |
| 22 | * transmit channel, both of them optional at synthesis time. |
| 23 | * |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame] | 24 | * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory |
| 25 | * Access (DMA) between a memory-mapped source address and a memory-mapped |
| 26 | * destination address. |
| 27 | * |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 28 | * This program is free software: you can redistribute it and/or modify |
| 29 | * it under the terms of the GNU General Public License as published by |
| 30 | * the Free Software Foundation, either version 2 of the License, or |
| 31 | * (at your option) any later version. |
| 32 | */ |
| 33 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 34 | #include <linux/bitops.h> |
| 35 | #include <linux/dmapool.h> |
Kedareswara rao Appana | 937abe8 | 2015-03-02 23:24:24 +0530 | [diff] [blame] | 36 | #include <linux/dma/xilinx_dma.h> |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 37 | #include <linux/init.h> |
| 38 | #include <linux/interrupt.h> |
| 39 | #include <linux/io.h> |
Kedareswara rao Appana | 9495f26 | 2016-02-26 19:33:54 +0530 | [diff] [blame] | 40 | #include <linux/iopoll.h> |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 41 | #include <linux/module.h> |
| 42 | #include <linux/of_address.h> |
| 43 | #include <linux/of_dma.h> |
| 44 | #include <linux/of_platform.h> |
| 45 | #include <linux/of_irq.h> |
| 46 | #include <linux/slab.h> |
Kedareswara rao Appana | ba16db3 | 2016-05-13 12:33:31 +0530 | [diff] [blame^] | 47 | #include <linux/clk.h> |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 48 | |
| 49 | #include "../dmaengine.h" |
| 50 | |
| 51 | /* Register/Descriptor Offsets */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 52 | #define XILINX_DMA_MM2S_CTRL_OFFSET 0x0000 |
| 53 | #define XILINX_DMA_S2MM_CTRL_OFFSET 0x0030 |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 54 | #define XILINX_VDMA_MM2S_DESC_OFFSET 0x0050 |
| 55 | #define XILINX_VDMA_S2MM_DESC_OFFSET 0x00a0 |
| 56 | |
| 57 | /* Control Registers */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 58 | #define XILINX_DMA_REG_DMACR 0x0000 |
| 59 | #define XILINX_DMA_DMACR_DELAY_MAX 0xff |
| 60 | #define XILINX_DMA_DMACR_DELAY_SHIFT 24 |
| 61 | #define XILINX_DMA_DMACR_FRAME_COUNT_MAX 0xff |
| 62 | #define XILINX_DMA_DMACR_FRAME_COUNT_SHIFT 16 |
| 63 | #define XILINX_DMA_DMACR_ERR_IRQ BIT(14) |
| 64 | #define XILINX_DMA_DMACR_DLY_CNT_IRQ BIT(13) |
| 65 | #define XILINX_DMA_DMACR_FRM_CNT_IRQ BIT(12) |
| 66 | #define XILINX_DMA_DMACR_MASTER_SHIFT 8 |
| 67 | #define XILINX_DMA_DMACR_FSYNCSRC_SHIFT 5 |
| 68 | #define XILINX_DMA_DMACR_FRAMECNT_EN BIT(4) |
| 69 | #define XILINX_DMA_DMACR_GENLOCK_EN BIT(3) |
| 70 | #define XILINX_DMA_DMACR_RESET BIT(2) |
| 71 | #define XILINX_DMA_DMACR_CIRC_EN BIT(1) |
| 72 | #define XILINX_DMA_DMACR_RUNSTOP BIT(0) |
| 73 | #define XILINX_DMA_DMACR_FSYNCSRC_MASK GENMASK(6, 5) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 74 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 75 | #define XILINX_DMA_REG_DMASR 0x0004 |
| 76 | #define XILINX_DMA_DMASR_EOL_LATE_ERR BIT(15) |
| 77 | #define XILINX_DMA_DMASR_ERR_IRQ BIT(14) |
| 78 | #define XILINX_DMA_DMASR_DLY_CNT_IRQ BIT(13) |
| 79 | #define XILINX_DMA_DMASR_FRM_CNT_IRQ BIT(12) |
| 80 | #define XILINX_DMA_DMASR_SOF_LATE_ERR BIT(11) |
| 81 | #define XILINX_DMA_DMASR_SG_DEC_ERR BIT(10) |
| 82 | #define XILINX_DMA_DMASR_SG_SLV_ERR BIT(9) |
| 83 | #define XILINX_DMA_DMASR_EOF_EARLY_ERR BIT(8) |
| 84 | #define XILINX_DMA_DMASR_SOF_EARLY_ERR BIT(7) |
| 85 | #define XILINX_DMA_DMASR_DMA_DEC_ERR BIT(6) |
| 86 | #define XILINX_DMA_DMASR_DMA_SLAVE_ERR BIT(5) |
| 87 | #define XILINX_DMA_DMASR_DMA_INT_ERR BIT(4) |
| 88 | #define XILINX_DMA_DMASR_IDLE BIT(1) |
| 89 | #define XILINX_DMA_DMASR_HALTED BIT(0) |
| 90 | #define XILINX_DMA_DMASR_DELAY_MASK GENMASK(31, 24) |
| 91 | #define XILINX_DMA_DMASR_FRAME_COUNT_MASK GENMASK(23, 16) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 92 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 93 | #define XILINX_DMA_REG_CURDESC 0x0008 |
| 94 | #define XILINX_DMA_REG_TAILDESC 0x0010 |
| 95 | #define XILINX_DMA_REG_REG_INDEX 0x0014 |
| 96 | #define XILINX_DMA_REG_FRMSTORE 0x0018 |
| 97 | #define XILINX_DMA_REG_THRESHOLD 0x001c |
| 98 | #define XILINX_DMA_REG_FRMPTR_STS 0x0024 |
| 99 | #define XILINX_DMA_REG_PARK_PTR 0x0028 |
| 100 | #define XILINX_DMA_PARK_PTR_WR_REF_SHIFT 8 |
| 101 | #define XILINX_DMA_PARK_PTR_RD_REF_SHIFT 0 |
| 102 | #define XILINX_DMA_REG_VDMA_VERSION 0x002c |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 103 | |
| 104 | /* Register Direct Mode Registers */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 105 | #define XILINX_DMA_REG_VSIZE 0x0000 |
| 106 | #define XILINX_DMA_REG_HSIZE 0x0004 |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 107 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 108 | #define XILINX_DMA_REG_FRMDLY_STRIDE 0x0008 |
| 109 | #define XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT 24 |
| 110 | #define XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT 0 |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 111 | |
| 112 | #define XILINX_VDMA_REG_START_ADDRESS(n) (0x000c + 4 * (n)) |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 113 | #define XILINX_VDMA_REG_START_ADDRESS_64(n) (0x000c + 8 * (n)) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 114 | |
| 115 | /* HW specific definitions */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 116 | #define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x2 |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 117 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 118 | #define XILINX_DMA_DMAXR_ALL_IRQ_MASK \ |
| 119 | (XILINX_DMA_DMASR_FRM_CNT_IRQ | \ |
| 120 | XILINX_DMA_DMASR_DLY_CNT_IRQ | \ |
| 121 | XILINX_DMA_DMASR_ERR_IRQ) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 122 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 123 | #define XILINX_DMA_DMASR_ALL_ERR_MASK \ |
| 124 | (XILINX_DMA_DMASR_EOL_LATE_ERR | \ |
| 125 | XILINX_DMA_DMASR_SOF_LATE_ERR | \ |
| 126 | XILINX_DMA_DMASR_SG_DEC_ERR | \ |
| 127 | XILINX_DMA_DMASR_SG_SLV_ERR | \ |
| 128 | XILINX_DMA_DMASR_EOF_EARLY_ERR | \ |
| 129 | XILINX_DMA_DMASR_SOF_EARLY_ERR | \ |
| 130 | XILINX_DMA_DMASR_DMA_DEC_ERR | \ |
| 131 | XILINX_DMA_DMASR_DMA_SLAVE_ERR | \ |
| 132 | XILINX_DMA_DMASR_DMA_INT_ERR) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 133 | |
| 134 | /* |
| 135 | * Recoverable errors are DMA Internal error, SOF Early, EOF Early |
| 136 | * and SOF Late. They are only recoverable when C_FLUSH_ON_FSYNC |
| 137 | * is enabled in the h/w system. |
| 138 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 139 | #define XILINX_DMA_DMASR_ERR_RECOVER_MASK \ |
| 140 | (XILINX_DMA_DMASR_SOF_LATE_ERR | \ |
| 141 | XILINX_DMA_DMASR_EOF_EARLY_ERR | \ |
| 142 | XILINX_DMA_DMASR_SOF_EARLY_ERR | \ |
| 143 | XILINX_DMA_DMASR_DMA_INT_ERR) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 144 | |
| 145 | /* Axi VDMA Flush on Fsync bits */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 146 | #define XILINX_DMA_FLUSH_S2MM 3 |
| 147 | #define XILINX_DMA_FLUSH_MM2S 2 |
| 148 | #define XILINX_DMA_FLUSH_BOTH 1 |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 149 | |
| 150 | /* Delay loop counter to prevent hardware failure */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 151 | #define XILINX_DMA_LOOP_COUNT 1000000 |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 152 | |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 153 | /* AXI DMA Specific Registers/Offsets */ |
| 154 | #define XILINX_DMA_REG_SRCDSTADDR 0x18 |
| 155 | #define XILINX_DMA_REG_BTT 0x28 |
| 156 | |
| 157 | /* AXI DMA Specific Masks/Bit fields */ |
| 158 | #define XILINX_DMA_MAX_TRANS_LEN GENMASK(22, 0) |
| 159 | #define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16) |
| 160 | #define XILINX_DMA_CR_COALESCE_SHIFT 16 |
| 161 | #define XILINX_DMA_BD_SOP BIT(27) |
| 162 | #define XILINX_DMA_BD_EOP BIT(26) |
| 163 | #define XILINX_DMA_COALESCE_MAX 255 |
| 164 | #define XILINX_DMA_NUM_APP_WORDS 5 |
| 165 | |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame] | 166 | /* AXI CDMA Specific Registers/Offsets */ |
| 167 | #define XILINX_CDMA_REG_SRCADDR 0x18 |
| 168 | #define XILINX_CDMA_REG_DSTADDR 0x20 |
| 169 | |
| 170 | /* AXI CDMA Specific Masks */ |
| 171 | #define XILINX_CDMA_CR_SGMODE BIT(3) |
| 172 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 173 | /** |
| 174 | * struct xilinx_vdma_desc_hw - Hardware Descriptor |
| 175 | * @next_desc: Next Descriptor Pointer @0x00 |
| 176 | * @pad1: Reserved @0x04 |
| 177 | * @buf_addr: Buffer address @0x08 |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 178 | * @buf_addr_msb: MSB of Buffer address @0x0C |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 179 | * @vsize: Vertical Size @0x10 |
| 180 | * @hsize: Horizontal Size @0x14 |
| 181 | * @stride: Number of bytes between the first |
| 182 | * pixels of each horizontal line @0x18 |
| 183 | */ |
| 184 | struct xilinx_vdma_desc_hw { |
| 185 | u32 next_desc; |
| 186 | u32 pad1; |
| 187 | u32 buf_addr; |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 188 | u32 buf_addr_msb; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 189 | u32 vsize; |
| 190 | u32 hsize; |
| 191 | u32 stride; |
| 192 | } __aligned(64); |
| 193 | |
| 194 | /** |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 195 | * struct xilinx_axidma_desc_hw - Hardware Descriptor for AXI DMA |
| 196 | * @next_desc: Next Descriptor Pointer @0x00 |
| 197 | * @pad1: Reserved @0x04 |
| 198 | * @buf_addr: Buffer address @0x08 |
| 199 | * @pad2: Reserved @0x0C |
| 200 | * @pad3: Reserved @0x10 |
| 201 | * @pad4: Reserved @0x14 |
| 202 | * @control: Control field @0x18 |
| 203 | * @status: Status field @0x1C |
| 204 | * @app: APP Fields @0x20 - 0x30 |
| 205 | */ |
| 206 | struct xilinx_axidma_desc_hw { |
| 207 | u32 next_desc; |
| 208 | u32 pad1; |
| 209 | u32 buf_addr; |
| 210 | u32 pad2; |
| 211 | u32 pad3; |
| 212 | u32 pad4; |
| 213 | u32 control; |
| 214 | u32 status; |
| 215 | u32 app[XILINX_DMA_NUM_APP_WORDS]; |
| 216 | } __aligned(64); |
| 217 | |
| 218 | /** |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame] | 219 | * struct xilinx_cdma_desc_hw - Hardware Descriptor |
| 220 | * @next_desc: Next Descriptor Pointer @0x00 |
| 221 | * @pad1: Reserved @0x04 |
| 222 | * @src_addr: Source address @0x08 |
| 223 | * @pad2: Reserved @0x0C |
| 224 | * @dest_addr: Destination address @0x10 |
| 225 | * @pad3: Reserved @0x14 |
| 226 | * @control: Control field @0x18 |
| 227 | * @status: Status field @0x1C |
| 228 | */ |
| 229 | struct xilinx_cdma_desc_hw { |
| 230 | u32 next_desc; |
| 231 | u32 pad1; |
| 232 | u32 src_addr; |
| 233 | u32 pad2; |
| 234 | u32 dest_addr; |
| 235 | u32 pad3; |
| 236 | u32 control; |
| 237 | u32 status; |
| 238 | } __aligned(64); |
| 239 | |
| 240 | /** |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 241 | * struct xilinx_vdma_tx_segment - Descriptor segment |
| 242 | * @hw: Hardware descriptor |
| 243 | * @node: Node in the descriptor segments list |
| 244 | * @phys: Physical address of segment |
| 245 | */ |
| 246 | struct xilinx_vdma_tx_segment { |
| 247 | struct xilinx_vdma_desc_hw hw; |
| 248 | struct list_head node; |
| 249 | dma_addr_t phys; |
| 250 | } __aligned(64); |
| 251 | |
| 252 | /** |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 253 | * struct xilinx_axidma_tx_segment - Descriptor segment |
| 254 | * @hw: Hardware descriptor |
| 255 | * @node: Node in the descriptor segments list |
| 256 | * @phys: Physical address of segment |
| 257 | */ |
| 258 | struct xilinx_axidma_tx_segment { |
| 259 | struct xilinx_axidma_desc_hw hw; |
| 260 | struct list_head node; |
| 261 | dma_addr_t phys; |
| 262 | } __aligned(64); |
| 263 | |
| 264 | /** |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame] | 265 | * struct xilinx_cdma_tx_segment - Descriptor segment |
| 266 | * @hw: Hardware descriptor |
| 267 | * @node: Node in the descriptor segments list |
| 268 | * @phys: Physical address of segment |
| 269 | */ |
| 270 | struct xilinx_cdma_tx_segment { |
| 271 | struct xilinx_cdma_desc_hw hw; |
| 272 | struct list_head node; |
| 273 | dma_addr_t phys; |
| 274 | } __aligned(64); |
| 275 | |
| 276 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 277 | * struct xilinx_dma_tx_descriptor - Per Transaction structure |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 278 | * @async_tx: Async transaction descriptor |
| 279 | * @segments: TX segments list |
| 280 | * @node: Node in the channel descriptors list |
| 281 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 282 | struct xilinx_dma_tx_descriptor { |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 283 | struct dma_async_tx_descriptor async_tx; |
| 284 | struct list_head segments; |
| 285 | struct list_head node; |
| 286 | }; |
| 287 | |
| 288 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 289 | * struct xilinx_dma_chan - Driver specific DMA channel structure |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 290 | * @xdev: Driver specific device structure |
| 291 | * @ctrl_offset: Control registers offset |
| 292 | * @desc_offset: TX descriptor registers offset |
| 293 | * @lock: Descriptor operation lock |
| 294 | * @pending_list: Descriptors waiting |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 295 | * @active_list: Descriptors ready to submit |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 296 | * @done_list: Complete descriptors |
| 297 | * @common: DMA common channel |
| 298 | * @desc_pool: Descriptors pool |
| 299 | * @dev: The dma device |
| 300 | * @irq: Channel IRQ |
| 301 | * @id: Channel ID |
| 302 | * @direction: Transfer direction |
| 303 | * @num_frms: Number of frames |
| 304 | * @has_sg: Support scatter transfers |
| 305 | * @genlock: Support genlock mode |
| 306 | * @err: Channel has errors |
| 307 | * @tasklet: Cleanup work after irq |
| 308 | * @config: Device configuration info |
| 309 | * @flush_on_fsync: Flush on Frame sync |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 310 | * @desc_pendingcount: Descriptor pending count |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 311 | * @ext_addr: Indicates 64 bit addressing is supported by dma channel |
Kedareswara rao Appana | a65cf512 | 2016-04-06 10:38:09 +0530 | [diff] [blame] | 312 | * @desc_submitcount: Descriptor h/w submitted count |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 313 | * @residue: Residue for AXI DMA |
| 314 | * @seg_v: Statically allocated segments base |
| 315 | * @start_transfer: Differentiate b/w DMA IP's transfer |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 316 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 317 | struct xilinx_dma_chan { |
| 318 | struct xilinx_dma_device *xdev; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 319 | u32 ctrl_offset; |
| 320 | u32 desc_offset; |
| 321 | spinlock_t lock; |
| 322 | struct list_head pending_list; |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 323 | struct list_head active_list; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 324 | struct list_head done_list; |
| 325 | struct dma_chan common; |
| 326 | struct dma_pool *desc_pool; |
| 327 | struct device *dev; |
| 328 | int irq; |
| 329 | int id; |
| 330 | enum dma_transfer_direction direction; |
| 331 | int num_frms; |
| 332 | bool has_sg; |
| 333 | bool genlock; |
| 334 | bool err; |
| 335 | struct tasklet_struct tasklet; |
| 336 | struct xilinx_vdma_config config; |
| 337 | bool flush_on_fsync; |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 338 | u32 desc_pendingcount; |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 339 | bool ext_addr; |
Kedareswara rao Appana | a65cf512 | 2016-04-06 10:38:09 +0530 | [diff] [blame] | 340 | u32 desc_submitcount; |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 341 | u32 residue; |
| 342 | struct xilinx_axidma_tx_segment *seg_v; |
| 343 | void (*start_transfer)(struct xilinx_dma_chan *chan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 344 | }; |
| 345 | |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 346 | struct xilinx_dma_config { |
| 347 | enum xdma_ip_type dmatype; |
Kedareswara rao Appana | ba16db3 | 2016-05-13 12:33:31 +0530 | [diff] [blame^] | 348 | int (*clk_init)(struct platform_device *pdev, struct clk **axi_clk, |
| 349 | struct clk **tx_clk, struct clk **txs_clk, |
| 350 | struct clk **rx_clk, struct clk **rxs_clk); |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 351 | }; |
| 352 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 353 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 354 | * struct xilinx_dma_device - DMA device structure |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 355 | * @regs: I/O mapped base address |
| 356 | * @dev: Device Structure |
| 357 | * @common: DMA device structure |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 358 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 359 | * @has_sg: Specifies whether Scatter-Gather is present or not |
| 360 | * @flush_on_fsync: Flush on frame sync |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 361 | * @ext_addr: Indicates 64 bit addressing is supported by dma device |
Kedareswara rao Appana | ba16db3 | 2016-05-13 12:33:31 +0530 | [diff] [blame^] | 362 | * @pdev: Platform device structure pointer |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 363 | * @dma_config: DMA config structure |
Kedareswara rao Appana | ba16db3 | 2016-05-13 12:33:31 +0530 | [diff] [blame^] | 364 | * @axi_clk: DMA Axi4-lite interace clock |
| 365 | * @tx_clk: DMA mm2s clock |
| 366 | * @txs_clk: DMA mm2s stream clock |
| 367 | * @rx_clk: DMA s2mm clock |
| 368 | * @rxs_clk: DMA s2mm stream clock |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 369 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 370 | struct xilinx_dma_device { |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 371 | void __iomem *regs; |
| 372 | struct device *dev; |
| 373 | struct dma_device common; |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 374 | struct xilinx_dma_chan *chan[XILINX_DMA_MAX_CHANS_PER_DEVICE]; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 375 | bool has_sg; |
| 376 | u32 flush_on_fsync; |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 377 | bool ext_addr; |
Kedareswara rao Appana | ba16db3 | 2016-05-13 12:33:31 +0530 | [diff] [blame^] | 378 | struct platform_device *pdev; |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 379 | const struct xilinx_dma_config *dma_config; |
Kedareswara rao Appana | ba16db3 | 2016-05-13 12:33:31 +0530 | [diff] [blame^] | 380 | struct clk *axi_clk; |
| 381 | struct clk *tx_clk; |
| 382 | struct clk *txs_clk; |
| 383 | struct clk *rx_clk; |
| 384 | struct clk *rxs_clk; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 385 | }; |
| 386 | |
| 387 | /* Macros */ |
| 388 | #define to_xilinx_chan(chan) \ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 389 | container_of(chan, struct xilinx_dma_chan, common) |
| 390 | #define to_dma_tx_descriptor(tx) \ |
| 391 | container_of(tx, struct xilinx_dma_tx_descriptor, async_tx) |
| 392 | #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \ |
Kedareswara rao Appana | 9495f26 | 2016-02-26 19:33:54 +0530 | [diff] [blame] | 393 | readl_poll_timeout(chan->xdev->regs + chan->ctrl_offset + reg, val, \ |
| 394 | cond, delay_us, timeout_us) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 395 | |
| 396 | /* IO accessors */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 397 | static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 398 | { |
| 399 | return ioread32(chan->xdev->regs + reg); |
| 400 | } |
| 401 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 402 | static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 403 | { |
| 404 | iowrite32(value, chan->xdev->regs + reg); |
| 405 | } |
| 406 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 407 | static inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 408 | u32 value) |
| 409 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 410 | dma_write(chan, chan->desc_offset + reg, value); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 411 | } |
| 412 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 413 | static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 414 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 415 | return dma_read(chan, chan->ctrl_offset + reg); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 416 | } |
| 417 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 418 | static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 419 | u32 value) |
| 420 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 421 | dma_write(chan, chan->ctrl_offset + reg, value); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 422 | } |
| 423 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 424 | static inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 425 | u32 clr) |
| 426 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 427 | dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 428 | } |
| 429 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 430 | static inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 431 | u32 set) |
| 432 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 433 | dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 434 | } |
| 435 | |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 436 | /** |
| 437 | * vdma_desc_write_64 - 64-bit descriptor write |
| 438 | * @chan: Driver specific VDMA channel |
| 439 | * @reg: Register to write |
| 440 | * @value_lsb: lower address of the descriptor. |
| 441 | * @value_msb: upper address of the descriptor. |
| 442 | * |
| 443 | * Since vdma driver is trying to write to a register offset which is not a |
| 444 | * multiple of 64 bits(ex : 0x5c), we are writing as two separate 32 bits |
| 445 | * instead of a single 64 bit register write. |
| 446 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 447 | static inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg, |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 448 | u32 value_lsb, u32 value_msb) |
| 449 | { |
| 450 | /* Write the lsb 32 bits*/ |
| 451 | writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg); |
| 452 | |
| 453 | /* Write the msb 32 bits */ |
| 454 | writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4); |
| 455 | } |
| 456 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 457 | /* ----------------------------------------------------------------------------- |
| 458 | * Descriptors and segments alloc and free |
| 459 | */ |
| 460 | |
| 461 | /** |
| 462 | * xilinx_vdma_alloc_tx_segment - Allocate transaction segment |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 463 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 464 | * |
| 465 | * Return: The allocated segment on success and NULL on failure. |
| 466 | */ |
| 467 | static struct xilinx_vdma_tx_segment * |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 468 | xilinx_vdma_alloc_tx_segment(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 469 | { |
| 470 | struct xilinx_vdma_tx_segment *segment; |
| 471 | dma_addr_t phys; |
| 472 | |
Julia Lawall | 2ba4f8a | 2016-04-29 22:09:09 +0200 | [diff] [blame] | 473 | segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 474 | if (!segment) |
| 475 | return NULL; |
| 476 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 477 | segment->phys = phys; |
| 478 | |
| 479 | return segment; |
| 480 | } |
| 481 | |
| 482 | /** |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame] | 483 | * xilinx_cdma_alloc_tx_segment - Allocate transaction segment |
| 484 | * @chan: Driver specific DMA channel |
| 485 | * |
| 486 | * Return: The allocated segment on success and NULL on failure. |
| 487 | */ |
| 488 | static struct xilinx_cdma_tx_segment * |
| 489 | xilinx_cdma_alloc_tx_segment(struct xilinx_dma_chan *chan) |
| 490 | { |
| 491 | struct xilinx_cdma_tx_segment *segment; |
| 492 | dma_addr_t phys; |
| 493 | |
| 494 | segment = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &phys); |
| 495 | if (!segment) |
| 496 | return NULL; |
| 497 | |
| 498 | memset(segment, 0, sizeof(*segment)); |
| 499 | segment->phys = phys; |
| 500 | |
| 501 | return segment; |
| 502 | } |
| 503 | |
| 504 | /** |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 505 | * xilinx_axidma_alloc_tx_segment - Allocate transaction segment |
| 506 | * @chan: Driver specific DMA channel |
| 507 | * |
| 508 | * Return: The allocated segment on success and NULL on failure. |
| 509 | */ |
| 510 | static struct xilinx_axidma_tx_segment * |
| 511 | xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan) |
| 512 | { |
| 513 | struct xilinx_axidma_tx_segment *segment; |
| 514 | dma_addr_t phys; |
| 515 | |
| 516 | segment = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &phys); |
| 517 | if (!segment) |
| 518 | return NULL; |
| 519 | |
| 520 | memset(segment, 0, sizeof(*segment)); |
| 521 | segment->phys = phys; |
| 522 | |
| 523 | return segment; |
| 524 | } |
| 525 | |
| 526 | /** |
| 527 | * xilinx_dma_free_tx_segment - Free transaction segment |
| 528 | * @chan: Driver specific DMA channel |
| 529 | * @segment: DMA transaction segment |
| 530 | */ |
| 531 | static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan, |
| 532 | struct xilinx_axidma_tx_segment *segment) |
| 533 | { |
| 534 | dma_pool_free(chan->desc_pool, segment, segment->phys); |
| 535 | } |
| 536 | |
| 537 | /** |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame] | 538 | * xilinx_cdma_free_tx_segment - Free transaction segment |
| 539 | * @chan: Driver specific DMA channel |
| 540 | * @segment: DMA transaction segment |
| 541 | */ |
| 542 | static void xilinx_cdma_free_tx_segment(struct xilinx_dma_chan *chan, |
| 543 | struct xilinx_cdma_tx_segment *segment) |
| 544 | { |
| 545 | dma_pool_free(chan->desc_pool, segment, segment->phys); |
| 546 | } |
| 547 | |
| 548 | /** |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 549 | * xilinx_vdma_free_tx_segment - Free transaction segment |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 550 | * @chan: Driver specific DMA channel |
| 551 | * @segment: DMA transaction segment |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 552 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 553 | static void xilinx_vdma_free_tx_segment(struct xilinx_dma_chan *chan, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 554 | struct xilinx_vdma_tx_segment *segment) |
| 555 | { |
| 556 | dma_pool_free(chan->desc_pool, segment, segment->phys); |
| 557 | } |
| 558 | |
| 559 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 560 | * xilinx_dma_tx_descriptor - Allocate transaction descriptor |
| 561 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 562 | * |
| 563 | * Return: The allocated descriptor on success and NULL on failure. |
| 564 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 565 | static struct xilinx_dma_tx_descriptor * |
| 566 | xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 567 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 568 | struct xilinx_dma_tx_descriptor *desc; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 569 | |
| 570 | desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
| 571 | if (!desc) |
| 572 | return NULL; |
| 573 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 574 | INIT_LIST_HEAD(&desc->segments); |
| 575 | |
| 576 | return desc; |
| 577 | } |
| 578 | |
| 579 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 580 | * xilinx_dma_free_tx_descriptor - Free transaction descriptor |
| 581 | * @chan: Driver specific DMA channel |
| 582 | * @desc: DMA transaction descriptor |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 583 | */ |
| 584 | static void |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 585 | xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan, |
| 586 | struct xilinx_dma_tx_descriptor *desc) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 587 | { |
| 588 | struct xilinx_vdma_tx_segment *segment, *next; |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame] | 589 | struct xilinx_cdma_tx_segment *cdma_segment, *cdma_next; |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 590 | struct xilinx_axidma_tx_segment *axidma_segment, *axidma_next; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 591 | |
| 592 | if (!desc) |
| 593 | return; |
| 594 | |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 595 | if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 596 | list_for_each_entry_safe(segment, next, &desc->segments, node) { |
| 597 | list_del(&segment->node); |
| 598 | xilinx_vdma_free_tx_segment(chan, segment); |
| 599 | } |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 600 | } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame] | 601 | list_for_each_entry_safe(cdma_segment, cdma_next, |
| 602 | &desc->segments, node) { |
| 603 | list_del(&cdma_segment->node); |
| 604 | xilinx_cdma_free_tx_segment(chan, cdma_segment); |
| 605 | } |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 606 | } else { |
| 607 | list_for_each_entry_safe(axidma_segment, axidma_next, |
| 608 | &desc->segments, node) { |
| 609 | list_del(&axidma_segment->node); |
| 610 | xilinx_dma_free_tx_segment(chan, axidma_segment); |
| 611 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 612 | } |
| 613 | |
| 614 | kfree(desc); |
| 615 | } |
| 616 | |
| 617 | /* Required functions */ |
| 618 | |
| 619 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 620 | * xilinx_dma_free_desc_list - Free descriptors list |
| 621 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 622 | * @list: List to parse and delete the descriptor |
| 623 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 624 | static void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 625 | struct list_head *list) |
| 626 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 627 | struct xilinx_dma_tx_descriptor *desc, *next; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 628 | |
| 629 | list_for_each_entry_safe(desc, next, list, node) { |
| 630 | list_del(&desc->node); |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 631 | xilinx_dma_free_tx_descriptor(chan, desc); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 632 | } |
| 633 | } |
| 634 | |
| 635 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 636 | * xilinx_dma_free_descriptors - Free channel descriptors |
| 637 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 638 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 639 | static void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 640 | { |
| 641 | unsigned long flags; |
| 642 | |
| 643 | spin_lock_irqsave(&chan->lock, flags); |
| 644 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 645 | xilinx_dma_free_desc_list(chan, &chan->pending_list); |
| 646 | xilinx_dma_free_desc_list(chan, &chan->done_list); |
| 647 | xilinx_dma_free_desc_list(chan, &chan->active_list); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 648 | |
| 649 | spin_unlock_irqrestore(&chan->lock, flags); |
| 650 | } |
| 651 | |
| 652 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 653 | * xilinx_dma_free_chan_resources - Free channel resources |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 654 | * @dchan: DMA channel |
| 655 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 656 | static void xilinx_dma_free_chan_resources(struct dma_chan *dchan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 657 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 658 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 659 | |
| 660 | dev_dbg(chan->dev, "Free all channel resources.\n"); |
| 661 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 662 | xilinx_dma_free_descriptors(chan); |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 663 | if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 664 | xilinx_dma_free_tx_segment(chan, chan->seg_v); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 665 | dma_pool_destroy(chan->desc_pool); |
| 666 | chan->desc_pool = NULL; |
| 667 | } |
| 668 | |
| 669 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 670 | * xilinx_dma_chan_desc_cleanup - Clean channel descriptors |
| 671 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 672 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 673 | static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 674 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 675 | struct xilinx_dma_tx_descriptor *desc, *next; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 676 | unsigned long flags; |
| 677 | |
| 678 | spin_lock_irqsave(&chan->lock, flags); |
| 679 | |
| 680 | list_for_each_entry_safe(desc, next, &chan->done_list, node) { |
| 681 | dma_async_tx_callback callback; |
| 682 | void *callback_param; |
| 683 | |
| 684 | /* Remove from the list of running transactions */ |
| 685 | list_del(&desc->node); |
| 686 | |
| 687 | /* Run the link descriptor callback function */ |
| 688 | callback = desc->async_tx.callback; |
| 689 | callback_param = desc->async_tx.callback_param; |
| 690 | if (callback) { |
| 691 | spin_unlock_irqrestore(&chan->lock, flags); |
| 692 | callback(callback_param); |
| 693 | spin_lock_irqsave(&chan->lock, flags); |
| 694 | } |
| 695 | |
| 696 | /* Run any dependencies, then free the descriptor */ |
| 697 | dma_run_dependencies(&desc->async_tx); |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 698 | xilinx_dma_free_tx_descriptor(chan, desc); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 699 | } |
| 700 | |
| 701 | spin_unlock_irqrestore(&chan->lock, flags); |
| 702 | } |
| 703 | |
| 704 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 705 | * xilinx_dma_do_tasklet - Schedule completion tasklet |
| 706 | * @data: Pointer to the Xilinx DMA channel structure |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 707 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 708 | static void xilinx_dma_do_tasklet(unsigned long data) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 709 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 710 | struct xilinx_dma_chan *chan = (struct xilinx_dma_chan *)data; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 711 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 712 | xilinx_dma_chan_desc_cleanup(chan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 713 | } |
| 714 | |
| 715 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 716 | * xilinx_dma_alloc_chan_resources - Allocate channel resources |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 717 | * @dchan: DMA channel |
| 718 | * |
| 719 | * Return: '0' on success and failure value on error |
| 720 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 721 | static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 722 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 723 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 724 | |
| 725 | /* Has this channel already been allocated? */ |
| 726 | if (chan->desc_pool) |
| 727 | return 0; |
| 728 | |
| 729 | /* |
| 730 | * We need the descriptor to be aligned to 64bytes |
| 731 | * for meeting Xilinx VDMA specification requirement. |
| 732 | */ |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 733 | if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 734 | chan->desc_pool = dma_pool_create("xilinx_dma_desc_pool", |
| 735 | chan->dev, |
| 736 | sizeof(struct xilinx_axidma_tx_segment), |
| 737 | __alignof__(struct xilinx_axidma_tx_segment), |
| 738 | 0); |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 739 | } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame] | 740 | chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool", |
| 741 | chan->dev, |
| 742 | sizeof(struct xilinx_cdma_tx_segment), |
| 743 | __alignof__(struct xilinx_cdma_tx_segment), |
| 744 | 0); |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 745 | } else { |
| 746 | chan->desc_pool = dma_pool_create("xilinx_vdma_desc_pool", |
| 747 | chan->dev, |
| 748 | sizeof(struct xilinx_vdma_tx_segment), |
| 749 | __alignof__(struct xilinx_vdma_tx_segment), |
| 750 | 0); |
| 751 | } |
| 752 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 753 | if (!chan->desc_pool) { |
| 754 | dev_err(chan->dev, |
| 755 | "unable to allocate channel %d descriptor pool\n", |
| 756 | chan->id); |
| 757 | return -ENOMEM; |
| 758 | } |
| 759 | |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 760 | if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 761 | /* |
| 762 | * For AXI DMA case after submitting a pending_list, keep |
| 763 | * an extra segment allocated so that the "next descriptor" |
| 764 | * pointer on the tail descriptor always points to a |
| 765 | * valid descriptor, even when paused after reaching taildesc. |
| 766 | * This way, it is possible to issue additional |
| 767 | * transfers without halting and restarting the channel. |
| 768 | */ |
| 769 | chan->seg_v = xilinx_axidma_alloc_tx_segment(chan); |
| 770 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 771 | dma_cookie_init(dchan); |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 772 | |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 773 | if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 774 | /* For AXI DMA resetting once channel will reset the |
| 775 | * other channel as well so enable the interrupts here. |
| 776 | */ |
| 777 | dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, |
| 778 | XILINX_DMA_DMAXR_ALL_IRQ_MASK); |
| 779 | } |
| 780 | |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 781 | if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame] | 782 | dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, |
| 783 | XILINX_CDMA_CR_SGMODE); |
| 784 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 785 | return 0; |
| 786 | } |
| 787 | |
| 788 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 789 | * xilinx_dma_tx_status - Get DMA transaction status |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 790 | * @dchan: DMA channel |
| 791 | * @cookie: Transaction identifier |
| 792 | * @txstate: Transaction state |
| 793 | * |
| 794 | * Return: DMA transaction status |
| 795 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 796 | static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 797 | dma_cookie_t cookie, |
| 798 | struct dma_tx_state *txstate) |
| 799 | { |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 800 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
| 801 | struct xilinx_dma_tx_descriptor *desc; |
| 802 | struct xilinx_axidma_tx_segment *segment; |
| 803 | struct xilinx_axidma_desc_hw *hw; |
| 804 | enum dma_status ret; |
| 805 | unsigned long flags; |
| 806 | u32 residue = 0; |
| 807 | |
| 808 | ret = dma_cookie_status(dchan, cookie, txstate); |
| 809 | if (ret == DMA_COMPLETE || !txstate) |
| 810 | return ret; |
| 811 | |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 812 | if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 813 | spin_lock_irqsave(&chan->lock, flags); |
| 814 | |
| 815 | desc = list_last_entry(&chan->active_list, |
| 816 | struct xilinx_dma_tx_descriptor, node); |
| 817 | if (chan->has_sg) { |
| 818 | list_for_each_entry(segment, &desc->segments, node) { |
| 819 | hw = &segment->hw; |
| 820 | residue += (hw->control - hw->status) & |
| 821 | XILINX_DMA_MAX_TRANS_LEN; |
| 822 | } |
| 823 | } |
| 824 | spin_unlock_irqrestore(&chan->lock, flags); |
| 825 | |
| 826 | chan->residue = residue; |
| 827 | dma_set_residue(txstate, chan->residue); |
| 828 | } |
| 829 | |
| 830 | return ret; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 831 | } |
| 832 | |
| 833 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 834 | * xilinx_dma_is_running - Check if DMA channel is running |
| 835 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 836 | * |
| 837 | * Return: '1' if running, '0' if not. |
| 838 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 839 | static bool xilinx_dma_is_running(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 840 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 841 | return !(dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) & |
| 842 | XILINX_DMA_DMASR_HALTED) && |
| 843 | (dma_ctrl_read(chan, XILINX_DMA_REG_DMACR) & |
| 844 | XILINX_DMA_DMACR_RUNSTOP); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 845 | } |
| 846 | |
| 847 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 848 | * xilinx_dma_is_idle - Check if DMA channel is idle |
| 849 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 850 | * |
| 851 | * Return: '1' if idle, '0' if not. |
| 852 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 853 | static bool xilinx_dma_is_idle(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 854 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 855 | return dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) & |
| 856 | XILINX_DMA_DMASR_IDLE; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 857 | } |
| 858 | |
| 859 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 860 | * xilinx_dma_halt - Halt DMA channel |
| 861 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 862 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 863 | static void xilinx_dma_halt(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 864 | { |
Kedareswara rao Appana | 6949063 | 2016-03-03 23:02:42 +0530 | [diff] [blame] | 865 | int err; |
Kedareswara rao Appana | 9495f26 | 2016-02-26 19:33:54 +0530 | [diff] [blame] | 866 | u32 val; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 867 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 868 | dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 869 | |
| 870 | /* Wait for the hardware to halt */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 871 | err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, |
| 872 | (val & XILINX_DMA_DMASR_HALTED), 0, |
| 873 | XILINX_DMA_LOOP_COUNT); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 874 | |
Kedareswara rao Appana | 9495f26 | 2016-02-26 19:33:54 +0530 | [diff] [blame] | 875 | if (err) { |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 876 | dev_err(chan->dev, "Cannot stop channel %p: %x\n", |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 877 | chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 878 | chan->err = true; |
| 879 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 880 | } |
| 881 | |
| 882 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 883 | * xilinx_dma_start - Start DMA channel |
| 884 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 885 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 886 | static void xilinx_dma_start(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 887 | { |
Kedareswara rao Appana | 6949063 | 2016-03-03 23:02:42 +0530 | [diff] [blame] | 888 | int err; |
Kedareswara rao Appana | 9495f26 | 2016-02-26 19:33:54 +0530 | [diff] [blame] | 889 | u32 val; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 890 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 891 | dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 892 | |
| 893 | /* Wait for the hardware to start */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 894 | err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, |
| 895 | !(val & XILINX_DMA_DMASR_HALTED), 0, |
| 896 | XILINX_DMA_LOOP_COUNT); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 897 | |
Kedareswara rao Appana | 9495f26 | 2016-02-26 19:33:54 +0530 | [diff] [blame] | 898 | if (err) { |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 899 | dev_err(chan->dev, "Cannot start channel %p: %x\n", |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 900 | chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 901 | |
| 902 | chan->err = true; |
| 903 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 904 | } |
| 905 | |
| 906 | /** |
| 907 | * xilinx_vdma_start_transfer - Starts VDMA transfer |
| 908 | * @chan: Driver specific channel struct pointer |
| 909 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 910 | static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 911 | { |
| 912 | struct xilinx_vdma_config *config = &chan->config; |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 913 | struct xilinx_dma_tx_descriptor *desc, *tail_desc; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 914 | u32 reg; |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 915 | struct xilinx_vdma_tx_segment *tail_segment; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 916 | |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 917 | /* This function was invoked with lock held */ |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 918 | if (chan->err) |
| 919 | return; |
| 920 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 921 | if (list_empty(&chan->pending_list)) |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 922 | return; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 923 | |
| 924 | desc = list_first_entry(&chan->pending_list, |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 925 | struct xilinx_dma_tx_descriptor, node); |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 926 | tail_desc = list_last_entry(&chan->pending_list, |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 927 | struct xilinx_dma_tx_descriptor, node); |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 928 | |
| 929 | tail_segment = list_last_entry(&tail_desc->segments, |
| 930 | struct xilinx_vdma_tx_segment, node); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 931 | |
| 932 | /* If it is SG mode and hardware is busy, cannot submit */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 933 | if (chan->has_sg && xilinx_dma_is_running(chan) && |
| 934 | !xilinx_dma_is_idle(chan)) { |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 935 | dev_dbg(chan->dev, "DMA controller still busy\n"); |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 936 | return; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 937 | } |
| 938 | |
| 939 | /* |
| 940 | * If hardware is idle, then all descriptors on the running lists are |
| 941 | * done, start new transfers |
| 942 | */ |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 943 | if (chan->has_sg) |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 944 | dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC, |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 945 | desc->async_tx.phys); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 946 | |
| 947 | /* Configure the hardware using info in the config structure */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 948 | reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 949 | |
| 950 | if (config->frm_cnt_en) |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 951 | reg |= XILINX_DMA_DMACR_FRAMECNT_EN; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 952 | else |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 953 | reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 954 | |
Kedareswara rao Appana | e2b538a | 2016-02-26 19:33:53 +0530 | [diff] [blame] | 955 | /* Configure channel to allow number frame buffers */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 956 | dma_ctrl_write(chan, XILINX_DMA_REG_FRMSTORE, |
Kedareswara rao Appana | e2b538a | 2016-02-26 19:33:53 +0530 | [diff] [blame] | 957 | chan->desc_pendingcount); |
| 958 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 959 | /* |
| 960 | * With SG, start with circular mode, so that BDs can be fetched. |
| 961 | * In direct register mode, if not parking, enable circular mode |
| 962 | */ |
| 963 | if (chan->has_sg || !config->park) |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 964 | reg |= XILINX_DMA_DMACR_CIRC_EN; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 965 | |
| 966 | if (config->park) |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 967 | reg &= ~XILINX_DMA_DMACR_CIRC_EN; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 968 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 969 | dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 970 | |
| 971 | if (config->park && (config->park_frm >= 0) && |
| 972 | (config->park_frm < chan->num_frms)) { |
| 973 | if (chan->direction == DMA_MEM_TO_DEV) |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 974 | dma_write(chan, XILINX_DMA_REG_PARK_PTR, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 975 | config->park_frm << |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 976 | XILINX_DMA_PARK_PTR_RD_REF_SHIFT); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 977 | else |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 978 | dma_write(chan, XILINX_DMA_REG_PARK_PTR, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 979 | config->park_frm << |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 980 | XILINX_DMA_PARK_PTR_WR_REF_SHIFT); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 981 | } |
| 982 | |
| 983 | /* Start the hardware */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 984 | xilinx_dma_start(chan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 985 | |
| 986 | if (chan->err) |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 987 | return; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 988 | |
| 989 | /* Start the transfer */ |
| 990 | if (chan->has_sg) { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 991 | dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC, |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 992 | tail_segment->phys); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 993 | } else { |
| 994 | struct xilinx_vdma_tx_segment *segment, *last = NULL; |
| 995 | int i = 0; |
| 996 | |
Kedareswara rao Appana | a65cf512 | 2016-04-06 10:38:09 +0530 | [diff] [blame] | 997 | if (chan->desc_submitcount < chan->num_frms) |
| 998 | i = chan->desc_submitcount; |
| 999 | |
| 1000 | list_for_each_entry(segment, &desc->segments, node) { |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 1001 | if (chan->ext_addr) |
| 1002 | vdma_desc_write_64(chan, |
| 1003 | XILINX_VDMA_REG_START_ADDRESS_64(i++), |
| 1004 | segment->hw.buf_addr, |
| 1005 | segment->hw.buf_addr_msb); |
| 1006 | else |
| 1007 | vdma_desc_write(chan, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1008 | XILINX_VDMA_REG_START_ADDRESS(i++), |
| 1009 | segment->hw.buf_addr); |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 1010 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1011 | last = segment; |
| 1012 | } |
| 1013 | |
| 1014 | if (!last) |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 1015 | return; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1016 | |
| 1017 | /* HW expects these parameters to be same for one transaction */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1018 | vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize); |
| 1019 | vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1020 | last->hw.stride); |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1021 | vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1022 | } |
| 1023 | |
Kedareswara rao Appana | a65cf512 | 2016-04-06 10:38:09 +0530 | [diff] [blame] | 1024 | if (!chan->has_sg) { |
| 1025 | list_del(&desc->node); |
| 1026 | list_add_tail(&desc->node, &chan->active_list); |
| 1027 | chan->desc_submitcount++; |
| 1028 | chan->desc_pendingcount--; |
| 1029 | if (chan->desc_submitcount == chan->num_frms) |
| 1030 | chan->desc_submitcount = 0; |
| 1031 | } else { |
| 1032 | list_splice_tail_init(&chan->pending_list, &chan->active_list); |
| 1033 | chan->desc_pendingcount = 0; |
| 1034 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1035 | } |
| 1036 | |
| 1037 | /** |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame] | 1038 | * xilinx_cdma_start_transfer - Starts cdma transfer |
| 1039 | * @chan: Driver specific channel struct pointer |
| 1040 | */ |
| 1041 | static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan) |
| 1042 | { |
| 1043 | struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; |
| 1044 | struct xilinx_cdma_tx_segment *tail_segment; |
| 1045 | u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR); |
| 1046 | |
| 1047 | if (chan->err) |
| 1048 | return; |
| 1049 | |
| 1050 | if (list_empty(&chan->pending_list)) |
| 1051 | return; |
| 1052 | |
| 1053 | head_desc = list_first_entry(&chan->pending_list, |
| 1054 | struct xilinx_dma_tx_descriptor, node); |
| 1055 | tail_desc = list_last_entry(&chan->pending_list, |
| 1056 | struct xilinx_dma_tx_descriptor, node); |
| 1057 | tail_segment = list_last_entry(&tail_desc->segments, |
| 1058 | struct xilinx_cdma_tx_segment, node); |
| 1059 | |
| 1060 | if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { |
| 1061 | ctrl_reg &= ~XILINX_DMA_CR_COALESCE_MAX; |
| 1062 | ctrl_reg |= chan->desc_pendingcount << |
| 1063 | XILINX_DMA_CR_COALESCE_SHIFT; |
| 1064 | dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg); |
| 1065 | } |
| 1066 | |
| 1067 | if (chan->has_sg) { |
| 1068 | dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC, |
| 1069 | head_desc->async_tx.phys); |
| 1070 | |
| 1071 | /* Update tail ptr register which will start the transfer */ |
| 1072 | dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC, |
| 1073 | tail_segment->phys); |
| 1074 | } else { |
| 1075 | /* In simple mode */ |
| 1076 | struct xilinx_cdma_tx_segment *segment; |
| 1077 | struct xilinx_cdma_desc_hw *hw; |
| 1078 | |
| 1079 | segment = list_first_entry(&head_desc->segments, |
| 1080 | struct xilinx_cdma_tx_segment, |
| 1081 | node); |
| 1082 | |
| 1083 | hw = &segment->hw; |
| 1084 | |
| 1085 | dma_ctrl_write(chan, XILINX_CDMA_REG_SRCADDR, hw->src_addr); |
| 1086 | dma_ctrl_write(chan, XILINX_CDMA_REG_DSTADDR, hw->dest_addr); |
| 1087 | |
| 1088 | /* Start the transfer */ |
| 1089 | dma_ctrl_write(chan, XILINX_DMA_REG_BTT, |
| 1090 | hw->control & XILINX_DMA_MAX_TRANS_LEN); |
| 1091 | } |
| 1092 | |
| 1093 | list_splice_tail_init(&chan->pending_list, &chan->active_list); |
| 1094 | chan->desc_pendingcount = 0; |
| 1095 | } |
| 1096 | |
| 1097 | /** |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1098 | * xilinx_dma_start_transfer - Starts DMA transfer |
| 1099 | * @chan: Driver specific channel struct pointer |
| 1100 | */ |
| 1101 | static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan) |
| 1102 | { |
| 1103 | struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; |
| 1104 | struct xilinx_axidma_tx_segment *tail_segment, *old_head, *new_head; |
| 1105 | u32 reg; |
| 1106 | |
| 1107 | if (chan->err) |
| 1108 | return; |
| 1109 | |
| 1110 | if (list_empty(&chan->pending_list)) |
| 1111 | return; |
| 1112 | |
| 1113 | /* If it is SG mode and hardware is busy, cannot submit */ |
| 1114 | if (chan->has_sg && xilinx_dma_is_running(chan) && |
| 1115 | !xilinx_dma_is_idle(chan)) { |
| 1116 | dev_dbg(chan->dev, "DMA controller still busy\n"); |
| 1117 | return; |
| 1118 | } |
| 1119 | |
| 1120 | head_desc = list_first_entry(&chan->pending_list, |
| 1121 | struct xilinx_dma_tx_descriptor, node); |
| 1122 | tail_desc = list_last_entry(&chan->pending_list, |
| 1123 | struct xilinx_dma_tx_descriptor, node); |
| 1124 | tail_segment = list_last_entry(&tail_desc->segments, |
| 1125 | struct xilinx_axidma_tx_segment, node); |
| 1126 | |
| 1127 | old_head = list_first_entry(&head_desc->segments, |
| 1128 | struct xilinx_axidma_tx_segment, node); |
| 1129 | new_head = chan->seg_v; |
| 1130 | /* Copy Buffer Descriptor fields. */ |
| 1131 | new_head->hw = old_head->hw; |
| 1132 | |
| 1133 | /* Swap and save new reserve */ |
| 1134 | list_replace_init(&old_head->node, &new_head->node); |
| 1135 | chan->seg_v = old_head; |
| 1136 | |
| 1137 | tail_segment->hw.next_desc = chan->seg_v->phys; |
| 1138 | head_desc->async_tx.phys = new_head->phys; |
| 1139 | |
| 1140 | reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); |
| 1141 | |
| 1142 | if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { |
| 1143 | reg &= ~XILINX_DMA_CR_COALESCE_MAX; |
| 1144 | reg |= chan->desc_pendingcount << |
| 1145 | XILINX_DMA_CR_COALESCE_SHIFT; |
| 1146 | dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); |
| 1147 | } |
| 1148 | |
| 1149 | if (chan->has_sg) |
| 1150 | dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC, |
| 1151 | head_desc->async_tx.phys); |
| 1152 | |
| 1153 | xilinx_dma_start(chan); |
| 1154 | |
| 1155 | if (chan->err) |
| 1156 | return; |
| 1157 | |
| 1158 | /* Start the transfer */ |
| 1159 | if (chan->has_sg) { |
| 1160 | dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC, |
| 1161 | tail_segment->phys); |
| 1162 | } else { |
| 1163 | struct xilinx_axidma_tx_segment *segment; |
| 1164 | struct xilinx_axidma_desc_hw *hw; |
| 1165 | |
| 1166 | segment = list_first_entry(&head_desc->segments, |
| 1167 | struct xilinx_axidma_tx_segment, |
| 1168 | node); |
| 1169 | hw = &segment->hw; |
| 1170 | |
| 1171 | dma_ctrl_write(chan, XILINX_DMA_REG_SRCDSTADDR, hw->buf_addr); |
| 1172 | |
| 1173 | /* Start the transfer */ |
| 1174 | dma_ctrl_write(chan, XILINX_DMA_REG_BTT, |
| 1175 | hw->control & XILINX_DMA_MAX_TRANS_LEN); |
| 1176 | } |
| 1177 | |
| 1178 | list_splice_tail_init(&chan->pending_list, &chan->active_list); |
| 1179 | chan->desc_pendingcount = 0; |
| 1180 | } |
| 1181 | |
| 1182 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1183 | * xilinx_dma_issue_pending - Issue pending transactions |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1184 | * @dchan: DMA channel |
| 1185 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1186 | static void xilinx_dma_issue_pending(struct dma_chan *dchan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1187 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1188 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 1189 | unsigned long flags; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1190 | |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 1191 | spin_lock_irqsave(&chan->lock, flags); |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1192 | chan->start_transfer(chan); |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 1193 | spin_unlock_irqrestore(&chan->lock, flags); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1194 | } |
| 1195 | |
| 1196 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1197 | * xilinx_dma_complete_descriptor - Mark the active descriptor as complete |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1198 | * @chan : xilinx DMA channel |
| 1199 | * |
| 1200 | * CONTEXT: hardirq |
| 1201 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1202 | static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1203 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1204 | struct xilinx_dma_tx_descriptor *desc, *next; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1205 | |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 1206 | /* This function was invoked with lock held */ |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 1207 | if (list_empty(&chan->active_list)) |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 1208 | return; |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 1209 | |
| 1210 | list_for_each_entry_safe(desc, next, &chan->active_list, node) { |
| 1211 | list_del(&desc->node); |
| 1212 | dma_cookie_complete(&desc->async_tx); |
| 1213 | list_add_tail(&desc->node, &chan->done_list); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1214 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1215 | } |
| 1216 | |
| 1217 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1218 | * xilinx_dma_reset - Reset DMA channel |
| 1219 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1220 | * |
| 1221 | * Return: '0' on success and failure value on error |
| 1222 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1223 | static int xilinx_dma_reset(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1224 | { |
Kedareswara rao Appana | 6949063 | 2016-03-03 23:02:42 +0530 | [diff] [blame] | 1225 | int err; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1226 | u32 tmp; |
| 1227 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1228 | dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1229 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1230 | /* Wait for the hardware to finish reset */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1231 | err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp, |
| 1232 | !(tmp & XILINX_DMA_DMACR_RESET), 0, |
| 1233 | XILINX_DMA_LOOP_COUNT); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1234 | |
Kedareswara rao Appana | 9495f26 | 2016-02-26 19:33:54 +0530 | [diff] [blame] | 1235 | if (err) { |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1236 | dev_err(chan->dev, "reset timeout, cr %x, sr %x\n", |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1237 | dma_ctrl_read(chan, XILINX_DMA_REG_DMACR), |
| 1238 | dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1239 | return -ETIMEDOUT; |
| 1240 | } |
| 1241 | |
| 1242 | chan->err = false; |
| 1243 | |
Kedareswara rao Appana | 9495f26 | 2016-02-26 19:33:54 +0530 | [diff] [blame] | 1244 | return err; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1245 | } |
| 1246 | |
| 1247 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1248 | * xilinx_dma_chan_reset - Reset DMA channel and enable interrupts |
| 1249 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1250 | * |
| 1251 | * Return: '0' on success and failure value on error |
| 1252 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1253 | static int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1254 | { |
| 1255 | int err; |
| 1256 | |
| 1257 | /* Reset VDMA */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1258 | err = xilinx_dma_reset(chan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1259 | if (err) |
| 1260 | return err; |
| 1261 | |
| 1262 | /* Enable interrupts */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1263 | dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, |
| 1264 | XILINX_DMA_DMAXR_ALL_IRQ_MASK); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1265 | |
| 1266 | return 0; |
| 1267 | } |
| 1268 | |
| 1269 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1270 | * xilinx_dma_irq_handler - DMA Interrupt handler |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1271 | * @irq: IRQ number |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1272 | * @data: Pointer to the Xilinx DMA channel structure |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1273 | * |
| 1274 | * Return: IRQ_HANDLED/IRQ_NONE |
| 1275 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1276 | static irqreturn_t xilinx_dma_irq_handler(int irq, void *data) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1277 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1278 | struct xilinx_dma_chan *chan = data; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1279 | u32 status; |
| 1280 | |
| 1281 | /* Read the status and ack the interrupts. */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1282 | status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR); |
| 1283 | if (!(status & XILINX_DMA_DMAXR_ALL_IRQ_MASK)) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1284 | return IRQ_NONE; |
| 1285 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1286 | dma_ctrl_write(chan, XILINX_DMA_REG_DMASR, |
| 1287 | status & XILINX_DMA_DMAXR_ALL_IRQ_MASK); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1288 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1289 | if (status & XILINX_DMA_DMASR_ERR_IRQ) { |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1290 | /* |
| 1291 | * An error occurred. If C_FLUSH_ON_FSYNC is enabled and the |
| 1292 | * error is recoverable, ignore it. Otherwise flag the error. |
| 1293 | * |
| 1294 | * Only recoverable errors can be cleared in the DMASR register, |
| 1295 | * make sure not to write to other error bits to 1. |
| 1296 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1297 | u32 errors = status & XILINX_DMA_DMASR_ALL_ERR_MASK; |
Kedareswara rao Appana | 48a59ed | 2016-04-06 10:44:55 +0530 | [diff] [blame] | 1298 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1299 | dma_ctrl_write(chan, XILINX_DMA_REG_DMASR, |
| 1300 | errors & XILINX_DMA_DMASR_ERR_RECOVER_MASK); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1301 | |
| 1302 | if (!chan->flush_on_fsync || |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1303 | (errors & ~XILINX_DMA_DMASR_ERR_RECOVER_MASK)) { |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1304 | dev_err(chan->dev, |
| 1305 | "Channel %p has errors %x, cdr %x tdr %x\n", |
| 1306 | chan, errors, |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1307 | dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC), |
| 1308 | dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC)); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1309 | chan->err = true; |
| 1310 | } |
| 1311 | } |
| 1312 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1313 | if (status & XILINX_DMA_DMASR_DLY_CNT_IRQ) { |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1314 | /* |
| 1315 | * Device takes too long to do the transfer when user requires |
| 1316 | * responsiveness. |
| 1317 | */ |
| 1318 | dev_dbg(chan->dev, "Inter-packet latency too long\n"); |
| 1319 | } |
| 1320 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1321 | if (status & XILINX_DMA_DMASR_FRM_CNT_IRQ) { |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 1322 | spin_lock(&chan->lock); |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1323 | xilinx_dma_complete_descriptor(chan); |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1324 | chan->start_transfer(chan); |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 1325 | spin_unlock(&chan->lock); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1326 | } |
| 1327 | |
| 1328 | tasklet_schedule(&chan->tasklet); |
| 1329 | return IRQ_HANDLED; |
| 1330 | } |
| 1331 | |
| 1332 | /** |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 1333 | * append_desc_queue - Queuing descriptor |
| 1334 | * @chan: Driver specific dma channel |
| 1335 | * @desc: dma transaction descriptor |
| 1336 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1337 | static void append_desc_queue(struct xilinx_dma_chan *chan, |
| 1338 | struct xilinx_dma_tx_descriptor *desc) |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 1339 | { |
| 1340 | struct xilinx_vdma_tx_segment *tail_segment; |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1341 | struct xilinx_dma_tx_descriptor *tail_desc; |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1342 | struct xilinx_axidma_tx_segment *axidma_tail_segment; |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame] | 1343 | struct xilinx_cdma_tx_segment *cdma_tail_segment; |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 1344 | |
| 1345 | if (list_empty(&chan->pending_list)) |
| 1346 | goto append; |
| 1347 | |
| 1348 | /* |
| 1349 | * Add the hardware descriptor to the chain of hardware descriptors |
| 1350 | * that already exists in memory. |
| 1351 | */ |
| 1352 | tail_desc = list_last_entry(&chan->pending_list, |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1353 | struct xilinx_dma_tx_descriptor, node); |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 1354 | if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1355 | tail_segment = list_last_entry(&tail_desc->segments, |
| 1356 | struct xilinx_vdma_tx_segment, |
| 1357 | node); |
| 1358 | tail_segment->hw.next_desc = (u32)desc->async_tx.phys; |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 1359 | } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame] | 1360 | cdma_tail_segment = list_last_entry(&tail_desc->segments, |
| 1361 | struct xilinx_cdma_tx_segment, |
| 1362 | node); |
| 1363 | cdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1364 | } else { |
| 1365 | axidma_tail_segment = list_last_entry(&tail_desc->segments, |
| 1366 | struct xilinx_axidma_tx_segment, |
| 1367 | node); |
| 1368 | axidma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; |
| 1369 | } |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 1370 | |
| 1371 | /* |
| 1372 | * Add the software descriptor and all children to the list |
| 1373 | * of pending transactions |
| 1374 | */ |
| 1375 | append: |
| 1376 | list_add_tail(&desc->node, &chan->pending_list); |
| 1377 | chan->desc_pendingcount++; |
| 1378 | |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 1379 | if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) |
| 1380 | && unlikely(chan->desc_pendingcount > chan->num_frms)) { |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 1381 | dev_dbg(chan->dev, "desc pendingcount is too high\n"); |
| 1382 | chan->desc_pendingcount = chan->num_frms; |
| 1383 | } |
| 1384 | } |
| 1385 | |
| 1386 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1387 | * xilinx_dma_tx_submit - Submit DMA transaction |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1388 | * @tx: Async transaction descriptor |
| 1389 | * |
| 1390 | * Return: cookie value on success and failure value on error |
| 1391 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1392 | static dma_cookie_t xilinx_dma_tx_submit(struct dma_async_tx_descriptor *tx) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1393 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1394 | struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx); |
| 1395 | struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1396 | dma_cookie_t cookie; |
| 1397 | unsigned long flags; |
| 1398 | int err; |
| 1399 | |
| 1400 | if (chan->err) { |
| 1401 | /* |
| 1402 | * If reset fails, need to hard reset the system. |
| 1403 | * Channel is no longer functional |
| 1404 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1405 | err = xilinx_dma_chan_reset(chan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1406 | if (err < 0) |
| 1407 | return err; |
| 1408 | } |
| 1409 | |
| 1410 | spin_lock_irqsave(&chan->lock, flags); |
| 1411 | |
| 1412 | cookie = dma_cookie_assign(tx); |
| 1413 | |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 1414 | /* Put this transaction onto the tail of the pending queue */ |
| 1415 | append_desc_queue(chan, desc); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1416 | |
| 1417 | spin_unlock_irqrestore(&chan->lock, flags); |
| 1418 | |
| 1419 | return cookie; |
| 1420 | } |
| 1421 | |
| 1422 | /** |
| 1423 | * xilinx_vdma_dma_prep_interleaved - prepare a descriptor for a |
| 1424 | * DMA_SLAVE transaction |
| 1425 | * @dchan: DMA channel |
| 1426 | * @xt: Interleaved template pointer |
| 1427 | * @flags: transfer ack flags |
| 1428 | * |
| 1429 | * Return: Async transaction descriptor on success and NULL on failure |
| 1430 | */ |
| 1431 | static struct dma_async_tx_descriptor * |
| 1432 | xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan, |
| 1433 | struct dma_interleaved_template *xt, |
| 1434 | unsigned long flags) |
| 1435 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1436 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
| 1437 | struct xilinx_dma_tx_descriptor *desc; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1438 | struct xilinx_vdma_tx_segment *segment, *prev = NULL; |
| 1439 | struct xilinx_vdma_desc_hw *hw; |
| 1440 | |
| 1441 | if (!is_slave_direction(xt->dir)) |
| 1442 | return NULL; |
| 1443 | |
| 1444 | if (!xt->numf || !xt->sgl[0].size) |
| 1445 | return NULL; |
| 1446 | |
Srikanth Thokala | a5e48e2 | 2014-11-05 20:37:01 +0200 | [diff] [blame] | 1447 | if (xt->frame_size != 1) |
| 1448 | return NULL; |
| 1449 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1450 | /* Allocate a transaction descriptor. */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1451 | desc = xilinx_dma_alloc_tx_descriptor(chan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1452 | if (!desc) |
| 1453 | return NULL; |
| 1454 | |
| 1455 | dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1456 | desc->async_tx.tx_submit = xilinx_dma_tx_submit; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1457 | async_tx_ack(&desc->async_tx); |
| 1458 | |
| 1459 | /* Allocate the link descriptor from DMA pool */ |
| 1460 | segment = xilinx_vdma_alloc_tx_segment(chan); |
| 1461 | if (!segment) |
| 1462 | goto error; |
| 1463 | |
| 1464 | /* Fill in the hardware descriptor */ |
| 1465 | hw = &segment->hw; |
| 1466 | hw->vsize = xt->numf; |
| 1467 | hw->hsize = xt->sgl[0].size; |
Srikanth Thokala | 6d80f45 | 2014-11-05 20:37:02 +0200 | [diff] [blame] | 1468 | hw->stride = (xt->sgl[0].icg + xt->sgl[0].size) << |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1469 | XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1470 | hw->stride |= chan->config.frm_dly << |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1471 | XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1472 | |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 1473 | if (xt->dir != DMA_MEM_TO_DEV) { |
| 1474 | if (chan->ext_addr) { |
| 1475 | hw->buf_addr = lower_32_bits(xt->dst_start); |
| 1476 | hw->buf_addr_msb = upper_32_bits(xt->dst_start); |
| 1477 | } else { |
| 1478 | hw->buf_addr = xt->dst_start; |
| 1479 | } |
| 1480 | } else { |
| 1481 | if (chan->ext_addr) { |
| 1482 | hw->buf_addr = lower_32_bits(xt->src_start); |
| 1483 | hw->buf_addr_msb = upper_32_bits(xt->src_start); |
| 1484 | } else { |
| 1485 | hw->buf_addr = xt->src_start; |
| 1486 | } |
| 1487 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1488 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1489 | /* Insert the segment into the descriptor segments list. */ |
| 1490 | list_add_tail(&segment->node, &desc->segments); |
| 1491 | |
| 1492 | prev = segment; |
| 1493 | |
| 1494 | /* Link the last hardware descriptor with the first. */ |
| 1495 | segment = list_first_entry(&desc->segments, |
| 1496 | struct xilinx_vdma_tx_segment, node); |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 1497 | desc->async_tx.phys = segment->phys; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1498 | |
| 1499 | return &desc->async_tx; |
| 1500 | |
| 1501 | error: |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1502 | xilinx_dma_free_tx_descriptor(chan, desc); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1503 | return NULL; |
| 1504 | } |
| 1505 | |
| 1506 | /** |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame] | 1507 | * xilinx_cdma_prep_memcpy - prepare descriptors for a memcpy transaction |
| 1508 | * @dchan: DMA channel |
| 1509 | * @dma_dst: destination address |
| 1510 | * @dma_src: source address |
| 1511 | * @len: transfer length |
| 1512 | * @flags: transfer ack flags |
| 1513 | * |
| 1514 | * Return: Async transaction descriptor on success and NULL on failure |
| 1515 | */ |
| 1516 | static struct dma_async_tx_descriptor * |
| 1517 | xilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst, |
| 1518 | dma_addr_t dma_src, size_t len, unsigned long flags) |
| 1519 | { |
| 1520 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
| 1521 | struct xilinx_dma_tx_descriptor *desc; |
| 1522 | struct xilinx_cdma_tx_segment *segment, *prev; |
| 1523 | struct xilinx_cdma_desc_hw *hw; |
| 1524 | |
| 1525 | if (!len || len > XILINX_DMA_MAX_TRANS_LEN) |
| 1526 | return NULL; |
| 1527 | |
| 1528 | desc = xilinx_dma_alloc_tx_descriptor(chan); |
| 1529 | if (!desc) |
| 1530 | return NULL; |
| 1531 | |
| 1532 | dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); |
| 1533 | desc->async_tx.tx_submit = xilinx_dma_tx_submit; |
| 1534 | |
| 1535 | /* Allocate the link descriptor from DMA pool */ |
| 1536 | segment = xilinx_cdma_alloc_tx_segment(chan); |
| 1537 | if (!segment) |
| 1538 | goto error; |
| 1539 | |
| 1540 | hw = &segment->hw; |
| 1541 | hw->control = len; |
| 1542 | hw->src_addr = dma_src; |
| 1543 | hw->dest_addr = dma_dst; |
| 1544 | |
| 1545 | /* Fill the previous next descriptor with current */ |
| 1546 | prev = list_last_entry(&desc->segments, |
| 1547 | struct xilinx_cdma_tx_segment, node); |
| 1548 | prev->hw.next_desc = segment->phys; |
| 1549 | |
| 1550 | /* Insert the segment into the descriptor segments list. */ |
| 1551 | list_add_tail(&segment->node, &desc->segments); |
| 1552 | |
| 1553 | prev = segment; |
| 1554 | |
| 1555 | /* Link the last hardware descriptor with the first. */ |
| 1556 | segment = list_first_entry(&desc->segments, |
| 1557 | struct xilinx_cdma_tx_segment, node); |
| 1558 | desc->async_tx.phys = segment->phys; |
| 1559 | prev->hw.next_desc = segment->phys; |
| 1560 | |
| 1561 | return &desc->async_tx; |
| 1562 | |
| 1563 | error: |
| 1564 | xilinx_dma_free_tx_descriptor(chan, desc); |
| 1565 | return NULL; |
| 1566 | } |
| 1567 | |
| 1568 | /** |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1569 | * xilinx_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction |
| 1570 | * @dchan: DMA channel |
| 1571 | * @sgl: scatterlist to transfer to/from |
| 1572 | * @sg_len: number of entries in @scatterlist |
| 1573 | * @direction: DMA direction |
| 1574 | * @flags: transfer ack flags |
| 1575 | * @context: APP words of the descriptor |
| 1576 | * |
| 1577 | * Return: Async transaction descriptor on success and NULL on failure |
| 1578 | */ |
| 1579 | static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( |
| 1580 | struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, |
| 1581 | enum dma_transfer_direction direction, unsigned long flags, |
| 1582 | void *context) |
| 1583 | { |
| 1584 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
| 1585 | struct xilinx_dma_tx_descriptor *desc; |
| 1586 | struct xilinx_axidma_tx_segment *segment = NULL, *prev = NULL; |
| 1587 | u32 *app_w = (u32 *)context; |
| 1588 | struct scatterlist *sg; |
| 1589 | size_t copy; |
| 1590 | size_t sg_used; |
| 1591 | unsigned int i; |
| 1592 | |
| 1593 | if (!is_slave_direction(direction)) |
| 1594 | return NULL; |
| 1595 | |
| 1596 | /* Allocate a transaction descriptor. */ |
| 1597 | desc = xilinx_dma_alloc_tx_descriptor(chan); |
| 1598 | if (!desc) |
| 1599 | return NULL; |
| 1600 | |
| 1601 | dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); |
| 1602 | desc->async_tx.tx_submit = xilinx_dma_tx_submit; |
| 1603 | |
| 1604 | /* Build transactions using information in the scatter gather list */ |
| 1605 | for_each_sg(sgl, sg, sg_len, i) { |
| 1606 | sg_used = 0; |
| 1607 | |
| 1608 | /* Loop until the entire scatterlist entry is used */ |
| 1609 | while (sg_used < sg_dma_len(sg)) { |
| 1610 | struct xilinx_axidma_desc_hw *hw; |
| 1611 | |
| 1612 | /* Get a free segment */ |
| 1613 | segment = xilinx_axidma_alloc_tx_segment(chan); |
| 1614 | if (!segment) |
| 1615 | goto error; |
| 1616 | |
| 1617 | /* |
| 1618 | * Calculate the maximum number of bytes to transfer, |
| 1619 | * making sure it is less than the hw limit |
| 1620 | */ |
| 1621 | copy = min_t(size_t, sg_dma_len(sg) - sg_used, |
| 1622 | XILINX_DMA_MAX_TRANS_LEN); |
| 1623 | hw = &segment->hw; |
| 1624 | |
| 1625 | /* Fill in the descriptor */ |
| 1626 | hw->buf_addr = sg_dma_address(sg) + sg_used; |
| 1627 | |
| 1628 | hw->control = copy; |
| 1629 | |
| 1630 | if (chan->direction == DMA_MEM_TO_DEV) { |
| 1631 | if (app_w) |
| 1632 | memcpy(hw->app, app_w, sizeof(u32) * |
| 1633 | XILINX_DMA_NUM_APP_WORDS); |
| 1634 | } |
| 1635 | |
| 1636 | if (prev) |
| 1637 | prev->hw.next_desc = segment->phys; |
| 1638 | |
| 1639 | prev = segment; |
| 1640 | sg_used += copy; |
| 1641 | |
| 1642 | /* |
| 1643 | * Insert the segment into the descriptor segments |
| 1644 | * list. |
| 1645 | */ |
| 1646 | list_add_tail(&segment->node, &desc->segments); |
| 1647 | } |
| 1648 | } |
| 1649 | |
| 1650 | segment = list_first_entry(&desc->segments, |
| 1651 | struct xilinx_axidma_tx_segment, node); |
| 1652 | desc->async_tx.phys = segment->phys; |
| 1653 | prev->hw.next_desc = segment->phys; |
| 1654 | |
| 1655 | /* For the last DMA_MEM_TO_DEV transfer, set EOP */ |
| 1656 | if (chan->direction == DMA_MEM_TO_DEV) { |
| 1657 | segment->hw.control |= XILINX_DMA_BD_SOP; |
| 1658 | segment = list_last_entry(&desc->segments, |
| 1659 | struct xilinx_axidma_tx_segment, |
| 1660 | node); |
| 1661 | segment->hw.control |= XILINX_DMA_BD_EOP; |
| 1662 | } |
| 1663 | |
| 1664 | return &desc->async_tx; |
| 1665 | |
| 1666 | error: |
| 1667 | xilinx_dma_free_tx_descriptor(chan, desc); |
| 1668 | return NULL; |
| 1669 | } |
| 1670 | |
| 1671 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1672 | * xilinx_dma_terminate_all - Halt the channel and free descriptors |
| 1673 | * @chan: Driver specific DMA Channel pointer |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1674 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1675 | static int xilinx_dma_terminate_all(struct dma_chan *dchan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1676 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1677 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
Maxime Ripard | ba71404 | 2014-11-17 14:42:38 +0100 | [diff] [blame] | 1678 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1679 | /* Halt the DMA engine */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1680 | xilinx_dma_halt(chan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1681 | |
| 1682 | /* Remove and free all of the descriptors in the lists */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1683 | xilinx_dma_free_descriptors(chan); |
Maxime Ripard | ba71404 | 2014-11-17 14:42:38 +0100 | [diff] [blame] | 1684 | |
| 1685 | return 0; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1686 | } |
| 1687 | |
| 1688 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1689 | * xilinx_dma_channel_set_config - Configure VDMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1690 | * Run-time configuration for Axi VDMA, supports: |
| 1691 | * . halt the channel |
| 1692 | * . configure interrupt coalescing and inter-packet delay threshold |
| 1693 | * . start/stop parking |
| 1694 | * . enable genlock |
| 1695 | * |
| 1696 | * @dchan: DMA channel |
| 1697 | * @cfg: VDMA device configuration pointer |
| 1698 | * |
| 1699 | * Return: '0' on success and failure value on error |
| 1700 | */ |
| 1701 | int xilinx_vdma_channel_set_config(struct dma_chan *dchan, |
| 1702 | struct xilinx_vdma_config *cfg) |
| 1703 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1704 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1705 | u32 dmacr; |
| 1706 | |
| 1707 | if (cfg->reset) |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1708 | return xilinx_dma_chan_reset(chan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1709 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1710 | dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1711 | |
| 1712 | chan->config.frm_dly = cfg->frm_dly; |
| 1713 | chan->config.park = cfg->park; |
| 1714 | |
| 1715 | /* genlock settings */ |
| 1716 | chan->config.gen_lock = cfg->gen_lock; |
| 1717 | chan->config.master = cfg->master; |
| 1718 | |
| 1719 | if (cfg->gen_lock && chan->genlock) { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1720 | dmacr |= XILINX_DMA_DMACR_GENLOCK_EN; |
| 1721 | dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1722 | } |
| 1723 | |
| 1724 | chan->config.frm_cnt_en = cfg->frm_cnt_en; |
| 1725 | if (cfg->park) |
| 1726 | chan->config.park_frm = cfg->park_frm; |
| 1727 | else |
| 1728 | chan->config.park_frm = -1; |
| 1729 | |
| 1730 | chan->config.coalesc = cfg->coalesc; |
| 1731 | chan->config.delay = cfg->delay; |
| 1732 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1733 | if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) { |
| 1734 | dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1735 | chan->config.coalesc = cfg->coalesc; |
| 1736 | } |
| 1737 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1738 | if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) { |
| 1739 | dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1740 | chan->config.delay = cfg->delay; |
| 1741 | } |
| 1742 | |
| 1743 | /* FSync Source selection */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1744 | dmacr &= ~XILINX_DMA_DMACR_FSYNCSRC_MASK; |
| 1745 | dmacr |= cfg->ext_fsync << XILINX_DMA_DMACR_FSYNCSRC_SHIFT; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1746 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1747 | dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1748 | |
| 1749 | return 0; |
| 1750 | } |
| 1751 | EXPORT_SYMBOL(xilinx_vdma_channel_set_config); |
| 1752 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1753 | /* ----------------------------------------------------------------------------- |
| 1754 | * Probe and remove |
| 1755 | */ |
| 1756 | |
| 1757 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1758 | * xilinx_dma_chan_remove - Per Channel remove function |
| 1759 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1760 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1761 | static void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1762 | { |
| 1763 | /* Disable all interrupts */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1764 | dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, |
| 1765 | XILINX_DMA_DMAXR_ALL_IRQ_MASK); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1766 | |
| 1767 | if (chan->irq > 0) |
| 1768 | free_irq(chan->irq, chan); |
| 1769 | |
| 1770 | tasklet_kill(&chan->tasklet); |
| 1771 | |
| 1772 | list_del(&chan->common.device_node); |
| 1773 | } |
| 1774 | |
Kedareswara rao Appana | ba16db3 | 2016-05-13 12:33:31 +0530 | [diff] [blame^] | 1775 | static int axidma_clk_init(struct platform_device *pdev, struct clk **axi_clk, |
| 1776 | struct clk **tx_clk, struct clk **rx_clk, |
| 1777 | struct clk **sg_clk, struct clk **tmp_clk) |
| 1778 | { |
| 1779 | int err; |
| 1780 | |
| 1781 | *tmp_clk = NULL; |
| 1782 | |
| 1783 | *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); |
| 1784 | if (IS_ERR(*axi_clk)) { |
| 1785 | err = PTR_ERR(*axi_clk); |
| 1786 | dev_err(&pdev->dev, "failed to get axi_aclk (%u)\n", err); |
| 1787 | return err; |
| 1788 | } |
| 1789 | |
| 1790 | *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk"); |
| 1791 | if (IS_ERR(*tx_clk)) |
| 1792 | *tx_clk = NULL; |
| 1793 | |
| 1794 | *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk"); |
| 1795 | if (IS_ERR(*rx_clk)) |
| 1796 | *rx_clk = NULL; |
| 1797 | |
| 1798 | *sg_clk = devm_clk_get(&pdev->dev, "m_axi_sg_aclk"); |
| 1799 | if (IS_ERR(*sg_clk)) |
| 1800 | *sg_clk = NULL; |
| 1801 | |
| 1802 | err = clk_prepare_enable(*axi_clk); |
| 1803 | if (err) { |
| 1804 | dev_err(&pdev->dev, "failed to enable axi_clk (%u)\n", err); |
| 1805 | return err; |
| 1806 | } |
| 1807 | |
| 1808 | err = clk_prepare_enable(*tx_clk); |
| 1809 | if (err) { |
| 1810 | dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err); |
| 1811 | goto err_disable_axiclk; |
| 1812 | } |
| 1813 | |
| 1814 | err = clk_prepare_enable(*rx_clk); |
| 1815 | if (err) { |
| 1816 | dev_err(&pdev->dev, "failed to enable rx_clk (%u)\n", err); |
| 1817 | goto err_disable_txclk; |
| 1818 | } |
| 1819 | |
| 1820 | err = clk_prepare_enable(*sg_clk); |
| 1821 | if (err) { |
| 1822 | dev_err(&pdev->dev, "failed to enable sg_clk (%u)\n", err); |
| 1823 | goto err_disable_rxclk; |
| 1824 | } |
| 1825 | |
| 1826 | return 0; |
| 1827 | |
| 1828 | err_disable_rxclk: |
| 1829 | clk_disable_unprepare(*rx_clk); |
| 1830 | err_disable_txclk: |
| 1831 | clk_disable_unprepare(*tx_clk); |
| 1832 | err_disable_axiclk: |
| 1833 | clk_disable_unprepare(*axi_clk); |
| 1834 | |
| 1835 | return err; |
| 1836 | } |
| 1837 | |
| 1838 | static int axicdma_clk_init(struct platform_device *pdev, struct clk **axi_clk, |
| 1839 | struct clk **dev_clk, struct clk **tmp_clk, |
| 1840 | struct clk **tmp1_clk, struct clk **tmp2_clk) |
| 1841 | { |
| 1842 | int err; |
| 1843 | |
| 1844 | *tmp_clk = NULL; |
| 1845 | *tmp1_clk = NULL; |
| 1846 | *tmp2_clk = NULL; |
| 1847 | |
| 1848 | *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); |
| 1849 | if (IS_ERR(*axi_clk)) { |
| 1850 | err = PTR_ERR(*axi_clk); |
| 1851 | dev_err(&pdev->dev, "failed to get axi_clk (%u)\n", err); |
| 1852 | return err; |
| 1853 | } |
| 1854 | |
| 1855 | *dev_clk = devm_clk_get(&pdev->dev, "m_axi_aclk"); |
| 1856 | if (IS_ERR(*dev_clk)) { |
| 1857 | err = PTR_ERR(*dev_clk); |
| 1858 | dev_err(&pdev->dev, "failed to get dev_clk (%u)\n", err); |
| 1859 | return err; |
| 1860 | } |
| 1861 | |
| 1862 | err = clk_prepare_enable(*axi_clk); |
| 1863 | if (err) { |
| 1864 | dev_err(&pdev->dev, "failed to enable axi_clk (%u)\n", err); |
| 1865 | return err; |
| 1866 | } |
| 1867 | |
| 1868 | err = clk_prepare_enable(*dev_clk); |
| 1869 | if (err) { |
| 1870 | dev_err(&pdev->dev, "failed to enable dev_clk (%u)\n", err); |
| 1871 | goto err_disable_axiclk; |
| 1872 | } |
| 1873 | |
| 1874 | return 0; |
| 1875 | |
| 1876 | err_disable_axiclk: |
| 1877 | clk_disable_unprepare(*axi_clk); |
| 1878 | |
| 1879 | return err; |
| 1880 | } |
| 1881 | |
| 1882 | static int axivdma_clk_init(struct platform_device *pdev, struct clk **axi_clk, |
| 1883 | struct clk **tx_clk, struct clk **txs_clk, |
| 1884 | struct clk **rx_clk, struct clk **rxs_clk) |
| 1885 | { |
| 1886 | int err; |
| 1887 | |
| 1888 | *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); |
| 1889 | if (IS_ERR(*axi_clk)) { |
| 1890 | err = PTR_ERR(*axi_clk); |
| 1891 | dev_err(&pdev->dev, "failed to get axi_aclk (%u)\n", err); |
| 1892 | return err; |
| 1893 | } |
| 1894 | |
| 1895 | *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk"); |
| 1896 | if (IS_ERR(*tx_clk)) |
| 1897 | *tx_clk = NULL; |
| 1898 | |
| 1899 | *txs_clk = devm_clk_get(&pdev->dev, "m_axis_mm2s_aclk"); |
| 1900 | if (IS_ERR(*txs_clk)) |
| 1901 | *txs_clk = NULL; |
| 1902 | |
| 1903 | *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk"); |
| 1904 | if (IS_ERR(*rx_clk)) |
| 1905 | *rx_clk = NULL; |
| 1906 | |
| 1907 | *rxs_clk = devm_clk_get(&pdev->dev, "s_axis_s2mm_aclk"); |
| 1908 | if (IS_ERR(*rxs_clk)) |
| 1909 | *rxs_clk = NULL; |
| 1910 | |
| 1911 | err = clk_prepare_enable(*axi_clk); |
| 1912 | if (err) { |
| 1913 | dev_err(&pdev->dev, "failed to enable axi_clk (%u)\n", err); |
| 1914 | return err; |
| 1915 | } |
| 1916 | |
| 1917 | err = clk_prepare_enable(*tx_clk); |
| 1918 | if (err) { |
| 1919 | dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err); |
| 1920 | goto err_disable_axiclk; |
| 1921 | } |
| 1922 | |
| 1923 | err = clk_prepare_enable(*txs_clk); |
| 1924 | if (err) { |
| 1925 | dev_err(&pdev->dev, "failed to enable txs_clk (%u)\n", err); |
| 1926 | goto err_disable_txclk; |
| 1927 | } |
| 1928 | |
| 1929 | err = clk_prepare_enable(*rx_clk); |
| 1930 | if (err) { |
| 1931 | dev_err(&pdev->dev, "failed to enable rx_clk (%u)\n", err); |
| 1932 | goto err_disable_txsclk; |
| 1933 | } |
| 1934 | |
| 1935 | err = clk_prepare_enable(*rxs_clk); |
| 1936 | if (err) { |
| 1937 | dev_err(&pdev->dev, "failed to enable rxs_clk (%u)\n", err); |
| 1938 | goto err_disable_rxclk; |
| 1939 | } |
| 1940 | |
| 1941 | return 0; |
| 1942 | |
| 1943 | err_disable_rxclk: |
| 1944 | clk_disable_unprepare(*rx_clk); |
| 1945 | err_disable_txsclk: |
| 1946 | clk_disable_unprepare(*txs_clk); |
| 1947 | err_disable_txclk: |
| 1948 | clk_disable_unprepare(*tx_clk); |
| 1949 | err_disable_axiclk: |
| 1950 | clk_disable_unprepare(*axi_clk); |
| 1951 | |
| 1952 | return err; |
| 1953 | } |
| 1954 | |
| 1955 | static void xdma_disable_allclks(struct xilinx_dma_device *xdev) |
| 1956 | { |
| 1957 | clk_disable_unprepare(xdev->rxs_clk); |
| 1958 | clk_disable_unprepare(xdev->rx_clk); |
| 1959 | clk_disable_unprepare(xdev->txs_clk); |
| 1960 | clk_disable_unprepare(xdev->tx_clk); |
| 1961 | clk_disable_unprepare(xdev->axi_clk); |
| 1962 | } |
| 1963 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1964 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1965 | * xilinx_dma_chan_probe - Per Channel Probing |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1966 | * It get channel features from the device tree entry and |
| 1967 | * initialize special channel handling routines |
| 1968 | * |
| 1969 | * @xdev: Driver specific device structure |
| 1970 | * @node: Device node |
| 1971 | * |
| 1972 | * Return: '0' on success and failure value on error |
| 1973 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1974 | static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1975 | struct device_node *node) |
| 1976 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1977 | struct xilinx_dma_chan *chan; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1978 | bool has_dre = false; |
| 1979 | u32 value, width; |
| 1980 | int err; |
| 1981 | |
| 1982 | /* Allocate and initialize the channel structure */ |
| 1983 | chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL); |
| 1984 | if (!chan) |
| 1985 | return -ENOMEM; |
| 1986 | |
| 1987 | chan->dev = xdev->dev; |
| 1988 | chan->xdev = xdev; |
| 1989 | chan->has_sg = xdev->has_sg; |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 1990 | chan->desc_pendingcount = 0x0; |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 1991 | chan->ext_addr = xdev->ext_addr; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1992 | |
| 1993 | spin_lock_init(&chan->lock); |
| 1994 | INIT_LIST_HEAD(&chan->pending_list); |
| 1995 | INIT_LIST_HEAD(&chan->done_list); |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 1996 | INIT_LIST_HEAD(&chan->active_list); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1997 | |
| 1998 | /* Retrieve the channel properties from the device tree */ |
| 1999 | has_dre = of_property_read_bool(node, "xlnx,include-dre"); |
| 2000 | |
| 2001 | chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode"); |
| 2002 | |
| 2003 | err = of_property_read_u32(node, "xlnx,datawidth", &value); |
| 2004 | if (err) { |
| 2005 | dev_err(xdev->dev, "missing xlnx,datawidth property\n"); |
| 2006 | return err; |
| 2007 | } |
| 2008 | width = value >> 3; /* Convert bits to bytes */ |
| 2009 | |
| 2010 | /* If data width is greater than 8 bytes, DRE is not in hw */ |
| 2011 | if (width > 8) |
| 2012 | has_dre = false; |
| 2013 | |
| 2014 | if (!has_dre) |
| 2015 | xdev->common.copy_align = fls(width - 1); |
| 2016 | |
| 2017 | if (of_device_is_compatible(node, "xlnx,axi-vdma-mm2s-channel")) { |
| 2018 | chan->direction = DMA_MEM_TO_DEV; |
| 2019 | chan->id = 0; |
| 2020 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2021 | chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 2022 | if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 2023 | chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2024 | |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 2025 | if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH || |
| 2026 | xdev->flush_on_fsync == XILINX_DMA_FLUSH_MM2S) |
| 2027 | chan->flush_on_fsync = true; |
| 2028 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2029 | } else if (of_device_is_compatible(node, |
| 2030 | "xlnx,axi-vdma-s2mm-channel")) { |
| 2031 | chan->direction = DMA_DEV_TO_MEM; |
| 2032 | chan->id = 1; |
| 2033 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2034 | chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 2035 | if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 2036 | chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2037 | |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 2038 | if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH || |
| 2039 | xdev->flush_on_fsync == XILINX_DMA_FLUSH_S2MM) |
| 2040 | chan->flush_on_fsync = true; |
| 2041 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2042 | } else { |
| 2043 | dev_err(xdev->dev, "Invalid channel compatible node\n"); |
| 2044 | return -EINVAL; |
| 2045 | } |
| 2046 | |
| 2047 | /* Request the interrupt */ |
| 2048 | chan->irq = irq_of_parse_and_map(node, 0); |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2049 | err = request_irq(chan->irq, xilinx_dma_irq_handler, IRQF_SHARED, |
| 2050 | "xilinx-dma-controller", chan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2051 | if (err) { |
| 2052 | dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq); |
| 2053 | return err; |
| 2054 | } |
| 2055 | |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 2056 | if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 2057 | chan->start_transfer = xilinx_dma_start_transfer; |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 2058 | else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame] | 2059 | chan->start_transfer = xilinx_cdma_start_transfer; |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 2060 | else |
| 2061 | chan->start_transfer = xilinx_vdma_start_transfer; |
| 2062 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2063 | /* Initialize the tasklet */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2064 | tasklet_init(&chan->tasklet, xilinx_dma_do_tasklet, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2065 | (unsigned long)chan); |
| 2066 | |
| 2067 | /* |
| 2068 | * Initialize the DMA channel and add it to the DMA engine channels |
| 2069 | * list. |
| 2070 | */ |
| 2071 | chan->common.device = &xdev->common; |
| 2072 | |
| 2073 | list_add_tail(&chan->common.device_node, &xdev->common.channels); |
| 2074 | xdev->chan[chan->id] = chan; |
| 2075 | |
| 2076 | /* Reset the channel */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2077 | err = xilinx_dma_chan_reset(chan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2078 | if (err < 0) { |
| 2079 | dev_err(xdev->dev, "Reset channel failed\n"); |
| 2080 | return err; |
| 2081 | } |
| 2082 | |
| 2083 | return 0; |
| 2084 | } |
| 2085 | |
| 2086 | /** |
| 2087 | * of_dma_xilinx_xlate - Translation function |
| 2088 | * @dma_spec: Pointer to DMA specifier as found in the device tree |
| 2089 | * @ofdma: Pointer to DMA controller data |
| 2090 | * |
| 2091 | * Return: DMA channel pointer on success and NULL on error |
| 2092 | */ |
| 2093 | static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec, |
| 2094 | struct of_dma *ofdma) |
| 2095 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2096 | struct xilinx_dma_device *xdev = ofdma->of_dma_data; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2097 | int chan_id = dma_spec->args[0]; |
| 2098 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2099 | if (chan_id >= XILINX_DMA_MAX_CHANS_PER_DEVICE) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2100 | return NULL; |
| 2101 | |
| 2102 | return dma_get_slave_channel(&xdev->chan[chan_id]->common); |
| 2103 | } |
| 2104 | |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 2105 | static const struct xilinx_dma_config axidma_config = { |
| 2106 | .dmatype = XDMA_TYPE_AXIDMA, |
Kedareswara rao Appana | ba16db3 | 2016-05-13 12:33:31 +0530 | [diff] [blame^] | 2107 | .clk_init = axidma_clk_init, |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 2108 | }; |
| 2109 | |
| 2110 | static const struct xilinx_dma_config axicdma_config = { |
| 2111 | .dmatype = XDMA_TYPE_CDMA, |
Kedareswara rao Appana | ba16db3 | 2016-05-13 12:33:31 +0530 | [diff] [blame^] | 2112 | .clk_init = axicdma_clk_init, |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 2113 | }; |
| 2114 | |
| 2115 | static const struct xilinx_dma_config axivdma_config = { |
| 2116 | .dmatype = XDMA_TYPE_VDMA, |
Kedareswara rao Appana | ba16db3 | 2016-05-13 12:33:31 +0530 | [diff] [blame^] | 2117 | .clk_init = axivdma_clk_init, |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 2118 | }; |
| 2119 | |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 2120 | static const struct of_device_id xilinx_dma_of_ids[] = { |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 2121 | { .compatible = "xlnx,axi-dma-1.00.a", .data = &axidma_config }, |
| 2122 | { .compatible = "xlnx,axi-cdma-1.00.a", .data = &axicdma_config }, |
| 2123 | { .compatible = "xlnx,axi-vdma-1.00.a", .data = &axivdma_config }, |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 2124 | {} |
| 2125 | }; |
| 2126 | MODULE_DEVICE_TABLE(of, xilinx_dma_of_ids); |
| 2127 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2128 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2129 | * xilinx_dma_probe - Driver probe function |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2130 | * @pdev: Pointer to the platform_device structure |
| 2131 | * |
| 2132 | * Return: '0' on success and failure value on error |
| 2133 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2134 | static int xilinx_dma_probe(struct platform_device *pdev) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2135 | { |
Kedareswara rao Appana | ba16db3 | 2016-05-13 12:33:31 +0530 | [diff] [blame^] | 2136 | int (*clk_init)(struct platform_device *, struct clk **, struct clk **, |
| 2137 | struct clk **, struct clk **, struct clk **) |
| 2138 | = axivdma_clk_init; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2139 | struct device_node *node = pdev->dev.of_node; |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2140 | struct xilinx_dma_device *xdev; |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 2141 | struct device_node *child, *np = pdev->dev.of_node; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2142 | struct resource *io; |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 2143 | u32 num_frames, addr_width; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2144 | int i, err; |
| 2145 | |
| 2146 | /* Allocate and initialize the DMA engine structure */ |
| 2147 | xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL); |
| 2148 | if (!xdev) |
| 2149 | return -ENOMEM; |
| 2150 | |
| 2151 | xdev->dev = &pdev->dev; |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 2152 | if (np) { |
| 2153 | const struct of_device_id *match; |
| 2154 | |
| 2155 | match = of_match_node(xilinx_dma_of_ids, np); |
Kedareswara rao Appana | ba16db3 | 2016-05-13 12:33:31 +0530 | [diff] [blame^] | 2156 | if (match && match->data) { |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 2157 | xdev->dma_config = match->data; |
Kedareswara rao Appana | ba16db3 | 2016-05-13 12:33:31 +0530 | [diff] [blame^] | 2158 | clk_init = xdev->dma_config->clk_init; |
| 2159 | } |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 2160 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2161 | |
Kedareswara rao Appana | ba16db3 | 2016-05-13 12:33:31 +0530 | [diff] [blame^] | 2162 | err = clk_init(pdev, &xdev->axi_clk, &xdev->tx_clk, &xdev->txs_clk, |
| 2163 | &xdev->rx_clk, &xdev->rxs_clk); |
| 2164 | if (err) |
| 2165 | return err; |
| 2166 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2167 | /* Request and map I/O memory */ |
| 2168 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 2169 | xdev->regs = devm_ioremap_resource(&pdev->dev, io); |
| 2170 | if (IS_ERR(xdev->regs)) |
| 2171 | return PTR_ERR(xdev->regs); |
| 2172 | |
| 2173 | /* Retrieve the DMA engine properties from the device tree */ |
| 2174 | xdev->has_sg = of_property_read_bool(node, "xlnx,include-sg"); |
| 2175 | |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 2176 | if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 2177 | err = of_property_read_u32(node, "xlnx,num-fstores", |
| 2178 | &num_frames); |
| 2179 | if (err < 0) { |
| 2180 | dev_err(xdev->dev, |
| 2181 | "missing xlnx,num-fstores property\n"); |
| 2182 | return err; |
| 2183 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2184 | |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 2185 | err = of_property_read_u32(node, "xlnx,flush-fsync", |
| 2186 | &xdev->flush_on_fsync); |
| 2187 | if (err < 0) |
| 2188 | dev_warn(xdev->dev, |
| 2189 | "missing xlnx,flush-fsync property\n"); |
| 2190 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2191 | |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 2192 | err = of_property_read_u32(node, "xlnx,addrwidth", &addr_width); |
| 2193 | if (err < 0) |
| 2194 | dev_warn(xdev->dev, "missing xlnx,addrwidth property\n"); |
| 2195 | |
| 2196 | if (addr_width > 32) |
| 2197 | xdev->ext_addr = true; |
| 2198 | else |
| 2199 | xdev->ext_addr = false; |
| 2200 | |
| 2201 | /* Set the dma mask bits */ |
| 2202 | dma_set_mask(xdev->dev, DMA_BIT_MASK(addr_width)); |
| 2203 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2204 | /* Initialize the DMA engine */ |
| 2205 | xdev->common.dev = &pdev->dev; |
| 2206 | |
| 2207 | INIT_LIST_HEAD(&xdev->common.channels); |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 2208 | if (!(xdev->dma_config->dmatype == XDMA_TYPE_CDMA)) { |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame] | 2209 | dma_cap_set(DMA_SLAVE, xdev->common.cap_mask); |
| 2210 | dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask); |
| 2211 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2212 | |
| 2213 | xdev->common.device_alloc_chan_resources = |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2214 | xilinx_dma_alloc_chan_resources; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2215 | xdev->common.device_free_chan_resources = |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2216 | xilinx_dma_free_chan_resources; |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2217 | xdev->common.device_terminate_all = xilinx_dma_terminate_all; |
| 2218 | xdev->common.device_tx_status = xilinx_dma_tx_status; |
| 2219 | xdev->common.device_issue_pending = xilinx_dma_issue_pending; |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 2220 | if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 2221 | xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg; |
| 2222 | /* Residue calculation is supported by only AXI DMA */ |
| 2223 | xdev->common.residue_granularity = |
| 2224 | DMA_RESIDUE_GRANULARITY_SEGMENT; |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 2225 | } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame] | 2226 | dma_cap_set(DMA_MEMCPY, xdev->common.cap_mask); |
| 2227 | xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy; |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 2228 | } else { |
| 2229 | xdev->common.device_prep_interleaved_dma = |
| 2230 | xilinx_vdma_dma_prep_interleaved; |
| 2231 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2232 | |
| 2233 | platform_set_drvdata(pdev, xdev); |
| 2234 | |
| 2235 | /* Initialize the channels */ |
| 2236 | for_each_child_of_node(node, child) { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2237 | err = xilinx_dma_chan_probe(xdev, child); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2238 | if (err < 0) |
Kedareswara rao Appana | ba16db3 | 2016-05-13 12:33:31 +0530 | [diff] [blame^] | 2239 | goto disable_clks; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2240 | } |
| 2241 | |
Kedareswara rao Appana | fb23666 | 2016-05-13 12:33:29 +0530 | [diff] [blame] | 2242 | if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 2243 | for (i = 0; i < XILINX_DMA_MAX_CHANS_PER_DEVICE; i++) |
| 2244 | if (xdev->chan[i]) |
| 2245 | xdev->chan[i]->num_frms = num_frames; |
| 2246 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2247 | |
| 2248 | /* Register the DMA engine with the core */ |
| 2249 | dma_async_device_register(&xdev->common); |
| 2250 | |
| 2251 | err = of_dma_controller_register(node, of_dma_xilinx_xlate, |
| 2252 | xdev); |
| 2253 | if (err < 0) { |
| 2254 | dev_err(&pdev->dev, "Unable to register DMA to DT\n"); |
| 2255 | dma_async_device_unregister(&xdev->common); |
| 2256 | goto error; |
| 2257 | } |
| 2258 | |
| 2259 | dev_info(&pdev->dev, "Xilinx AXI VDMA Engine Driver Probed!!\n"); |
| 2260 | |
| 2261 | return 0; |
| 2262 | |
Kedareswara rao Appana | ba16db3 | 2016-05-13 12:33:31 +0530 | [diff] [blame^] | 2263 | disable_clks: |
| 2264 | xdma_disable_allclks(xdev); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2265 | error: |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2266 | for (i = 0; i < XILINX_DMA_MAX_CHANS_PER_DEVICE; i++) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2267 | if (xdev->chan[i]) |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2268 | xilinx_dma_chan_remove(xdev->chan[i]); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2269 | |
| 2270 | return err; |
| 2271 | } |
| 2272 | |
| 2273 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2274 | * xilinx_dma_remove - Driver remove function |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2275 | * @pdev: Pointer to the platform_device structure |
| 2276 | * |
| 2277 | * Return: Always '0' |
| 2278 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2279 | static int xilinx_dma_remove(struct platform_device *pdev) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2280 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2281 | struct xilinx_dma_device *xdev = platform_get_drvdata(pdev); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2282 | int i; |
| 2283 | |
| 2284 | of_dma_controller_free(pdev->dev.of_node); |
| 2285 | |
| 2286 | dma_async_device_unregister(&xdev->common); |
| 2287 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2288 | for (i = 0; i < XILINX_DMA_MAX_CHANS_PER_DEVICE; i++) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2289 | if (xdev->chan[i]) |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2290 | xilinx_dma_chan_remove(xdev->chan[i]); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2291 | |
Kedareswara rao Appana | ba16db3 | 2016-05-13 12:33:31 +0530 | [diff] [blame^] | 2292 | xdma_disable_allclks(xdev); |
| 2293 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2294 | return 0; |
| 2295 | } |
| 2296 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2297 | static struct platform_driver xilinx_vdma_driver = { |
| 2298 | .driver = { |
| 2299 | .name = "xilinx-vdma", |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2300 | .of_match_table = xilinx_dma_of_ids, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2301 | }, |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2302 | .probe = xilinx_dma_probe, |
| 2303 | .remove = xilinx_dma_remove, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2304 | }; |
| 2305 | |
| 2306 | module_platform_driver(xilinx_vdma_driver); |
| 2307 | |
| 2308 | MODULE_AUTHOR("Xilinx, Inc."); |
| 2309 | MODULE_DESCRIPTION("Xilinx VDMA driver"); |
| 2310 | MODULE_LICENSE("GPL v2"); |