Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Alex Deucher |
| 23 | */ |
| 24 | #include <linux/firmware.h> |
| 25 | #include <linux/platform_device.h> |
| 26 | #include <linux/slab.h> |
| 27 | #include <linux/module.h> |
| 28 | #include "drmP.h" |
| 29 | #include "radeon.h" |
Alex Deucher | 6f2043c | 2013-04-09 12:43:41 -0400 | [diff] [blame] | 30 | #include "radeon_asic.h" |
Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 31 | #include "cikd.h" |
| 32 | #include "atom.h" |
| 33 | |
Alex Deucher | 02c8132 | 2012-12-18 21:43:07 -0500 | [diff] [blame] | 34 | /* GFX */ |
| 35 | #define CIK_PFP_UCODE_SIZE 2144 |
| 36 | #define CIK_ME_UCODE_SIZE 2144 |
| 37 | #define CIK_CE_UCODE_SIZE 2144 |
| 38 | /* compute */ |
| 39 | #define CIK_MEC_UCODE_SIZE 4192 |
| 40 | /* interrupts */ |
| 41 | #define BONAIRE_RLC_UCODE_SIZE 2048 |
| 42 | #define KB_RLC_UCODE_SIZE 2560 |
| 43 | #define KV_RLC_UCODE_SIZE 2560 |
| 44 | /* gddr controller */ |
| 45 | #define CIK_MC_UCODE_SIZE 7866 |
| 46 | |
| 47 | MODULE_FIRMWARE("radeon/BONAIRE_pfp.bin"); |
| 48 | MODULE_FIRMWARE("radeon/BONAIRE_me.bin"); |
| 49 | MODULE_FIRMWARE("radeon/BONAIRE_ce.bin"); |
| 50 | MODULE_FIRMWARE("radeon/BONAIRE_mec.bin"); |
| 51 | MODULE_FIRMWARE("radeon/BONAIRE_mc.bin"); |
| 52 | MODULE_FIRMWARE("radeon/BONAIRE_rlc.bin"); |
| 53 | MODULE_FIRMWARE("radeon/KAVERI_pfp.bin"); |
| 54 | MODULE_FIRMWARE("radeon/KAVERI_me.bin"); |
| 55 | MODULE_FIRMWARE("radeon/KAVERI_ce.bin"); |
| 56 | MODULE_FIRMWARE("radeon/KAVERI_mec.bin"); |
| 57 | MODULE_FIRMWARE("radeon/KAVERI_rlc.bin"); |
| 58 | MODULE_FIRMWARE("radeon/KABINI_pfp.bin"); |
| 59 | MODULE_FIRMWARE("radeon/KABINI_me.bin"); |
| 60 | MODULE_FIRMWARE("radeon/KABINI_ce.bin"); |
| 61 | MODULE_FIRMWARE("radeon/KABINI_mec.bin"); |
| 62 | MODULE_FIRMWARE("radeon/KABINI_rlc.bin"); |
| 63 | |
Alex Deucher | 6f2043c | 2013-04-09 12:43:41 -0400 | [diff] [blame] | 64 | extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); |
| 65 | extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); |
Alex Deucher | 1c49165 | 2013-04-09 12:45:26 -0400 | [diff] [blame] | 66 | extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
Alex Deucher | 6f2043c | 2013-04-09 12:43:41 -0400 | [diff] [blame] | 67 | |
Alex Deucher | bc8273f | 2012-06-29 19:44:04 -0400 | [diff] [blame^] | 68 | #define BONAIRE_IO_MC_REGS_SIZE 36 |
| 69 | |
| 70 | static const u32 bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] = |
| 71 | { |
| 72 | {0x00000070, 0x04400000}, |
| 73 | {0x00000071, 0x80c01803}, |
| 74 | {0x00000072, 0x00004004}, |
| 75 | {0x00000073, 0x00000100}, |
| 76 | {0x00000074, 0x00ff0000}, |
| 77 | {0x00000075, 0x34000000}, |
| 78 | {0x00000076, 0x08000014}, |
| 79 | {0x00000077, 0x00cc08ec}, |
| 80 | {0x00000078, 0x00000400}, |
| 81 | {0x00000079, 0x00000000}, |
| 82 | {0x0000007a, 0x04090000}, |
| 83 | {0x0000007c, 0x00000000}, |
| 84 | {0x0000007e, 0x4408a8e8}, |
| 85 | {0x0000007f, 0x00000304}, |
| 86 | {0x00000080, 0x00000000}, |
| 87 | {0x00000082, 0x00000001}, |
| 88 | {0x00000083, 0x00000002}, |
| 89 | {0x00000084, 0xf3e4f400}, |
| 90 | {0x00000085, 0x052024e3}, |
| 91 | {0x00000087, 0x00000000}, |
| 92 | {0x00000088, 0x01000000}, |
| 93 | {0x0000008a, 0x1c0a0000}, |
| 94 | {0x0000008b, 0xff010000}, |
| 95 | {0x0000008d, 0xffffefff}, |
| 96 | {0x0000008e, 0xfff3efff}, |
| 97 | {0x0000008f, 0xfff3efbf}, |
| 98 | {0x00000092, 0xf7ffffff}, |
| 99 | {0x00000093, 0xffffff7f}, |
| 100 | {0x00000095, 0x00101101}, |
| 101 | {0x00000096, 0x00000fff}, |
| 102 | {0x00000097, 0x00116fff}, |
| 103 | {0x00000098, 0x60010000}, |
| 104 | {0x00000099, 0x10010000}, |
| 105 | {0x0000009a, 0x00006000}, |
| 106 | {0x0000009b, 0x00001000}, |
| 107 | {0x0000009f, 0x00b48000} |
| 108 | }; |
| 109 | |
| 110 | /* ucode loading */ |
| 111 | /** |
| 112 | * ci_mc_load_microcode - load MC ucode into the hw |
| 113 | * |
| 114 | * @rdev: radeon_device pointer |
| 115 | * |
| 116 | * Load the GDDR MC ucode into the hw (CIK). |
| 117 | * Returns 0 on success, error on failure. |
| 118 | */ |
| 119 | static int ci_mc_load_microcode(struct radeon_device *rdev) |
| 120 | { |
| 121 | const __be32 *fw_data; |
| 122 | u32 running, blackout = 0; |
| 123 | u32 *io_mc_regs; |
| 124 | int i, ucode_size, regs_size; |
| 125 | |
| 126 | if (!rdev->mc_fw) |
| 127 | return -EINVAL; |
| 128 | |
| 129 | switch (rdev->family) { |
| 130 | case CHIP_BONAIRE: |
| 131 | default: |
| 132 | io_mc_regs = (u32 *)&bonaire_io_mc_regs; |
| 133 | ucode_size = CIK_MC_UCODE_SIZE; |
| 134 | regs_size = BONAIRE_IO_MC_REGS_SIZE; |
| 135 | break; |
| 136 | } |
| 137 | |
| 138 | running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; |
| 139 | |
| 140 | if (running == 0) { |
| 141 | if (running) { |
| 142 | blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); |
| 143 | WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); |
| 144 | } |
| 145 | |
| 146 | /* reset the engine and set to writable */ |
| 147 | WREG32(MC_SEQ_SUP_CNTL, 0x00000008); |
| 148 | WREG32(MC_SEQ_SUP_CNTL, 0x00000010); |
| 149 | |
| 150 | /* load mc io regs */ |
| 151 | for (i = 0; i < regs_size; i++) { |
| 152 | WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); |
| 153 | WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); |
| 154 | } |
| 155 | /* load the MC ucode */ |
| 156 | fw_data = (const __be32 *)rdev->mc_fw->data; |
| 157 | for (i = 0; i < ucode_size; i++) |
| 158 | WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); |
| 159 | |
| 160 | /* put the engine back into the active state */ |
| 161 | WREG32(MC_SEQ_SUP_CNTL, 0x00000008); |
| 162 | WREG32(MC_SEQ_SUP_CNTL, 0x00000004); |
| 163 | WREG32(MC_SEQ_SUP_CNTL, 0x00000001); |
| 164 | |
| 165 | /* wait for training to complete */ |
| 166 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 167 | if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) |
| 168 | break; |
| 169 | udelay(1); |
| 170 | } |
| 171 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 172 | if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1) |
| 173 | break; |
| 174 | udelay(1); |
| 175 | } |
| 176 | |
| 177 | if (running) |
| 178 | WREG32(MC_SHARED_BLACKOUT_CNTL, blackout); |
| 179 | } |
| 180 | |
| 181 | return 0; |
| 182 | } |
| 183 | |
Alex Deucher | 02c8132 | 2012-12-18 21:43:07 -0500 | [diff] [blame] | 184 | /** |
| 185 | * cik_init_microcode - load ucode images from disk |
| 186 | * |
| 187 | * @rdev: radeon_device pointer |
| 188 | * |
| 189 | * Use the firmware interface to load the ucode images into |
| 190 | * the driver (not loaded into hw). |
| 191 | * Returns 0 on success, error on failure. |
| 192 | */ |
| 193 | static int cik_init_microcode(struct radeon_device *rdev) |
| 194 | { |
| 195 | struct platform_device *pdev; |
| 196 | const char *chip_name; |
| 197 | size_t pfp_req_size, me_req_size, ce_req_size, |
| 198 | mec_req_size, rlc_req_size, mc_req_size; |
| 199 | char fw_name[30]; |
| 200 | int err; |
| 201 | |
| 202 | DRM_DEBUG("\n"); |
| 203 | |
| 204 | pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); |
| 205 | err = IS_ERR(pdev); |
| 206 | if (err) { |
| 207 | printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); |
| 208 | return -EINVAL; |
| 209 | } |
| 210 | |
| 211 | switch (rdev->family) { |
| 212 | case CHIP_BONAIRE: |
| 213 | chip_name = "BONAIRE"; |
| 214 | pfp_req_size = CIK_PFP_UCODE_SIZE * 4; |
| 215 | me_req_size = CIK_ME_UCODE_SIZE * 4; |
| 216 | ce_req_size = CIK_CE_UCODE_SIZE * 4; |
| 217 | mec_req_size = CIK_MEC_UCODE_SIZE * 4; |
| 218 | rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4; |
| 219 | mc_req_size = CIK_MC_UCODE_SIZE * 4; |
| 220 | break; |
| 221 | case CHIP_KAVERI: |
| 222 | chip_name = "KAVERI"; |
| 223 | pfp_req_size = CIK_PFP_UCODE_SIZE * 4; |
| 224 | me_req_size = CIK_ME_UCODE_SIZE * 4; |
| 225 | ce_req_size = CIK_CE_UCODE_SIZE * 4; |
| 226 | mec_req_size = CIK_MEC_UCODE_SIZE * 4; |
| 227 | rlc_req_size = KV_RLC_UCODE_SIZE * 4; |
| 228 | break; |
| 229 | case CHIP_KABINI: |
| 230 | chip_name = "KABINI"; |
| 231 | pfp_req_size = CIK_PFP_UCODE_SIZE * 4; |
| 232 | me_req_size = CIK_ME_UCODE_SIZE * 4; |
| 233 | ce_req_size = CIK_CE_UCODE_SIZE * 4; |
| 234 | mec_req_size = CIK_MEC_UCODE_SIZE * 4; |
| 235 | rlc_req_size = KB_RLC_UCODE_SIZE * 4; |
| 236 | break; |
| 237 | default: BUG(); |
| 238 | } |
| 239 | |
| 240 | DRM_INFO("Loading %s Microcode\n", chip_name); |
| 241 | |
| 242 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); |
| 243 | err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); |
| 244 | if (err) |
| 245 | goto out; |
| 246 | if (rdev->pfp_fw->size != pfp_req_size) { |
| 247 | printk(KERN_ERR |
| 248 | "cik_cp: Bogus length %zu in firmware \"%s\"\n", |
| 249 | rdev->pfp_fw->size, fw_name); |
| 250 | err = -EINVAL; |
| 251 | goto out; |
| 252 | } |
| 253 | |
| 254 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); |
| 255 | err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); |
| 256 | if (err) |
| 257 | goto out; |
| 258 | if (rdev->me_fw->size != me_req_size) { |
| 259 | printk(KERN_ERR |
| 260 | "cik_cp: Bogus length %zu in firmware \"%s\"\n", |
| 261 | rdev->me_fw->size, fw_name); |
| 262 | err = -EINVAL; |
| 263 | } |
| 264 | |
| 265 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name); |
| 266 | err = request_firmware(&rdev->ce_fw, fw_name, &pdev->dev); |
| 267 | if (err) |
| 268 | goto out; |
| 269 | if (rdev->ce_fw->size != ce_req_size) { |
| 270 | printk(KERN_ERR |
| 271 | "cik_cp: Bogus length %zu in firmware \"%s\"\n", |
| 272 | rdev->ce_fw->size, fw_name); |
| 273 | err = -EINVAL; |
| 274 | } |
| 275 | |
| 276 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name); |
| 277 | err = request_firmware(&rdev->mec_fw, fw_name, &pdev->dev); |
| 278 | if (err) |
| 279 | goto out; |
| 280 | if (rdev->mec_fw->size != mec_req_size) { |
| 281 | printk(KERN_ERR |
| 282 | "cik_cp: Bogus length %zu in firmware \"%s\"\n", |
| 283 | rdev->mec_fw->size, fw_name); |
| 284 | err = -EINVAL; |
| 285 | } |
| 286 | |
| 287 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name); |
| 288 | err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); |
| 289 | if (err) |
| 290 | goto out; |
| 291 | if (rdev->rlc_fw->size != rlc_req_size) { |
| 292 | printk(KERN_ERR |
| 293 | "cik_rlc: Bogus length %zu in firmware \"%s\"\n", |
| 294 | rdev->rlc_fw->size, fw_name); |
| 295 | err = -EINVAL; |
| 296 | } |
| 297 | |
| 298 | /* No MC ucode on APUs */ |
| 299 | if (!(rdev->flags & RADEON_IS_IGP)) { |
| 300 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); |
| 301 | err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev); |
| 302 | if (err) |
| 303 | goto out; |
| 304 | if (rdev->mc_fw->size != mc_req_size) { |
| 305 | printk(KERN_ERR |
| 306 | "cik_mc: Bogus length %zu in firmware \"%s\"\n", |
| 307 | rdev->mc_fw->size, fw_name); |
| 308 | err = -EINVAL; |
| 309 | } |
| 310 | } |
| 311 | |
| 312 | out: |
| 313 | platform_device_unregister(pdev); |
| 314 | |
| 315 | if (err) { |
| 316 | if (err != -EINVAL) |
| 317 | printk(KERN_ERR |
| 318 | "cik_cp: Failed to load firmware \"%s\"\n", |
| 319 | fw_name); |
| 320 | release_firmware(rdev->pfp_fw); |
| 321 | rdev->pfp_fw = NULL; |
| 322 | release_firmware(rdev->me_fw); |
| 323 | rdev->me_fw = NULL; |
| 324 | release_firmware(rdev->ce_fw); |
| 325 | rdev->ce_fw = NULL; |
| 326 | release_firmware(rdev->rlc_fw); |
| 327 | rdev->rlc_fw = NULL; |
| 328 | release_firmware(rdev->mc_fw); |
| 329 | rdev->mc_fw = NULL; |
| 330 | } |
| 331 | return err; |
| 332 | } |
| 333 | |
Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 334 | /* |
| 335 | * Core functions |
| 336 | */ |
| 337 | /** |
| 338 | * cik_tiling_mode_table_init - init the hw tiling table |
| 339 | * |
| 340 | * @rdev: radeon_device pointer |
| 341 | * |
| 342 | * Starting with SI, the tiling setup is done globally in a |
| 343 | * set of 32 tiling modes. Rather than selecting each set of |
| 344 | * parameters per surface as on older asics, we just select |
| 345 | * which index in the tiling table we want to use, and the |
| 346 | * surface uses those parameters (CIK). |
| 347 | */ |
| 348 | static void cik_tiling_mode_table_init(struct radeon_device *rdev) |
| 349 | { |
| 350 | const u32 num_tile_mode_states = 32; |
| 351 | const u32 num_secondary_tile_mode_states = 16; |
| 352 | u32 reg_offset, gb_tile_moden, split_equal_to_row_size; |
| 353 | u32 num_pipe_configs; |
| 354 | u32 num_rbs = rdev->config.cik.max_backends_per_se * |
| 355 | rdev->config.cik.max_shader_engines; |
| 356 | |
| 357 | switch (rdev->config.cik.mem_row_size_in_kb) { |
| 358 | case 1: |
| 359 | split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; |
| 360 | break; |
| 361 | case 2: |
| 362 | default: |
| 363 | split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; |
| 364 | break; |
| 365 | case 4: |
| 366 | split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; |
| 367 | break; |
| 368 | } |
| 369 | |
| 370 | num_pipe_configs = rdev->config.cik.max_tile_pipes; |
| 371 | if (num_pipe_configs > 8) |
| 372 | num_pipe_configs = 8; /* ??? */ |
| 373 | |
| 374 | if (num_pipe_configs == 8) { |
| 375 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { |
| 376 | switch (reg_offset) { |
| 377 | case 0: |
| 378 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 379 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 380 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 381 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)); |
| 382 | break; |
| 383 | case 1: |
| 384 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 385 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 386 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 387 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)); |
| 388 | break; |
| 389 | case 2: |
| 390 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 391 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 392 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 393 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); |
| 394 | break; |
| 395 | case 3: |
| 396 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 397 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 398 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 399 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B)); |
| 400 | break; |
| 401 | case 4: |
| 402 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 403 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 404 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 405 | TILE_SPLIT(split_equal_to_row_size)); |
| 406 | break; |
| 407 | case 5: |
| 408 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 409 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 410 | break; |
| 411 | case 6: |
| 412 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| 413 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 414 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 415 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); |
| 416 | break; |
| 417 | case 7: |
| 418 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| 419 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 420 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 421 | TILE_SPLIT(split_equal_to_row_size)); |
| 422 | break; |
| 423 | case 8: |
| 424 | gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | |
| 425 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)); |
| 426 | break; |
| 427 | case 9: |
| 428 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 429 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); |
| 430 | break; |
| 431 | case 10: |
| 432 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 433 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 434 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 435 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 436 | break; |
| 437 | case 11: |
| 438 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 439 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 440 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | |
| 441 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 442 | break; |
| 443 | case 12: |
| 444 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| 445 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 446 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 447 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 448 | break; |
| 449 | case 13: |
| 450 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 451 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); |
| 452 | break; |
| 453 | case 14: |
| 454 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 455 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 456 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 457 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 458 | break; |
| 459 | case 16: |
| 460 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 461 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 462 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | |
| 463 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 464 | break; |
| 465 | case 17: |
| 466 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| 467 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 468 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 469 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 470 | break; |
| 471 | case 27: |
| 472 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 473 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); |
| 474 | break; |
| 475 | case 28: |
| 476 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 477 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| 478 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 479 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 480 | break; |
| 481 | case 29: |
| 482 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 483 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| 484 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | |
| 485 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 486 | break; |
| 487 | case 30: |
| 488 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| 489 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| 490 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 491 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 492 | break; |
| 493 | default: |
| 494 | gb_tile_moden = 0; |
| 495 | break; |
| 496 | } |
| 497 | WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); |
| 498 | } |
| 499 | for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { |
| 500 | switch (reg_offset) { |
| 501 | case 0: |
| 502 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 503 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 504 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 505 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 506 | break; |
| 507 | case 1: |
| 508 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 509 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| 510 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 511 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 512 | break; |
| 513 | case 2: |
| 514 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 515 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 516 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 517 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 518 | break; |
| 519 | case 3: |
| 520 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 521 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 522 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 523 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 524 | break; |
| 525 | case 4: |
| 526 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 527 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 528 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 529 | NUM_BANKS(ADDR_SURF_8_BANK)); |
| 530 | break; |
| 531 | case 5: |
| 532 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 533 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 534 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 535 | NUM_BANKS(ADDR_SURF_4_BANK)); |
| 536 | break; |
| 537 | case 6: |
| 538 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 539 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 540 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 541 | NUM_BANKS(ADDR_SURF_2_BANK)); |
| 542 | break; |
| 543 | case 8: |
| 544 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 545 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | |
| 546 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 547 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 548 | break; |
| 549 | case 9: |
| 550 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 551 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 552 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 553 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 554 | break; |
| 555 | case 10: |
| 556 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 557 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| 558 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 559 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 560 | break; |
| 561 | case 11: |
| 562 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 563 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 564 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 565 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 566 | break; |
| 567 | case 12: |
| 568 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 569 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 570 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 571 | NUM_BANKS(ADDR_SURF_8_BANK)); |
| 572 | break; |
| 573 | case 13: |
| 574 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 575 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 576 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 577 | NUM_BANKS(ADDR_SURF_4_BANK)); |
| 578 | break; |
| 579 | case 14: |
| 580 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 581 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 582 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 583 | NUM_BANKS(ADDR_SURF_2_BANK)); |
| 584 | break; |
| 585 | default: |
| 586 | gb_tile_moden = 0; |
| 587 | break; |
| 588 | } |
| 589 | WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); |
| 590 | } |
| 591 | } else if (num_pipe_configs == 4) { |
| 592 | if (num_rbs == 4) { |
| 593 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { |
| 594 | switch (reg_offset) { |
| 595 | case 0: |
| 596 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 597 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 598 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| 599 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)); |
| 600 | break; |
| 601 | case 1: |
| 602 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 603 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 604 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| 605 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)); |
| 606 | break; |
| 607 | case 2: |
| 608 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 609 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 610 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| 611 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); |
| 612 | break; |
| 613 | case 3: |
| 614 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 615 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 616 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| 617 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B)); |
| 618 | break; |
| 619 | case 4: |
| 620 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 621 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 622 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| 623 | TILE_SPLIT(split_equal_to_row_size)); |
| 624 | break; |
| 625 | case 5: |
| 626 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 627 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 628 | break; |
| 629 | case 6: |
| 630 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| 631 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 632 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| 633 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); |
| 634 | break; |
| 635 | case 7: |
| 636 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| 637 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 638 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| 639 | TILE_SPLIT(split_equal_to_row_size)); |
| 640 | break; |
| 641 | case 8: |
| 642 | gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | |
| 643 | PIPE_CONFIG(ADDR_SURF_P4_16x16)); |
| 644 | break; |
| 645 | case 9: |
| 646 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 647 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); |
| 648 | break; |
| 649 | case 10: |
| 650 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 651 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 652 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| 653 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 654 | break; |
| 655 | case 11: |
| 656 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 657 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 658 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | |
| 659 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 660 | break; |
| 661 | case 12: |
| 662 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| 663 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 664 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| 665 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 666 | break; |
| 667 | case 13: |
| 668 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 669 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); |
| 670 | break; |
| 671 | case 14: |
| 672 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 673 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 674 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| 675 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 676 | break; |
| 677 | case 16: |
| 678 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 679 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 680 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | |
| 681 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 682 | break; |
| 683 | case 17: |
| 684 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| 685 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 686 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| 687 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 688 | break; |
| 689 | case 27: |
| 690 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 691 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); |
| 692 | break; |
| 693 | case 28: |
| 694 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| 695 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| 696 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| 697 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 698 | break; |
| 699 | case 29: |
| 700 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 701 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| 702 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | |
| 703 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 704 | break; |
| 705 | case 30: |
| 706 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| 707 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| 708 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| 709 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 710 | break; |
| 711 | default: |
| 712 | gb_tile_moden = 0; |
| 713 | break; |
| 714 | } |
| 715 | WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); |
| 716 | } |
| 717 | } else if (num_rbs < 4) { |
| 718 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { |
| 719 | switch (reg_offset) { |
| 720 | case 0: |
| 721 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 722 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 723 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | |
| 724 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)); |
| 725 | break; |
| 726 | case 1: |
| 727 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 728 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 729 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | |
| 730 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)); |
| 731 | break; |
| 732 | case 2: |
| 733 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 734 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 735 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | |
| 736 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); |
| 737 | break; |
| 738 | case 3: |
| 739 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 740 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 741 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | |
| 742 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B)); |
| 743 | break; |
| 744 | case 4: |
| 745 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 746 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 747 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | |
| 748 | TILE_SPLIT(split_equal_to_row_size)); |
| 749 | break; |
| 750 | case 5: |
| 751 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 752 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 753 | break; |
| 754 | case 6: |
| 755 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| 756 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 757 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | |
| 758 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); |
| 759 | break; |
| 760 | case 7: |
| 761 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| 762 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 763 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | |
| 764 | TILE_SPLIT(split_equal_to_row_size)); |
| 765 | break; |
| 766 | case 8: |
| 767 | gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | |
| 768 | PIPE_CONFIG(ADDR_SURF_P4_8x16)); |
| 769 | break; |
| 770 | case 9: |
| 771 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 772 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); |
| 773 | break; |
| 774 | case 10: |
| 775 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 776 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 777 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | |
| 778 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 779 | break; |
| 780 | case 11: |
| 781 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 782 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 783 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | |
| 784 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 785 | break; |
| 786 | case 12: |
| 787 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| 788 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 789 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | |
| 790 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 791 | break; |
| 792 | case 13: |
| 793 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 794 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); |
| 795 | break; |
| 796 | case 14: |
| 797 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 798 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 799 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | |
| 800 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 801 | break; |
| 802 | case 16: |
| 803 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 804 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 805 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | |
| 806 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 807 | break; |
| 808 | case 17: |
| 809 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| 810 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 811 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | |
| 812 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 813 | break; |
| 814 | case 27: |
| 815 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 816 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); |
| 817 | break; |
| 818 | case 28: |
| 819 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| 820 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| 821 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | |
| 822 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 823 | break; |
| 824 | case 29: |
| 825 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 826 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| 827 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | |
| 828 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 829 | break; |
| 830 | case 30: |
| 831 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| 832 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| 833 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | |
| 834 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 835 | break; |
| 836 | default: |
| 837 | gb_tile_moden = 0; |
| 838 | break; |
| 839 | } |
| 840 | WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); |
| 841 | } |
| 842 | } |
| 843 | for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { |
| 844 | switch (reg_offset) { |
| 845 | case 0: |
| 846 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 847 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 848 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 849 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 850 | break; |
| 851 | case 1: |
| 852 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 853 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| 854 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 855 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 856 | break; |
| 857 | case 2: |
| 858 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 859 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 860 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 861 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 862 | break; |
| 863 | case 3: |
| 864 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 865 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 866 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 867 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 868 | break; |
| 869 | case 4: |
| 870 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 871 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 872 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 873 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 874 | break; |
| 875 | case 5: |
| 876 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 877 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 878 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 879 | NUM_BANKS(ADDR_SURF_8_BANK)); |
| 880 | break; |
| 881 | case 6: |
| 882 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 883 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 884 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 885 | NUM_BANKS(ADDR_SURF_4_BANK)); |
| 886 | break; |
| 887 | case 8: |
| 888 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | |
| 889 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | |
| 890 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 891 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 892 | break; |
| 893 | case 9: |
| 894 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | |
| 895 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 896 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 897 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 898 | break; |
| 899 | case 10: |
| 900 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 901 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 902 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 903 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 904 | break; |
| 905 | case 11: |
| 906 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 907 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| 908 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 909 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 910 | break; |
| 911 | case 12: |
| 912 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 913 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 914 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 915 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 916 | break; |
| 917 | case 13: |
| 918 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 919 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 920 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 921 | NUM_BANKS(ADDR_SURF_8_BANK)); |
| 922 | break; |
| 923 | case 14: |
| 924 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 925 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 926 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 927 | NUM_BANKS(ADDR_SURF_4_BANK)); |
| 928 | break; |
| 929 | default: |
| 930 | gb_tile_moden = 0; |
| 931 | break; |
| 932 | } |
| 933 | WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); |
| 934 | } |
| 935 | } else if (num_pipe_configs == 2) { |
| 936 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { |
| 937 | switch (reg_offset) { |
| 938 | case 0: |
| 939 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 940 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 941 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 942 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)); |
| 943 | break; |
| 944 | case 1: |
| 945 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 946 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 947 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 948 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)); |
| 949 | break; |
| 950 | case 2: |
| 951 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 952 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 953 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 954 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); |
| 955 | break; |
| 956 | case 3: |
| 957 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 958 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 959 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 960 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B)); |
| 961 | break; |
| 962 | case 4: |
| 963 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 964 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 965 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 966 | TILE_SPLIT(split_equal_to_row_size)); |
| 967 | break; |
| 968 | case 5: |
| 969 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 970 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 971 | break; |
| 972 | case 6: |
| 973 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| 974 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 975 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 976 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); |
| 977 | break; |
| 978 | case 7: |
| 979 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| 980 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| 981 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 982 | TILE_SPLIT(split_equal_to_row_size)); |
| 983 | break; |
| 984 | case 8: |
| 985 | gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); |
| 986 | break; |
| 987 | case 9: |
| 988 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 989 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); |
| 990 | break; |
| 991 | case 10: |
| 992 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 993 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 994 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 995 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 996 | break; |
| 997 | case 11: |
| 998 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 999 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 1000 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1001 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1002 | break; |
| 1003 | case 12: |
| 1004 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| 1005 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 1006 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1007 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1008 | break; |
| 1009 | case 13: |
| 1010 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 1011 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); |
| 1012 | break; |
| 1013 | case 14: |
| 1014 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1015 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 1016 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1017 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1018 | break; |
| 1019 | case 16: |
| 1020 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 1021 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 1022 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1023 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1024 | break; |
| 1025 | case 17: |
| 1026 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| 1027 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 1028 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1029 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1030 | break; |
| 1031 | case 27: |
| 1032 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 1033 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); |
| 1034 | break; |
| 1035 | case 28: |
| 1036 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| 1037 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| 1038 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1039 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1040 | break; |
| 1041 | case 29: |
| 1042 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 1043 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| 1044 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1045 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1046 | break; |
| 1047 | case 30: |
| 1048 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| 1049 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| 1050 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1051 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1052 | break; |
| 1053 | default: |
| 1054 | gb_tile_moden = 0; |
| 1055 | break; |
| 1056 | } |
| 1057 | WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); |
| 1058 | } |
| 1059 | for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { |
| 1060 | switch (reg_offset) { |
| 1061 | case 0: |
| 1062 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | |
| 1063 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 1064 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1065 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1066 | break; |
| 1067 | case 1: |
| 1068 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | |
| 1069 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| 1070 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1071 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1072 | break; |
| 1073 | case 2: |
| 1074 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1075 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| 1076 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1077 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1078 | break; |
| 1079 | case 3: |
| 1080 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1081 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 1082 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1083 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1084 | break; |
| 1085 | case 4: |
| 1086 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1087 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 1088 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1089 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1090 | break; |
| 1091 | case 5: |
| 1092 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1093 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 1094 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1095 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1096 | break; |
| 1097 | case 6: |
| 1098 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1099 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 1100 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 1101 | NUM_BANKS(ADDR_SURF_8_BANK)); |
| 1102 | break; |
| 1103 | case 8: |
| 1104 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | |
| 1105 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | |
| 1106 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1107 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1108 | break; |
| 1109 | case 9: |
| 1110 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | |
| 1111 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 1112 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1113 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1114 | break; |
| 1115 | case 10: |
| 1116 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | |
| 1117 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 1118 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1119 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1120 | break; |
| 1121 | case 11: |
| 1122 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | |
| 1123 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| 1124 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1125 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1126 | break; |
| 1127 | case 12: |
| 1128 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1129 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| 1130 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1131 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1132 | break; |
| 1133 | case 13: |
| 1134 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1135 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 1136 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1137 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1138 | break; |
| 1139 | case 14: |
| 1140 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1141 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 1142 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 1143 | NUM_BANKS(ADDR_SURF_8_BANK)); |
| 1144 | break; |
| 1145 | default: |
| 1146 | gb_tile_moden = 0; |
| 1147 | break; |
| 1148 | } |
| 1149 | WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); |
| 1150 | } |
| 1151 | } else |
| 1152 | DRM_ERROR("unknown num pipe config: 0x%x\n", num_pipe_configs); |
| 1153 | } |
| 1154 | |
| 1155 | /** |
| 1156 | * cik_select_se_sh - select which SE, SH to address |
| 1157 | * |
| 1158 | * @rdev: radeon_device pointer |
| 1159 | * @se_num: shader engine to address |
| 1160 | * @sh_num: sh block to address |
| 1161 | * |
| 1162 | * Select which SE, SH combinations to address. Certain |
| 1163 | * registers are instanced per SE or SH. 0xffffffff means |
| 1164 | * broadcast to all SEs or SHs (CIK). |
| 1165 | */ |
| 1166 | static void cik_select_se_sh(struct radeon_device *rdev, |
| 1167 | u32 se_num, u32 sh_num) |
| 1168 | { |
| 1169 | u32 data = INSTANCE_BROADCAST_WRITES; |
| 1170 | |
| 1171 | if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) |
| 1172 | data = SH_BROADCAST_WRITES | SE_BROADCAST_WRITES; |
| 1173 | else if (se_num == 0xffffffff) |
| 1174 | data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num); |
| 1175 | else if (sh_num == 0xffffffff) |
| 1176 | data |= SH_BROADCAST_WRITES | SE_INDEX(se_num); |
| 1177 | else |
| 1178 | data |= SH_INDEX(sh_num) | SE_INDEX(se_num); |
| 1179 | WREG32(GRBM_GFX_INDEX, data); |
| 1180 | } |
| 1181 | |
| 1182 | /** |
| 1183 | * cik_create_bitmask - create a bitmask |
| 1184 | * |
| 1185 | * @bit_width: length of the mask |
| 1186 | * |
| 1187 | * create a variable length bit mask (CIK). |
| 1188 | * Returns the bitmask. |
| 1189 | */ |
| 1190 | static u32 cik_create_bitmask(u32 bit_width) |
| 1191 | { |
| 1192 | u32 i, mask = 0; |
| 1193 | |
| 1194 | for (i = 0; i < bit_width; i++) { |
| 1195 | mask <<= 1; |
| 1196 | mask |= 1; |
| 1197 | } |
| 1198 | return mask; |
| 1199 | } |
| 1200 | |
| 1201 | /** |
| 1202 | * cik_select_se_sh - select which SE, SH to address |
| 1203 | * |
| 1204 | * @rdev: radeon_device pointer |
| 1205 | * @max_rb_num: max RBs (render backends) for the asic |
| 1206 | * @se_num: number of SEs (shader engines) for the asic |
| 1207 | * @sh_per_se: number of SH blocks per SE for the asic |
| 1208 | * |
| 1209 | * Calculates the bitmask of disabled RBs (CIK). |
| 1210 | * Returns the disabled RB bitmask. |
| 1211 | */ |
| 1212 | static u32 cik_get_rb_disabled(struct radeon_device *rdev, |
| 1213 | u32 max_rb_num, u32 se_num, |
| 1214 | u32 sh_per_se) |
| 1215 | { |
| 1216 | u32 data, mask; |
| 1217 | |
| 1218 | data = RREG32(CC_RB_BACKEND_DISABLE); |
| 1219 | if (data & 1) |
| 1220 | data &= BACKEND_DISABLE_MASK; |
| 1221 | else |
| 1222 | data = 0; |
| 1223 | data |= RREG32(GC_USER_RB_BACKEND_DISABLE); |
| 1224 | |
| 1225 | data >>= BACKEND_DISABLE_SHIFT; |
| 1226 | |
| 1227 | mask = cik_create_bitmask(max_rb_num / se_num / sh_per_se); |
| 1228 | |
| 1229 | return data & mask; |
| 1230 | } |
| 1231 | |
| 1232 | /** |
| 1233 | * cik_setup_rb - setup the RBs on the asic |
| 1234 | * |
| 1235 | * @rdev: radeon_device pointer |
| 1236 | * @se_num: number of SEs (shader engines) for the asic |
| 1237 | * @sh_per_se: number of SH blocks per SE for the asic |
| 1238 | * @max_rb_num: max RBs (render backends) for the asic |
| 1239 | * |
| 1240 | * Configures per-SE/SH RB registers (CIK). |
| 1241 | */ |
| 1242 | static void cik_setup_rb(struct radeon_device *rdev, |
| 1243 | u32 se_num, u32 sh_per_se, |
| 1244 | u32 max_rb_num) |
| 1245 | { |
| 1246 | int i, j; |
| 1247 | u32 data, mask; |
| 1248 | u32 disabled_rbs = 0; |
| 1249 | u32 enabled_rbs = 0; |
| 1250 | |
| 1251 | for (i = 0; i < se_num; i++) { |
| 1252 | for (j = 0; j < sh_per_se; j++) { |
| 1253 | cik_select_se_sh(rdev, i, j); |
| 1254 | data = cik_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se); |
| 1255 | disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH); |
| 1256 | } |
| 1257 | } |
| 1258 | cik_select_se_sh(rdev, 0xffffffff, 0xffffffff); |
| 1259 | |
| 1260 | mask = 1; |
| 1261 | for (i = 0; i < max_rb_num; i++) { |
| 1262 | if (!(disabled_rbs & mask)) |
| 1263 | enabled_rbs |= mask; |
| 1264 | mask <<= 1; |
| 1265 | } |
| 1266 | |
| 1267 | for (i = 0; i < se_num; i++) { |
| 1268 | cik_select_se_sh(rdev, i, 0xffffffff); |
| 1269 | data = 0; |
| 1270 | for (j = 0; j < sh_per_se; j++) { |
| 1271 | switch (enabled_rbs & 3) { |
| 1272 | case 1: |
| 1273 | data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2); |
| 1274 | break; |
| 1275 | case 2: |
| 1276 | data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2); |
| 1277 | break; |
| 1278 | case 3: |
| 1279 | default: |
| 1280 | data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2); |
| 1281 | break; |
| 1282 | } |
| 1283 | enabled_rbs >>= 2; |
| 1284 | } |
| 1285 | WREG32(PA_SC_RASTER_CONFIG, data); |
| 1286 | } |
| 1287 | cik_select_se_sh(rdev, 0xffffffff, 0xffffffff); |
| 1288 | } |
| 1289 | |
| 1290 | /** |
| 1291 | * cik_gpu_init - setup the 3D engine |
| 1292 | * |
| 1293 | * @rdev: radeon_device pointer |
| 1294 | * |
| 1295 | * Configures the 3D engine and tiling configuration |
| 1296 | * registers so that the 3D engine is usable. |
| 1297 | */ |
| 1298 | static void cik_gpu_init(struct radeon_device *rdev) |
| 1299 | { |
| 1300 | u32 gb_addr_config = RREG32(GB_ADDR_CONFIG); |
| 1301 | u32 mc_shared_chmap, mc_arb_ramcfg; |
| 1302 | u32 hdp_host_path_cntl; |
| 1303 | u32 tmp; |
| 1304 | int i, j; |
| 1305 | |
| 1306 | switch (rdev->family) { |
| 1307 | case CHIP_BONAIRE: |
| 1308 | rdev->config.cik.max_shader_engines = 2; |
| 1309 | rdev->config.cik.max_tile_pipes = 4; |
| 1310 | rdev->config.cik.max_cu_per_sh = 7; |
| 1311 | rdev->config.cik.max_sh_per_se = 1; |
| 1312 | rdev->config.cik.max_backends_per_se = 2; |
| 1313 | rdev->config.cik.max_texture_channel_caches = 4; |
| 1314 | rdev->config.cik.max_gprs = 256; |
| 1315 | rdev->config.cik.max_gs_threads = 32; |
| 1316 | rdev->config.cik.max_hw_contexts = 8; |
| 1317 | |
| 1318 | rdev->config.cik.sc_prim_fifo_size_frontend = 0x20; |
| 1319 | rdev->config.cik.sc_prim_fifo_size_backend = 0x100; |
| 1320 | rdev->config.cik.sc_hiz_tile_fifo_size = 0x30; |
| 1321 | rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130; |
| 1322 | gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; |
| 1323 | break; |
| 1324 | case CHIP_KAVERI: |
| 1325 | /* TODO */ |
| 1326 | break; |
| 1327 | case CHIP_KABINI: |
| 1328 | default: |
| 1329 | rdev->config.cik.max_shader_engines = 1; |
| 1330 | rdev->config.cik.max_tile_pipes = 2; |
| 1331 | rdev->config.cik.max_cu_per_sh = 2; |
| 1332 | rdev->config.cik.max_sh_per_se = 1; |
| 1333 | rdev->config.cik.max_backends_per_se = 1; |
| 1334 | rdev->config.cik.max_texture_channel_caches = 2; |
| 1335 | rdev->config.cik.max_gprs = 256; |
| 1336 | rdev->config.cik.max_gs_threads = 16; |
| 1337 | rdev->config.cik.max_hw_contexts = 8; |
| 1338 | |
| 1339 | rdev->config.cik.sc_prim_fifo_size_frontend = 0x20; |
| 1340 | rdev->config.cik.sc_prim_fifo_size_backend = 0x100; |
| 1341 | rdev->config.cik.sc_hiz_tile_fifo_size = 0x30; |
| 1342 | rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130; |
| 1343 | gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; |
| 1344 | break; |
| 1345 | } |
| 1346 | |
| 1347 | /* Initialize HDP */ |
| 1348 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { |
| 1349 | WREG32((0x2c14 + j), 0x00000000); |
| 1350 | WREG32((0x2c18 + j), 0x00000000); |
| 1351 | WREG32((0x2c1c + j), 0x00000000); |
| 1352 | WREG32((0x2c20 + j), 0x00000000); |
| 1353 | WREG32((0x2c24 + j), 0x00000000); |
| 1354 | } |
| 1355 | |
| 1356 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
| 1357 | |
| 1358 | WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); |
| 1359 | |
| 1360 | mc_shared_chmap = RREG32(MC_SHARED_CHMAP); |
| 1361 | mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); |
| 1362 | |
| 1363 | rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes; |
| 1364 | rdev->config.cik.mem_max_burst_length_bytes = 256; |
| 1365 | tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; |
| 1366 | rdev->config.cik.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; |
| 1367 | if (rdev->config.cik.mem_row_size_in_kb > 4) |
| 1368 | rdev->config.cik.mem_row_size_in_kb = 4; |
| 1369 | /* XXX use MC settings? */ |
| 1370 | rdev->config.cik.shader_engine_tile_size = 32; |
| 1371 | rdev->config.cik.num_gpus = 1; |
| 1372 | rdev->config.cik.multi_gpu_tile_size = 64; |
| 1373 | |
| 1374 | /* fix up row size */ |
| 1375 | gb_addr_config &= ~ROW_SIZE_MASK; |
| 1376 | switch (rdev->config.cik.mem_row_size_in_kb) { |
| 1377 | case 1: |
| 1378 | default: |
| 1379 | gb_addr_config |= ROW_SIZE(0); |
| 1380 | break; |
| 1381 | case 2: |
| 1382 | gb_addr_config |= ROW_SIZE(1); |
| 1383 | break; |
| 1384 | case 4: |
| 1385 | gb_addr_config |= ROW_SIZE(2); |
| 1386 | break; |
| 1387 | } |
| 1388 | |
| 1389 | /* setup tiling info dword. gb_addr_config is not adequate since it does |
| 1390 | * not have bank info, so create a custom tiling dword. |
| 1391 | * bits 3:0 num_pipes |
| 1392 | * bits 7:4 num_banks |
| 1393 | * bits 11:8 group_size |
| 1394 | * bits 15:12 row_size |
| 1395 | */ |
| 1396 | rdev->config.cik.tile_config = 0; |
| 1397 | switch (rdev->config.cik.num_tile_pipes) { |
| 1398 | case 1: |
| 1399 | rdev->config.cik.tile_config |= (0 << 0); |
| 1400 | break; |
| 1401 | case 2: |
| 1402 | rdev->config.cik.tile_config |= (1 << 0); |
| 1403 | break; |
| 1404 | case 4: |
| 1405 | rdev->config.cik.tile_config |= (2 << 0); |
| 1406 | break; |
| 1407 | case 8: |
| 1408 | default: |
| 1409 | /* XXX what about 12? */ |
| 1410 | rdev->config.cik.tile_config |= (3 << 0); |
| 1411 | break; |
| 1412 | } |
| 1413 | if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) |
| 1414 | rdev->config.cik.tile_config |= 1 << 4; |
| 1415 | else |
| 1416 | rdev->config.cik.tile_config |= 0 << 4; |
| 1417 | rdev->config.cik.tile_config |= |
| 1418 | ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; |
| 1419 | rdev->config.cik.tile_config |= |
| 1420 | ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; |
| 1421 | |
| 1422 | WREG32(GB_ADDR_CONFIG, gb_addr_config); |
| 1423 | WREG32(HDP_ADDR_CONFIG, gb_addr_config); |
| 1424 | WREG32(DMIF_ADDR_CALC, gb_addr_config); |
| 1425 | |
| 1426 | cik_tiling_mode_table_init(rdev); |
| 1427 | |
| 1428 | cik_setup_rb(rdev, rdev->config.cik.max_shader_engines, |
| 1429 | rdev->config.cik.max_sh_per_se, |
| 1430 | rdev->config.cik.max_backends_per_se); |
| 1431 | |
| 1432 | /* set HW defaults for 3D engine */ |
| 1433 | WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); |
| 1434 | |
| 1435 | WREG32(SX_DEBUG_1, 0x20); |
| 1436 | |
| 1437 | WREG32(TA_CNTL_AUX, 0x00010000); |
| 1438 | |
| 1439 | tmp = RREG32(SPI_CONFIG_CNTL); |
| 1440 | tmp |= 0x03000000; |
| 1441 | WREG32(SPI_CONFIG_CNTL, tmp); |
| 1442 | |
| 1443 | WREG32(SQ_CONFIG, 1); |
| 1444 | |
| 1445 | WREG32(DB_DEBUG, 0); |
| 1446 | |
| 1447 | tmp = RREG32(DB_DEBUG2) & ~0xf00fffff; |
| 1448 | tmp |= 0x00000400; |
| 1449 | WREG32(DB_DEBUG2, tmp); |
| 1450 | |
| 1451 | tmp = RREG32(DB_DEBUG3) & ~0x0002021c; |
| 1452 | tmp |= 0x00020200; |
| 1453 | WREG32(DB_DEBUG3, tmp); |
| 1454 | |
| 1455 | tmp = RREG32(CB_HW_CONTROL) & ~0x00010000; |
| 1456 | tmp |= 0x00018208; |
| 1457 | WREG32(CB_HW_CONTROL, tmp); |
| 1458 | |
| 1459 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); |
| 1460 | |
| 1461 | WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) | |
| 1462 | SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_backend) | |
| 1463 | SC_HIZ_TILE_FIFO_SIZE(rdev->config.cik.sc_hiz_tile_fifo_size) | |
| 1464 | SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cik.sc_earlyz_tile_fifo_size))); |
| 1465 | |
| 1466 | WREG32(VGT_NUM_INSTANCES, 1); |
| 1467 | |
| 1468 | WREG32(CP_PERFMON_CNTL, 0); |
| 1469 | |
| 1470 | WREG32(SQ_CONFIG, 0); |
| 1471 | |
| 1472 | WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | |
| 1473 | FORCE_EOV_MAX_REZ_CNT(255))); |
| 1474 | |
| 1475 | WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | |
| 1476 | AUTO_INVLD_EN(ES_AND_GS_AUTO)); |
| 1477 | |
| 1478 | WREG32(VGT_GS_VERTEX_REUSE, 16); |
| 1479 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); |
| 1480 | |
| 1481 | tmp = RREG32(HDP_MISC_CNTL); |
| 1482 | tmp |= HDP_FLUSH_INVALIDATE_CACHE; |
| 1483 | WREG32(HDP_MISC_CNTL, tmp); |
| 1484 | |
| 1485 | hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); |
| 1486 | WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); |
| 1487 | |
| 1488 | WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); |
| 1489 | WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER); |
| 1490 | |
| 1491 | udelay(50); |
| 1492 | } |
| 1493 | |
Alex Deucher | 6f2043c | 2013-04-09 12:43:41 -0400 | [diff] [blame] | 1494 | /** |
| 1495 | * cik_gpu_is_lockup - check if the 3D engine is locked up |
| 1496 | * |
| 1497 | * @rdev: radeon_device pointer |
| 1498 | * @ring: radeon_ring structure holding ring information |
| 1499 | * |
| 1500 | * Check if the 3D engine is locked up (CIK). |
| 1501 | * Returns true if the engine is locked, false if not. |
| 1502 | */ |
| 1503 | bool cik_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
| 1504 | { |
| 1505 | u32 srbm_status, srbm_status2; |
| 1506 | u32 grbm_status, grbm_status2; |
| 1507 | u32 grbm_status_se0, grbm_status_se1, grbm_status_se2, grbm_status_se3; |
| 1508 | |
| 1509 | srbm_status = RREG32(SRBM_STATUS); |
| 1510 | srbm_status2 = RREG32(SRBM_STATUS2); |
| 1511 | grbm_status = RREG32(GRBM_STATUS); |
| 1512 | grbm_status2 = RREG32(GRBM_STATUS2); |
| 1513 | grbm_status_se0 = RREG32(GRBM_STATUS_SE0); |
| 1514 | grbm_status_se1 = RREG32(GRBM_STATUS_SE1); |
| 1515 | grbm_status_se2 = RREG32(GRBM_STATUS_SE2); |
| 1516 | grbm_status_se3 = RREG32(GRBM_STATUS_SE3); |
| 1517 | if (!(grbm_status & GUI_ACTIVE)) { |
| 1518 | radeon_ring_lockup_update(ring); |
| 1519 | return false; |
| 1520 | } |
| 1521 | /* force CP activities */ |
| 1522 | radeon_ring_force_activity(rdev, ring); |
| 1523 | return radeon_ring_test_lockup(rdev, ring); |
| 1524 | } |
| 1525 | |
| 1526 | /** |
| 1527 | * cik_gfx_gpu_soft_reset - soft reset the 3D engine and CPG |
| 1528 | * |
| 1529 | * @rdev: radeon_device pointer |
| 1530 | * |
| 1531 | * Soft reset the GFX engine and CPG blocks (CIK). |
| 1532 | * XXX: deal with reseting RLC and CPF |
| 1533 | * Returns 0 for success. |
| 1534 | */ |
| 1535 | static int cik_gfx_gpu_soft_reset(struct radeon_device *rdev) |
| 1536 | { |
| 1537 | struct evergreen_mc_save save; |
| 1538 | u32 grbm_reset = 0; |
| 1539 | |
| 1540 | if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) |
| 1541 | return 0; |
| 1542 | |
| 1543 | dev_info(rdev->dev, "GPU GFX softreset \n"); |
| 1544 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", |
| 1545 | RREG32(GRBM_STATUS)); |
| 1546 | dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n", |
| 1547 | RREG32(GRBM_STATUS2)); |
| 1548 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", |
| 1549 | RREG32(GRBM_STATUS_SE0)); |
| 1550 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", |
| 1551 | RREG32(GRBM_STATUS_SE1)); |
| 1552 | dev_info(rdev->dev, " GRBM_STATUS_SE2=0x%08X\n", |
| 1553 | RREG32(GRBM_STATUS_SE2)); |
| 1554 | dev_info(rdev->dev, " GRBM_STATUS_SE3=0x%08X\n", |
| 1555 | RREG32(GRBM_STATUS_SE3)); |
| 1556 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", |
| 1557 | RREG32(SRBM_STATUS)); |
| 1558 | dev_info(rdev->dev, " SRBM_STATUS2=0x%08X\n", |
| 1559 | RREG32(SRBM_STATUS2)); |
| 1560 | evergreen_mc_stop(rdev, &save); |
| 1561 | if (radeon_mc_wait_for_idle(rdev)) { |
| 1562 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
| 1563 | } |
| 1564 | /* Disable CP parsing/prefetching */ |
| 1565 | WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); |
| 1566 | |
| 1567 | /* reset all the gfx block and all CPG blocks */ |
| 1568 | grbm_reset = SOFT_RESET_CPG | SOFT_RESET_GFX; |
| 1569 | |
| 1570 | dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset); |
| 1571 | WREG32(GRBM_SOFT_RESET, grbm_reset); |
| 1572 | (void)RREG32(GRBM_SOFT_RESET); |
| 1573 | udelay(50); |
| 1574 | WREG32(GRBM_SOFT_RESET, 0); |
| 1575 | (void)RREG32(GRBM_SOFT_RESET); |
| 1576 | /* Wait a little for things to settle down */ |
| 1577 | udelay(50); |
| 1578 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", |
| 1579 | RREG32(GRBM_STATUS)); |
| 1580 | dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n", |
| 1581 | RREG32(GRBM_STATUS2)); |
| 1582 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", |
| 1583 | RREG32(GRBM_STATUS_SE0)); |
| 1584 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", |
| 1585 | RREG32(GRBM_STATUS_SE1)); |
| 1586 | dev_info(rdev->dev, " GRBM_STATUS_SE2=0x%08X\n", |
| 1587 | RREG32(GRBM_STATUS_SE2)); |
| 1588 | dev_info(rdev->dev, " GRBM_STATUS_SE3=0x%08X\n", |
| 1589 | RREG32(GRBM_STATUS_SE3)); |
| 1590 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", |
| 1591 | RREG32(SRBM_STATUS)); |
| 1592 | dev_info(rdev->dev, " SRBM_STATUS2=0x%08X\n", |
| 1593 | RREG32(SRBM_STATUS2)); |
| 1594 | evergreen_mc_resume(rdev, &save); |
| 1595 | return 0; |
| 1596 | } |
| 1597 | |
| 1598 | /** |
| 1599 | * cik_compute_gpu_soft_reset - soft reset CPC |
| 1600 | * |
| 1601 | * @rdev: radeon_device pointer |
| 1602 | * |
| 1603 | * Soft reset the CPC blocks (CIK). |
| 1604 | * XXX: deal with reseting RLC and CPF |
| 1605 | * Returns 0 for success. |
| 1606 | */ |
| 1607 | static int cik_compute_gpu_soft_reset(struct radeon_device *rdev) |
| 1608 | { |
| 1609 | struct evergreen_mc_save save; |
| 1610 | u32 grbm_reset = 0; |
| 1611 | |
| 1612 | dev_info(rdev->dev, "GPU compute softreset \n"); |
| 1613 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", |
| 1614 | RREG32(GRBM_STATUS)); |
| 1615 | dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n", |
| 1616 | RREG32(GRBM_STATUS2)); |
| 1617 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", |
| 1618 | RREG32(GRBM_STATUS_SE0)); |
| 1619 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", |
| 1620 | RREG32(GRBM_STATUS_SE1)); |
| 1621 | dev_info(rdev->dev, " GRBM_STATUS_SE2=0x%08X\n", |
| 1622 | RREG32(GRBM_STATUS_SE2)); |
| 1623 | dev_info(rdev->dev, " GRBM_STATUS_SE3=0x%08X\n", |
| 1624 | RREG32(GRBM_STATUS_SE3)); |
| 1625 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", |
| 1626 | RREG32(SRBM_STATUS)); |
| 1627 | dev_info(rdev->dev, " SRBM_STATUS2=0x%08X\n", |
| 1628 | RREG32(SRBM_STATUS2)); |
| 1629 | evergreen_mc_stop(rdev, &save); |
| 1630 | if (radeon_mc_wait_for_idle(rdev)) { |
| 1631 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
| 1632 | } |
| 1633 | /* Disable CP parsing/prefetching */ |
| 1634 | WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT); |
| 1635 | |
| 1636 | /* reset all the CPC blocks */ |
| 1637 | grbm_reset = SOFT_RESET_CPG; |
| 1638 | |
| 1639 | dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset); |
| 1640 | WREG32(GRBM_SOFT_RESET, grbm_reset); |
| 1641 | (void)RREG32(GRBM_SOFT_RESET); |
| 1642 | udelay(50); |
| 1643 | WREG32(GRBM_SOFT_RESET, 0); |
| 1644 | (void)RREG32(GRBM_SOFT_RESET); |
| 1645 | /* Wait a little for things to settle down */ |
| 1646 | udelay(50); |
| 1647 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", |
| 1648 | RREG32(GRBM_STATUS)); |
| 1649 | dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n", |
| 1650 | RREG32(GRBM_STATUS2)); |
| 1651 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", |
| 1652 | RREG32(GRBM_STATUS_SE0)); |
| 1653 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", |
| 1654 | RREG32(GRBM_STATUS_SE1)); |
| 1655 | dev_info(rdev->dev, " GRBM_STATUS_SE2=0x%08X\n", |
| 1656 | RREG32(GRBM_STATUS_SE2)); |
| 1657 | dev_info(rdev->dev, " GRBM_STATUS_SE3=0x%08X\n", |
| 1658 | RREG32(GRBM_STATUS_SE3)); |
| 1659 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", |
| 1660 | RREG32(SRBM_STATUS)); |
| 1661 | dev_info(rdev->dev, " SRBM_STATUS2=0x%08X\n", |
| 1662 | RREG32(SRBM_STATUS2)); |
| 1663 | evergreen_mc_resume(rdev, &save); |
| 1664 | return 0; |
| 1665 | } |
| 1666 | |
| 1667 | /** |
| 1668 | * cik_asic_reset - soft reset compute and gfx |
| 1669 | * |
| 1670 | * @rdev: radeon_device pointer |
| 1671 | * |
| 1672 | * Soft reset the CPC blocks (CIK). |
| 1673 | * XXX: make this more fine grained and only reset |
| 1674 | * what is necessary. |
| 1675 | * Returns 0 for success. |
| 1676 | */ |
| 1677 | int cik_asic_reset(struct radeon_device *rdev) |
| 1678 | { |
| 1679 | int r; |
| 1680 | |
| 1681 | r = cik_compute_gpu_soft_reset(rdev); |
| 1682 | if (r) |
| 1683 | dev_info(rdev->dev, "Compute reset failed!\n"); |
| 1684 | |
| 1685 | return cik_gfx_gpu_soft_reset(rdev); |
| 1686 | } |
Alex Deucher | 1c49165 | 2013-04-09 12:45:26 -0400 | [diff] [blame] | 1687 | |
| 1688 | /* MC */ |
| 1689 | /** |
| 1690 | * cik_mc_program - program the GPU memory controller |
| 1691 | * |
| 1692 | * @rdev: radeon_device pointer |
| 1693 | * |
| 1694 | * Set the location of vram, gart, and AGP in the GPU's |
| 1695 | * physical address space (CIK). |
| 1696 | */ |
| 1697 | static void cik_mc_program(struct radeon_device *rdev) |
| 1698 | { |
| 1699 | struct evergreen_mc_save save; |
| 1700 | u32 tmp; |
| 1701 | int i, j; |
| 1702 | |
| 1703 | /* Initialize HDP */ |
| 1704 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { |
| 1705 | WREG32((0x2c14 + j), 0x00000000); |
| 1706 | WREG32((0x2c18 + j), 0x00000000); |
| 1707 | WREG32((0x2c1c + j), 0x00000000); |
| 1708 | WREG32((0x2c20 + j), 0x00000000); |
| 1709 | WREG32((0x2c24 + j), 0x00000000); |
| 1710 | } |
| 1711 | WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); |
| 1712 | |
| 1713 | evergreen_mc_stop(rdev, &save); |
| 1714 | if (radeon_mc_wait_for_idle(rdev)) { |
| 1715 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
| 1716 | } |
| 1717 | /* Lockout access through VGA aperture*/ |
| 1718 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); |
| 1719 | /* Update configuration */ |
| 1720 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
| 1721 | rdev->mc.vram_start >> 12); |
| 1722 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
| 1723 | rdev->mc.vram_end >> 12); |
| 1724 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, |
| 1725 | rdev->vram_scratch.gpu_addr >> 12); |
| 1726 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
| 1727 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); |
| 1728 | WREG32(MC_VM_FB_LOCATION, tmp); |
| 1729 | /* XXX double check these! */ |
| 1730 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); |
| 1731 | WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); |
| 1732 | WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); |
| 1733 | WREG32(MC_VM_AGP_BASE, 0); |
| 1734 | WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); |
| 1735 | WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); |
| 1736 | if (radeon_mc_wait_for_idle(rdev)) { |
| 1737 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
| 1738 | } |
| 1739 | evergreen_mc_resume(rdev, &save); |
| 1740 | /* we need to own VRAM, so turn off the VGA renderer here |
| 1741 | * to stop it overwriting our objects */ |
| 1742 | rv515_vga_render_disable(rdev); |
| 1743 | } |
| 1744 | |
| 1745 | /** |
| 1746 | * cik_mc_init - initialize the memory controller driver params |
| 1747 | * |
| 1748 | * @rdev: radeon_device pointer |
| 1749 | * |
| 1750 | * Look up the amount of vram, vram width, and decide how to place |
| 1751 | * vram and gart within the GPU's physical address space (CIK). |
| 1752 | * Returns 0 for success. |
| 1753 | */ |
| 1754 | static int cik_mc_init(struct radeon_device *rdev) |
| 1755 | { |
| 1756 | u32 tmp; |
| 1757 | int chansize, numchan; |
| 1758 | |
| 1759 | /* Get VRAM informations */ |
| 1760 | rdev->mc.vram_is_ddr = true; |
| 1761 | tmp = RREG32(MC_ARB_RAMCFG); |
| 1762 | if (tmp & CHANSIZE_MASK) { |
| 1763 | chansize = 64; |
| 1764 | } else { |
| 1765 | chansize = 32; |
| 1766 | } |
| 1767 | tmp = RREG32(MC_SHARED_CHMAP); |
| 1768 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { |
| 1769 | case 0: |
| 1770 | default: |
| 1771 | numchan = 1; |
| 1772 | break; |
| 1773 | case 1: |
| 1774 | numchan = 2; |
| 1775 | break; |
| 1776 | case 2: |
| 1777 | numchan = 4; |
| 1778 | break; |
| 1779 | case 3: |
| 1780 | numchan = 8; |
| 1781 | break; |
| 1782 | case 4: |
| 1783 | numchan = 3; |
| 1784 | break; |
| 1785 | case 5: |
| 1786 | numchan = 6; |
| 1787 | break; |
| 1788 | case 6: |
| 1789 | numchan = 10; |
| 1790 | break; |
| 1791 | case 7: |
| 1792 | numchan = 12; |
| 1793 | break; |
| 1794 | case 8: |
| 1795 | numchan = 16; |
| 1796 | break; |
| 1797 | } |
| 1798 | rdev->mc.vram_width = numchan * chansize; |
| 1799 | /* Could aper size report 0 ? */ |
| 1800 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
| 1801 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
| 1802 | /* size in MB on si */ |
| 1803 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; |
| 1804 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; |
| 1805 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
| 1806 | si_vram_gtt_location(rdev, &rdev->mc); |
| 1807 | radeon_update_bandwidth_info(rdev); |
| 1808 | |
| 1809 | return 0; |
| 1810 | } |
| 1811 | |
| 1812 | /* |
| 1813 | * GART |
| 1814 | * VMID 0 is the physical GPU addresses as used by the kernel. |
| 1815 | * VMIDs 1-15 are used for userspace clients and are handled |
| 1816 | * by the radeon vm/hsa code. |
| 1817 | */ |
| 1818 | /** |
| 1819 | * cik_pcie_gart_tlb_flush - gart tlb flush callback |
| 1820 | * |
| 1821 | * @rdev: radeon_device pointer |
| 1822 | * |
| 1823 | * Flush the TLB for the VMID 0 page table (CIK). |
| 1824 | */ |
| 1825 | void cik_pcie_gart_tlb_flush(struct radeon_device *rdev) |
| 1826 | { |
| 1827 | /* flush hdp cache */ |
| 1828 | WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0); |
| 1829 | |
| 1830 | /* bits 0-15 are the VM contexts0-15 */ |
| 1831 | WREG32(VM_INVALIDATE_REQUEST, 0x1); |
| 1832 | } |
| 1833 | |
| 1834 | /** |
| 1835 | * cik_pcie_gart_enable - gart enable |
| 1836 | * |
| 1837 | * @rdev: radeon_device pointer |
| 1838 | * |
| 1839 | * This sets up the TLBs, programs the page tables for VMID0, |
| 1840 | * sets up the hw for VMIDs 1-15 which are allocated on |
| 1841 | * demand, and sets up the global locations for the LDS, GDS, |
| 1842 | * and GPUVM for FSA64 clients (CIK). |
| 1843 | * Returns 0 for success, errors for failure. |
| 1844 | */ |
| 1845 | static int cik_pcie_gart_enable(struct radeon_device *rdev) |
| 1846 | { |
| 1847 | int r, i; |
| 1848 | |
| 1849 | if (rdev->gart.robj == NULL) { |
| 1850 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
| 1851 | return -EINVAL; |
| 1852 | } |
| 1853 | r = radeon_gart_table_vram_pin(rdev); |
| 1854 | if (r) |
| 1855 | return r; |
| 1856 | radeon_gart_restore(rdev); |
| 1857 | /* Setup TLB control */ |
| 1858 | WREG32(MC_VM_MX_L1_TLB_CNTL, |
| 1859 | (0xA << 7) | |
| 1860 | ENABLE_L1_TLB | |
| 1861 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
| 1862 | ENABLE_ADVANCED_DRIVER_MODEL | |
| 1863 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); |
| 1864 | /* Setup L2 cache */ |
| 1865 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | |
| 1866 | ENABLE_L2_FRAGMENT_PROCESSING | |
| 1867 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
| 1868 | ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | |
| 1869 | EFFECTIVE_L2_QUEUE_SIZE(7) | |
| 1870 | CONTEXT1_IDENTITY_ACCESS_MODE(1)); |
| 1871 | WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); |
| 1872 | WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | |
| 1873 | L2_CACHE_BIGK_FRAGMENT_SIZE(6)); |
| 1874 | /* setup context0 */ |
| 1875 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); |
| 1876 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
| 1877 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
| 1878 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, |
| 1879 | (u32)(rdev->dummy_page.addr >> 12)); |
| 1880 | WREG32(VM_CONTEXT0_CNTL2, 0); |
| 1881 | WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | |
| 1882 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT)); |
| 1883 | |
| 1884 | WREG32(0x15D4, 0); |
| 1885 | WREG32(0x15D8, 0); |
| 1886 | WREG32(0x15DC, 0); |
| 1887 | |
| 1888 | /* empty context1-15 */ |
| 1889 | /* FIXME start with 4G, once using 2 level pt switch to full |
| 1890 | * vm size space |
| 1891 | */ |
| 1892 | /* set vm size, must be a multiple of 4 */ |
| 1893 | WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); |
| 1894 | WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn); |
| 1895 | for (i = 1; i < 16; i++) { |
| 1896 | if (i < 8) |
| 1897 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), |
| 1898 | rdev->gart.table_addr >> 12); |
| 1899 | else |
| 1900 | WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), |
| 1901 | rdev->gart.table_addr >> 12); |
| 1902 | } |
| 1903 | |
| 1904 | /* enable context1-15 */ |
| 1905 | WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, |
| 1906 | (u32)(rdev->dummy_page.addr >> 12)); |
Alex Deucher | a00024b | 2012-09-18 16:06:01 -0400 | [diff] [blame] | 1907 | WREG32(VM_CONTEXT1_CNTL2, 4); |
Alex Deucher | 1c49165 | 2013-04-09 12:45:26 -0400 | [diff] [blame] | 1908 | WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | |
Alex Deucher | a00024b | 2012-09-18 16:06:01 -0400 | [diff] [blame] | 1909 | RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | |
| 1910 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | |
| 1911 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | |
| 1912 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT | |
| 1913 | PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT | |
| 1914 | PDE0_PROTECTION_FAULT_ENABLE_DEFAULT | |
| 1915 | VALID_PROTECTION_FAULT_ENABLE_INTERRUPT | |
| 1916 | VALID_PROTECTION_FAULT_ENABLE_DEFAULT | |
| 1917 | READ_PROTECTION_FAULT_ENABLE_INTERRUPT | |
| 1918 | READ_PROTECTION_FAULT_ENABLE_DEFAULT | |
| 1919 | WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT | |
| 1920 | WRITE_PROTECTION_FAULT_ENABLE_DEFAULT); |
Alex Deucher | 1c49165 | 2013-04-09 12:45:26 -0400 | [diff] [blame] | 1921 | |
| 1922 | /* TC cache setup ??? */ |
| 1923 | WREG32(TC_CFG_L1_LOAD_POLICY0, 0); |
| 1924 | WREG32(TC_CFG_L1_LOAD_POLICY1, 0); |
| 1925 | WREG32(TC_CFG_L1_STORE_POLICY, 0); |
| 1926 | |
| 1927 | WREG32(TC_CFG_L2_LOAD_POLICY0, 0); |
| 1928 | WREG32(TC_CFG_L2_LOAD_POLICY1, 0); |
| 1929 | WREG32(TC_CFG_L2_STORE_POLICY0, 0); |
| 1930 | WREG32(TC_CFG_L2_STORE_POLICY1, 0); |
| 1931 | WREG32(TC_CFG_L2_ATOMIC_POLICY, 0); |
| 1932 | |
| 1933 | WREG32(TC_CFG_L1_VOLATILE, 0); |
| 1934 | WREG32(TC_CFG_L2_VOLATILE, 0); |
| 1935 | |
| 1936 | if (rdev->family == CHIP_KAVERI) { |
| 1937 | u32 tmp = RREG32(CHUB_CONTROL); |
| 1938 | tmp &= ~BYPASS_VM; |
| 1939 | WREG32(CHUB_CONTROL, tmp); |
| 1940 | } |
| 1941 | |
| 1942 | /* XXX SH_MEM regs */ |
| 1943 | /* where to put LDS, scratch, GPUVM in FSA64 space */ |
| 1944 | for (i = 0; i < 16; i++) { |
| 1945 | WREG32(SRBM_GFX_CNTL, VMID(i)); |
| 1946 | WREG32(SH_MEM_CONFIG, 0); |
| 1947 | WREG32(SH_MEM_APE1_BASE, 1); |
| 1948 | WREG32(SH_MEM_APE1_LIMIT, 0); |
| 1949 | WREG32(SH_MEM_BASES, 0); |
| 1950 | } |
| 1951 | WREG32(SRBM_GFX_CNTL, 0); |
| 1952 | |
| 1953 | cik_pcie_gart_tlb_flush(rdev); |
| 1954 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
| 1955 | (unsigned)(rdev->mc.gtt_size >> 20), |
| 1956 | (unsigned long long)rdev->gart.table_addr); |
| 1957 | rdev->gart.ready = true; |
| 1958 | return 0; |
| 1959 | } |
| 1960 | |
| 1961 | /** |
| 1962 | * cik_pcie_gart_disable - gart disable |
| 1963 | * |
| 1964 | * @rdev: radeon_device pointer |
| 1965 | * |
| 1966 | * This disables all VM page table (CIK). |
| 1967 | */ |
| 1968 | static void cik_pcie_gart_disable(struct radeon_device *rdev) |
| 1969 | { |
| 1970 | /* Disable all tables */ |
| 1971 | WREG32(VM_CONTEXT0_CNTL, 0); |
| 1972 | WREG32(VM_CONTEXT1_CNTL, 0); |
| 1973 | /* Setup TLB control */ |
| 1974 | WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
| 1975 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); |
| 1976 | /* Setup L2 cache */ |
| 1977 | WREG32(VM_L2_CNTL, |
| 1978 | ENABLE_L2_FRAGMENT_PROCESSING | |
| 1979 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
| 1980 | ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | |
| 1981 | EFFECTIVE_L2_QUEUE_SIZE(7) | |
| 1982 | CONTEXT1_IDENTITY_ACCESS_MODE(1)); |
| 1983 | WREG32(VM_L2_CNTL2, 0); |
| 1984 | WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | |
| 1985 | L2_CACHE_BIGK_FRAGMENT_SIZE(6)); |
| 1986 | radeon_gart_table_vram_unpin(rdev); |
| 1987 | } |
| 1988 | |
| 1989 | /** |
| 1990 | * cik_pcie_gart_fini - vm fini callback |
| 1991 | * |
| 1992 | * @rdev: radeon_device pointer |
| 1993 | * |
| 1994 | * Tears down the driver GART/VM setup (CIK). |
| 1995 | */ |
| 1996 | static void cik_pcie_gart_fini(struct radeon_device *rdev) |
| 1997 | { |
| 1998 | cik_pcie_gart_disable(rdev); |
| 1999 | radeon_gart_table_vram_free(rdev); |
| 2000 | radeon_gart_fini(rdev); |
| 2001 | } |
| 2002 | |
| 2003 | /* vm parser */ |
| 2004 | /** |
| 2005 | * cik_ib_parse - vm ib_parse callback |
| 2006 | * |
| 2007 | * @rdev: radeon_device pointer |
| 2008 | * @ib: indirect buffer pointer |
| 2009 | * |
| 2010 | * CIK uses hw IB checking so this is a nop (CIK). |
| 2011 | */ |
| 2012 | int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib) |
| 2013 | { |
| 2014 | return 0; |
| 2015 | } |
| 2016 | |
| 2017 | /* |
| 2018 | * vm |
| 2019 | * VMID 0 is the physical GPU addresses as used by the kernel. |
| 2020 | * VMIDs 1-15 are used for userspace clients and are handled |
| 2021 | * by the radeon vm/hsa code. |
| 2022 | */ |
| 2023 | /** |
| 2024 | * cik_vm_init - cik vm init callback |
| 2025 | * |
| 2026 | * @rdev: radeon_device pointer |
| 2027 | * |
| 2028 | * Inits cik specific vm parameters (number of VMs, base of vram for |
| 2029 | * VMIDs 1-15) (CIK). |
| 2030 | * Returns 0 for success. |
| 2031 | */ |
| 2032 | int cik_vm_init(struct radeon_device *rdev) |
| 2033 | { |
| 2034 | /* number of VMs */ |
| 2035 | rdev->vm_manager.nvm = 16; |
| 2036 | /* base offset of vram pages */ |
| 2037 | if (rdev->flags & RADEON_IS_IGP) { |
| 2038 | u64 tmp = RREG32(MC_VM_FB_OFFSET); |
| 2039 | tmp <<= 22; |
| 2040 | rdev->vm_manager.vram_base_offset = tmp; |
| 2041 | } else |
| 2042 | rdev->vm_manager.vram_base_offset = 0; |
| 2043 | |
| 2044 | return 0; |
| 2045 | } |
| 2046 | |
| 2047 | /** |
| 2048 | * cik_vm_fini - cik vm fini callback |
| 2049 | * |
| 2050 | * @rdev: radeon_device pointer |
| 2051 | * |
| 2052 | * Tear down any asic specific VM setup (CIK). |
| 2053 | */ |
| 2054 | void cik_vm_fini(struct radeon_device *rdev) |
| 2055 | { |
| 2056 | } |
| 2057 | |