Mythri P K | 94c5298 | 2011-09-08 19:06:21 +0530 | [diff] [blame] | 1 | /* |
| 2 | * ti_hdmi.h |
| 3 | * |
| 4 | * HDMI driver definition for TI OMAP4, DM81xx, DM38xx Processor. |
| 5 | * |
| 6 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License version 2 as published by |
| 10 | * the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 15 | * more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along with |
| 18 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #ifndef _TI_HDMI_H |
| 22 | #define _TI_HDMI_H |
| 23 | |
Archit Taneja | bdb8bfc | 2013-09-12 18:07:49 +0530 | [diff] [blame^] | 24 | #include <linux/delay.h> |
| 25 | #include <linux/io.h> |
Archit Taneja | f382d9e | 2013-08-06 14:56:55 +0530 | [diff] [blame] | 26 | #include <linux/platform_device.h> |
Archit Taneja | bdb8bfc | 2013-09-12 18:07:49 +0530 | [diff] [blame^] | 27 | #include <video/omapdss.h> |
| 28 | |
| 29 | #include "dss.h" |
| 30 | |
| 31 | /* HDMI Wrapper */ |
| 32 | |
| 33 | #define HDMI_WP_REVISION 0x0 |
| 34 | #define HDMI_WP_SYSCONFIG 0x10 |
| 35 | #define HDMI_WP_IRQSTATUS_RAW 0x24 |
| 36 | #define HDMI_WP_IRQSTATUS 0x28 |
| 37 | #define HDMI_WP_IRQENABLE_SET 0x2C |
| 38 | #define HDMI_WP_IRQENABLE_CLR 0x30 |
| 39 | #define HDMI_WP_IRQWAKEEN 0x34 |
| 40 | #define HDMI_WP_PWR_CTRL 0x40 |
| 41 | #define HDMI_WP_DEBOUNCE 0x44 |
| 42 | #define HDMI_WP_VIDEO_CFG 0x50 |
| 43 | #define HDMI_WP_VIDEO_SIZE 0x60 |
| 44 | #define HDMI_WP_VIDEO_TIMING_H 0x68 |
| 45 | #define HDMI_WP_VIDEO_TIMING_V 0x6C |
| 46 | #define HDMI_WP_WP_CLK 0x70 |
| 47 | #define HDMI_WP_AUDIO_CFG 0x80 |
| 48 | #define HDMI_WP_AUDIO_CFG2 0x84 |
| 49 | #define HDMI_WP_AUDIO_CTRL 0x88 |
| 50 | #define HDMI_WP_AUDIO_DATA 0x8C |
| 51 | |
| 52 | /* HDMI PLL */ |
| 53 | |
| 54 | #define PLLCTRL_PLL_CONTROL 0x0 |
| 55 | #define PLLCTRL_PLL_STATUS 0x4 |
| 56 | #define PLLCTRL_PLL_GO 0x8 |
| 57 | #define PLLCTRL_CFG1 0xC |
| 58 | #define PLLCTRL_CFG2 0x10 |
| 59 | #define PLLCTRL_CFG3 0x14 |
| 60 | #define PLLCTRL_SSC_CFG1 0x18 |
| 61 | #define PLLCTRL_SSC_CFG2 0x1C |
| 62 | #define PLLCTRL_CFG4 0x20 |
| 63 | |
| 64 | /* HDMI PHY */ |
| 65 | |
| 66 | #define HDMI_TXPHY_TX_CTRL 0x0 |
| 67 | #define HDMI_TXPHY_DIGITAL_CTRL 0x4 |
| 68 | #define HDMI_TXPHY_POWER_CTRL 0x8 |
| 69 | #define HDMI_TXPHY_PAD_CFG_CTRL 0xC |
Archit Taneja | f382d9e | 2013-08-06 14:56:55 +0530 | [diff] [blame] | 70 | |
Mythri P K | 94c5298 | 2011-09-08 19:06:21 +0530 | [diff] [blame] | 71 | enum hdmi_pll_pwr { |
| 72 | HDMI_PLLPWRCMD_ALLOFF = 0, |
| 73 | HDMI_PLLPWRCMD_PLLONLY = 1, |
| 74 | HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2, |
| 75 | HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3 |
| 76 | }; |
| 77 | |
Archit Taneja | f382d9e | 2013-08-06 14:56:55 +0530 | [diff] [blame] | 78 | enum hdmi_phy_pwr { |
| 79 | HDMI_PHYPWRCMD_OFF = 0, |
| 80 | HDMI_PHYPWRCMD_LDOON = 1, |
| 81 | HDMI_PHYPWRCMD_TXON = 2 |
| 82 | }; |
| 83 | |
Mythri P K | 94c5298 | 2011-09-08 19:06:21 +0530 | [diff] [blame] | 84 | enum hdmi_core_hdmi_dvi { |
| 85 | HDMI_DVI = 0, |
| 86 | HDMI_HDMI = 1 |
| 87 | }; |
| 88 | |
| 89 | enum hdmi_clk_refsel { |
| 90 | HDMI_REFSEL_PCLK = 0, |
| 91 | HDMI_REFSEL_REF1 = 1, |
| 92 | HDMI_REFSEL_REF2 = 2, |
| 93 | HDMI_REFSEL_SYSCLK = 3 |
| 94 | }; |
| 95 | |
Archit Taneja | f382d9e | 2013-08-06 14:56:55 +0530 | [diff] [blame] | 96 | enum hdmi_packing_mode { |
| 97 | HDMI_PACK_10b_RGB_YUV444 = 0, |
| 98 | HDMI_PACK_24b_RGB_YUV444_YUV422 = 1, |
| 99 | HDMI_PACK_20b_YUV422 = 2, |
| 100 | HDMI_PACK_ALREADYPACKED = 7 |
| 101 | }; |
| 102 | |
| 103 | enum hdmi_stereo_channels { |
| 104 | HDMI_AUDIO_STEREO_NOCHANNELS = 0, |
| 105 | HDMI_AUDIO_STEREO_ONECHANNEL = 1, |
| 106 | HDMI_AUDIO_STEREO_TWOCHANNELS = 2, |
| 107 | HDMI_AUDIO_STEREO_THREECHANNELS = 3, |
| 108 | HDMI_AUDIO_STEREO_FOURCHANNELS = 4 |
| 109 | }; |
| 110 | |
| 111 | enum hdmi_audio_type { |
| 112 | HDMI_AUDIO_TYPE_LPCM = 0, |
| 113 | HDMI_AUDIO_TYPE_IEC = 1 |
| 114 | }; |
| 115 | |
| 116 | enum hdmi_audio_justify { |
| 117 | HDMI_AUDIO_JUSTIFY_LEFT = 0, |
| 118 | HDMI_AUDIO_JUSTIFY_RIGHT = 1 |
| 119 | }; |
| 120 | |
| 121 | enum hdmi_audio_sample_order { |
| 122 | HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0, |
| 123 | HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1 |
| 124 | }; |
| 125 | |
| 126 | enum hdmi_audio_samples_perword { |
| 127 | HDMI_AUDIO_ONEWORD_ONESAMPLE = 0, |
| 128 | HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1 |
| 129 | }; |
| 130 | |
| 131 | enum hdmi_audio_sample_size { |
| 132 | HDMI_AUDIO_SAMPLE_16BITS = 0, |
| 133 | HDMI_AUDIO_SAMPLE_24BITS = 1 |
| 134 | }; |
| 135 | |
| 136 | enum hdmi_audio_transf_mode { |
| 137 | HDMI_AUDIO_TRANSF_DMA = 0, |
| 138 | HDMI_AUDIO_TRANSF_IRQ = 1 |
| 139 | }; |
| 140 | |
| 141 | enum hdmi_audio_blk_strt_end_sig { |
| 142 | HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0, |
| 143 | HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1 |
| 144 | }; |
| 145 | |
Archit Taneja | bdb8bfc | 2013-09-12 18:07:49 +0530 | [diff] [blame^] | 146 | enum hdmi_core_audio_layout { |
| 147 | HDMI_AUDIO_LAYOUT_2CH = 0, |
| 148 | HDMI_AUDIO_LAYOUT_8CH = 1 |
| 149 | }; |
| 150 | |
| 151 | enum hdmi_core_cts_mode { |
| 152 | HDMI_AUDIO_CTS_MODE_HW = 0, |
| 153 | HDMI_AUDIO_CTS_MODE_SW = 1 |
| 154 | }; |
| 155 | |
| 156 | enum hdmi_audio_mclk_mode { |
| 157 | HDMI_AUDIO_MCLK_128FS = 0, |
| 158 | HDMI_AUDIO_MCLK_256FS = 1, |
| 159 | HDMI_AUDIO_MCLK_384FS = 2, |
| 160 | HDMI_AUDIO_MCLK_512FS = 3, |
| 161 | HDMI_AUDIO_MCLK_768FS = 4, |
| 162 | HDMI_AUDIO_MCLK_1024FS = 5, |
| 163 | HDMI_AUDIO_MCLK_1152FS = 6, |
| 164 | HDMI_AUDIO_MCLK_192FS = 7 |
| 165 | }; |
| 166 | |
| 167 | /* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */ |
| 168 | enum hdmi_core_infoframe { |
| 169 | HDMI_INFOFRAME_AVI_DB1Y_RGB = 0, |
| 170 | HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1, |
| 171 | HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2, |
| 172 | HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0, |
| 173 | HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON = 1, |
| 174 | HDMI_INFOFRAME_AVI_DB1B_NO = 0, |
| 175 | HDMI_INFOFRAME_AVI_DB1B_VERT = 1, |
| 176 | HDMI_INFOFRAME_AVI_DB1B_HORI = 2, |
| 177 | HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3, |
| 178 | HDMI_INFOFRAME_AVI_DB1S_0 = 0, |
| 179 | HDMI_INFOFRAME_AVI_DB1S_1 = 1, |
| 180 | HDMI_INFOFRAME_AVI_DB1S_2 = 2, |
| 181 | HDMI_INFOFRAME_AVI_DB2C_NO = 0, |
| 182 | HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1, |
| 183 | HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2, |
| 184 | HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3, |
| 185 | HDMI_INFOFRAME_AVI_DB2M_NO = 0, |
| 186 | HDMI_INFOFRAME_AVI_DB2M_43 = 1, |
| 187 | HDMI_INFOFRAME_AVI_DB2M_169 = 2, |
| 188 | HDMI_INFOFRAME_AVI_DB2R_SAME = 8, |
| 189 | HDMI_INFOFRAME_AVI_DB2R_43 = 9, |
| 190 | HDMI_INFOFRAME_AVI_DB2R_169 = 10, |
| 191 | HDMI_INFOFRAME_AVI_DB2R_149 = 11, |
| 192 | HDMI_INFOFRAME_AVI_DB3ITC_NO = 0, |
| 193 | HDMI_INFOFRAME_AVI_DB3ITC_YES = 1, |
| 194 | HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0, |
| 195 | HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1, |
| 196 | HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0, |
| 197 | HDMI_INFOFRAME_AVI_DB3Q_LR = 1, |
| 198 | HDMI_INFOFRAME_AVI_DB3Q_FR = 2, |
| 199 | HDMI_INFOFRAME_AVI_DB3SC_NO = 0, |
| 200 | HDMI_INFOFRAME_AVI_DB3SC_HORI = 1, |
| 201 | HDMI_INFOFRAME_AVI_DB3SC_VERT = 2, |
| 202 | HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3, |
| 203 | HDMI_INFOFRAME_AVI_DB5PR_NO = 0, |
| 204 | HDMI_INFOFRAME_AVI_DB5PR_2 = 1, |
| 205 | HDMI_INFOFRAME_AVI_DB5PR_3 = 2, |
| 206 | HDMI_INFOFRAME_AVI_DB5PR_4 = 3, |
| 207 | HDMI_INFOFRAME_AVI_DB5PR_5 = 4, |
| 208 | HDMI_INFOFRAME_AVI_DB5PR_6 = 5, |
| 209 | HDMI_INFOFRAME_AVI_DB5PR_7 = 6, |
| 210 | HDMI_INFOFRAME_AVI_DB5PR_8 = 7, |
| 211 | HDMI_INFOFRAME_AVI_DB5PR_9 = 8, |
| 212 | HDMI_INFOFRAME_AVI_DB5PR_10 = 9, |
| 213 | }; |
| 214 | |
Mythri P K | 94c5298 | 2011-09-08 19:06:21 +0530 | [diff] [blame] | 215 | struct hdmi_cm { |
| 216 | int code; |
| 217 | int mode; |
| 218 | }; |
| 219 | |
Archit Taneja | f382d9e | 2013-08-06 14:56:55 +0530 | [diff] [blame] | 220 | struct hdmi_video_format { |
| 221 | enum hdmi_packing_mode packing_mode; |
| 222 | u32 y_res; /* Line per panel */ |
| 223 | u32 x_res; /* pixel per line */ |
| 224 | }; |
| 225 | |
Mythri P K | 94c5298 | 2011-09-08 19:06:21 +0530 | [diff] [blame] | 226 | struct hdmi_config { |
Archit Taneja | cc937e5 | 2012-06-24 13:08:10 +0530 | [diff] [blame] | 227 | struct omap_video_timings timings; |
Mythri P K | 94c5298 | 2011-09-08 19:06:21 +0530 | [diff] [blame] | 228 | struct hdmi_cm cm; |
| 229 | }; |
| 230 | |
| 231 | /* HDMI PLL structure */ |
| 232 | struct hdmi_pll_info { |
| 233 | u16 regn; |
| 234 | u16 regm; |
| 235 | u32 regmf; |
| 236 | u16 regm2; |
| 237 | u16 regsd; |
| 238 | u16 dcofreq; |
| 239 | enum hdmi_clk_refsel refsel; |
| 240 | }; |
| 241 | |
Archit Taneja | f382d9e | 2013-08-06 14:56:55 +0530 | [diff] [blame] | 242 | struct hdmi_audio_format { |
| 243 | enum hdmi_stereo_channels stereo_channels; |
| 244 | u8 active_chnnls_msk; |
| 245 | enum hdmi_audio_type type; |
| 246 | enum hdmi_audio_justify justification; |
| 247 | enum hdmi_audio_sample_order sample_order; |
| 248 | enum hdmi_audio_samples_perword samples_per_word; |
| 249 | enum hdmi_audio_sample_size sample_size; |
| 250 | enum hdmi_audio_blk_strt_end_sig en_sig_blk_strt_end; |
| 251 | }; |
| 252 | |
| 253 | struct hdmi_audio_dma { |
| 254 | u8 transfer_size; |
| 255 | u8 block_size; |
| 256 | enum hdmi_audio_transf_mode mode; |
| 257 | u16 fifo_threshold; |
| 258 | }; |
| 259 | |
Archit Taneja | bdb8bfc | 2013-09-12 18:07:49 +0530 | [diff] [blame^] | 260 | struct hdmi_core_audio_i2s_config { |
| 261 | u8 in_length_bits; |
| 262 | u8 justification; |
| 263 | u8 sck_edge_mode; |
| 264 | u8 vbit; |
| 265 | u8 direction; |
| 266 | u8 shift; |
| 267 | u8 active_sds; |
| 268 | }; |
| 269 | |
| 270 | struct hdmi_core_audio_config { |
| 271 | struct hdmi_core_audio_i2s_config i2s_cfg; |
| 272 | struct snd_aes_iec958 *iec60958_cfg; |
| 273 | bool fs_override; |
| 274 | u32 n; |
| 275 | u32 cts; |
| 276 | u32 aud_par_busclk; |
| 277 | enum hdmi_core_audio_layout layout; |
| 278 | enum hdmi_core_cts_mode cts_mode; |
| 279 | bool use_mclk; |
| 280 | enum hdmi_audio_mclk_mode mclk_mode; |
| 281 | bool en_acr_pkt; |
| 282 | bool en_dsd_audio; |
| 283 | bool en_parallel_aud_input; |
| 284 | bool en_spdif; |
| 285 | }; |
| 286 | |
Mythri P K | da8f14f | 2012-02-08 11:54:19 +0530 | [diff] [blame] | 287 | /* |
| 288 | * Refer to section 8.2 in HDMI 1.3 specification for |
| 289 | * details about infoframe databytes |
| 290 | */ |
| 291 | struct hdmi_core_infoframe_avi { |
| 292 | /* Y0, Y1 rgb,yCbCr */ |
| 293 | u8 db1_format; |
| 294 | /* A0 Active information Present */ |
| 295 | u8 db1_active_info; |
| 296 | /* B0, B1 Bar info data valid */ |
| 297 | u8 db1_bar_info_dv; |
| 298 | /* S0, S1 scan information */ |
| 299 | u8 db1_scan_info; |
| 300 | /* C0, C1 colorimetry */ |
| 301 | u8 db2_colorimetry; |
| 302 | /* M0, M1 Aspect ratio (4:3, 16:9) */ |
| 303 | u8 db2_aspect_ratio; |
| 304 | /* R0...R3 Active format aspect ratio */ |
| 305 | u8 db2_active_fmt_ar; |
| 306 | /* ITC IT content. */ |
| 307 | u8 db3_itc; |
| 308 | /* EC0, EC1, EC2 Extended colorimetry */ |
| 309 | u8 db3_ec; |
| 310 | /* Q1, Q0 Quantization range */ |
| 311 | u8 db3_q_range; |
| 312 | /* SC1, SC0 Non-uniform picture scaling */ |
| 313 | u8 db3_nup_scaling; |
| 314 | /* VIC0..6 Video format identification */ |
| 315 | u8 db4_videocode; |
| 316 | /* PR0..PR3 Pixel repetition factor */ |
| 317 | u8 db5_pixel_repeat; |
| 318 | /* Line number end of top bar */ |
| 319 | u16 db6_7_line_eoftop; |
| 320 | /* Line number start of bottom bar */ |
| 321 | u16 db8_9_line_sofbottom; |
| 322 | /* Pixel number end of left bar */ |
| 323 | u16 db10_11_pixel_eofleft; |
| 324 | /* Pixel number start of right bar */ |
| 325 | u16 db12_13_pixel_sofright; |
| 326 | }; |
| 327 | |
Archit Taneja | f382d9e | 2013-08-06 14:56:55 +0530 | [diff] [blame] | 328 | struct hdmi_wp_data { |
| 329 | void __iomem *base; |
| 330 | }; |
| 331 | |
Archit Taneja | c1577c1 | 2013-10-08 12:55:26 +0530 | [diff] [blame] | 332 | struct hdmi_pll_data { |
| 333 | void __iomem *base; |
| 334 | |
| 335 | struct hdmi_pll_info info; |
| 336 | }; |
| 337 | |
Archit Taneja | 5cac5ae | 2013-10-08 13:07:00 +0530 | [diff] [blame] | 338 | struct hdmi_phy_data { |
| 339 | void __iomem *base; |
| 340 | |
| 341 | int irq; |
| 342 | }; |
| 343 | |
Archit Taneja | 425f02f | 2013-10-08 14:16:05 +0530 | [diff] [blame] | 344 | struct hdmi_core_data { |
| 345 | void __iomem *base; |
| 346 | |
| 347 | struct hdmi_core_infoframe_avi avi_cfg; |
| 348 | }; |
| 349 | |
Archit Taneja | bdb8bfc | 2013-09-12 18:07:49 +0530 | [diff] [blame^] | 350 | static inline void hdmi_write_reg(void __iomem *base_addr, const u16 idx, |
| 351 | u32 val) |
| 352 | { |
| 353 | __raw_writel(val, base_addr + idx); |
| 354 | } |
| 355 | |
| 356 | static inline u32 hdmi_read_reg(void __iomem *base_addr, const u16 idx) |
| 357 | { |
| 358 | return __raw_readl(base_addr + idx); |
| 359 | } |
| 360 | |
| 361 | #define REG_FLD_MOD(base, idx, val, start, end) \ |
| 362 | hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\ |
| 363 | val, start, end)) |
| 364 | #define REG_GET(base, idx, start, end) \ |
| 365 | FLD_GET(hdmi_read_reg(base, idx), start, end) |
| 366 | |
| 367 | static inline int hdmi_wait_for_bit_change(void __iomem *base_addr, |
| 368 | const u16 idx, int b2, int b1, u32 val) |
| 369 | { |
| 370 | u32 t = 0; |
| 371 | while (val != REG_GET(base_addr, idx, b2, b1)) { |
| 372 | udelay(1); |
| 373 | if (t++ > 10000) |
| 374 | return !val; |
| 375 | } |
| 376 | return val; |
| 377 | } |
| 378 | |
Archit Taneja | f382d9e | 2013-08-06 14:56:55 +0530 | [diff] [blame] | 379 | /* HDMI wrapper funcs */ |
| 380 | int hdmi_wp_video_start(struct hdmi_wp_data *wp); |
| 381 | void hdmi_wp_video_stop(struct hdmi_wp_data *wp); |
| 382 | void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s); |
| 383 | u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp); |
| 384 | void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus); |
| 385 | void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask); |
| 386 | void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask); |
| 387 | int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val); |
| 388 | int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val); |
| 389 | void hdmi_wp_video_config_format(struct hdmi_wp_data *wp, |
| 390 | struct hdmi_video_format *video_fmt); |
| 391 | void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp, |
| 392 | struct omap_video_timings *timings); |
| 393 | void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, |
| 394 | struct omap_video_timings *timings); |
| 395 | void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, |
| 396 | struct omap_video_timings *timings, struct hdmi_config *param); |
| 397 | int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp); |
| 398 | |
Archit Taneja | c1577c1 | 2013-10-08 12:55:26 +0530 | [diff] [blame] | 399 | /* HDMI PLL funcs */ |
| 400 | int hdmi_pll_enable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp); |
| 401 | void hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp); |
| 402 | void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s); |
| 403 | void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy); |
| 404 | int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll); |
| 405 | |
Archit Taneja | 5cac5ae | 2013-10-08 13:07:00 +0530 | [diff] [blame] | 406 | /* HDMI PHY funcs */ |
| 407 | int hdmi_phy_enable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp, |
| 408 | struct hdmi_config *cfg); |
| 409 | void hdmi_phy_disable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp); |
| 410 | void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s); |
| 411 | int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy); |
| 412 | |
Ricardo Neri | 7e151f7 | 2012-03-15 14:08:03 -0600 | [diff] [blame] | 413 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) |
Ricardo Neri | 3554762 | 2012-03-20 21:02:01 -0600 | [diff] [blame] | 414 | int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts); |
Archit Taneja | f382d9e | 2013-08-06 14:56:55 +0530 | [diff] [blame] | 415 | int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable); |
| 416 | int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable); |
| 417 | void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp, |
| 418 | struct hdmi_audio_format *aud_fmt); |
| 419 | void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp, |
| 420 | struct hdmi_audio_dma *aud_dma); |
Ricardo Neri | 80a4859 | 2011-11-27 16:09:58 -0600 | [diff] [blame] | 421 | #endif |
Mythri P K | 94c5298 | 2011-09-08 19:06:21 +0530 | [diff] [blame] | 422 | #endif |