blob: 092cef4160a10a481219f7f0c624ca35306d7ad7 [file] [log] [blame]
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001/*
2 * Support for PCI bridges found on Power Macintoshes.
Paul Mackerras14cf11a2005-09-26 16:04:21 +10003 *
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +11004 * Copyright (C) 2003-2005 Benjamin Herrenschmuidt (benh@kernel.crashing.org)
Paul Mackerras14cf11a2005-09-26 16:04:21 +10005 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#include <linux/kernel.h>
14#include <linux/pci.h>
15#include <linux/delay.h>
16#include <linux/string.h>
17#include <linux/init.h>
18#include <linux/bootmem.h>
Benjamin Herrenschmidt6e99e452006-07-10 04:44:42 -070019#include <linux/irq.h>
Paul Mackerras14cf11a2005-09-26 16:04:21 +100020
21#include <asm/sections.h>
22#include <asm/io.h>
23#include <asm/prom.h>
24#include <asm/pci-bridge.h>
25#include <asm/machdep.h>
26#include <asm/pmac_feature.h>
Paul Mackerras830825d2005-10-26 17:16:38 +100027#include <asm/grackle.h>
Paul Mackerras3c3f42d2005-10-10 22:58:41 +100028#include <asm/ppc-pci.h>
Paul Mackerras14cf11a2005-09-26 16:04:21 +100029
30#undef DEBUG
31
32#ifdef DEBUG
33#define DBG(x...) printk(x)
34#else
35#define DBG(x...)
36#endif
37
38static int add_bridge(struct device_node *dev);
Paul Mackerras14cf11a2005-09-26 16:04:21 +100039
40/* XXX Could be per-controller, but I don't think we risk anything by
41 * assuming we won't have both UniNorth and Bandit */
42static int has_uninorth;
Paul Mackerras35499c02005-10-22 16:02:39 +100043#ifdef CONFIG_PPC64
Paul Mackerras14cf11a2005-09-26 16:04:21 +100044static struct pci_controller *u3_agp;
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +110045static struct pci_controller *u4_pcie;
Paul Mackerras35499c02005-10-22 16:02:39 +100046static struct pci_controller *u3_ht;
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +100047#else
48static int has_second_ohare;
Paul Mackerras35499c02005-10-22 16:02:39 +100049#endif /* CONFIG_PPC64 */
Paul Mackerras14cf11a2005-09-26 16:04:21 +100050
Paul Mackerras14cf11a2005-09-26 16:04:21 +100051extern int pcibios_assign_bus_offset;
52
53struct device_node *k2_skiplist[2];
54
55/*
56 * Magic constants for enabling cache coherency in the bandit/PSX bridge.
57 */
58#define BANDIT_DEVID_2 8
59#define BANDIT_REVID 3
60
61#define BANDIT_DEVNUM 11
62#define BANDIT_MAGIC 0x50
63#define BANDIT_COHERENT 0x40
64
65static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
66{
67 for (; node != 0;node = node->sibling) {
Jeremy Kerr018a3d12006-07-12 15:40:29 +100068 const int * bus_range;
69 const unsigned int *class_code;
Paul Mackerras14cf11a2005-09-26 16:04:21 +100070 int len;
71
72 /* For PCI<->PCI bridges or CardBus bridges, we go down */
Stephen Rothwelle2eb6392007-04-03 22:26:41 +100073 class_code = of_get_property(node, "class-code", NULL);
Paul Mackerras14cf11a2005-09-26 16:04:21 +100074 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
75 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
76 continue;
Stephen Rothwelle2eb6392007-04-03 22:26:41 +100077 bus_range = of_get_property(node, "bus-range", &len);
Paul Mackerras14cf11a2005-09-26 16:04:21 +100078 if (bus_range != NULL && len > 2 * sizeof(int)) {
79 if (bus_range[1] > higher)
80 higher = bus_range[1];
81 }
82 higher = fixup_one_level_bus_range(node->child, higher);
83 }
84 return higher;
85}
86
87/* This routine fixes the "bus-range" property of all bridges in the
88 * system since they tend to have their "last" member wrong on macs
89 *
90 * Note that the bus numbers manipulated here are OF bus numbers, they
91 * are not Linux bus numbers.
92 */
93static void __init fixup_bus_range(struct device_node *bridge)
94{
Jeremy Kerr018a3d12006-07-12 15:40:29 +100095 int *bus_range, len;
96 struct property *prop;
Paul Mackerras14cf11a2005-09-26 16:04:21 +100097
98 /* Lookup the "bus-range" property for the hose */
Jeremy Kerr018a3d12006-07-12 15:40:29 +100099 prop = of_find_property(bridge, "bus-range", &len);
100 if (prop == NULL || prop->length < 2 * sizeof(int))
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000101 return;
Jeremy Kerr018a3d12006-07-12 15:40:29 +1000102
Stephen Rothwell1a381472007-04-03 10:58:52 +1000103 bus_range = prop->value;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000104 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
105}
106
107/*
108 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers.
109 *
110 * The "Bandit" version is present in all early PCI PowerMacs,
111 * and up to the first ones using Grackle. Some machines may
112 * have 2 bandit controllers (2 PCI busses).
113 *
114 * "Chaos" is used in some "Bandit"-type machines as a bridge
115 * for the separate display bus. It is accessed the same
116 * way as bandit, but cannot be probed for devices. It therefore
117 * has its own config access functions.
118 *
119 * The "UniNorth" version is present in all Core99 machines
120 * (iBook, G4, new IMacs, and all the recent Apple machines).
121 * It contains 3 controllers in one ASIC.
122 *
123 * The U3 is the bridge used on G5 machines. It contains an
124 * AGP bus which is dealt with the old UniNorth access routines
125 * and a HyperTransport bus which uses its own set of access
126 * functions.
127 */
128
129#define MACRISC_CFA0(devfn, off) \
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100130 ((1 << (unsigned int)PCI_SLOT(dev_fn)) \
131 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \
132 | (((unsigned int)(off)) & 0xFCUL))
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000133
134#define MACRISC_CFA1(bus, devfn, off) \
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100135 ((((unsigned int)(bus)) << 16) \
136 |(((unsigned int)(devfn)) << 8) \
137 |(((unsigned int)(off)) & 0xFCUL) \
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000138 |1UL)
139
Al Virode125bf2006-02-01 05:18:43 -0500140static volatile void __iomem *macrisc_cfg_access(struct pci_controller* hose,
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000141 u8 bus, u8 dev_fn, u8 offset)
142{
143 unsigned int caddr;
144
145 if (bus == hose->first_busno) {
146 if (dev_fn < (11 << 3))
Al Virode125bf2006-02-01 05:18:43 -0500147 return NULL;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000148 caddr = MACRISC_CFA0(dev_fn, offset);
149 } else
150 caddr = MACRISC_CFA1(bus, dev_fn, offset);
151
152 /* Uninorth will return garbage if we don't read back the value ! */
153 do {
154 out_le32(hose->cfg_addr, caddr);
155 } while (in_le32(hose->cfg_addr) != caddr);
156
157 offset &= has_uninorth ? 0x07 : 0x03;
Al Virode125bf2006-02-01 05:18:43 -0500158 return hose->cfg_data + offset;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000159}
160
161static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn,
162 int offset, int len, u32 *val)
163{
Paul Mackerras3c3f42d2005-10-10 22:58:41 +1000164 struct pci_controller *hose;
Al Virode125bf2006-02-01 05:18:43 -0500165 volatile void __iomem *addr;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000166
Paul Mackerras3c3f42d2005-10-10 22:58:41 +1000167 hose = pci_bus_to_host(bus);
168 if (hose == NULL)
169 return PCIBIOS_DEVICE_NOT_FOUND;
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100170 if (offset >= 0x100)
171 return PCIBIOS_BAD_REGISTER_NUMBER;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000172 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
173 if (!addr)
174 return PCIBIOS_DEVICE_NOT_FOUND;
175 /*
176 * Note: the caller has already checked that offset is
177 * suitably aligned and that len is 1, 2 or 4.
178 */
179 switch (len) {
180 case 1:
Al Virode125bf2006-02-01 05:18:43 -0500181 *val = in_8(addr);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000182 break;
183 case 2:
Al Virode125bf2006-02-01 05:18:43 -0500184 *val = in_le16(addr);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000185 break;
186 default:
Al Virode125bf2006-02-01 05:18:43 -0500187 *val = in_le32(addr);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000188 break;
189 }
190 return PCIBIOS_SUCCESSFUL;
191}
192
193static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn,
194 int offset, int len, u32 val)
195{
Paul Mackerras3c3f42d2005-10-10 22:58:41 +1000196 struct pci_controller *hose;
Al Virode125bf2006-02-01 05:18:43 -0500197 volatile void __iomem *addr;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000198
Paul Mackerras3c3f42d2005-10-10 22:58:41 +1000199 hose = pci_bus_to_host(bus);
200 if (hose == NULL)
201 return PCIBIOS_DEVICE_NOT_FOUND;
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100202 if (offset >= 0x100)
203 return PCIBIOS_BAD_REGISTER_NUMBER;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000204 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
205 if (!addr)
206 return PCIBIOS_DEVICE_NOT_FOUND;
207 /*
208 * Note: the caller has already checked that offset is
209 * suitably aligned and that len is 1, 2 or 4.
210 */
211 switch (len) {
212 case 1:
Al Virode125bf2006-02-01 05:18:43 -0500213 out_8(addr, val);
214 (void) in_8(addr);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000215 break;
216 case 2:
Al Virode125bf2006-02-01 05:18:43 -0500217 out_le16(addr, val);
218 (void) in_le16(addr);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000219 break;
220 default:
Al Virode125bf2006-02-01 05:18:43 -0500221 out_le32(addr, val);
222 (void) in_le32(addr);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000223 break;
224 }
225 return PCIBIOS_SUCCESSFUL;
226}
227
228static struct pci_ops macrisc_pci_ops =
229{
230 macrisc_read_config,
231 macrisc_write_config
232};
233
Paul Mackerras35499c02005-10-22 16:02:39 +1000234#ifdef CONFIG_PPC32
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000235/*
Paul Mackerras3c3f42d2005-10-10 22:58:41 +1000236 * Verify that a specific (bus, dev_fn) exists on chaos
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000237 */
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100238static int chaos_validate_dev(struct pci_bus *bus, int devfn, int offset)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000239{
240 struct device_node *np;
Jeremy Kerr018a3d12006-07-12 15:40:29 +1000241 const u32 *vendor, *device;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000242
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100243 if (offset >= 0x100)
244 return PCIBIOS_BAD_REGISTER_NUMBER;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000245 np = pci_busdev_to_OF_node(bus, devfn);
246 if (np == NULL)
247 return PCIBIOS_DEVICE_NOT_FOUND;
248
Stephen Rothwelle2eb6392007-04-03 22:26:41 +1000249 vendor = of_get_property(np, "vendor-id", NULL);
250 device = of_get_property(np, "device-id", NULL);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000251 if (vendor == NULL || device == NULL)
252 return PCIBIOS_DEVICE_NOT_FOUND;
253
254 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10)
255 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24))
256 return PCIBIOS_BAD_REGISTER_NUMBER;
257
258 return PCIBIOS_SUCCESSFUL;
259}
260
261static int
262chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
263 int len, u32 *val)
264{
265 int result = chaos_validate_dev(bus, devfn, offset);
266 if (result == PCIBIOS_BAD_REGISTER_NUMBER)
267 *val = ~0U;
268 if (result != PCIBIOS_SUCCESSFUL)
269 return result;
270 return macrisc_read_config(bus, devfn, offset, len, val);
271}
272
273static int
274chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
275 int len, u32 val)
276{
277 int result = chaos_validate_dev(bus, devfn, offset);
278 if (result != PCIBIOS_SUCCESSFUL)
279 return result;
280 return macrisc_write_config(bus, devfn, offset, len, val);
281}
282
283static struct pci_ops chaos_pci_ops =
284{
285 chaos_read_config,
286 chaos_write_config
287};
288
Paul Mackerras35499c02005-10-22 16:02:39 +1000289static void __init setup_chaos(struct pci_controller *hose,
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +1100290 struct resource *addr)
Paul Mackerras35499c02005-10-22 16:02:39 +1000291{
292 /* assume a `chaos' bridge */
293 hose->ops = &chaos_pci_ops;
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +1100294 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
295 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
Paul Mackerras35499c02005-10-22 16:02:39 +1000296}
Paul Mackerras35499c02005-10-22 16:02:39 +1000297#endif /* CONFIG_PPC32 */
298
299#ifdef CONFIG_PPC64
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000300/*
301 * These versions of U3 HyperTransport config space access ops do not
302 * implement self-view of the HT host yet
303 */
304
305/*
306 * This function deals with some "special cases" devices.
307 *
308 * 0 -> No special case
309 * 1 -> Skip the device but act as if the access was successfull
310 * (return 0xff's on reads, eventually, cache config space
311 * accesses in a later version)
312 * -1 -> Hide the device (unsuccessful acess)
313 */
314static int u3_ht_skip_device(struct pci_controller *hose,
315 struct pci_bus *bus, unsigned int devfn)
316{
317 struct device_node *busdn, *dn;
318 int i;
319
320 /* We only allow config cycles to devices that are in OF device-tree
321 * as we are apparently having some weird things going on with some
322 * revs of K2 on recent G5s
323 */
324 if (bus->self)
325 busdn = pci_device_to_OF_node(bus->self);
326 else
327 busdn = hose->arch_data;
328 for (dn = busdn->child; dn; dn = dn->sibling)
linase07102d2005-12-05 19:37:35 -0600329 if (PCI_DN(dn) && PCI_DN(dn)->devfn == devfn)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000330 break;
331 if (dn == NULL)
332 return -1;
333
334 /*
335 * When a device in K2 is powered down, we die on config
336 * cycle accesses. Fix that here.
337 */
338 for (i=0; i<2; i++)
339 if (k2_skiplist[i] == dn)
340 return 1;
341
342 return 0;
343}
344
345#define U3_HT_CFA0(devfn, off) \
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100346 ((((unsigned int)devfn) << 8) | offset)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000347#define U3_HT_CFA1(bus, devfn, off) \
348 (U3_HT_CFA0(devfn, off) \
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100349 + (((unsigned int)bus) << 16) \
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000350 + 0x01000000UL)
351
Al Virode125bf2006-02-01 05:18:43 -0500352static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose,
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000353 u8 bus, u8 devfn, u8 offset)
354{
355 if (bus == hose->first_busno) {
356 /* For now, we don't self probe U3 HT bridge */
357 if (PCI_SLOT(devfn) == 0)
Al Virode125bf2006-02-01 05:18:43 -0500358 return NULL;
359 return hose->cfg_data + U3_HT_CFA0(devfn, offset);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000360 } else
Al Virode125bf2006-02-01 05:18:43 -0500361 return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000362}
363
364static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
365 int offset, int len, u32 *val)
366{
Paul Mackerras3c3f42d2005-10-10 22:58:41 +1000367 struct pci_controller *hose;
Al Virode125bf2006-02-01 05:18:43 -0500368 volatile void __iomem *addr;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000369
Paul Mackerras3c3f42d2005-10-10 22:58:41 +1000370 hose = pci_bus_to_host(bus);
371 if (hose == NULL)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000372 return PCIBIOS_DEVICE_NOT_FOUND;
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100373 if (offset >= 0x100)
374 return PCIBIOS_BAD_REGISTER_NUMBER;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000375 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
376 if (!addr)
377 return PCIBIOS_DEVICE_NOT_FOUND;
378
379 switch (u3_ht_skip_device(hose, bus, devfn)) {
380 case 0:
381 break;
382 case 1:
Paul Mackerras3c3f42d2005-10-10 22:58:41 +1000383 switch (len) {
384 case 1:
385 *val = 0xff; break;
386 case 2:
387 *val = 0xffff; break;
388 default:
389 *val = 0xfffffffful; break;
390 }
391 return PCIBIOS_SUCCESSFUL;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000392 default:
393 return PCIBIOS_DEVICE_NOT_FOUND;
Paul Mackerras3c3f42d2005-10-10 22:58:41 +1000394 }
395
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000396 /*
397 * Note: the caller has already checked that offset is
398 * suitably aligned and that len is 1, 2 or 4.
399 */
400 switch (len) {
401 case 1:
Al Virode125bf2006-02-01 05:18:43 -0500402 *val = in_8(addr);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000403 break;
404 case 2:
Al Virode125bf2006-02-01 05:18:43 -0500405 *val = in_le16(addr);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000406 break;
407 default:
Al Virode125bf2006-02-01 05:18:43 -0500408 *val = in_le32(addr);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000409 break;
410 }
411 return PCIBIOS_SUCCESSFUL;
412}
413
414static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
415 int offset, int len, u32 val)
416{
Paul Mackerras3c3f42d2005-10-10 22:58:41 +1000417 struct pci_controller *hose;
Al Virode125bf2006-02-01 05:18:43 -0500418 volatile void __iomem *addr;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000419
Paul Mackerras3c3f42d2005-10-10 22:58:41 +1000420 hose = pci_bus_to_host(bus);
421 if (hose == NULL)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000422 return PCIBIOS_DEVICE_NOT_FOUND;
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100423 if (offset >= 0x100)
424 return PCIBIOS_BAD_REGISTER_NUMBER;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000425 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
426 if (!addr)
427 return PCIBIOS_DEVICE_NOT_FOUND;
428
429 switch (u3_ht_skip_device(hose, bus, devfn)) {
430 case 0:
431 break;
432 case 1:
433 return PCIBIOS_SUCCESSFUL;
434 default:
435 return PCIBIOS_DEVICE_NOT_FOUND;
436 }
437
438 /*
439 * Note: the caller has already checked that offset is
440 * suitably aligned and that len is 1, 2 or 4.
441 */
442 switch (len) {
443 case 1:
Al Virode125bf2006-02-01 05:18:43 -0500444 out_8(addr, val);
445 (void) in_8(addr);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000446 break;
447 case 2:
Al Virode125bf2006-02-01 05:18:43 -0500448 out_le16(addr, val);
449 (void) in_le16(addr);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000450 break;
451 default:
Al Virode125bf2006-02-01 05:18:43 -0500452 out_le32((u32 __iomem *)addr, val);
453 (void) in_le32(addr);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000454 break;
455 }
456 return PCIBIOS_SUCCESSFUL;
457}
458
459static struct pci_ops u3_ht_pci_ops =
460{
461 u3_ht_read_config,
462 u3_ht_write_config
463};
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100464
465#define U4_PCIE_CFA0(devfn, off) \
466 ((1 << ((unsigned int)PCI_SLOT(dev_fn))) \
467 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \
468 | ((((unsigned int)(off)) >> 8) << 28) \
469 | (((unsigned int)(off)) & 0xfcU))
470
471#define U4_PCIE_CFA1(bus, devfn, off) \
472 ((((unsigned int)(bus)) << 16) \
473 |(((unsigned int)(devfn)) << 8) \
474 | ((((unsigned int)(off)) >> 8) << 28) \
475 |(((unsigned int)(off)) & 0xfcU) \
476 |1UL)
477
Al Virode125bf2006-02-01 05:18:43 -0500478static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose,
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100479 u8 bus, u8 dev_fn, int offset)
480{
481 unsigned int caddr;
482
483 if (bus == hose->first_busno) {
484 caddr = U4_PCIE_CFA0(dev_fn, offset);
485 } else
486 caddr = U4_PCIE_CFA1(bus, dev_fn, offset);
487
488 /* Uninorth will return garbage if we don't read back the value ! */
489 do {
490 out_le32(hose->cfg_addr, caddr);
491 } while (in_le32(hose->cfg_addr) != caddr);
492
493 offset &= 0x03;
Al Virode125bf2006-02-01 05:18:43 -0500494 return hose->cfg_data + offset;
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100495}
496
497static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
498 int offset, int len, u32 *val)
499{
500 struct pci_controller *hose;
Al Virode125bf2006-02-01 05:18:43 -0500501 volatile void __iomem *addr;
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100502
503 hose = pci_bus_to_host(bus);
504 if (hose == NULL)
505 return PCIBIOS_DEVICE_NOT_FOUND;
506 if (offset >= 0x1000)
507 return PCIBIOS_BAD_REGISTER_NUMBER;
508 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
509 if (!addr)
510 return PCIBIOS_DEVICE_NOT_FOUND;
511 /*
512 * Note: the caller has already checked that offset is
513 * suitably aligned and that len is 1, 2 or 4.
514 */
515 switch (len) {
516 case 1:
Al Virode125bf2006-02-01 05:18:43 -0500517 *val = in_8(addr);
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100518 break;
519 case 2:
Al Virode125bf2006-02-01 05:18:43 -0500520 *val = in_le16(addr);
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100521 break;
522 default:
Al Virode125bf2006-02-01 05:18:43 -0500523 *val = in_le32(addr);
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100524 break;
525 }
526 return PCIBIOS_SUCCESSFUL;
527}
528
529static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
530 int offset, int len, u32 val)
531{
532 struct pci_controller *hose;
Al Virode125bf2006-02-01 05:18:43 -0500533 volatile void __iomem *addr;
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100534
535 hose = pci_bus_to_host(bus);
536 if (hose == NULL)
537 return PCIBIOS_DEVICE_NOT_FOUND;
538 if (offset >= 0x1000)
539 return PCIBIOS_BAD_REGISTER_NUMBER;
540 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
541 if (!addr)
542 return PCIBIOS_DEVICE_NOT_FOUND;
543 /*
544 * Note: the caller has already checked that offset is
545 * suitably aligned and that len is 1, 2 or 4.
546 */
547 switch (len) {
548 case 1:
Al Virode125bf2006-02-01 05:18:43 -0500549 out_8(addr, val);
550 (void) in_8(addr);
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100551 break;
552 case 2:
Al Virode125bf2006-02-01 05:18:43 -0500553 out_le16(addr, val);
554 (void) in_le16(addr);
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100555 break;
556 default:
Al Virode125bf2006-02-01 05:18:43 -0500557 out_le32(addr, val);
558 (void) in_le32(addr);
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100559 break;
560 }
561 return PCIBIOS_SUCCESSFUL;
562}
563
564static struct pci_ops u4_pcie_pci_ops =
565{
566 u4_pcie_read_config,
567 u4_pcie_write_config
568};
569
Paul Mackerras35499c02005-10-22 16:02:39 +1000570#endif /* CONFIG_PPC64 */
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000571
Paul Mackerras35499c02005-10-22 16:02:39 +1000572#ifdef CONFIG_PPC32
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000573/*
574 * For a bandit bridge, turn on cache coherency if necessary.
575 * N.B. we could clean this up using the hose ops directly.
576 */
Paul Mackerras3c3f42d2005-10-10 22:58:41 +1000577static void __init init_bandit(struct pci_controller *bp)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000578{
579 unsigned int vendev, magic;
580 int rev;
581
582 /* read the word at offset 0 in config space for device 11 */
583 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID);
584 udelay(2);
585 vendev = in_le32(bp->cfg_data);
586 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) +
587 PCI_VENDOR_ID_APPLE) {
588 /* read the revision id */
589 out_le32(bp->cfg_addr,
590 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID);
591 udelay(2);
592 rev = in_8(bp->cfg_data);
593 if (rev != BANDIT_REVID)
594 printk(KERN_WARNING
595 "Unknown revision %d for bandit\n", rev);
596 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) {
597 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev);
598 return;
599 }
600
601 /* read the word at offset 0x50 */
602 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC);
603 udelay(2);
604 magic = in_le32(bp->cfg_data);
605 if ((magic & BANDIT_COHERENT) != 0)
606 return;
607 magic |= BANDIT_COHERENT;
608 udelay(2);
609 out_le32(bp->cfg_data, magic);
610 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n");
611}
612
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000613/*
614 * Tweak the PCI-PCI bridge chip on the blue & white G3s.
615 */
Paul Mackerras3c3f42d2005-10-10 22:58:41 +1000616static void __init init_p2pbridge(void)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000617{
618 struct device_node *p2pbridge;
619 struct pci_controller* hose;
620 u8 bus, devfn;
621 u16 val;
622
623 /* XXX it would be better here to identify the specific
624 PCI-PCI bridge chip we have. */
625 if ((p2pbridge = find_devices("pci-bridge")) == 0
626 || p2pbridge->parent == NULL
627 || strcmp(p2pbridge->parent->name, "pci") != 0)
628 return;
629 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) {
630 DBG("Can't find PCI infos for PCI<->PCI bridge\n");
631 return;
632 }
633 /* Warning: At this point, we have not yet renumbered all busses.
634 * So we must use OF walking to find out hose
635 */
636 hose = pci_find_hose_for_OF_device(p2pbridge);
637 if (!hose) {
638 DBG("Can't find hose for PCI<->PCI bridge\n");
639 return;
640 }
641 if (early_read_config_word(hose, bus, devfn,
642 PCI_BRIDGE_CONTROL, &val) < 0) {
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +1100643 printk(KERN_ERR "init_p2pbridge: couldn't read bridge"
644 " control\n");
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000645 return;
646 }
647 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT;
648 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val);
649}
650
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000651static void __init init_second_ohare(void)
652{
653 struct device_node *np = of_find_node_by_name(NULL, "pci106b,7");
654 unsigned char bus, devfn;
655 unsigned short cmd;
656
657 if (np == NULL)
658 return;
659
660 /* This must run before we initialize the PICs since the second
661 * ohare hosts a PIC that will be accessed there.
662 */
663 if (pci_device_from_OF_node(np, &bus, &devfn) == 0) {
664 struct pci_controller* hose =
665 pci_find_hose_for_OF_device(np);
666 if (!hose) {
667 printk(KERN_ERR "Can't find PCI hose for OHare2 !\n");
668 return;
669 }
670 early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd);
671 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
672 cmd &= ~PCI_COMMAND_IO;
673 early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd);
674 }
675 has_second_ohare = 1;
676}
677
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000678/*
679 * Some Apple desktop machines have a NEC PD720100A USB2 controller
680 * on the motherboard. Open Firmware, on these, will disable the
681 * EHCI part of it so it behaves like a pair of OHCI's. This fixup
682 * code re-enables it ;)
683 */
Paul Mackerras3c3f42d2005-10-10 22:58:41 +1000684static void __init fixup_nec_usb2(void)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000685{
686 struct device_node *nec;
687
688 for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) {
689 struct pci_controller *hose;
Jeremy Kerr018a3d12006-07-12 15:40:29 +1000690 u32 data;
691 const u32 *prop;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000692 u8 bus, devfn;
Paul Mackerras35499c02005-10-22 16:02:39 +1000693
Stephen Rothwelle2eb6392007-04-03 22:26:41 +1000694 prop = of_get_property(nec, "vendor-id", NULL);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000695 if (prop == NULL)
696 continue;
697 if (0x1033 != *prop)
698 continue;
Stephen Rothwelle2eb6392007-04-03 22:26:41 +1000699 prop = of_get_property(nec, "device-id", NULL);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000700 if (prop == NULL)
701 continue;
702 if (0x0035 != *prop)
703 continue;
Stephen Rothwelle2eb6392007-04-03 22:26:41 +1000704 prop = of_get_property(nec, "reg", NULL);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000705 if (prop == NULL)
706 continue;
707 devfn = (prop[0] >> 8) & 0xff;
708 bus = (prop[0] >> 16) & 0xff;
709 if (PCI_FUNC(devfn) != 0)
710 continue;
711 hose = pci_find_hose_for_OF_device(nec);
712 if (!hose)
713 continue;
714 early_read_config_dword(hose, bus, devfn, 0xe4, &data);
715 if (data & 1UL) {
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +1100716 printk("Found NEC PD720100A USB2 chip with disabled"
717 " EHCI, fixing up...\n");
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000718 data &= ~1UL;
719 early_write_config_dword(hose, bus, devfn, 0xe4, data);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000720 }
721 }
722}
723
Paul Mackerras35499c02005-10-22 16:02:39 +1000724static void __init setup_bandit(struct pci_controller *hose,
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +1100725 struct resource *addr)
Paul Mackerras35499c02005-10-22 16:02:39 +1000726{
727 hose->ops = &macrisc_pci_ops;
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +1100728 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
729 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
Paul Mackerras35499c02005-10-22 16:02:39 +1000730 init_bandit(hose);
731}
732
733static int __init setup_uninorth(struct pci_controller *hose,
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +1100734 struct resource *addr)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000735{
Paul Mackerras399fe2b2005-10-20 20:57:05 +1000736 pci_assign_all_buses = 1;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000737 has_uninorth = 1;
738 hose->ops = &macrisc_pci_ops;
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +1100739 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
740 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000741 /* We "know" that the bridge at f2000000 has the PCI slots. */
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +1100742 return addr->start == 0xf2000000;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000743}
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +1100744#endif /* CONFIG_PPC32 */
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000745
Paul Mackerras35499c02005-10-22 16:02:39 +1000746#ifdef CONFIG_PPC64
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000747static void __init setup_u3_agp(struct pci_controller* hose)
748{
749 /* On G5, we move AGP up to high bus number so we don't need
750 * to reassign bus numbers for HT. If we ever have P2P bridges
Paul Mackerras35499c02005-10-22 16:02:39 +1000751 * on AGP, we'll have to move pci_assign_all_busses to the
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000752 * pci_controller structure so we enable it for AGP and not for
753 * HT childs.
754 * We hard code the address because of the different size of
755 * the reg address cell, we shall fix that by killing struct
756 * reg_property and using some accessor functions instead
757 */
Paul Mackerras3c3f42d2005-10-10 22:58:41 +1000758 hose->first_busno = 0xf0;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000759 hose->last_busno = 0xff;
760 has_uninorth = 1;
761 hose->ops = &macrisc_pci_ops;
762 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
763 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000764 u3_agp = hose;
765}
766
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100767static void __init setup_u4_pcie(struct pci_controller* hose)
768{
769 /* We currently only implement the "non-atomic" config space, to
770 * be optimised later.
771 */
772 hose->ops = &u4_pcie_pci_ops;
773 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
774 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
775
776 /* The bus contains a bridge from root -> device, we need to
777 * make it visible on bus 0 so that we pick the right type
778 * of config cycles. If we didn't, we would have to force all
779 * config cycles to be type 1. So we override the "bus-range"
780 * property here
781 */
782 hose->first_busno = 0x00;
783 hose->last_busno = 0xff;
784 u4_pcie = hose;
785}
786
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000787static void __init setup_u3_ht(struct pci_controller* hose)
788{
789 struct device_node *np = (struct device_node *)hose->arch_data;
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100790 struct pci_controller *other = NULL;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000791 int i, cur;
792
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100793
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000794 hose->ops = &u3_ht_pci_ops;
795
796 /* We hard code the address because of the different size of
797 * the reg address cell, we shall fix that by killing struct
798 * reg_property and using some accessor functions instead
799 */
Al Virode125bf2006-02-01 05:18:43 -0500800 hose->cfg_data = ioremap(0xf2000000, 0x02000000);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000801
802 /*
Benjamin Herrenschmidtb5166cc2005-11-15 16:05:33 +1100803 * /ht node doesn't expose a "ranges" property, so we "remove"
804 * regions that have been allocated to AGP. So far, this version of
805 * the code doesn't assign any of the 0xfxxxxxxx "fine" memory regions
806 * to /ht. We need to fix that sooner or later by either parsing all
807 * child "ranges" properties or figuring out the U3 address space
808 * decoding logic and then read its configuration register (if any).
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000809 */
810 hose->io_base_phys = 0xf4000000;
Paul Mackerras35499c02005-10-22 16:02:39 +1000811 hose->pci_io_size = 0x00400000;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000812 hose->io_resource.name = np->full_name;
813 hose->io_resource.start = 0;
814 hose->io_resource.end = 0x003fffff;
815 hose->io_resource.flags = IORESOURCE_IO;
816 hose->pci_mem_offset = 0;
817 hose->first_busno = 0;
818 hose->last_busno = 0xef;
819 hose->mem_resources[0].name = np->full_name;
820 hose->mem_resources[0].start = 0x80000000;
821 hose->mem_resources[0].end = 0xefffffff;
822 hose->mem_resources[0].flags = IORESOURCE_MEM;
823
Paul Mackerras35499c02005-10-22 16:02:39 +1000824 u3_ht = hose;
825
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100826 if (u3_agp != NULL)
827 other = u3_agp;
828 else if (u4_pcie != NULL)
829 other = u4_pcie;
830
831 if (other == NULL) {
832 DBG("U3/4 has no AGP/PCIE, using full resource range\n");
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000833 return;
834 }
835
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100836 /* Fixup bus range vs. PCIE */
837 if (u4_pcie)
838 hose->last_busno = u4_pcie->first_busno - 1;
839
Benjamin Herrenschmidtb5166cc2005-11-15 16:05:33 +1100840 /* We "remove" the AGP resources from the resources allocated to HT,
841 * that is we create "holes". However, that code does assumptions
842 * that so far happen to be true (cross fingers...), typically that
843 * resources in the AGP node are properly ordered
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000844 */
845 cur = 0;
846 for (i=0; i<3; i++) {
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100847 struct resource *res = &other->mem_resources[i];
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000848 if (res->flags != IORESOURCE_MEM)
849 continue;
850 /* We don't care about "fine" resources */
851 if (res->start >= 0xf0000000)
852 continue;
Benjamin Herrenschmidtb5166cc2005-11-15 16:05:33 +1100853 /* Check if it's just a matter of "shrinking" us in one
854 * direction
855 */
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000856 if (hose->mem_resources[cur].start == res->start) {
857 DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n",
Benjamin Herrenschmidtb5166cc2005-11-15 16:05:33 +1100858 cur, hose->mem_resources[cur].start,
859 res->end + 1);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000860 hose->mem_resources[cur].start = res->end + 1;
861 continue;
862 }
863 if (hose->mem_resources[cur].end == res->end) {
864 DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n",
Benjamin Herrenschmidtb5166cc2005-11-15 16:05:33 +1100865 cur, hose->mem_resources[cur].end,
866 res->start - 1);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000867 hose->mem_resources[cur].end = res->start - 1;
868 continue;
869 }
870 /* No, it's not the case, we need a hole */
871 if (cur == 2) {
Benjamin Herrenschmidtb5166cc2005-11-15 16:05:33 +1100872 /* not enough resources for a hole, we drop part
873 * of the range
874 */
875 printk(KERN_WARNING "Running out of resources"
876 " for /ht host !\n");
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000877 hose->mem_resources[cur].end = res->start - 1;
878 continue;
Paul Mackerras35499c02005-10-22 16:02:39 +1000879 }
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000880 cur++;
Paul Mackerras3c3f42d2005-10-10 22:58:41 +1000881 DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n",
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000882 cur-1, res->start - 1, cur, res->end + 1);
883 hose->mem_resources[cur].name = np->full_name;
884 hose->mem_resources[cur].flags = IORESOURCE_MEM;
885 hose->mem_resources[cur].start = res->end + 1;
886 hose->mem_resources[cur].end = hose->mem_resources[cur-1].end;
887 hose->mem_resources[cur-1].end = res->start - 1;
888 }
889}
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +1100890#endif /* CONFIG_PPC64 */
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000891
892/*
893 * We assume that if we have a G3 powermac, we have one bridge called
894 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise,
895 * if we have one or more bandit or chaos bridges, we don't have a MPC106.
896 */
897static int __init add_bridge(struct device_node *dev)
898{
899 int len;
900 struct pci_controller *hose;
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +1100901 struct resource rsrc;
Paul Mackerras35499c02005-10-22 16:02:39 +1000902 char *disp_name;
Jeremy Kerr018a3d12006-07-12 15:40:29 +1000903 const int *bus_range;
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +1100904 int primary = 1, has_address = 0;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000905
906 DBG("Adding PCI host bridge %s\n", dev->full_name);
907
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +1100908 /* Fetch host bridge registers address */
909 has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
910
911 /* Get bus range if any */
Stephen Rothwelle2eb6392007-04-03 22:26:41 +1000912 bus_range = of_get_property(dev, "bus-range", &len);
Paul Mackerras35499c02005-10-22 16:02:39 +1000913 if (bus_range == NULL || len < 2 * sizeof(int)) {
Benjamin Herrenschmidtb5166cc2005-11-15 16:05:33 +1100914 printk(KERN_WARNING "Can't get bus-range for %s, assume"
915 " bus 0\n", dev->full_name);
Paul Mackerras35499c02005-10-22 16:02:39 +1000916 }
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000917
Benjamin Herrenschmidtb5166cc2005-11-15 16:05:33 +1100918 /* XXX Different prototypes, to be merged */
919#ifdef CONFIG_PPC64
920 hose = pcibios_alloc_controller(dev);
921#else
Paul Mackerras35499c02005-10-22 16:02:39 +1000922 hose = pcibios_alloc_controller();
Benjamin Herrenschmidtb5166cc2005-11-15 16:05:33 +1100923#endif
Paul Mackerras35499c02005-10-22 16:02:39 +1000924 if (!hose)
925 return -ENOMEM;
926 hose->arch_data = dev;
927 hose->first_busno = bus_range ? bus_range[0] : 0;
928 hose->last_busno = bus_range ? bus_range[1] : 0xff;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000929
930 disp_name = NULL;
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +1100931
932 /* 64 bits only bridges */
Benjamin Herrenschmidtb5166cc2005-11-15 16:05:33 +1100933#ifdef CONFIG_PPC64
Paul Mackerras35499c02005-10-22 16:02:39 +1000934 if (device_is_compatible(dev, "u3-agp")) {
935 setup_u3_agp(hose);
936 disp_name = "U3-AGP";
937 primary = 0;
938 } else if (device_is_compatible(dev, "u3-ht")) {
939 setup_u3_ht(hose);
940 disp_name = "U3-HT";
941 primary = 1;
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100942 } else if (device_is_compatible(dev, "u4-pcie")) {
943 setup_u4_pcie(hose);
944 disp_name = "U4-PCIE";
945 primary = 0;
Paul Mackerras35499c02005-10-22 16:02:39 +1000946 }
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100947 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number:"
948 " %d->%d\n", disp_name, hose->first_busno, hose->last_busno);
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +1100949#endif /* CONFIG_PPC64 */
950
951 /* 32 bits only bridges */
952#ifdef CONFIG_PPC32
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000953 if (device_is_compatible(dev, "uni-north")) {
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +1100954 primary = setup_uninorth(hose, &rsrc);
Paul Mackerras35499c02005-10-22 16:02:39 +1000955 disp_name = "UniNorth";
Paul Mackerras3c3f42d2005-10-10 22:58:41 +1000956 } else if (strcmp(dev->name, "pci") == 0) {
Paul Mackerras35499c02005-10-22 16:02:39 +1000957 /* XXX assume this is a mpc106 (grackle) */
958 setup_grackle(hose);
959 disp_name = "Grackle (MPC106)";
960 } else if (strcmp(dev->name, "bandit") == 0) {
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +1100961 setup_bandit(hose, &rsrc);
Paul Mackerras35499c02005-10-22 16:02:39 +1000962 disp_name = "Bandit";
963 } else if (strcmp(dev->name, "chaos") == 0) {
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +1100964 setup_chaos(hose, &rsrc);
Paul Mackerras35499c02005-10-22 16:02:39 +1000965 disp_name = "Chaos";
966 primary = 0;
967 }
Greg Kroah-Hartman685143ac2006-06-12 15:18:31 -0700968 printk(KERN_INFO "Found %s PCI host bridge at 0x%016llx. "
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +1100969 "Firmware bus number: %d->%d\n",
Greg Kroah-Hartman685143ac2006-06-12 15:18:31 -0700970 disp_name, (unsigned long long)rsrc.start, hose->first_busno,
971 hose->last_busno);
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +1100972#endif /* CONFIG_PPC32 */
973
Paul Mackerras35499c02005-10-22 16:02:39 +1000974 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
975 hose, hose->cfg_addr, hose->cfg_data);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000976
Paul Mackerras35499c02005-10-22 16:02:39 +1000977 /* Interpret the "ranges" property */
978 /* This also maps the I/O region and sets isa_io/mem_base */
979 pci_process_bridge_OF_ranges(hose, dev, primary);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000980
Paul Mackerras35499c02005-10-22 16:02:39 +1000981 /* Fixup "bus-range" OF property */
982 fixup_bus_range(dev);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000983
984 return 0;
985}
986
Benjamin Herrenschmidtf90bb152006-11-11 17:24:51 +1100987void __devinit pmac_pci_irq_fixup(struct pci_dev *dev)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000988{
Benjamin Herrenschmidt6e99e452006-07-10 04:44:42 -0700989#ifdef CONFIG_PPC32
Benjamin Herrenschmidtf90bb152006-11-11 17:24:51 +1100990 /* Fixup interrupt for the modem/ethernet combo controller.
991 * on machines with a second ohare chip.
992 * The number in the device tree (27) is bogus (correct for
993 * the ethernet-only board but not the combo ethernet/modem
994 * board). The real interrupt is 28 on the second controller
995 * -> 28+32 = 60.
996 */
997 if (has_second_ohare &&
998 dev->vendor == PCI_VENDOR_ID_DEC &&
999 dev->device == PCI_DEVICE_ID_DEC_TULIP_PLUS) {
1000 dev->irq = irq_create_mapping(NULL, 60);
1001 set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW);
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001002 }
Benjamin Herrenschmidtf90bb152006-11-11 17:24:51 +11001003#endif /* CONFIG_PPC32 */
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001004}
1005
Paul Mackerras35499c02005-10-22 16:02:39 +10001006#ifdef CONFIG_PPC64
1007static void __init pmac_fixup_phb_resources(void)
1008{
1009 struct pci_controller *hose, *tmp;
1010
1011 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1012 printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n",
1013 hose->global_number,
1014 hose->io_resource.start, hose->io_resource.end);
1015 }
1016}
1017#endif
1018
1019void __init pmac_pci_init(void)
Paul Mackerras3c3f42d2005-10-10 22:58:41 +10001020{
1021 struct device_node *np, *root;
1022 struct device_node *ht = NULL;
1023
1024 root = of_find_node_by_path("/");
1025 if (root == NULL) {
Paul Mackerras35499c02005-10-22 16:02:39 +10001026 printk(KERN_CRIT "pmac_pci_init: can't find root "
1027 "of device tree\n");
Paul Mackerras3c3f42d2005-10-10 22:58:41 +10001028 return;
1029 }
1030 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
1031 if (np->name == NULL)
1032 continue;
1033 if (strcmp(np->name, "bandit") == 0
1034 || strcmp(np->name, "chaos") == 0
1035 || strcmp(np->name, "pci") == 0) {
1036 if (add_bridge(np) == 0)
1037 of_node_get(np);
1038 }
1039 if (strcmp(np->name, "ht") == 0) {
1040 of_node_get(np);
1041 ht = np;
1042 }
1043 }
1044 of_node_put(root);
1045
Paul Mackerras35499c02005-10-22 16:02:39 +10001046#ifdef CONFIG_PPC64
Paul Mackerras3c3f42d2005-10-10 22:58:41 +10001047 /* Probe HT last as it relies on the agp resources to be already
1048 * setup
1049 */
1050 if (ht && add_bridge(ht) != 0)
1051 of_node_put(ht);
1052
Paul Mackerras35499c02005-10-22 16:02:39 +10001053 /*
1054 * We need to call pci_setup_phb_io for the HT bridge first
1055 * so it gets the I/O port numbers starting at 0, and we
1056 * need to call it for the AGP bridge after that so it gets
1057 * small positive I/O port numbers.
1058 */
1059 if (u3_ht)
1060 pci_setup_phb_io(u3_ht, 1);
1061 if (u3_agp)
1062 pci_setup_phb_io(u3_agp, 0);
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +11001063 if (u4_pcie)
1064 pci_setup_phb_io(u4_pcie, 0);
Paul Mackerras35499c02005-10-22 16:02:39 +10001065
1066 /*
1067 * On ppc64, fixup the IO resources on our host bridges as
1068 * the common code does it only for children of the host bridges
1069 */
1070 pmac_fixup_phb_resources();
1071
1072 /* Setup the linkage between OF nodes and PHBs */
1073 pci_devs_phb_init();
1074
1075 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
1076 * assume there is no P2P bridge on the AGP bus, which should be a
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +11001077 * safe assumptions for now. We should do something better in the
1078 * future though
Paul Mackerras35499c02005-10-22 16:02:39 +10001079 */
1080 if (u3_agp) {
1081 struct device_node *np = u3_agp->arch_data;
1082 PCI_DN(np)->busno = 0xf0;
1083 for (np = np->child; np; np = np->sibling)
1084 PCI_DN(np)->busno = 0xf0;
1085 }
Paul Mackerras35499c02005-10-22 16:02:39 +10001086 /* pmac_check_ht_link(); */
1087
1088 /* Tell pci.c to not use the common resource allocation mechanism */
1089 pci_probe_only = 1;
1090
Paul Mackerras35499c02005-10-22 16:02:39 +10001091#else /* CONFIG_PPC64 */
Paul Mackerras3c3f42d2005-10-10 22:58:41 +10001092 init_p2pbridge();
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001093 init_second_ohare();
Paul Mackerras3c3f42d2005-10-10 22:58:41 +10001094 fixup_nec_usb2();
Paul Mackerras35499c02005-10-22 16:02:39 +10001095
Paul Mackerras3c3f42d2005-10-10 22:58:41 +10001096 /* We are still having some issues with the Xserve G4, enabling
1097 * some offset between bus number and domains for now when we
1098 * assign all busses should help for now
1099 */
Paul Mackerras399fe2b2005-10-20 20:57:05 +10001100 if (pci_assign_all_buses)
Paul Mackerras3c3f42d2005-10-10 22:58:41 +10001101 pcibios_assign_bus_offset = 0x10;
Paul Mackerras35499c02005-10-22 16:02:39 +10001102#endif
Paul Mackerras3c3f42d2005-10-10 22:58:41 +10001103}
1104
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001105int
1106pmac_pci_enable_device_hook(struct pci_dev *dev, int initial)
1107{
1108 struct device_node* node;
1109 int updatecfg = 0;
1110 int uninorth_child;
1111
1112 node = pci_device_to_OF_node(dev);
1113
1114 /* We don't want to enable USB controllers absent from the OF tree
1115 * (iBook second controller)
1116 */
1117 if (dev->vendor == PCI_VENDOR_ID_APPLE
Jean Delvarec67808e2006-04-09 20:07:35 +02001118 && dev->class == PCI_CLASS_SERIAL_USB_OHCI
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001119 && !node) {
1120 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n",
1121 pci_name(dev));
1122 return -EINVAL;
1123 }
1124
1125 if (!node)
1126 return 0;
1127
1128 uninorth_child = node->parent &&
1129 device_is_compatible(node->parent, "uni-north");
Paul Mackerras35499c02005-10-22 16:02:39 +10001130
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001131 /* Firewire & GMAC were disabled after PCI probe, the driver is
1132 * claiming them, we must re-enable them now.
1133 */
1134 if (uninorth_child && !strcmp(node->name, "firewire") &&
1135 (device_is_compatible(node, "pci106b,18") ||
1136 device_is_compatible(node, "pci106b,30") ||
1137 device_is_compatible(node, "pci11c1,5811"))) {
1138 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1);
1139 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1);
1140 updatecfg = 1;
1141 }
1142 if (uninorth_child && !strcmp(node->name, "ethernet") &&
1143 device_is_compatible(node, "gmac")) {
1144 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1);
1145 updatecfg = 1;
1146 }
1147
1148 if (updatecfg) {
1149 u16 cmd;
Paul Mackerras35499c02005-10-22 16:02:39 +10001150
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001151 /*
1152 * Make sure PCI is correctly configured
1153 *
1154 * We use old pci_bios versions of the function since, by
1155 * default, gmac is not powered up, and so will be absent
1156 * from the kernel initial PCI lookup.
1157 *
1158 * Should be replaced by 2.4 new PCI mechanisms and really
1159 * register the device.
1160 */
1161 pci_read_config_word(dev, PCI_COMMAND, &cmd);
Paul Mackerras35499c02005-10-22 16:02:39 +10001162 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
1163 | PCI_COMMAND_INVALIDATE;
1164 pci_write_config_word(dev, PCI_COMMAND, cmd);
1165 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16);
1166 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
1167 L1_CACHE_BYTES >> 2);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001168 }
1169
1170 return 0;
1171}
1172
1173/* We power down some devices after they have been probed. They'll
1174 * be powered back on later on
1175 */
Paul Mackerras35499c02005-10-22 16:02:39 +10001176void __init pmac_pcibios_after_init(void)
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001177{
1178 struct device_node* nd;
1179
1180#ifdef CONFIG_BLK_DEV_IDE
1181 struct pci_dev *dev = NULL;
1182
1183 /* OF fails to initialize IDE controllers on macs
1184 * (and maybe other machines)
1185 *
1186 * Ideally, this should be moved to the IDE layer, but we need
1187 * to check specifically with Andre Hedrick how to do it cleanly
1188 * since the common IDE code seem to care about the fact that the
1189 * BIOS may have disabled a controller.
1190 *
1191 * -- BenH
1192 */
1193 for_each_pci_dev(dev) {
Benjamin Herrenschmidtb5d99e62007-03-07 11:27:55 +01001194 if ((dev->class >> 16) != PCI_BASE_CLASS_STORAGE)
1195 continue;
1196 if (pci_enable_device(dev))
1197 printk(KERN_WARNING
1198 "pci: Failed to enable %s\n", pci_name(dev));
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001199 }
1200#endif /* CONFIG_BLK_DEV_IDE */
1201
1202 nd = find_devices("firewire");
1203 while (nd) {
1204 if (nd->parent && (device_is_compatible(nd, "pci106b,18") ||
1205 device_is_compatible(nd, "pci106b,30") ||
1206 device_is_compatible(nd, "pci11c1,5811"))
1207 && device_is_compatible(nd->parent, "uni-north")) {
1208 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0);
1209 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0);
1210 }
1211 nd = nd->next;
1212 }
1213 nd = find_devices("ethernet");
1214 while (nd) {
1215 if (nd->parent && device_is_compatible(nd, "gmac")
1216 && device_is_compatible(nd->parent, "uni-north"))
1217 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0);
1218 nd = nd->next;
1219 }
1220}
1221
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001222#ifdef CONFIG_PPC32
1223void pmac_pci_fixup_cardbus(struct pci_dev* dev)
1224{
Benjamin Herrenschmidte8222502006-03-28 23:15:54 +11001225 if (!machine_is(powermac))
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001226 return;
1227 /*
1228 * Fix the interrupt routing on the various cardbus bridges
1229 * used on powerbooks
1230 */
1231 if (dev->vendor != PCI_VENDOR_ID_TI)
1232 return;
1233 if (dev->device == PCI_DEVICE_ID_TI_1130 ||
1234 dev->device == PCI_DEVICE_ID_TI_1131) {
1235 u8 val;
Paul Mackerras35499c02005-10-22 16:02:39 +10001236 /* Enable PCI interrupt */
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001237 if (pci_read_config_byte(dev, 0x91, &val) == 0)
1238 pci_write_config_byte(dev, 0x91, val | 0x30);
1239 /* Disable ISA interrupt mode */
1240 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1241 pci_write_config_byte(dev, 0x92, val & ~0x06);
1242 }
1243 if (dev->device == PCI_DEVICE_ID_TI_1210 ||
1244 dev->device == PCI_DEVICE_ID_TI_1211 ||
1245 dev->device == PCI_DEVICE_ID_TI_1410 ||
1246 dev->device == PCI_DEVICE_ID_TI_1510) {
1247 u8 val;
1248 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA
1249 signal out the MFUNC0 pin */
1250 if (pci_read_config_byte(dev, 0x8c, &val) == 0)
1251 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2);
1252 /* Disable ISA interrupt mode */
1253 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1254 pci_write_config_byte(dev, 0x92, val & ~0x06);
1255 }
1256}
1257
1258DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus);
1259
1260void pmac_pci_fixup_pciata(struct pci_dev* dev)
1261{
1262 u8 progif = 0;
1263
1264 /*
1265 * On PowerMacs, we try to switch any PCI ATA controller to
1266 * fully native mode
1267 */
Benjamin Herrenschmidte8222502006-03-28 23:15:54 +11001268 if (!machine_is(powermac))
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001269 return;
Benjamin Herrenschmidte8222502006-03-28 23:15:54 +11001270
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001271 /* Some controllers don't have the class IDE */
1272 if (dev->vendor == PCI_VENDOR_ID_PROMISE)
1273 switch(dev->device) {
1274 case PCI_DEVICE_ID_PROMISE_20246:
1275 case PCI_DEVICE_ID_PROMISE_20262:
1276 case PCI_DEVICE_ID_PROMISE_20263:
1277 case PCI_DEVICE_ID_PROMISE_20265:
1278 case PCI_DEVICE_ID_PROMISE_20267:
1279 case PCI_DEVICE_ID_PROMISE_20268:
1280 case PCI_DEVICE_ID_PROMISE_20269:
1281 case PCI_DEVICE_ID_PROMISE_20270:
1282 case PCI_DEVICE_ID_PROMISE_20271:
1283 case PCI_DEVICE_ID_PROMISE_20275:
1284 case PCI_DEVICE_ID_PROMISE_20276:
1285 case PCI_DEVICE_ID_PROMISE_20277:
1286 goto good;
1287 }
1288 /* Others, check PCI class */
1289 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
1290 return;
1291 good:
1292 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1293 if ((progif & 5) != 5) {
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +11001294 printk(KERN_INFO "Forcing PCI IDE into native mode: %s\n",
1295 pci_name(dev));
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001296 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
1297 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
1298 (progif & 5) != 5)
1299 printk(KERN_ERR "Rewrite of PROGIF failed !\n");
1300 }
1301}
1302DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata);
1303#endif
1304
1305/*
1306 * Disable second function on K2-SATA, it's broken
1307 * and disable IO BARs on first one
1308 */
1309static void fixup_k2_sata(struct pci_dev* dev)
1310{
1311 int i;
1312 u16 cmd;
1313
1314 if (PCI_FUNC(dev->devfn) > 0) {
1315 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1316 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1317 pci_write_config_word(dev, PCI_COMMAND, cmd);
1318 for (i = 0; i < 6; i++) {
1319 dev->resource[i].start = dev->resource[i].end = 0;
1320 dev->resource[i].flags = 0;
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +11001321 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i,
1322 0);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001323 }
1324 } else {
1325 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1326 cmd &= ~PCI_COMMAND_IO;
1327 pci_write_config_word(dev, PCI_COMMAND, cmd);
1328 for (i = 0; i < 5; i++) {
1329 dev->resource[i].start = dev->resource[i].end = 0;
1330 dev->resource[i].flags = 0;
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +11001331 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i,
1332 0);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001333 }
1334 }
1335}
1336DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata);
1337