Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Support for Marvell's Cryptographic Engine and Security Accelerator (CESA) |
| 3 | * that can be found on the following platform: Orion, Kirkwood, Armada. This |
| 4 | * driver supports the TDMA engine on platforms on which it is available. |
| 5 | * |
| 6 | * Author: Boris Brezillon <boris.brezillon@free-electrons.com> |
| 7 | * Author: Arnaud Ebalard <arno@natisbad.org> |
| 8 | * |
| 9 | * This work is based on an initial version written by |
| 10 | * Sebastian Andrzej Siewior < sebastian at breakpoint dot cc > |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify it |
| 13 | * under the terms of the GNU General Public License version 2 as published |
| 14 | * by the Free Software Foundation. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/delay.h> |
| 18 | #include <linux/genalloc.h> |
| 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/io.h> |
| 21 | #include <linux/kthread.h> |
| 22 | #include <linux/mbus.h> |
| 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/scatterlist.h> |
| 25 | #include <linux/slab.h> |
| 26 | #include <linux/module.h> |
| 27 | #include <linux/clk.h> |
| 28 | #include <linux/of.h> |
| 29 | #include <linux/of_platform.h> |
| 30 | #include <linux/of_irq.h> |
| 31 | |
| 32 | #include "cesa.h" |
| 33 | |
Romain Perier | e26df73 | 2016-06-21 10:08:31 +0200 | [diff] [blame] | 34 | /* Limit of the crypto queue before reaching the backlog */ |
| 35 | #define CESA_CRYPTO_DEFAULT_MAX_QLEN 50 |
| 36 | |
Boris BREZILLON | 64c55d4 | 2015-06-18 15:46:27 +0200 | [diff] [blame] | 37 | static int allhwsupport = !IS_ENABLED(CONFIG_CRYPTO_DEV_MV_CESA); |
| 38 | module_param_named(allhwsupport, allhwsupport, int, 0444); |
| 39 | MODULE_PARM_DESC(allhwsupport, "Enable support for all hardware (even it if overlaps with the mv_cesa driver)"); |
| 40 | |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 41 | struct mv_cesa_dev *cesa_dev; |
| 42 | |
Romain Perier | bf8f91e | 2016-06-21 10:08:38 +0200 | [diff] [blame^] | 43 | static void mv_cesa_dequeue_req_locked(struct mv_cesa_engine *engine) |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 44 | { |
| 45 | struct crypto_async_request *req, *backlog; |
| 46 | struct mv_cesa_ctx *ctx; |
| 47 | |
Romain Perier | bf8f91e | 2016-06-21 10:08:38 +0200 | [diff] [blame^] | 48 | backlog = crypto_get_backlog(&engine->queue); |
| 49 | req = crypto_dequeue_request(&engine->queue); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 50 | engine->req = req; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 51 | |
| 52 | if (!req) |
| 53 | return; |
| 54 | |
| 55 | if (backlog) |
| 56 | backlog->complete(backlog, -EINPROGRESS); |
| 57 | |
| 58 | ctx = crypto_tfm_ctx(req->tfm); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 59 | ctx->ops->step(req); |
| 60 | } |
| 61 | |
| 62 | static irqreturn_t mv_cesa_int(int irq, void *priv) |
| 63 | { |
| 64 | struct mv_cesa_engine *engine = priv; |
| 65 | struct crypto_async_request *req; |
| 66 | struct mv_cesa_ctx *ctx; |
| 67 | u32 status, mask; |
| 68 | irqreturn_t ret = IRQ_NONE; |
| 69 | |
| 70 | while (true) { |
| 71 | int res; |
| 72 | |
| 73 | mask = mv_cesa_get_int_mask(engine); |
| 74 | status = readl(engine->regs + CESA_SA_INT_STATUS); |
| 75 | |
| 76 | if (!(status & mask)) |
| 77 | break; |
| 78 | |
| 79 | /* |
| 80 | * TODO: avoid clearing the FPGA_INT_STATUS if this not |
| 81 | * relevant on some platforms. |
| 82 | */ |
| 83 | writel(~status, engine->regs + CESA_SA_FPGA_INT_STATUS); |
| 84 | writel(~status, engine->regs + CESA_SA_INT_STATUS); |
| 85 | |
| 86 | ret = IRQ_HANDLED; |
| 87 | spin_lock_bh(&engine->lock); |
| 88 | req = engine->req; |
| 89 | spin_unlock_bh(&engine->lock); |
| 90 | if (req) { |
| 91 | ctx = crypto_tfm_ctx(req->tfm); |
| 92 | res = ctx->ops->process(req, status & mask); |
| 93 | if (res != -EINPROGRESS) { |
| 94 | spin_lock_bh(&engine->lock); |
| 95 | engine->req = NULL; |
Romain Perier | bf8f91e | 2016-06-21 10:08:38 +0200 | [diff] [blame^] | 96 | mv_cesa_dequeue_req_locked(engine); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 97 | spin_unlock_bh(&engine->lock); |
Romain Perier | 1bf6682 | 2016-06-21 10:08:36 +0200 | [diff] [blame] | 98 | ctx->ops->complete(req); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 99 | ctx->ops->cleanup(req); |
| 100 | local_bh_disable(); |
| 101 | req->complete(req, res); |
| 102 | local_bh_enable(); |
| 103 | } else { |
| 104 | ctx->ops->step(req); |
| 105 | } |
| 106 | } |
| 107 | } |
| 108 | |
| 109 | return ret; |
| 110 | } |
| 111 | |
Romain Perier | 53da740 | 2016-06-21 10:08:35 +0200 | [diff] [blame] | 112 | int mv_cesa_queue_req(struct crypto_async_request *req, |
| 113 | struct mv_cesa_req *creq) |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 114 | { |
| 115 | int ret; |
Romain Perier | bf8f91e | 2016-06-21 10:08:38 +0200 | [diff] [blame^] | 116 | struct mv_cesa_engine *engine = creq->engine; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 117 | |
Romain Perier | bf8f91e | 2016-06-21 10:08:38 +0200 | [diff] [blame^] | 118 | spin_lock_bh(&engine->lock); |
| 119 | ret = crypto_enqueue_request(&engine->queue, req); |
| 120 | spin_unlock_bh(&engine->lock); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 121 | |
| 122 | if (ret != -EINPROGRESS) |
| 123 | return ret; |
| 124 | |
Romain Perier | bf8f91e | 2016-06-21 10:08:38 +0200 | [diff] [blame^] | 125 | spin_lock_bh(&engine->lock); |
| 126 | if (!engine->req) |
| 127 | mv_cesa_dequeue_req_locked(engine); |
| 128 | spin_unlock_bh(&engine->lock); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 129 | |
| 130 | return -EINPROGRESS; |
| 131 | } |
| 132 | |
| 133 | static int mv_cesa_add_algs(struct mv_cesa_dev *cesa) |
| 134 | { |
| 135 | int ret; |
| 136 | int i, j; |
| 137 | |
| 138 | for (i = 0; i < cesa->caps->ncipher_algs; i++) { |
| 139 | ret = crypto_register_alg(cesa->caps->cipher_algs[i]); |
| 140 | if (ret) |
| 141 | goto err_unregister_crypto; |
| 142 | } |
| 143 | |
| 144 | for (i = 0; i < cesa->caps->nahash_algs; i++) { |
| 145 | ret = crypto_register_ahash(cesa->caps->ahash_algs[i]); |
| 146 | if (ret) |
| 147 | goto err_unregister_ahash; |
| 148 | } |
| 149 | |
| 150 | return 0; |
| 151 | |
| 152 | err_unregister_ahash: |
| 153 | for (j = 0; j < i; j++) |
| 154 | crypto_unregister_ahash(cesa->caps->ahash_algs[j]); |
| 155 | i = cesa->caps->ncipher_algs; |
| 156 | |
| 157 | err_unregister_crypto: |
| 158 | for (j = 0; j < i; j++) |
| 159 | crypto_unregister_alg(cesa->caps->cipher_algs[j]); |
| 160 | |
| 161 | return ret; |
| 162 | } |
| 163 | |
| 164 | static void mv_cesa_remove_algs(struct mv_cesa_dev *cesa) |
| 165 | { |
| 166 | int i; |
| 167 | |
| 168 | for (i = 0; i < cesa->caps->nahash_algs; i++) |
| 169 | crypto_unregister_ahash(cesa->caps->ahash_algs[i]); |
| 170 | |
| 171 | for (i = 0; i < cesa->caps->ncipher_algs; i++) |
| 172 | crypto_unregister_alg(cesa->caps->cipher_algs[i]); |
| 173 | } |
| 174 | |
Boris BREZILLON | 0bf6948 | 2015-06-18 15:46:28 +0200 | [diff] [blame] | 175 | static struct crypto_alg *orion_cipher_algs[] = { |
| 176 | &mv_cesa_ecb_des_alg, |
| 177 | &mv_cesa_cbc_des_alg, |
| 178 | &mv_cesa_ecb_des3_ede_alg, |
| 179 | &mv_cesa_cbc_des3_ede_alg, |
| 180 | &mv_cesa_ecb_aes_alg, |
| 181 | &mv_cesa_cbc_aes_alg, |
| 182 | }; |
| 183 | |
| 184 | static struct ahash_alg *orion_ahash_algs[] = { |
| 185 | &mv_md5_alg, |
| 186 | &mv_sha1_alg, |
| 187 | &mv_ahmac_md5_alg, |
| 188 | &mv_ahmac_sha1_alg, |
| 189 | }; |
| 190 | |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 191 | static struct crypto_alg *armada_370_cipher_algs[] = { |
Boris BREZILLON | 7b3aaaa | 2015-06-18 15:46:22 +0200 | [diff] [blame] | 192 | &mv_cesa_ecb_des_alg, |
| 193 | &mv_cesa_cbc_des_alg, |
Arnaud Ebalard | 4ada483 | 2015-06-18 15:46:23 +0200 | [diff] [blame] | 194 | &mv_cesa_ecb_des3_ede_alg, |
| 195 | &mv_cesa_cbc_des3_ede_alg, |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 196 | &mv_cesa_ecb_aes_alg, |
| 197 | &mv_cesa_cbc_aes_alg, |
| 198 | }; |
| 199 | |
| 200 | static struct ahash_alg *armada_370_ahash_algs[] = { |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 201 | &mv_md5_alg, |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 202 | &mv_sha1_alg, |
Arnaud Ebalard | f85a762 | 2015-06-18 15:46:25 +0200 | [diff] [blame] | 203 | &mv_sha256_alg, |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 204 | &mv_ahmac_md5_alg, |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 205 | &mv_ahmac_sha1_alg, |
Arnaud Ebalard | f85a762 | 2015-06-18 15:46:25 +0200 | [diff] [blame] | 206 | &mv_ahmac_sha256_alg, |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 207 | }; |
| 208 | |
Boris BREZILLON | 0bf6948 | 2015-06-18 15:46:28 +0200 | [diff] [blame] | 209 | static const struct mv_cesa_caps orion_caps = { |
| 210 | .nengines = 1, |
| 211 | .cipher_algs = orion_cipher_algs, |
| 212 | .ncipher_algs = ARRAY_SIZE(orion_cipher_algs), |
| 213 | .ahash_algs = orion_ahash_algs, |
| 214 | .nahash_algs = ARRAY_SIZE(orion_ahash_algs), |
| 215 | .has_tdma = false, |
| 216 | }; |
| 217 | |
Arnaud Ebalard | 7240425 | 2015-06-18 15:46:29 +0200 | [diff] [blame] | 218 | static const struct mv_cesa_caps kirkwood_caps = { |
| 219 | .nengines = 1, |
| 220 | .cipher_algs = orion_cipher_algs, |
| 221 | .ncipher_algs = ARRAY_SIZE(orion_cipher_algs), |
| 222 | .ahash_algs = orion_ahash_algs, |
| 223 | .nahash_algs = ARRAY_SIZE(orion_ahash_algs), |
| 224 | .has_tdma = true, |
| 225 | }; |
| 226 | |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 227 | static const struct mv_cesa_caps armada_370_caps = { |
| 228 | .nengines = 1, |
| 229 | .cipher_algs = armada_370_cipher_algs, |
| 230 | .ncipher_algs = ARRAY_SIZE(armada_370_cipher_algs), |
| 231 | .ahash_algs = armada_370_ahash_algs, |
| 232 | .nahash_algs = ARRAY_SIZE(armada_370_ahash_algs), |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 233 | .has_tdma = true, |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 234 | }; |
| 235 | |
Boris BREZILLON | 898c9d5 | 2015-06-18 15:46:26 +0200 | [diff] [blame] | 236 | static const struct mv_cesa_caps armada_xp_caps = { |
| 237 | .nengines = 2, |
| 238 | .cipher_algs = armada_370_cipher_algs, |
| 239 | .ncipher_algs = ARRAY_SIZE(armada_370_cipher_algs), |
| 240 | .ahash_algs = armada_370_ahash_algs, |
| 241 | .nahash_algs = ARRAY_SIZE(armada_370_ahash_algs), |
| 242 | .has_tdma = true, |
| 243 | }; |
| 244 | |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 245 | static const struct of_device_id mv_cesa_of_match_table[] = { |
Boris BREZILLON | 0bf6948 | 2015-06-18 15:46:28 +0200 | [diff] [blame] | 246 | { .compatible = "marvell,orion-crypto", .data = &orion_caps }, |
Arnaud Ebalard | 7240425 | 2015-06-18 15:46:29 +0200 | [diff] [blame] | 247 | { .compatible = "marvell,kirkwood-crypto", .data = &kirkwood_caps }, |
| 248 | { .compatible = "marvell,dove-crypto", .data = &kirkwood_caps }, |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 249 | { .compatible = "marvell,armada-370-crypto", .data = &armada_370_caps }, |
Boris BREZILLON | 898c9d5 | 2015-06-18 15:46:26 +0200 | [diff] [blame] | 250 | { .compatible = "marvell,armada-xp-crypto", .data = &armada_xp_caps }, |
| 251 | { .compatible = "marvell,armada-375-crypto", .data = &armada_xp_caps }, |
| 252 | { .compatible = "marvell,armada-38x-crypto", .data = &armada_xp_caps }, |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 253 | {} |
| 254 | }; |
| 255 | MODULE_DEVICE_TABLE(of, mv_cesa_of_match_table); |
| 256 | |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 257 | static void |
| 258 | mv_cesa_conf_mbus_windows(struct mv_cesa_engine *engine, |
| 259 | const struct mbus_dram_target_info *dram) |
| 260 | { |
| 261 | void __iomem *iobase = engine->regs; |
| 262 | int i; |
| 263 | |
| 264 | for (i = 0; i < 4; i++) { |
| 265 | writel(0, iobase + CESA_TDMA_WINDOW_CTRL(i)); |
| 266 | writel(0, iobase + CESA_TDMA_WINDOW_BASE(i)); |
| 267 | } |
| 268 | |
| 269 | for (i = 0; i < dram->num_cs; i++) { |
| 270 | const struct mbus_dram_window *cs = dram->cs + i; |
| 271 | |
| 272 | writel(((cs->size - 1) & 0xffff0000) | |
| 273 | (cs->mbus_attr << 8) | |
| 274 | (dram->mbus_dram_target_id << 4) | 1, |
| 275 | iobase + CESA_TDMA_WINDOW_CTRL(i)); |
| 276 | writel(cs->base, iobase + CESA_TDMA_WINDOW_BASE(i)); |
| 277 | } |
| 278 | } |
| 279 | |
| 280 | static int mv_cesa_dev_dma_init(struct mv_cesa_dev *cesa) |
| 281 | { |
| 282 | struct device *dev = cesa->dev; |
| 283 | struct mv_cesa_dev_dma *dma; |
| 284 | |
| 285 | if (!cesa->caps->has_tdma) |
| 286 | return 0; |
| 287 | |
| 288 | dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); |
| 289 | if (!dma) |
| 290 | return -ENOMEM; |
| 291 | |
| 292 | dma->tdma_desc_pool = dmam_pool_create("tdma_desc", dev, |
| 293 | sizeof(struct mv_cesa_tdma_desc), |
| 294 | 16, 0); |
| 295 | if (!dma->tdma_desc_pool) |
| 296 | return -ENOMEM; |
| 297 | |
| 298 | dma->op_pool = dmam_pool_create("cesa_op", dev, |
| 299 | sizeof(struct mv_cesa_op_ctx), 16, 0); |
| 300 | if (!dma->op_pool) |
| 301 | return -ENOMEM; |
| 302 | |
| 303 | dma->cache_pool = dmam_pool_create("cesa_cache", dev, |
| 304 | CESA_MAX_HASH_BLOCK_SIZE, 1, 0); |
| 305 | if (!dma->cache_pool) |
| 306 | return -ENOMEM; |
| 307 | |
| 308 | dma->padding_pool = dmam_pool_create("cesa_padding", dev, 72, 1, 0); |
Boris BREZILLON | 8a3978a | 2016-02-05 17:45:48 +0100 | [diff] [blame] | 309 | if (!dma->padding_pool) |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 310 | return -ENOMEM; |
| 311 | |
Romain Perier | bac8e80 | 2016-06-21 10:08:34 +0200 | [diff] [blame] | 312 | dma->iv_pool = dmam_pool_create("cesa_iv", dev, 16, 1, 0); |
| 313 | if (!dma->iv_pool) |
| 314 | return -ENOMEM; |
| 315 | |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 316 | cesa->dma = dma; |
| 317 | |
| 318 | return 0; |
| 319 | } |
| 320 | |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 321 | static int mv_cesa_get_sram(struct platform_device *pdev, int idx) |
| 322 | { |
| 323 | struct mv_cesa_dev *cesa = platform_get_drvdata(pdev); |
| 324 | struct mv_cesa_engine *engine = &cesa->engines[idx]; |
| 325 | const char *res_name = "sram"; |
| 326 | struct resource *res; |
| 327 | |
Vladimir Zapolskiy | abdd4a7 | 2015-06-30 15:00:07 -0700 | [diff] [blame] | 328 | engine->pool = of_gen_pool_get(cesa->dev->of_node, |
| 329 | "marvell,crypto-srams", idx); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 330 | if (engine->pool) { |
| 331 | engine->sram = gen_pool_dma_alloc(engine->pool, |
| 332 | cesa->sram_size, |
| 333 | &engine->sram_dma); |
| 334 | if (engine->sram) |
| 335 | return 0; |
| 336 | |
| 337 | engine->pool = NULL; |
| 338 | return -ENOMEM; |
| 339 | } |
| 340 | |
| 341 | if (cesa->caps->nengines > 1) { |
| 342 | if (!idx) |
| 343 | res_name = "sram0"; |
| 344 | else |
| 345 | res_name = "sram1"; |
| 346 | } |
| 347 | |
| 348 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 349 | res_name); |
| 350 | if (!res || resource_size(res) < cesa->sram_size) |
| 351 | return -EINVAL; |
| 352 | |
| 353 | engine->sram = devm_ioremap_resource(cesa->dev, res); |
| 354 | if (IS_ERR(engine->sram)) |
| 355 | return PTR_ERR(engine->sram); |
| 356 | |
| 357 | engine->sram_dma = phys_to_dma(cesa->dev, |
| 358 | (phys_addr_t)res->start); |
| 359 | |
| 360 | return 0; |
| 361 | } |
| 362 | |
| 363 | static void mv_cesa_put_sram(struct platform_device *pdev, int idx) |
| 364 | { |
| 365 | struct mv_cesa_dev *cesa = platform_get_drvdata(pdev); |
| 366 | struct mv_cesa_engine *engine = &cesa->engines[idx]; |
| 367 | |
| 368 | if (!engine->pool) |
| 369 | return; |
| 370 | |
| 371 | gen_pool_free(engine->pool, (unsigned long)engine->sram, |
| 372 | cesa->sram_size); |
| 373 | } |
| 374 | |
| 375 | static int mv_cesa_probe(struct platform_device *pdev) |
| 376 | { |
Boris BREZILLON | 0bf6948 | 2015-06-18 15:46:28 +0200 | [diff] [blame] | 377 | const struct mv_cesa_caps *caps = &orion_caps; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 378 | const struct mbus_dram_target_info *dram; |
| 379 | const struct of_device_id *match; |
| 380 | struct device *dev = &pdev->dev; |
| 381 | struct mv_cesa_dev *cesa; |
| 382 | struct mv_cesa_engine *engines; |
| 383 | struct resource *res; |
| 384 | int irq, ret, i; |
| 385 | u32 sram_size; |
| 386 | |
| 387 | if (cesa_dev) { |
| 388 | dev_err(&pdev->dev, "Only one CESA device authorized\n"); |
| 389 | return -EEXIST; |
| 390 | } |
| 391 | |
Boris BREZILLON | 0bf6948 | 2015-06-18 15:46:28 +0200 | [diff] [blame] | 392 | if (dev->of_node) { |
| 393 | match = of_match_node(mv_cesa_of_match_table, dev->of_node); |
| 394 | if (!match || !match->data) |
| 395 | return -ENOTSUPP; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 396 | |
Boris BREZILLON | 0bf6948 | 2015-06-18 15:46:28 +0200 | [diff] [blame] | 397 | caps = match->data; |
| 398 | } |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 399 | |
Arnaud Ebalard | 7240425 | 2015-06-18 15:46:29 +0200 | [diff] [blame] | 400 | if ((caps == &orion_caps || caps == &kirkwood_caps) && !allhwsupport) |
Boris BREZILLON | 0bf6948 | 2015-06-18 15:46:28 +0200 | [diff] [blame] | 401 | return -ENOTSUPP; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 402 | |
| 403 | cesa = devm_kzalloc(dev, sizeof(*cesa), GFP_KERNEL); |
| 404 | if (!cesa) |
| 405 | return -ENOMEM; |
| 406 | |
| 407 | cesa->caps = caps; |
| 408 | cesa->dev = dev; |
| 409 | |
| 410 | sram_size = CESA_SA_DEFAULT_SRAM_SIZE; |
| 411 | of_property_read_u32(cesa->dev->of_node, "marvell,crypto-sram-size", |
| 412 | &sram_size); |
| 413 | if (sram_size < CESA_SA_MIN_SRAM_SIZE) |
| 414 | sram_size = CESA_SA_MIN_SRAM_SIZE; |
| 415 | |
| 416 | cesa->sram_size = sram_size; |
| 417 | cesa->engines = devm_kzalloc(dev, caps->nengines * sizeof(*engines), |
| 418 | GFP_KERNEL); |
| 419 | if (!cesa->engines) |
| 420 | return -ENOMEM; |
| 421 | |
| 422 | spin_lock_init(&cesa->lock); |
Romain Perier | bf8f91e | 2016-06-21 10:08:38 +0200 | [diff] [blame^] | 423 | |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 424 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); |
| 425 | cesa->regs = devm_ioremap_resource(dev, res); |
| 426 | if (IS_ERR(cesa->regs)) |
Boris BREZILLON | dfe97ad | 2016-03-17 10:47:10 +0100 | [diff] [blame] | 427 | return PTR_ERR(cesa->regs); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 428 | |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 429 | ret = mv_cesa_dev_dma_init(cesa); |
| 430 | if (ret) |
| 431 | return ret; |
| 432 | |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 433 | dram = mv_mbus_dram_info_nooverlap(); |
| 434 | |
| 435 | platform_set_drvdata(pdev, cesa); |
| 436 | |
| 437 | for (i = 0; i < caps->nengines; i++) { |
| 438 | struct mv_cesa_engine *engine = &cesa->engines[i]; |
| 439 | char res_name[7]; |
| 440 | |
| 441 | engine->id = i; |
| 442 | spin_lock_init(&engine->lock); |
| 443 | |
| 444 | ret = mv_cesa_get_sram(pdev, i); |
| 445 | if (ret) |
| 446 | goto err_cleanup; |
| 447 | |
| 448 | irq = platform_get_irq(pdev, i); |
| 449 | if (irq < 0) { |
| 450 | ret = irq; |
| 451 | goto err_cleanup; |
| 452 | } |
| 453 | |
| 454 | /* |
| 455 | * Not all platforms can gate the CESA clocks: do not complain |
| 456 | * if the clock does not exist. |
| 457 | */ |
| 458 | snprintf(res_name, sizeof(res_name), "cesa%d", i); |
| 459 | engine->clk = devm_clk_get(dev, res_name); |
| 460 | if (IS_ERR(engine->clk)) { |
| 461 | engine->clk = devm_clk_get(dev, NULL); |
| 462 | if (IS_ERR(engine->clk)) |
| 463 | engine->clk = NULL; |
| 464 | } |
| 465 | |
| 466 | snprintf(res_name, sizeof(res_name), "cesaz%d", i); |
| 467 | engine->zclk = devm_clk_get(dev, res_name); |
| 468 | if (IS_ERR(engine->zclk)) |
| 469 | engine->zclk = NULL; |
| 470 | |
| 471 | ret = clk_prepare_enable(engine->clk); |
| 472 | if (ret) |
| 473 | goto err_cleanup; |
| 474 | |
| 475 | ret = clk_prepare_enable(engine->zclk); |
| 476 | if (ret) |
| 477 | goto err_cleanup; |
| 478 | |
| 479 | engine->regs = cesa->regs + CESA_ENGINE_OFF(i); |
| 480 | |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 481 | if (dram && cesa->caps->has_tdma) |
Romain Perier | 21ec757 | 2016-04-19 17:09:20 +0200 | [diff] [blame] | 482 | mv_cesa_conf_mbus_windows(engine, dram); |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 483 | |
Romain Perier | 21ec757 | 2016-04-19 17:09:20 +0200 | [diff] [blame] | 484 | writel(0, engine->regs + CESA_SA_INT_STATUS); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 485 | writel(CESA_SA_CFG_STOP_DIG_ERR, |
Romain Perier | 21ec757 | 2016-04-19 17:09:20 +0200 | [diff] [blame] | 486 | engine->regs + CESA_SA_CFG); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 487 | writel(engine->sram_dma & CESA_SA_SRAM_MSK, |
Romain Perier | 21ec757 | 2016-04-19 17:09:20 +0200 | [diff] [blame] | 488 | engine->regs + CESA_SA_DESC_P0); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 489 | |
| 490 | ret = devm_request_threaded_irq(dev, irq, NULL, mv_cesa_int, |
| 491 | IRQF_ONESHOT, |
| 492 | dev_name(&pdev->dev), |
Romain Perier | 21ec757 | 2016-04-19 17:09:20 +0200 | [diff] [blame] | 493 | engine); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 494 | if (ret) |
| 495 | goto err_cleanup; |
Romain Perier | bf8f91e | 2016-06-21 10:08:38 +0200 | [diff] [blame^] | 496 | |
| 497 | crypto_init_queue(&engine->queue, CESA_CRYPTO_DEFAULT_MAX_QLEN); |
| 498 | atomic_set(&engine->load, 0); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 499 | } |
| 500 | |
| 501 | cesa_dev = cesa; |
| 502 | |
| 503 | ret = mv_cesa_add_algs(cesa); |
| 504 | if (ret) { |
| 505 | cesa_dev = NULL; |
| 506 | goto err_cleanup; |
| 507 | } |
| 508 | |
| 509 | dev_info(dev, "CESA device successfully registered\n"); |
| 510 | |
| 511 | return 0; |
| 512 | |
| 513 | err_cleanup: |
| 514 | for (i = 0; i < caps->nengines; i++) { |
| 515 | clk_disable_unprepare(cesa->engines[i].zclk); |
| 516 | clk_disable_unprepare(cesa->engines[i].clk); |
| 517 | mv_cesa_put_sram(pdev, i); |
| 518 | } |
| 519 | |
| 520 | return ret; |
| 521 | } |
| 522 | |
| 523 | static int mv_cesa_remove(struct platform_device *pdev) |
| 524 | { |
| 525 | struct mv_cesa_dev *cesa = platform_get_drvdata(pdev); |
| 526 | int i; |
| 527 | |
| 528 | mv_cesa_remove_algs(cesa); |
| 529 | |
| 530 | for (i = 0; i < cesa->caps->nengines; i++) { |
| 531 | clk_disable_unprepare(cesa->engines[i].zclk); |
| 532 | clk_disable_unprepare(cesa->engines[i].clk); |
| 533 | mv_cesa_put_sram(pdev, i); |
| 534 | } |
| 535 | |
| 536 | return 0; |
| 537 | } |
| 538 | |
| 539 | static struct platform_driver marvell_cesa = { |
| 540 | .probe = mv_cesa_probe, |
| 541 | .remove = mv_cesa_remove, |
| 542 | .driver = { |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 543 | .name = "marvell-cesa", |
| 544 | .of_match_table = mv_cesa_of_match_table, |
| 545 | }, |
| 546 | }; |
| 547 | module_platform_driver(marvell_cesa); |
| 548 | |
| 549 | MODULE_ALIAS("platform:mv_crypto"); |
| 550 | MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>"); |
| 551 | MODULE_AUTHOR("Arnaud Ebalard <arno@natisbad.org>"); |
| 552 | MODULE_DESCRIPTION("Support for Marvell's cryptographic engine"); |
| 553 | MODULE_LICENSE("GPL v2"); |