Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 1 | /* |
| 2 | * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips |
Lennert Buytenhek | e84665c | 2009-03-20 09:52:09 +0000 | [diff] [blame] | 3 | * Copyright (c) 2008-2009 Marvell Semiconductor |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; either version 2 of the License, or |
| 8 | * (at your option) any later version. |
| 9 | */ |
| 10 | |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 11 | #include <linux/delay.h> |
| 12 | #include <linux/jiffies.h> |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 13 | #include <linux/list.h> |
Paul Gortmaker | 2bbba27 | 2012-01-24 10:41:40 +0000 | [diff] [blame] | 14 | #include <linux/module.h> |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 15 | #include <linux/netdevice.h> |
| 16 | #include <linux/phy.h> |
Ben Hutchings | c8f0b86 | 2011-11-27 17:06:08 +0000 | [diff] [blame] | 17 | #include <net/dsa.h> |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 18 | |
| 19 | #define REG_PORT(p) (8 + (p)) |
| 20 | #define REG_GLOBAL 0x0f |
| 21 | |
| 22 | static int reg_read(struct dsa_switch *ds, int addr, int reg) |
| 23 | { |
Guenter Roeck | b184e49 | 2014-10-17 12:30:58 -0700 | [diff] [blame] | 24 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); |
| 25 | |
| 26 | if (bus == NULL) |
| 27 | return -EINVAL; |
| 28 | |
| 29 | return mdiobus_read(bus, ds->pd->sw_addr + addr, reg); |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 30 | } |
| 31 | |
| 32 | #define REG_READ(addr, reg) \ |
| 33 | ({ \ |
| 34 | int __ret; \ |
| 35 | \ |
| 36 | __ret = reg_read(ds, addr, reg); \ |
| 37 | if (__ret < 0) \ |
| 38 | return __ret; \ |
| 39 | __ret; \ |
| 40 | }) |
| 41 | |
| 42 | |
| 43 | static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) |
| 44 | { |
Guenter Roeck | b184e49 | 2014-10-17 12:30:58 -0700 | [diff] [blame] | 45 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); |
| 46 | |
| 47 | if (bus == NULL) |
| 48 | return -EINVAL; |
| 49 | |
| 50 | return mdiobus_write(bus, ds->pd->sw_addr + addr, reg, val); |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 51 | } |
| 52 | |
| 53 | #define REG_WRITE(addr, reg, val) \ |
| 54 | ({ \ |
| 55 | int __ret; \ |
| 56 | \ |
| 57 | __ret = reg_write(ds, addr, reg, val); \ |
| 58 | if (__ret < 0) \ |
| 59 | return __ret; \ |
| 60 | }) |
| 61 | |
Alexander Duyck | b4d2394 | 2014-09-15 13:00:27 -0400 | [diff] [blame] | 62 | static char *mv88e6060_probe(struct device *host_dev, int sw_addr) |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 63 | { |
Alexander Duyck | b4d2394 | 2014-09-15 13:00:27 -0400 | [diff] [blame] | 64 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev); |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 65 | int ret; |
| 66 | |
Alexander Duyck | b4d2394 | 2014-09-15 13:00:27 -0400 | [diff] [blame] | 67 | if (bus == NULL) |
| 68 | return NULL; |
| 69 | |
Peter Korsgaard | fdb838c | 2011-03-07 05:49:47 +0000 | [diff] [blame] | 70 | ret = mdiobus_read(bus, sw_addr + REG_PORT(0), 0x03); |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 71 | if (ret >= 0) { |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 72 | if (ret == 0x0600) |
Guenter Roeck | 3de6aa4c | 2014-10-29 10:44:54 -0700 | [diff] [blame] | 73 | return "Marvell 88E6060 (A0)"; |
| 74 | if (ret == 0x0601 || ret == 0x0602) |
| 75 | return "Marvell 88E6060 (B0)"; |
| 76 | if ((ret & 0xfff0) == 0x0600) |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 77 | return "Marvell 88E6060"; |
| 78 | } |
| 79 | |
| 80 | return NULL; |
| 81 | } |
| 82 | |
| 83 | static int mv88e6060_switch_reset(struct dsa_switch *ds) |
| 84 | { |
| 85 | int i; |
| 86 | int ret; |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 87 | unsigned long timeout; |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 88 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 89 | /* Set all ports to the disabled state. */ |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 90 | for (i = 0; i < 6; i++) { |
| 91 | ret = REG_READ(REG_PORT(i), 0x04); |
| 92 | REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); |
| 93 | } |
| 94 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 95 | /* Wait for transmit queues to drain. */ |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 96 | usleep_range(2000, 4000); |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 97 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 98 | /* Reset the switch. */ |
Lennert Buytenhek | e84665c | 2009-03-20 09:52:09 +0000 | [diff] [blame] | 99 | REG_WRITE(REG_GLOBAL, 0x0a, 0xa130); |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 100 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 101 | /* Wait up to one second for reset to complete. */ |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 102 | timeout = jiffies + 1 * HZ; |
| 103 | while (time_before(jiffies, timeout)) { |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 104 | ret = REG_READ(REG_GLOBAL, 0x00); |
| 105 | if ((ret & 0x8000) == 0x0000) |
| 106 | break; |
| 107 | |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 108 | usleep_range(1000, 2000); |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 109 | } |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 110 | if (time_after(jiffies, timeout)) |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 111 | return -ETIMEDOUT; |
| 112 | |
| 113 | return 0; |
| 114 | } |
| 115 | |
| 116 | static int mv88e6060_setup_global(struct dsa_switch *ds) |
| 117 | { |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 118 | /* Disable discarding of frames with excessive collisions, |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 119 | * set the maximum frame size to 1536 bytes, and mask all |
| 120 | * interrupt sources. |
| 121 | */ |
| 122 | REG_WRITE(REG_GLOBAL, 0x04, 0x0800); |
| 123 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 124 | /* Enable automatic address learning, set the address |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 125 | * database size to 1024 entries, and set the default aging |
| 126 | * time to 5 minutes. |
| 127 | */ |
| 128 | REG_WRITE(REG_GLOBAL, 0x0a, 0x2130); |
| 129 | |
| 130 | return 0; |
| 131 | } |
| 132 | |
| 133 | static int mv88e6060_setup_port(struct dsa_switch *ds, int p) |
| 134 | { |
| 135 | int addr = REG_PORT(p); |
| 136 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 137 | /* Do not force flow control, disable Ingress and Egress |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 138 | * Header tagging, disable VLAN tunneling, and set the port |
| 139 | * state to Forwarding. Additionally, if this is the CPU |
| 140 | * port, enable Ingress and Egress Trailer tagging mode. |
| 141 | */ |
Lennert Buytenhek | e84665c | 2009-03-20 09:52:09 +0000 | [diff] [blame] | 142 | REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003); |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 143 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 144 | /* Port based VLAN map: give each port its own address |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 145 | * database, allow the CPU port to talk to each of the 'real' |
| 146 | * ports, and allow each of the 'real' ports to only talk to |
| 147 | * the CPU port. |
| 148 | */ |
| 149 | REG_WRITE(addr, 0x06, |
| 150 | ((p & 0xf) << 12) | |
Lennert Buytenhek | e84665c | 2009-03-20 09:52:09 +0000 | [diff] [blame] | 151 | (dsa_is_cpu_port(ds, p) ? |
| 152 | ds->phys_port_mask : |
| 153 | (1 << ds->dst->cpu_port))); |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 154 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 155 | /* Port Association Vector: when learning source addresses |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 156 | * of packets, add the address to the address database using |
| 157 | * a port bitmap that has only the bit for this port set and |
| 158 | * the other bits clear. |
| 159 | */ |
| 160 | REG_WRITE(addr, 0x0b, 1 << p); |
| 161 | |
| 162 | return 0; |
| 163 | } |
| 164 | |
| 165 | static int mv88e6060_setup(struct dsa_switch *ds) |
| 166 | { |
| 167 | int i; |
| 168 | int ret; |
| 169 | |
| 170 | ret = mv88e6060_switch_reset(ds); |
| 171 | if (ret < 0) |
| 172 | return ret; |
| 173 | |
| 174 | /* @@@ initialise atu */ |
| 175 | |
| 176 | ret = mv88e6060_setup_global(ds); |
| 177 | if (ret < 0) |
| 178 | return ret; |
| 179 | |
| 180 | for (i = 0; i < 6; i++) { |
| 181 | ret = mv88e6060_setup_port(ds, i); |
| 182 | if (ret < 0) |
| 183 | return ret; |
| 184 | } |
| 185 | |
| 186 | return 0; |
| 187 | } |
| 188 | |
| 189 | static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr) |
| 190 | { |
| 191 | REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]); |
| 192 | REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]); |
| 193 | REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]); |
| 194 | |
| 195 | return 0; |
| 196 | } |
| 197 | |
| 198 | static int mv88e6060_port_to_phy_addr(int port) |
| 199 | { |
| 200 | if (port >= 0 && port <= 5) |
| 201 | return port; |
| 202 | return -1; |
| 203 | } |
| 204 | |
| 205 | static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum) |
| 206 | { |
| 207 | int addr; |
| 208 | |
| 209 | addr = mv88e6060_port_to_phy_addr(port); |
| 210 | if (addr == -1) |
| 211 | return 0xffff; |
| 212 | |
| 213 | return reg_read(ds, addr, regnum); |
| 214 | } |
| 215 | |
| 216 | static int |
| 217 | mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) |
| 218 | { |
| 219 | int addr; |
| 220 | |
| 221 | addr = mv88e6060_port_to_phy_addr(port); |
| 222 | if (addr == -1) |
| 223 | return 0xffff; |
| 224 | |
| 225 | return reg_write(ds, addr, regnum, val); |
| 226 | } |
| 227 | |
| 228 | static void mv88e6060_poll_link(struct dsa_switch *ds) |
| 229 | { |
| 230 | int i; |
| 231 | |
| 232 | for (i = 0; i < DSA_MAX_PORTS; i++) { |
| 233 | struct net_device *dev; |
Ingo Molnar | d3f644d | 2008-11-25 16:51:13 -0800 | [diff] [blame] | 234 | int uninitialized_var(port_status); |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 235 | int link; |
| 236 | int speed; |
| 237 | int duplex; |
| 238 | int fc; |
| 239 | |
| 240 | dev = ds->ports[i]; |
| 241 | if (dev == NULL) |
| 242 | continue; |
| 243 | |
| 244 | link = 0; |
| 245 | if (dev->flags & IFF_UP) { |
| 246 | port_status = reg_read(ds, REG_PORT(i), 0x00); |
| 247 | if (port_status < 0) |
| 248 | continue; |
| 249 | |
| 250 | link = !!(port_status & 0x1000); |
| 251 | } |
| 252 | |
| 253 | if (!link) { |
| 254 | if (netif_carrier_ok(dev)) { |
Barry Grussling | ab381a9 | 2013-01-08 16:05:55 +0000 | [diff] [blame] | 255 | netdev_info(dev, "link down\n"); |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 256 | netif_carrier_off(dev); |
| 257 | } |
| 258 | continue; |
| 259 | } |
| 260 | |
| 261 | speed = (port_status & 0x0100) ? 100 : 10; |
| 262 | duplex = (port_status & 0x0200) ? 1 : 0; |
| 263 | fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0; |
| 264 | |
| 265 | if (!netif_carrier_ok(dev)) { |
Barry Grussling | ab381a9 | 2013-01-08 16:05:55 +0000 | [diff] [blame] | 266 | netdev_info(dev, |
| 267 | "link up, %d Mb/s, %s duplex, flow control %sabled\n", |
| 268 | speed, |
| 269 | duplex ? "full" : "half", |
| 270 | fc ? "en" : "dis"); |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 271 | netif_carrier_on(dev); |
| 272 | } |
| 273 | } |
| 274 | } |
| 275 | |
| 276 | static struct dsa_switch_driver mv88e6060_switch_driver = { |
Florian Fainelli | ac7a04c | 2014-09-11 21:18:09 -0700 | [diff] [blame] | 277 | .tag_protocol = DSA_TAG_PROTO_TRAILER, |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 278 | .probe = mv88e6060_probe, |
| 279 | .setup = mv88e6060_setup, |
| 280 | .set_addr = mv88e6060_set_addr, |
| 281 | .phy_read = mv88e6060_phy_read, |
| 282 | .phy_write = mv88e6060_phy_write, |
| 283 | .poll_link = mv88e6060_poll_link, |
| 284 | }; |
| 285 | |
Roel Kluin | 5eaa65b | 2008-12-10 15:18:31 -0800 | [diff] [blame] | 286 | static int __init mv88e6060_init(void) |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 287 | { |
| 288 | register_switch_driver(&mv88e6060_switch_driver); |
| 289 | return 0; |
| 290 | } |
| 291 | module_init(mv88e6060_init); |
| 292 | |
Roel Kluin | 5eaa65b | 2008-12-10 15:18:31 -0800 | [diff] [blame] | 293 | static void __exit mv88e6060_cleanup(void) |
Lennert Buytenhek | 2e16a77 | 2008-10-07 13:46:22 +0000 | [diff] [blame] | 294 | { |
| 295 | unregister_switch_driver(&mv88e6060_switch_driver); |
| 296 | } |
| 297 | module_exit(mv88e6060_cleanup); |
Ben Hutchings | 3d825ed | 2011-11-25 14:37:16 +0000 | [diff] [blame] | 298 | |
| 299 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); |
| 300 | MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip"); |
| 301 | MODULE_LICENSE("GPL"); |
| 302 | MODULE_ALIAS("platform:mv88e6060"); |