blob: ea57c0f6dccea46b98d4f06d40eb3446df8e5d10 [file] [log] [blame]
Stephen Warrenc80efba2012-04-20 16:57:38 -06001/dts-v1/;
2
3/include/ "tegra20.dtsi"
4
5/ {
Bryan Wu8fef5df2012-12-20 09:41:29 +00006 model = "NVIDIA Tegra20 Whistler evaluation board";
Stephen Warrenc80efba2012-04-20 16:57:38 -06007 compatible = "nvidia,whistler", "nvidia,tegra20";
8
9 memory {
10 reg = <0x00000000 0x20000000>;
11 };
12
Stephen Warren2658ef12012-11-16 10:53:04 -070013 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22 };
23 };
24
Stephen Warrenc80efba2012-04-20 16:57:38 -060025 pinmux {
26 pinctrl-names = "default";
27 pinctrl-0 = <&state_default>;
28
29 state_default: pinmux {
30 ata {
31 nvidia,pins = "ata", "atb", "ate", "gma", "gmb",
32 "gmc", "gmd", "gpu";
33 nvidia,function = "gmi";
34 };
35 atc {
36 nvidia,pins = "atc", "atd";
37 nvidia,function = "sdio4";
38 };
39 cdev1 {
40 nvidia,pins = "cdev1";
41 nvidia,function = "plla_out";
42 };
43 cdev2 {
44 nvidia,pins = "cdev2";
45 nvidia,function = "osc";
46 };
47 crtp {
48 nvidia,pins = "crtp";
49 nvidia,function = "crt";
50 };
51 csus {
52 nvidia,pins = "csus";
53 nvidia,function = "vi_sensor_clk";
54 };
55 dap1 {
56 nvidia,pins = "dap1";
57 nvidia,function = "dap1";
58 };
59 dap2 {
60 nvidia,pins = "dap2";
61 nvidia,function = "dap2";
62 };
63 dap3 {
64 nvidia,pins = "dap3";
65 nvidia,function = "dap3";
66 };
67 dap4 {
68 nvidia,pins = "dap4";
69 nvidia,function = "dap4";
70 };
71 ddc {
72 nvidia,pins = "ddc";
73 nvidia,function = "i2c2";
74 };
75 dta {
76 nvidia,pins = "dta", "dtb", "dtc", "dtd";
77 nvidia,function = "vi";
78 };
79 dte {
80 nvidia,pins = "dte";
81 nvidia,function = "rsvd1";
82 };
83 dtf {
84 nvidia,pins = "dtf";
85 nvidia,function = "i2c3";
86 };
87 gme {
88 nvidia,pins = "gme";
89 nvidia,function = "dap5";
90 };
91 gpu7 {
92 nvidia,pins = "gpu7";
93 nvidia,function = "rtck";
94 };
95 gpv {
96 nvidia,pins = "gpv";
97 nvidia,function = "pcie";
98 };
99 hdint {
100 nvidia,pins = "hdint", "pta";
101 nvidia,function = "hdmi";
102 };
103 i2cp {
104 nvidia,pins = "i2cp";
105 nvidia,function = "i2cp";
106 };
107 irrx {
108 nvidia,pins = "irrx", "irtx";
109 nvidia,function = "uartb";
110 };
111 kbca {
112 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
113 nvidia,function = "kbc";
114 };
115 kbcb {
116 nvidia,pins = "kbcb", "kbcd";
117 nvidia,function = "sdio2";
118 };
119 lcsn {
120 nvidia,pins = "lcsn", "lsck", "lsda", "lsdi",
121 "spia", "spib", "spic";
122 nvidia,function = "spi3";
123 };
124 ld0 {
125 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
126 "ld5", "ld6", "ld7", "ld8", "ld9",
127 "ld10", "ld11", "ld12", "ld13", "ld14",
128 "ld15", "ld16", "ld17", "ldc", "ldi",
129 "lhp0", "lhp1", "lhp2", "lhs", "lm0",
130 "lm1", "lpp", "lpw0", "lpw1", "lpw2",
131 "lsc0", "lsc1", "lspi", "lvp0", "lvp1",
132 "lvs";
133 nvidia,function = "displaya";
134 };
135 owc {
136 nvidia,pins = "owc", "uac";
137 nvidia,function = "owr";
138 };
139 pmc {
140 nvidia,pins = "pmc";
141 nvidia,function = "pwr_on";
142 };
143 rm {
144 nvidia,pins = "rm";
145 nvidia,function = "i2c1";
146 };
147 sdb {
148 nvidia,pins = "sdb", "sdc", "sdd", "slxa",
149 "slxc", "slxd", "slxk";
150 nvidia,function = "sdio3";
151 };
152 sdio1 {
153 nvidia,pins = "sdio1";
154 nvidia,function = "sdio1";
155 };
156 spdi {
157 nvidia,pins = "spdi", "spdo";
158 nvidia,function = "rsvd2";
159 };
160 spid {
161 nvidia,pins = "spid", "spie", "spig", "spih";
162 nvidia,function = "spi2_alt";
163 };
164 spif {
165 nvidia,pins = "spif";
166 nvidia,function = "spi2";
167 };
168 uaa {
169 nvidia,pins = "uaa", "uab";
170 nvidia,function = "uarta";
171 };
172 uad {
173 nvidia,pins = "uad";
174 nvidia,function = "irda";
175 };
176 uca {
177 nvidia,pins = "uca", "ucb";
178 nvidia,function = "uartc";
179 };
180 uda {
181 nvidia,pins = "uda";
182 nvidia,function = "spi1";
183 };
184 conf_ata {
185 nvidia,pins = "ata", "atb", "atc", "ddc", "gma",
186 "gmb", "gmc", "gmd", "irrx", "irtx",
187 "kbca", "kbcb", "kbcc", "kbcd", "kbce",
188 "kbcf", "sdc", "sdd", "spie", "spig",
189 "spih", "uaa", "uab", "uad", "uca",
190 "ucb";
191 nvidia,pull = <2>;
192 nvidia,tristate = <0>;
193 };
194 conf_atd {
195 nvidia,pins = "atd", "ate", "cdev1", "csus",
196 "dap1", "dap2", "dap3", "dap4", "dte",
197 "dtf", "gpu", "gpu7", "gpv", "i2cp",
198 "rm", "sdio1", "slxa", "slxc", "slxd",
199 "slxk", "spdi", "spdo", "uac", "uda";
200 nvidia,pull = <0>;
201 nvidia,tristate = <0>;
202 };
203 conf_cdev2 {
204 nvidia,pins = "cdev2", "spia", "spib";
205 nvidia,pull = <1>;
206 nvidia,tristate = <1>;
207 };
208 conf_ck32 {
209 nvidia,pins = "ck32", "ddrc", "lc", "pmca",
210 "pmcb", "pmcc", "pmcd", "xm2c",
211 "xm2d";
212 nvidia,pull = <0>;
213 };
214 conf_crtp {
215 nvidia,pins = "crtp";
216 nvidia,pull = <0>;
217 nvidia,tristate = <1>;
218 };
219 conf_dta {
220 nvidia,pins = "dta", "dtb", "dtc", "dtd",
221 "spid", "spif";
222 nvidia,pull = <1>;
223 nvidia,tristate = <0>;
224 };
225 conf_gme {
226 nvidia,pins = "gme", "owc", "pta", "spic";
227 nvidia,pull = <2>;
228 nvidia,tristate = <1>;
229 };
230 conf_ld17_0 {
231 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
232 "ld23_22";
233 nvidia,pull = <1>;
234 };
235 conf_ls {
236 nvidia,pins = "ls", "pmce";
237 nvidia,pull = <2>;
238 };
239 drive_dap1 {
240 nvidia,pins = "drive_dap1";
241 nvidia,high-speed-mode = <0>;
242 nvidia,schmitt = <1>;
243 nvidia,low-power-mode = <0>;
244 nvidia,pull-down-strength = <0>;
245 nvidia,pull-up-strength = <0>;
246 nvidia,slew-rate-rising = <0>;
247 nvidia,slew-rate-falling = <0>;
248 };
249 };
250 };
251
252 i2s@70002800 {
253 status = "okay";
254 };
255
256 serial@70006000 {
257 status = "okay";
Stephen Warrenc80efba2012-04-20 16:57:38 -0600258 };
259
Stephen Warren2658ef12012-11-16 10:53:04 -0700260 hdmi_ddc: i2c@7000c400 {
261 status = "okay";
262 clock-frequency = <100000>;
263 };
264
Stephen Warrenc80efba2012-04-20 16:57:38 -0600265 i2c@7000d000 {
266 status = "okay";
267 clock-frequency = <100000>;
268
269 codec: codec@1a {
270 compatible = "wlf,wm8753";
271 reg = <0x1a>;
272 };
273
274 tca6416: gpio@20 {
275 compatible = "ti,tca6416";
276 reg = <0x20>;
277 gpio-controller;
278 #gpio-cells = <2>;
279 };
Stephen Warrene7765b32012-06-25 16:41:25 -0600280
281 max8907@3c {
282 compatible = "maxim,max8907";
283 reg = <0x3c>;
284 interrupts = <0 86 0x4>;
285
Stephen Warrenb37ed4a2012-09-11 13:13:05 -0600286 maxim,system-power-controller;
287
Stephen Warrene7765b32012-06-25 16:41:25 -0600288 mbatt-supply = <&usb0_vbus_reg>;
289 in-v1-supply = <&mbatt_reg>;
290 in-v2-supply = <&mbatt_reg>;
291 in-v3-supply = <&mbatt_reg>;
292 in1-supply = <&mbatt_reg>;
293 in2-supply = <&nvvdd_sv3_reg>;
294 in3-supply = <&mbatt_reg>;
295 in4-supply = <&mbatt_reg>;
296 in5-supply = <&mbatt_reg>;
297 in6-supply = <&mbatt_reg>;
298 in7-supply = <&mbatt_reg>;
299 in8-supply = <&mbatt_reg>;
300 in9-supply = <&mbatt_reg>;
301 in10-supply = <&mbatt_reg>;
302 in11-supply = <&mbatt_reg>;
303 in12-supply = <&mbatt_reg>;
304 in13-supply = <&mbatt_reg>;
305 in14-supply = <&mbatt_reg>;
306 in15-supply = <&mbatt_reg>;
307 in16-supply = <&mbatt_reg>;
308 in17-supply = <&nvvdd_sv3_reg>;
309 in18-supply = <&nvvdd_sv3_reg>;
310 in19-supply = <&mbatt_reg>;
311 in20-supply = <&mbatt_reg>;
312
313 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600314 mbatt_reg: mbatt {
Stephen Warrene7765b32012-06-25 16:41:25 -0600315 regulator-name = "vbat_pmu";
316 regulator-always-on;
317 };
318
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600319 sd1 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600320 regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
321 regulator-min-microvolt = <1000000>;
322 regulator-max-microvolt = <1000000>;
323 regulator-always-on;
324 };
325
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600326 sd2 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600327 regulator-name = "nvvdd_sv2,vdd_core";
328 regulator-min-microvolt = <1200000>;
329 regulator-max-microvolt = <1200000>;
330 regulator-always-on;
331 };
332
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600333 nvvdd_sv3_reg: sd3 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600334 regulator-name = "nvvdd_sv3";
335 regulator-min-microvolt = <1800000>;
336 regulator-max-microvolt = <1800000>;
337 regulator-always-on;
338 };
339
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600340 ldo1 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600341 regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
342 regulator-min-microvolt = <3300000>;
343 regulator-max-microvolt = <3300000>;
344 regulator-always-on;
345 };
346
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600347 ldo2 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600348 regulator-name = "nvvdd_ldo2,avdd_pll*";
349 regulator-min-microvolt = <1100000>;
350 regulator-max-microvolt = <1100000>;
351 regulator-always-on;
352 };
353
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600354 ldo3 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600355 regulator-name = "nvvdd_ldo3,vcom_1v8b";
356 regulator-min-microvolt = <1800000>;
357 regulator-max-microvolt = <1800000>;
358 regulator-always-on;
359 };
360
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600361 ldo4 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600362 regulator-name = "nvvdd_ldo4,avdd_usb*";
363 regulator-min-microvolt = <3300000>;
364 regulator-max-microvolt = <3300000>;
365 regulator-always-on;
366 };
367
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600368 ldo5 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600369 regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
370 regulator-min-microvolt = <2800000>;
371 regulator-max-microvolt = <2800000>;
372 regulator-always-on;
373 };
374
Stephen Warren2658ef12012-11-16 10:53:04 -0700375 hdmi_pll_reg: ldo6 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600376 regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
377 regulator-min-microvolt = <1800000>;
378 regulator-max-microvolt = <1800000>;
379 };
380
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600381 ldo7 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600382 regulator-name = "nvvdd_ldo7,avddio_audio";
383 regulator-min-microvolt = <2800000>;
384 regulator-max-microvolt = <2800000>;
385 regulator-always-on;
386 };
387
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600388 ldo8 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600389 regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
390 regulator-min-microvolt = <3000000>;
391 regulator-max-microvolt = <3000000>;
392 };
393
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600394 ldo9 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600395 regulator-name = "nvvdd_ldo9,avdd_cam*";
396 regulator-min-microvolt = <2800000>;
397 regulator-max-microvolt = <2800000>;
398 };
399
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600400 ldo10 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600401 regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
402 regulator-min-microvolt = <3000000>;
403 regulator-max-microvolt = <3000000>;
404 regulator-always-on;
405 };
406
Stephen Warren2658ef12012-11-16 10:53:04 -0700407 hdmi_vdd_reg: ldo11 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600408 regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
409 regulator-min-microvolt = <3300000>;
410 regulator-max-microvolt = <3300000>;
411 };
412
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600413 ldo12 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600414 regulator-name = "nvvdd_ldo12,vddio_sdio";
415 regulator-min-microvolt = <2800000>;
416 regulator-max-microvolt = <2800000>;
417 regulator-always-on;
418 };
419
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600420 ldo13 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600421 regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
422 regulator-min-microvolt = <2800000>;
423 regulator-max-microvolt = <2800000>;
424 };
425
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600426 ldo14 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600427 regulator-name = "nvvdd_ldo14,avdd_vdac";
428 regulator-min-microvolt = <2800000>;
429 regulator-max-microvolt = <2800000>;
430 };
431
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600432 ldo15 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600433 regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
434 regulator-min-microvolt = <3300000>;
435 regulator-max-microvolt = <3300000>;
436 };
437
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600438 ldo16 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600439 regulator-name = "nvvdd_ldo16,vdd_dbrtr";
440 regulator-min-microvolt = <1300000>;
441 regulator-max-microvolt = <1300000>;
442 };
443
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600444 ldo17 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600445 regulator-name = "nvvdd_ldo17,vddio_mipi";
446 regulator-min-microvolt = <1200000>;
447 regulator-max-microvolt = <1200000>;
448 };
449
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600450 ldo18 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600451 regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
452 regulator-min-microvolt = <1800000>;
453 regulator-max-microvolt = <1800000>;
454 };
455
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600456 ldo19 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600457 regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
458 regulator-min-microvolt = <2800000>;
459 regulator-max-microvolt = <2800000>;
460 };
461
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600462 ldo20 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600463 regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
464 regulator-min-microvolt = <1200000>;
465 regulator-max-microvolt = <1200000>;
466 regulator-always-on;
467 };
468
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600469 out5v {
Stephen Warrene7765b32012-06-25 16:41:25 -0600470 regulator-name = "usb0_vbus_reg";
471 };
472
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600473 out33v {
Stephen Warrene7765b32012-06-25 16:41:25 -0600474 regulator-name = "pmu_out3v3";
475 };
476
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600477 bbat {
Stephen Warrene7765b32012-06-25 16:41:25 -0600478 regulator-name = "pmu_bbat";
479 regulator-min-microvolt = <2400000>;
480 regulator-max-microvolt = <2400000>;
481 regulator-always-on;
482 };
483
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600484 sdby {
Stephen Warrene7765b32012-06-25 16:41:25 -0600485 regulator-name = "vdd_aon";
486 regulator-always-on;
487 };
488
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600489 vrtc {
Stephen Warrene7765b32012-06-25 16:41:25 -0600490 regulator-name = "vrtc,pmu_vccadc";
491 regulator-always-on;
492 };
493 };
494 };
495 };
496
497 pmc {
498 nvidia,invert-interrupt;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600499 };
500
501 usb@c5000000 {
502 status = "okay";
503 nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
504 };
505
506 usb@c5008000 {
507 status = "okay";
508 nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
509 };
510
511 sdhci@c8000400 {
512 status = "okay";
513 wp-gpios = <&gpio 173 0>; /* gpio PV5 */
514 bus-width = <8>;
515 };
516
517 sdhci@c8000600 {
518 status = "okay";
519 bus-width = <8>;
520 };
521
Laxman Dewangan3a5c64d2013-01-18 11:28:43 +0530522 kbc {
523 status = "okay";
524 nvidia,debounce-delay-ms = <20>;
525 nvidia,repeat-delay-ms = <160>;
526 nvidia,kbc-row-pins = <0 1 2>;
527 nvidia,kbc-col-pins = <16 17>;
528 linux,keymap = <0x00000074 /* KEY_POWER */
529 0x01000066 /* KEY_HOME */
530 0x0101009E /* KEY_BACK */
531 0x0201008B>; /* KEY_MENU */
532 };
533
Stephen Warrene7765b32012-06-25 16:41:25 -0600534 regulators {
535 compatible = "simple-bus";
536 #address-cells = <1>;
537 #size-cells = <0>;
538
539 usb0_vbus_reg: regulator {
540 compatible = "regulator-fixed";
541 reg = <0>;
542 regulator-name = "usb0_vbus";
543 regulator-min-microvolt = <5000000>;
544 regulator-max-microvolt = <5000000>;
545 regulator-always-on;
546 };
547 };
548
Stephen Warrenc80efba2012-04-20 16:57:38 -0600549 sound {
550 compatible = "nvidia,tegra-audio-wm8753-whistler",
551 "nvidia,tegra-audio-wm8753";
552 nvidia,model = "NVIDIA Tegra Whistler";
553
554 nvidia,audio-routing =
555 "Headphone Jack", "LOUT1",
556 "Headphone Jack", "ROUT1",
557 "MIC2", "Mic Jack",
558 "MIC2N", "Mic Jack";
559
560 nvidia,i2s-controller = <&tegra_i2s1>;
561 nvidia,audio-codec = <&codec>;
562 };
563};