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Banajit Goswamib016de92017-02-15 21:02:30 -08001/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
Kyle Yan679cbee2016-07-27 16:55:20 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13&soc {
Channagoud Kadabieb7f0112017-04-03 20:39:27 -070014 tlmm: pinctrl@03400000 {
Kyle Yan6a20fae2017-02-14 13:34:41 -080015 compatible = "qcom,sdm845-pinctrl";
Channagoud Kadabieb7f0112017-04-03 20:39:27 -070016 reg = <0x03400000 0xc00000>;
Kyle Yan679cbee2016-07-27 16:55:20 -070017 interrupts = <0 208 0>;
18 gpio-controller;
19 #gpio-cells = <2>;
20 interrupt-controller;
21 #interrupt-cells = <2>;
Banajit Goswamib016de92017-02-15 21:02:30 -080022
Subhash Jadavaniafe2a792017-03-31 21:08:29 -070023 ufs_dev_reset_assert: ufs_dev_reset_assert {
24 config {
25 pins = "ufs_reset";
26 bias-pull-down; /* default: pull down */
27 /*
28 * UFS_RESET driver strengths are having
29 * different values/steps compared to typical
30 * GPIO drive strengths.
31 *
32 * Following table clarifies:
33 *
34 * HDRV value | UFS_RESET | Typical GPIO
35 * (dec) | (mA) | (mA)
36 * 0 | 0.8 | 2
37 * 1 | 1.55 | 4
38 * 2 | 2.35 | 6
39 * 3 | 3.1 | 8
40 * 4 | 3.9 | 10
41 * 5 | 4.65 | 12
42 * 6 | 5.4 | 14
43 * 7 | 6.15 | 16
44 *
45 * POR value for UFS_RESET HDRV is 3 which means
46 * 3.1mA and we want to use that. Hence just
47 * specify 8mA to "drive-strength" binding and
48 * that should result into writing 3 to HDRV
49 * field.
50 */
51 drive-strength = <8>; /* default: 3.1 mA */
52 output-low; /* active low reset */
53 };
54 };
55
56 ufs_dev_reset_deassert: ufs_dev_reset_deassert {
57 config {
58 pins = "ufs_reset";
59 bias-pull-down; /* default: pull down */
60 /*
61 * default: 3.1 mA
62 * check comments under ufs_dev_reset_assert
63 */
64 drive-strength = <8>;
65 output-high; /* active low reset */
66 };
67 };
68
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070069 flash_led3_front {
70 flash_led3_front_en: flash_led3_front_en {
71 mux {
72 pins = "gpio21";
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070073 function = "gpio";
74 };
75
76 config {
77 pins = "gpio21";
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070078 drive_strength = <2>;
79 output-high;
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070080 bias-disable;
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070081 };
82 };
83
84 flash_led3_front_dis: flash_led3_front_dis {
85 mux {
86 pins = "gpio21";
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070087 function = "gpio";
88 };
89
90 config {
91 pins = "gpio21";
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070092 drive_strength = <2>;
93 output-low;
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070094 bias-disable;
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070095 };
96 };
97 };
Subhash Jadavaniafe2a792017-03-31 21:08:29 -070098
Banajit Goswamib016de92017-02-15 21:02:30 -080099 wcd9xxx_intr {
100 wcd_intr_default: wcd_intr_default{
101 mux {
102 pins = "gpio54";
103 function = "gpio";
104 };
105
106 config {
107 pins = "gpio54";
108 drive-strength = <2>; /* 2 mA */
109 bias-pull-down; /* pull down */
110 input-enable;
111 };
112 };
113 };
114
115 cdc_reset_ctrl {
116 cdc_reset_sleep: cdc_reset_sleep {
117 mux {
118 pins = "gpio64";
119 function = "gpio";
120 };
121 config {
122 pins = "gpio64";
123 drive-strength = <2>;
124 bias-disable;
125 output-low;
126 };
127 };
128
129 cdc_reset_active:cdc_reset_active {
130 mux {
131 pins = "gpio64";
132 function = "gpio";
133 };
134 config {
135 pins = "gpio64";
136 drive-strength = <8>;
137 bias-pull-down;
138 output-high;
139 };
140 };
141 };
142
143 spkr_i2s_clk_pin {
144 spkr_i2s_clk_sleep: spkr_i2s_clk_sleep {
145 mux {
146 pins = "gpio69";
147 function = "spkr_i2s";
148 };
149
150 config {
151 pins = "gpio69";
152 drive-strength = <2>; /* 2 mA */
153 bias-pull-down; /* PULL DOWN */
154 };
155 };
156
157 spkr_i2s_clk_active: spkr_i2s_clk_active {
158 mux {
159 pins = "gpio69";
160 function = "spkr_i2s";
161 };
162
163 config {
164 pins = "gpio69";
165 drive-strength = <8>; /* 8 mA */
166 bias-disable; /* NO PULL */
167 };
168 };
169 };
170
171 wcd_gnd_mic_swap {
172 wcd_gnd_mic_swap_idle: wcd_gnd_mic_swap_idle {
173 mux {
174 pins = "gpio51";
175 function = "gpio";
176 };
177 config {
178 pins = "gpio51";
179 drive-strength = <2>;
180 bias-pull-down;
181 output-low;
182 };
183 };
184
185 wcd_gnd_mic_swap_active: wcd_gnd_mic_swap_active {
186 mux {
187 pins = "gpio51";
188 function = "gpio";
189 };
190 config {
191 pins = "gpio51";
192 drive-strength = <2>;
193 bias-disable;
194 output-high;
195 };
196 };
197 };
198
199 pri_aux_pcm_clk {
200 pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep {
201 mux {
202 pins = "gpio65";
203 function = "gpio";
204 };
205
206 config {
207 pins = "gpio65";
208 drive-strength = <2>; /* 2 mA */
209 bias-pull-down; /* PULL DOWN */
210 input-enable;
211 };
212 };
213
214 pri_aux_pcm_clk_active: pri_aux_pcm_clk_active {
215 mux {
216 pins = "gpio65";
217 function = "pri_mi2s";
218 };
219
220 config {
221 pins = "gpio65";
222 drive-strength = <8>; /* 8 mA */
223 bias-disable; /* NO PULL */
224 output-high;
225 };
226 };
227 };
228
229 pri_aux_pcm_sync {
230 pri_aux_pcm_sync_sleep: pri_aux_pcm_sync_sleep {
231 mux {
232 pins = "gpio66";
233 function = "gpio";
234 };
235
236 config {
237 pins = "gpio66";
238 drive-strength = <2>; /* 2 mA */
239 bias-pull-down; /* PULL DOWN */
240 input-enable;
241 };
242 };
243
244 pri_aux_pcm_sync_active: pri_aux_pcm_sync_active {
245 mux {
246 pins = "gpio66";
247 function = "pri_mi2s_ws";
248 };
249
250 config {
251 pins = "gpio66";
252 drive-strength = <8>; /* 8 mA */
253 bias-disable; /* NO PULL */
254 output-high;
255 };
256 };
257 };
258
259 pri_aux_pcm_din {
260 pri_aux_pcm_din_sleep: pri_aux_pcm_din_sleep {
261 mux {
262 pins = "gpio67";
263 function = "gpio";
264 };
265
266 config {
267 pins = "gpio67";
268 drive-strength = <2>; /* 2 mA */
269 bias-pull-down; /* PULL DOWN */
270 input-enable;
271 };
272 };
273
274 pri_aux_pcm_din_active: pri_aux_pcm_din_active {
275 mux {
276 pins = "gpio67";
277 function = "pri_mi2s";
278 };
279
280 config {
281 pins = "gpio67";
282 drive-strength = <8>; /* 8 mA */
283 bias-disable; /* NO PULL */
284 };
285 };
286 };
287
288 pri_aux_pcm_dout {
289 pri_aux_pcm_dout_sleep: pri_aux_pcm_dout_sleep {
290 mux {
291 pins = "gpio68";
292 function = "gpio";
293 };
294
295 config {
296 pins = "gpio68";
297 drive-strength = <2>; /* 2 mA */
298 bias-pull-down; /* PULL DOWN */
299 input-enable;
300 };
301 };
302
303 pri_aux_pcm_dout_active: pri_aux_pcm_dout_active {
304 mux {
305 pins = "gpio68";
306 function = "pri_mi2s";
307 };
308
309 config {
310 pins = "gpio68";
311 drive-strength = <8>; /* 8 mA */
312 bias-disable; /* NO PULL */
313 };
314 };
315 };
316
Shashank Babu Chinta Venkata2f40bc72017-03-21 15:31:38 -0700317 pmx_sde: pmx_sde {
318 sde_dsi_active: sde_dsi_active {
319 mux {
320 pins = "gpio6", "gpio52";
321 function = "gpio";
322 };
323
324 config {
325 pins = "gpio6", "gpio52";
326 drive-strength = <8>; /* 8 mA */
327 bias-disable = <0>; /* no pull */
328 };
329 };
330 sde_dsi_suspend: sde_dsi_suspend {
331 mux {
332 pins = "gpio6", "gpio52";
333 function = "gpio";
334 };
335
336 config {
337 pins = "gpio6", "gpio52";
338 drive-strength = <2>; /* 2 mA */
339 bias-pull-down; /* PULL DOWN */
340 };
341 };
342 };
343
344 pmx_sde_te {
345 sde_te_active: sde_te_active {
346 mux {
347 pins = "gpio10";
348 function = "mdp_vsync";
349 };
350
351 config {
352 pins = "gpio10";
353 drive-strength = <2>; /* 2 mA */
354 bias-pull-down; /* PULL DOWN */
355 };
356 };
357
358 sde_te_suspend: sde_te_suspend {
359 mux {
360 pins = "gpio10";
361 function = "mdp_vsync";
362 };
363
364 config {
365 pins = "gpio10";
366 drive-strength = <2>; /* 2 mA */
367 bias-pull-down; /* PULL DOWN */
368 };
369 };
370 };
371
Banajit Goswamib016de92017-02-15 21:02:30 -0800372 sec_aux_pcm {
373 sec_aux_pcm_sleep: sec_aux_pcm_sleep {
374 mux {
375 pins = "gpio80", "gpio81";
376 function = "gpio";
377 };
378
379 config {
380 pins = "gpio80", "gpio81";
381 drive-strength = <2>; /* 2 mA */
382 bias-pull-down; /* PULL DOWN */
383 input-enable;
384 };
385 };
386
387 sec_aux_pcm_active: sec_aux_pcm_active {
388 mux {
389 pins = "gpio80", "gpio81";
390 function = "sec_mi2s";
391 };
392
393 config {
394 pins = "gpio80", "gpio81";
395 drive-strength = <8>; /* 8 mA */
396 bias-disable; /* NO PULL */
397 };
398 };
399 };
400
401 sec_aux_pcm_din {
402 sec_aux_pcm_din_sleep: sec_aux_pcm_din_sleep {
403 mux {
404 pins = "gpio82";
405 function = "gpio";
406 };
407
408 config {
409 pins = "gpio82";
410 drive-strength = <2>; /* 2 mA */
411 bias-pull-down; /* PULL DOWN */
412 input-enable;
413 };
414 };
415
416 sec_aux_pcm_din_active: sec_aux_pcm_din_active {
417 mux {
418 pins = "gpio82";
419 function = "sec_mi2s";
420 };
421
422 config {
423 pins = "gpio82";
424 drive-strength = <8>; /* 8 mA */
425 bias-disable; /* NO PULL */
426 };
427 };
428 };
429
430 sec_aux_pcm_dout {
431 sec_aux_pcm_dout_sleep: sec_aux_pcm_dout_sleep {
432 mux {
433 pins = "gpio83";
434 function = "gpio";
435 };
436
437 config {
438 pins = "gpio83";
439 drive-strength = <2>; /* 2 mA */
440 bias-pull-down; /* PULL DOWN */
441 input-enable;
442 };
443 };
444
445 sec_aux_pcm_dout_active: sec_aux_pcm_dout_active {
446 mux {
447 pins = "gpio83";
448 function = "sec_mi2s";
449 };
450
451 config {
452 pins = "gpio83";
453 drive-strength = <8>; /* 8 mA */
454 bias-disable; /* NO PULL */
455 };
456 };
457 };
458
459 tert_aux_pcm {
460 tert_aux_pcm_sleep: tert_aux_pcm_sleep {
461 mux {
462 pins = "gpio75", "gpio76";
463 function = "gpio";
464 };
465
466 config {
467 pins = "gpio75", "gpio76";
468 drive-strength = <2>; /* 2 mA */
469 bias-pull-down; /* PULL DOWN */
470 input-enable;
471 };
472 };
473
474 tert_aux_pcm_active: tert_aux_pcm_active {
475 mux {
476 pins = "gpio75", "gpio76";
477 function = "ter_mi2s";
478 };
479
480 config {
481 pins = "gpio75", "gpio76";
482 drive-strength = <8>; /* 8 mA */
483 bias-disable; /* NO PULL */
484 output-high;
485 };
486 };
487 };
488
489 tert_aux_pcm_din {
490 tert_aux_pcm_din_sleep: tert_aux_pcm_din_sleep {
491 mux {
492 pins = "gpio77";
493 function = "gpio";
494 };
495
496 config {
497 pins = "gpio77";
498 drive-strength = <2>; /* 2 mA */
499 bias-pull-down; /* PULL DOWN */
500 input-enable;
501 };
502 };
503
504 tert_aux_pcm_din_active: tert_aux_pcm_din_active {
505 mux {
506 pins = "gpio77";
507 function = "ter_mi2s";
508 };
509
510 config {
511 pins = "gpio77";
512 drive-strength = <8>; /* 8 mA */
513 bias-disable; /* NO PULL */
514 };
515 };
516 };
517
518 tert_aux_pcm_dout {
519 tert_aux_pcm_dout_sleep: tert_aux_pcm_dout_sleep {
520 mux {
521 pins = "gpio78";
522 function = "gpio";
523 };
524
525 config {
526 pins = "gpio78";
527 drive-strength = <2>; /* 2 mA */
528 bias-pull-down; /* PULL DOWN */
529 input-enable;
530 };
531 };
532
533 tert_aux_pcm_dout_active: tert_aux_pcm_dout_active {
534 mux {
535 pins = "gpio78";
536 function = "ter_mi2s";
537 };
538
539 config {
540 pins = "gpio78";
541 drive-strength = <8>; /* 8 mA */
542 bias-disable; /* NO PULL */
543 };
544 };
545 };
546
547 quat_aux_pcm {
548 quat_aux_pcm_sleep: quat_aux_pcm_sleep {
549 mux {
550 pins = "gpio58", "gpio59";
551 function = "gpio";
552 };
553
554 config {
555 pins = "gpio58", "gpio59";
556 drive-strength = <2>; /* 2 mA */
557 bias-pull-down; /* PULL DOWN */
558 input-enable;
559 };
560 };
561
562 quat_aux_pcm_active: quat_aux_pcm_active {
563 mux {
564 pins = "gpio58", "gpio59";
565 function = "qua_mi2s";
566 };
567
568 config {
569 pins = "gpio58", "gpio59";
570 drive-strength = <8>; /* 8 mA */
571 bias-disable; /* NO PULL */
572 output-high;
573 };
574 };
575 };
576
577 quat_aux_pcm_din {
578 quat_aux_pcm_din_sleep: quat_aux_pcm_din_sleep {
579 mux {
580 pins = "gpio60";
581 function = "gpio";
582 };
583
584 config {
585 pins = "gpio60";
586 drive-strength = <2>; /* 2 mA */
587 bias-pull-down; /* PULL DOWN */
588 input-enable;
589 };
590 };
591
592 quat_aux_pcm_din_active: quat_aux_pcm_din_active {
593 mux {
594 pins = "gpio60";
595 function = "qua_mi2s";
596 };
597
598 config {
599 pins = "gpio60";
600 drive-strength = <8>; /* 8 mA */
601 bias-disable; /* NO PULL */
602 };
603 };
604 };
605
606 quat_aux_pcm_dout {
607 quat_aux_pcm_dout_sleep: quat_aux_pcm_dout_sleep {
608 mux {
609 pins = "gpio61";
610 function = "gpio";
611 };
612
613 config {
614 pins = "gpio61";
615 drive-strength = <2>; /* 2 mA */
616 bias-pull-down; /* PULL DOWN */
617 input-enable;
618 };
619 };
620
621 quat_aux_pcm_dout_active: quat_aux_pcm_dout_active {
622 mux {
623 pins = "gpio61";
624 function = "qua_mi2s";
625 };
626
627 config {
628 pins = "gpio61";
629 drive-strength = <8>; /* 8 mA */
630 bias-disable; /* NO PULL */
631 };
632 };
633 };
634
635 pri_mi2s_mclk {
636 pri_mi2s_mclk_sleep: pri_mi2s_mclk_sleep {
637 mux {
638 pins = "gpio64";
639 function = "gpio";
640 };
641
642 config {
643 pins = "gpio64";
644 drive-strength = <2>; /* 2 mA */
645 bias-pull-down; /* PULL DOWN */
646 input-enable;
647 };
648 };
649
650 pri_mi2s_mclk_active: pri_mi2s_mclk_active {
651 mux {
652 pins = "gpio64";
653 function = "pri_mi2s";
654 };
655
656 config {
657 pins = "gpio64";
658 drive-strength = <8>; /* 8 mA */
659 bias-disable; /* NO PULL */
660 output-high;
661 };
662 };
663 };
664
665 pri_mi2s_sck {
666 pri_mi2s_sck_sleep: pri_mi2s_sck_sleep {
667 mux {
668 pins = "gpio65";
669 function = "gpio";
670 };
671
672 config {
673 pins = "gpio65";
674 drive-strength = <2>; /* 2 mA */
675 bias-pull-down; /* PULL DOWN */
676 input-enable;
677 };
678 };
679
680 pri_mi2s_sck_active: pri_mi2s_sck_active {
681 mux {
682 pins = "gpio65";
683 function = "pri_mi2s";
684 };
685
686 config {
687 pins = "gpio65";
688 drive-strength = <8>; /* 8 mA */
689 bias-disable; /* NO PULL */
690 output-high;
691 };
692 };
693 };
694
695 pri_mi2s_ws {
696 pri_mi2s_ws_sleep: pri_mi2s_ws_sleep {
697 mux {
698 pins = "gpio66";
699 function = "gpio";
700 };
701
702 config {
703 pins = "gpio66";
704 drive-strength = <2>; /* 2 mA */
705 bias-pull-down; /* PULL DOWN */
706 input-enable;
707 };
708 };
709
710 pri_mi2s_ws_active: pri_mi2s_ws_active {
711 mux {
712 pins = "gpio66";
713 function = "pri_mi2s_ws";
714 };
715
716 config {
717 pins = "gpio66";
718 drive-strength = <8>; /* 8 mA */
719 bias-disable; /* NO PULL */
720 output-high;
721 };
722 };
723 };
724
725 pri_mi2s_sd0 {
726 pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep {
727 mux {
728 pins = "gpio67";
729 function = "gpio";
730 };
731
732 config {
733 pins = "gpio67";
734 drive-strength = <2>; /* 2 mA */
735 bias-pull-down; /* PULL DOWN */
736 input-enable;
737 };
738 };
739
740 pri_mi2s_sd0_active: pri_mi2s_sd0_active {
741 mux {
742 pins = "gpio67";
743 function = "pri_mi2s";
744 };
745
746 config {
747 pins = "gpio67";
748 drive-strength = <8>; /* 8 mA */
749 bias-disable; /* NO PULL */
750 };
751 };
752 };
753
754 pri_mi2s_sd1 {
755 pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep {
756 mux {
757 pins = "gpio68";
758 function = "gpio";
759 };
760
761 config {
762 pins = "gpio68";
763 drive-strength = <2>; /* 2 mA */
764 bias-pull-down; /* PULL DOWN */
765 input-enable;
766 };
767 };
768
769 pri_mi2s_sd1_active: pri_mi2s_sd1_active {
770 mux {
771 pins = "gpio68";
772 function = "pri_mi2s";
773 };
774
775 config {
776 pins = "gpio68";
777 drive-strength = <8>; /* 8 mA */
778 bias-disable; /* NO PULL */
779 };
780 };
781 };
782
783 sec_mi2s_mclk {
784 sec_mi2s_mclk_sleep: sec_mi2s_mclk_sleep {
785 mux {
786 pins = "gpio79";
787 function = "gpio";
788 };
789
790 config {
791 pins = "gpio79";
792 drive-strength = <2>; /* 2 mA */
793 bias-pull-down; /* PULL DOWN */
794 input-enable;
795 };
796 };
797
798 sec_mi2s_mclk_active: sec_mi2s_mclk_active {
799 mux {
800 pins = "gpio79";
801 function = "sec_mi2s";
802 };
803
804 config {
805 pins = "gpio79";
806 drive-strength = <8>; /* 8 mA */
807 bias-disable; /* NO PULL */
808 };
809 };
810 };
811
812 sec_mi2s {
813 sec_mi2s_sleep: sec_mi2s_sleep {
814 mux {
815 pins = "gpio80", "gpio81";
816 function = "gpio";
817 };
818
819 config {
820 pins = "gpio80", "gpio81";
821 drive-strength = <2>; /* 2 mA */
822 bias-disable; /* NO PULL */
823 input-enable;
824 };
825 };
826
827 sec_mi2s_active: sec_mi2s_active {
828 mux {
829 pins = "gpio80", "gpio81";
830 function = "sec_mi2s";
831 };
832
833 config {
834 pins = "gpio80", "gpio81";
835 drive-strength = <8>; /* 8 mA */
836 bias-disable; /* NO PULL */
837 };
838 };
839 };
840
841 sec_mi2s_sd0 {
842 sec_mi2s_sd0_sleep: sec_mi2s_sd0_sleep {
843 mux {
844 pins = "gpio82";
845 function = "gpio";
846 };
847
848 config {
849 pins = "gpio82";
850 drive-strength = <2>; /* 2 mA */
851 bias-pull-down; /* PULL DOWN */
852 input-enable;
853 };
854 };
855
856 sec_mi2s_sd0_active: sec_mi2s_sd0_active {
857 mux {
858 pins = "gpio82";
859 function = "sec_mi2s";
860 };
861
862 config {
863 pins = "gpio82";
864 drive-strength = <8>; /* 8 mA */
865 bias-disable; /* NO PULL */
866 };
867 };
868 };
869
870 sec_mi2s_sd1 {
871 sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep {
872 mux {
873 pins = "gpio83";
874 function = "gpio";
875 };
876
877 config {
878 pins = "gpio83";
879 drive-strength = <2>; /* 2 mA */
880 bias-pull-down; /* PULL DOWN */
881 input-enable;
882 };
883 };
884
885 sec_mi2s_sd1_active: sec_mi2s_sd1_active {
886 mux {
887 pins = "gpio83";
888 function = "sec_mi2s";
889 };
890
891 config {
892 pins = "gpio83";
893 drive-strength = <8>; /* 8 mA */
894 bias-disable; /* NO PULL */
895 };
896 };
897 };
898
899 tert_mi2s_mclk {
900 tert_mi2s_mclk_sleep: tert_mi2s_mclk_sleep {
901 mux {
902 pins = "gpio74";
903 function = "gpio";
904 };
905
906 config {
907 pins = "gpio74";
908 drive-strength = <2>; /* 2 mA */
909 bias-pull-down; /* PULL DOWN */
910 input-enable;
911 };
912 };
913
914 tert_mi2s_mclk_active: tert_mi2s_mclk_active {
915 mux {
916 pins = "gpio74";
917 function = "ter_mi2s";
918 };
919
920 config {
921 pins = "gpio74";
922 drive-strength = <8>; /* 8 mA */
923 bias-disable; /* NO PULL */
924 };
925 };
926 };
927
928 tert_mi2s {
929 tert_mi2s_sleep: tert_mi2s_sleep {
930 mux {
931 pins = "gpio75", "gpio76";
932 function = "gpio";
933 };
934
935 config {
936 pins = "gpio75", "gpio76";
937 drive-strength = <2>; /* 2 mA */
938 bias-pull-down; /* PULL DOWN */
939 input-enable;
940 };
941 };
942
943 tert_mi2s_active: tert_mi2s_active {
944 mux {
945 pins = "gpio75", "gpio76";
946 function = "ter_mi2s";
947 };
948
949 config {
950 pins = "gpio75", "gpio76";
951 drive-strength = <8>; /* 8 mA */
952 bias-disable; /* NO PULL */
953 output-high;
954 };
955 };
956 };
957
958 tert_mi2s_sd0 {
959 tert_mi2s_sd0_sleep: tert_mi2s_sd0_sleep {
960 mux {
961 pins = "gpio77";
962 function = "gpio";
963 };
964
965 config {
966 pins = "gpio77";
967 drive-strength = <2>; /* 2 mA */
968 bias-pull-down; /* PULL DOWN */
969 input-enable;
970 };
971 };
972
973 tert_mi2s_sd0_active: tert_mi2s_sd0_active {
974 mux {
975 pins = "gpio77";
976 function = "ter_mi2s";
977 };
978
979 config {
980 pins = "gpio77";
981 drive-strength = <8>; /* 8 mA */
982 bias-disable; /* NO PULL */
983 };
984 };
985 };
986
987 tert_mi2s_sd1 {
988 tert_mi2s_sd1_sleep: tert_mi2s_sd1_sleep {
989 mux {
990 pins = "gpio78";
991 function = "gpio";
992 };
993
994 config {
995 pins = "gpio78";
996 drive-strength = <2>; /* 2 mA */
997 bias-pull-down; /* PULL DOWN */
998 input-enable;
999 };
1000 };
1001
1002 tert_mi2s_sd1_active: tert_mi2s_sd1_active {
1003 mux {
1004 pins = "gpio78";
1005 function = "ter_mi2s";
1006 };
1007
1008 config {
1009 pins = "gpio78";
1010 drive-strength = <8>; /* 8 mA */
1011 bias-disable; /* NO PULL */
1012 };
1013 };
1014 };
1015
1016 quat_mi2s_mclk {
1017 quat_mi2s_mclk_sleep: quat_mi2s_mclk_sleep {
1018 mux {
1019 pins = "gpio57";
1020 function = "gpio";
1021 };
1022
1023 config {
1024 pins = "gpio57";
1025 drive-strength = <2>; /* 2 mA */
1026 bias-pull-down; /* PULL DOWN */
1027 input-enable;
1028 };
1029 };
1030
1031 quat_mi2s_mclk_active: quat_mi2s_mclk_active {
1032 mux {
1033 pins = "gpio57";
1034 function = "qua_mi2s";
1035 };
1036
1037 config {
1038 pins = "gpio57";
1039 drive-strength = <8>; /* 8 mA */
1040 bias-disable; /* NO PULL */
1041 };
1042 };
1043 };
1044
1045 quat_mi2s {
1046 quat_mi2s_sleep: quat_mi2s_sleep {
1047 mux {
1048 pins = "gpio58", "gpio59";
1049 function = "gpio";
1050 };
1051
1052 config {
1053 pins = "gpio58", "gpio59";
1054 drive-strength = <2>; /* 2 mA */
1055 bias-pull-down; /* PULL DOWN */
1056 input-enable;
1057 };
1058 };
1059
1060 quat_mi2s_active: quat_mi2s_active {
1061 mux {
1062 pins = "gpio58", "gpio59";
1063 function = "qua_mi2s";
1064 };
1065
1066 config {
1067 pins = "gpio58", "gpio59";
1068 drive-strength = <8>; /* 8 mA */
1069 bias-disable; /* NO PULL */
1070 output-high;
1071 };
1072 };
1073 };
1074
1075 quat_mi2s_sd0 {
1076 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
1077 mux {
1078 pins = "gpio60";
1079 function = "gpio";
1080 };
1081
1082 config {
1083 pins = "gpio60";
1084 drive-strength = <2>; /* 2 mA */
1085 bias-pull-down; /* PULL DOWN */
1086 input-enable;
1087 };
1088 };
1089
1090 quat_mi2s_sd0_active: quat_mi2s_sd0_active {
1091 mux {
1092 pins = "gpio60";
1093 function = "qua_mi2s";
1094 };
1095
1096 config {
1097 pins = "gpio60";
1098 drive-strength = <8>; /* 8 mA */
1099 bias-disable; /* NO PULL */
1100 };
1101 };
1102 };
1103
1104 quat_mi2s_sd1 {
1105 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
1106 mux {
1107 pins = "gpio61";
1108 function = "gpio";
1109 };
1110
1111 config {
1112 pins = "gpio61";
1113 drive-strength = <2>; /* 2 mA */
1114 bias-pull-down; /* PULL DOWN */
1115 input-enable;
1116 };
1117 };
1118
1119 quat_mi2s_sd1_active: quat_mi2s_sd1_active {
1120 mux {
1121 pins = "gpio61";
1122 function = "qua_mi2s";
1123 };
1124
1125 config {
1126 pins = "gpio61";
1127 drive-strength = <8>; /* 8 mA */
1128 bias-disable; /* NO PULL */
1129 };
1130 };
1131 };
1132
1133 quat_mi2s_sd2 {
1134 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
1135 mux {
1136 pins = "gpio62";
1137 function = "gpio";
1138 };
1139
1140 config {
1141 pins = "gpio62";
1142 drive-strength = <2>; /* 2 mA */
1143 bias-pull-down; /* PULL DOWN */
1144 input-enable;
1145 };
1146 };
1147
1148 quat_mi2s_sd2_active: quat_mi2s_sd2_active {
1149 mux {
1150 pins = "gpio62";
1151 function = "qua_mi2s";
1152 };
1153
1154 config {
1155 pins = "gpio62";
1156 drive-strength = <8>; /* 8 mA */
1157 bias-disable; /* NO PULL */
1158 };
1159 };
1160 };
1161
1162 quat_mi2s_sd3 {
1163 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
1164 mux {
1165 pins = "gpio63";
1166 function = "gpio";
1167 };
1168
1169 config {
1170 pins = "gpio63";
1171 drive-strength = <2>; /* 2 mA */
1172 bias-pull-down; /* PULL DOWN */
1173 input-enable;
1174 };
1175 };
1176
1177 quat_mi2s_sd3_active: quat_mi2s_sd3_active {
1178 mux {
1179 pins = "gpio63";
1180 function = "qua_mi2s";
1181 };
1182
1183 config {
1184 pins = "gpio63";
1185 drive-strength = <8>; /* 8 mA */
1186 bias-disable; /* NO PULL */
1187 };
1188 };
1189 };
Girish Mahadevan2e2fbe72017-03-28 13:28:18 -06001190
1191 /* QUPv3 South SE mappings */
1192 /* SE 0 pin mappings */
1193 qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
1194 qupv3_se0_i2c_active: qupv3_se0_i2c_active {
1195 mux {
1196 pins = "gpio0", "gpio1";
1197 function = "qup0";
1198 };
1199
1200 config {
1201 pins = "gpio0", "gpio1";
1202 drive-strength = <2>;
1203 bias-disable;
1204 };
1205 };
1206
1207 qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
1208 mux {
1209 pins = "gpio0", "gpio1";
1210 function = "gpio";
1211 };
1212
1213 config {
1214 pins = "gpio0", "gpio1";
1215 drive-strength = <2>;
1216 bias-pull-up;
1217 };
1218 };
1219 };
1220
1221 qupv3_se0_spi_pins: qupv3_se0_spi_pins {
1222 qupv3_se0_spi_active: qupv3_se0_spi_active {
1223 mux {
1224 pins = "gpio0", "gpio1", "gpio2",
1225 "gpio3";
1226 function = "qup0";
1227 };
1228
1229 config {
1230 pins = "gpio0", "gpio1", "gpio2",
1231 "gpio3";
1232 drive-strength = <6>;
1233 bias-disable;
1234 };
1235 };
1236
1237 qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
1238 mux {
1239 pins = "gpio0", "gpio1", "gpio2",
1240 "gpio3";
1241 function = "gpio";
1242 };
1243
1244 config {
1245 pins = "gpio0", "gpio1", "gpio2",
1246 "gpio3";
1247 drive-strength = <6>;
1248 bias-disable;
1249 };
1250 };
1251 };
1252
1253 /* SE 1 pin mappings */
1254 qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
1255 qupv3_se1_i2c_active: qupv3_se1_i2c_active {
1256 mux {
1257 pins = "gpio17", "gpio18";
1258 function = "qup1";
1259 };
1260
1261 config {
1262 pins = "gpio17", "gpio18";
1263 drive-strength = <2>;
1264 bias-disable;
1265 };
1266 };
1267
1268 qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
1269 mux {
1270 pins = "gpio17", "gpio18";
1271 function = "gpio";
1272 };
1273
1274 config {
1275 pins = "gpio17", "gpio18";
1276 drive-strength = <2>;
1277 bias-pull-up;
1278 };
1279 };
1280 };
1281
1282 qupv3_se1_spi_pins: qupv3_se1_spi_pins {
1283 qupv3_se1_spi_active: qupv3_se1_spi_active {
1284 mux {
1285 pins = "gpio17", "gpio18", "gpio19",
1286 "gpio20";
1287 function = "qup1";
1288 };
1289
1290 config {
1291 pins = "gpio17", "gpio18", "gpio19",
1292 "gpio20";
1293 drive-strength = <6>;
1294 bias-disable;
1295 };
1296 };
1297
1298 qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
1299 mux {
1300 pins = "gpio17", "gpio18", "gpio19",
1301 "gpio20";
1302 function = "gpio";
1303 };
1304
1305 config {
1306 pins = "gpio17", "gpio18", "gpio19",
1307 "gpio20";
1308 drive-strength = <6>;
1309 bias-disable;
1310 };
1311 };
1312 };
1313
1314 /* SE 2 pin mappings */
1315 qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
1316 qupv3_se2_i2c_active: qupv3_se2_i2c_active {
1317 mux {
1318 pins = "gpio27", "gpio28";
1319 function = "qup2";
1320 };
1321
1322 config {
1323 pins = "gpio27", "gpio28";
1324 drive-strength = <2>;
1325 bias-disable;
1326 };
1327 };
1328
1329 qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
1330 mux {
1331 pins = "gpio27", "gpio28";
1332 function = "gpio";
1333 };
1334
1335 config {
1336 pins = "gpio27", "gpio28";
1337 drive-strength = <2>;
1338 bias-pull-up;
1339 };
1340 };
1341 };
1342
1343 qupv3_se2_spi_pins: qupv3_se2_spi_pins {
1344 qupv3_se2_spi_active: qupv3_se2_spi_active {
1345 mux {
1346 pins = "gpio27", "gpio28", "gpio29",
1347 "gpio30";
1348 function = "qup2";
1349 };
1350
1351 config {
1352 pins = "gpio27", "gpio28", "gpio29",
1353 "gpio30";
1354 drive-strength = <6>;
1355 bias-disable;
1356 };
1357 };
1358
1359 qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
1360 mux {
1361 pins = "gpio27", "gpio28", "gpio29",
1362 "gpio30";
1363 function = "gpio";
1364 };
1365
1366 config {
1367 pins = "gpio27", "gpio28", "gpio29",
1368 "gpio30";
1369 drive-strength = <6>;
1370 bias-disable;
1371 };
1372 };
1373 };
1374
1375 /* SE 3 pin mappings */
1376 qupv3_se3_i2c_pins: qupv3_se3_i2c_pins {
1377 qupv3_se3_i2c_active: qupv3_se3_i2c_active {
1378 mux {
1379 pins = "gpio41", "gpio42";
1380 function = "qup3";
1381 };
1382
1383 config {
1384 pins = "gpio41", "gpio42";
1385 drive-strength = <2>;
1386 bias-disable;
1387 };
1388 };
1389
1390 qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep {
1391 mux {
1392 pins = "gpio41", "gpio42";
1393 function = "gpio";
1394 };
1395
1396 config {
1397 pins = "gpio41", "gpio42";
1398 drive-strength = <2>;
1399 bias-pull-up;
1400 };
1401 };
1402 };
1403
1404 qupv3_se3_spi_pins: qupv3_se3_spi_pins {
1405 qupv3_se3_spi_active: qupv3_se3_spi_active {
1406 mux {
1407 pins = "gpio41", "gpio42", "gpio43",
1408 "gpio44";
1409 function = "qup3";
1410 };
1411
1412 config {
1413 pins = "gpio41", "gpio42", "gpio43",
1414 "gpio44";
1415 drive-strength = <6>;
1416 bias-disable;
1417 };
1418 };
1419
1420 qupv3_se3_spi_sleep: qupv3_se3_spi_sleep {
1421 mux {
1422 pins = "gpio41", "gpio42", "gpio43",
1423 "gpio44";
1424 function = "gpio";
1425 };
1426
1427 config {
1428 pins = "gpio41", "gpio42", "gpio43",
1429 "gpio44";
1430 drive-strength = <6>;
1431 bias-disable;
1432 };
1433 };
1434 };
1435
1436 /* SE 4 pin mappings */
1437 qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
1438 qupv3_se4_i2c_active: qupv3_se4_i2c_active {
1439 mux {
1440 pins = "gpio89", "gpio90";
1441 function = "qup4";
1442 };
1443
1444 config {
1445 pins = "gpio89", "gpio90";
1446 drive-strength = <2>;
1447 bias-disable;
1448 };
1449 };
1450
1451 qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
1452 mux {
1453 pins = "gpio89", "gpio90";
1454 function = "gpio";
1455 };
1456
1457 config {
1458 pins = "gpio89", "gpio90";
1459 drive-strength = <2>;
1460 bias-pull-up;
1461 };
1462 };
1463 };
1464
1465 qupv3_se4_spi_pins: qupv3_se4_spi_pins {
1466 qupv3_se4_spi_active: qupv3_se4_spi_active {
1467 mux {
1468 pins = "gpio89", "gpio90", "gpio91",
1469 "gpio92";
1470 function = "qup4";
1471 };
1472
1473 config {
1474 pins = "gpio89", "gpio90", "gpio91",
1475 "gpio92";
1476 drive-strength = <6>;
1477 bias-disable;
1478 };
1479 };
1480
1481 qupv3_se4_spi_sleep: qupv3_se4_spi_sleep {
1482 mux {
1483 pins = "gpio89", "gpio90", "gpio91",
1484 "gpio92";
1485 function = "gpio";
1486 };
1487
1488 config {
1489 pins = "gpio89", "gpio90", "gpio91",
1490 "gpio92";
1491 drive-strength = <6>;
1492 bias-disable;
1493 };
1494 };
1495 };
1496
1497 /* SE 5 pin mappings */
1498 qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
1499 qupv3_se5_i2c_active: qupv3_se5_i2c_active {
1500 mux {
1501 pins = "gpio85", "gpio86";
1502 function = "qup5";
1503 };
1504
1505 config {
1506 pins = "gpio85", "gpio86";
1507 drive-strength = <2>;
1508 bias-disable;
1509 };
1510 };
1511
1512 qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
1513 mux {
1514 pins = "gpio85", "gpio86";
1515 function = "gpio";
1516 };
1517
1518 config {
1519 pins = "gpio85", "gpio86";
1520 drive-strength = <2>;
1521 bias-pull-up;
1522 };
1523 };
1524 };
1525
1526 qupv3_se5_spi_pins: qupv3_se5_spi_pins {
1527 qupv3_se5_spi_active: qupv3_se5_spi_active {
1528 mux {
1529 pins = "gpio85", "gpio86", "gpio87",
1530 "gpio88";
1531 function = "qup5";
1532 };
1533
1534 config {
1535 pins = "gpio85", "gpio86", "gpio87",
1536 "gpio88";
1537 drive-strength = <6>;
1538 bias-disable;
1539 };
1540 };
1541
1542 qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
1543 mux {
1544 pins = "gpio85", "gpio86", "gpio87",
1545 "gpio88";
1546 function = "gpio";
1547 };
1548
1549 config {
1550 pins = "gpio85", "gpio86", "gpio87",
1551 "gpio88";
1552 drive-strength = <6>;
1553 bias-disable;
1554 };
1555 };
1556 };
1557
1558 /* SE 6 pin mappings */
1559 qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
1560 qupv3_se6_i2c_active: qupv3_se6_i2c_active {
1561 mux {
1562 pins = "gpio45", "gpio46";
1563 function = "qup6";
1564 };
1565
1566 config {
1567 pins = "gpio45", "gpio46";
1568 drive-strength = <2>;
1569 bias-disable;
1570 };
1571 };
1572
1573 qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
1574 mux {
1575 pins = "gpio45", "gpio46";
1576 function = "gpio";
1577 };
1578
1579 config {
1580 pins = "gpio45", "gpio46";
1581 drive-strength = <2>;
1582 bias-pull-up;
1583 };
1584 };
1585 };
1586
1587 qupv3_se6_4uart_pins: qupv3_se6_4uart_pins {
1588 qupv3_se6_4uart_active: qupv3_se6_4uart_active {
1589 mux {
1590 pins = "gpio45", "gpio46", "gpio47",
1591 "gpio48";
1592 function = "qup6";
1593 };
1594
1595 config {
1596 pins = "gpio45", "gpio46", "gpio47",
1597 "gpio48";
1598 drive-strength = <2>;
1599 bias-disable;
1600 };
1601 };
1602
1603 qupv3_se6_4uart_sleep: qupv3_se6_4uart_sleep {
1604 mux {
1605 pins = "gpio45", "gpio46", "gpio47",
1606 "gpio48";
1607 function = "gpio";
1608 };
1609
1610 config {
1611 pins = "gpio45", "gpio46", "gpio47",
1612 "gpio48";
1613 drive-strength = <2>;
1614 bias-disable;
1615 };
1616 };
1617 };
1618
1619 qupv3_se6_spi_pins: qupv3_se6_spi_pins {
1620 qupv3_se6_spi_active: qupv3_se6_spi_active {
1621 mux {
1622 pins = "gpio45", "gpio46", "gpio47",
1623 "gpio48";
1624 function = "qup6";
1625 };
1626
1627 config {
1628 pins = "gpio45", "gpio46", "gpio47",
1629 "gpio48";
1630 drive-strength = <6>;
1631 bias-disable;
1632 };
1633 };
1634
1635 qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
1636 mux {
1637 pins = "gpio45", "gpio46", "gpio47",
1638 "gpio48";
1639 function = "gpio";
1640 };
1641
1642 config {
1643 pins = "gpio45", "gpio46", "gpio47",
1644 "gpio48";
1645 drive-strength = <6>;
1646 bias-disable;
1647 };
1648 };
1649 };
1650
1651 /* SE 7 pin mappings */
1652 qupv3_se7_i2c_pins: qupv3_se7_i2c_pins {
1653 qupv3_se7_i2c_active: qupv3_se7_i2c_active {
1654 mux {
1655 pins = "gpio93", "gpio94";
1656 function = "qup7";
1657 };
1658
1659 config {
1660 pins = "gpio93", "gpio94";
1661 drive-strength = <2>;
1662 bias-disable;
1663 };
1664 };
1665
1666 qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep {
1667 mux {
1668 pins = "gpio93", "gpio94";
1669 function = "gpio";
1670 };
1671
1672 config {
1673 pins = "gpio93", "gpio94";
1674 drive-strength = <2>;
1675 bias-pull-up;
1676 };
1677 };
1678 };
1679
1680 qupv3_se7_4uart_pins: qupv3_se7_4uart_pins {
1681 qupv3_se7_4uart_active: qupv3_se7_4uart_active {
1682 mux {
1683 pins = "gpio93", "gpio94", "gpio95",
1684 "gpio96";
1685 function = "qup7";
1686 };
1687
1688 config {
1689 pins = "gpio93", "gpio94", "gpio95",
1690 "gpio96";
1691 drive-strength = <2>;
1692 bias-disable;
1693 };
1694 };
1695
1696 qupv3_se7_4uart_sleep: qupv3_se7_4uart_sleep {
1697 mux {
1698 pins = "gpio93", "gpio94", "gpio95",
1699 "gpio96";
1700 function = "gpio";
1701 };
1702
1703 config {
1704 pins = "gpio93", "gpio94", "gpio95",
1705 "gpio96";
1706 drive-strength = <2>;
1707 bias-disable;
1708 };
1709 };
1710 };
1711
1712 qupv3_se7_spi_pins: qupv3_se7_spi_pins {
1713 qupv3_se7_spi_active: qupv3_se7_spi_active {
1714 mux {
1715 pins = "gpio93", "gpio94", "gpio95",
1716 "gpio96";
1717 function = "qup7";
1718 };
1719
1720 config {
1721 pins = "gpio93", "gpio94", "gpio95",
1722 "gpio96";
1723 drive-strength = <6>;
1724 bias-disable;
1725 };
1726 };
1727
1728 qupv3_se7_spi_sleep: qupv3_se7_spi_sleep {
1729 mux {
1730 pins = "gpio93", "gpio94", "gpio95",
1731 "gpio96";
1732 function = "gpio";
1733 };
1734
1735 config {
1736 pins = "gpio93", "gpio94", "gpio95",
1737 "gpio96";
1738 drive-strength = <6>;
1739 bias-disable;
1740 };
1741 };
1742 };
1743
1744 /* QUPv3 North instances */
1745 /* SE 8 pin mappings */
1746 qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
1747 qupv3_se8_i2c_active: qupv3_se8_i2c_active {
1748 mux {
1749 pins = "gpio65", "gpio66";
1750 function = "qup8";
1751 };
1752
1753 config {
1754 pins = "gpio65", "gpio66";
1755 drive-strength = <2>;
1756 bias-disable;
1757 };
1758 };
1759
1760 qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
1761 mux {
1762 pins = "gpio65", "gpio66";
1763 function = "gpio";
1764 };
1765
1766 config {
1767 pins = "gpio65", "gpio66";
1768 drive-strength = <2>;
1769 bias-pull-up;
1770 };
1771 };
1772 };
1773
1774 qupv3_se8_spi_pins: qupv3_se8_spi_pins {
1775 qupv3_se8_spi_active: qupv3_se8_spi_active {
1776 mux {
1777 pins = "gpio65", "gpio66", "gpio67",
1778 "gpio68";
1779 function = "qup8";
1780 };
1781
1782 config {
1783 pins = "gpio65", "gpio66", "gpio67",
1784 "gpio68";
1785 drive-strength = <6>;
1786 bias-disable;
1787 };
1788 };
1789
1790 qupv3_se8_spi_sleep: qupv3_se8_spi_sleep {
1791 mux {
1792 pins = "gpio65", "gpio66", "gpio67",
1793 "gpio68";
1794 function = "gpio";
1795 };
1796
1797 config {
1798 pins = "gpio65", "gpio66", "gpio67",
1799 "gpio68";
1800 drive-strength = <6>;
1801 bias-disable;
1802 };
1803 };
1804 };
1805
1806 /* SE 9 pin mappings */
1807 qupv3_se9_i2c_pins: qupv3_se9_i2c_pins {
1808 qupv3_se9_i2c_active: qupv3_se9_i2c_active {
1809 mux {
1810 pins = "gpio6", "gpio7";
1811 function = "qup9";
1812 };
1813
1814 config {
1815 pins = "gpio6", "gpio7";
1816 drive-strength = <2>;
1817 bias-disable;
1818 };
1819 };
1820
1821 qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep {
1822 mux {
1823 pins = "gpio6", "gpio7";
1824 function = "gpio";
1825 };
1826
1827 config {
1828 pins = "gpio6", "gpio7";
1829 drive-strength = <2>;
1830 bias-pull-up;
1831 };
1832 };
1833 };
1834
1835 qupv3_se9_2uart_pins: qupv3_se9_2uart_pins {
1836 qupv3_se9_2uart_active: qupv3_se9_2uart_active {
1837 mux {
1838 pins = "gpio4", "gpio5";
1839 function = "qup9";
1840 };
1841
1842 config {
1843 pins = "gpio4", "gpio5";
1844 drive-strength = <2>;
1845 bias-disable;
1846 };
1847 };
1848
1849 qupv3_se9_2uart_sleep: qupv3_se9_2uart_sleep {
1850 mux {
1851 pins = "gpio4", "gpio5";
1852 function = "gpio";
1853 };
1854
1855 config {
1856 pins = "gpio4", "gpio5";
1857 drive-strength = <2>;
1858 bias-disable;
1859 };
1860 };
1861 };
1862
1863 qupv3_se9_spi_pins: qupv3_se9_spi_pins {
1864 qupv3_se9_spi_active: qupv3_se9_spi_active {
1865 mux {
1866 pins = "gpio4", "gpio5", "gpio6",
1867 "gpio7";
1868 function = "qup9";
1869 };
1870
1871 config {
1872 pins = "gpio4", "gpio5", "gpio6",
1873 "gpio7";
1874 drive-strength = <6>;
1875 bias-disable;
1876 };
1877 };
1878
1879 qupv3_se9_spi_sleep: qupv3_se9_spi_sleep {
1880 mux {
1881 pins = "gpio4", "gpio5", "gpio6",
1882 "gpio7";
1883 function = "gpio";
1884 };
1885
1886 config {
1887 pins = "gpio4", "gpio5", "gpio6",
1888 "gpio7";
1889 drive-strength = <6>;
1890 bias-disable;
1891 };
1892 };
1893 };
1894
1895 /* SE 10 pin mappings */
1896 qupv3_se10_i2c_pins: qupv3_se10_i2c_pins {
1897 qupv3_se10_i2c_active: qupv3_se10_i2c_active {
1898 mux {
1899 pins = "gpio55", "gpio56";
1900 function = "qup10";
1901 };
1902
1903 config {
1904 pins = "gpio55", "gpio56";
1905 drive-strength = <2>;
1906 bias-disable;
1907 };
1908 };
1909
1910 qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep {
1911 mux {
1912 pins = "gpio55", "gpio56";
1913 function = "gpio";
1914 };
1915
1916 config {
1917 pins = "gpio55", "gpio56";
1918 drive-strength = <2>;
1919 bias-pull-up;
1920 };
1921 };
1922 };
1923
1924 qupv3_se10_2uart_pins: qupv3_se10_2uart_pins {
1925 qupv3_se10_2uart_active: qupv3_se10_2uart_active {
1926 mux {
1927 pins = "gpio53", "gpio54";
1928 function = "qup10";
1929 };
1930
1931 config {
1932 pins = "gpio53", "gpio54";
1933 drive-strength = <2>;
1934 bias-disable;
1935 };
1936 };
1937
1938 qupv3_se10_2uart_sleep: qupv3_se10_2uart_sleep {
1939 mux {
1940 pins = "gpio53", "gpio54";
1941 function = "gpio";
1942 };
1943
1944 config {
1945 pins = "gpio53", "gpio54";
1946 drive-strength = <2>;
1947 bias-disable;
1948 };
1949 };
1950 };
1951
1952 qupv3_se10_spi_pins: qupv3_se10_spi_pins {
1953 qupv3_se10_spi_active: qupv3_se10_spi_active {
1954 mux {
1955 pins = "gpio53", "gpio54", "gpio55",
1956 "gpio56";
1957 function = "qup10";
1958 };
1959
1960 config {
1961 pins = "gpio53", "gpio54", "gpio55",
1962 "gpio56";
1963 drive-strength = <6>;
1964 bias-disable;
1965 };
1966 };
1967
1968 qupv3_se10_spi_sleep: qupv3_se10_spi_sleep {
1969 mux {
1970 pins = "gpio53", "gpio54", "gpio55",
1971 "gpio56";
1972 function = "gpio";
1973 };
1974
1975 config {
1976 pins = "gpio53", "gpio54", "gpio55",
1977 "gpio56";
1978 drive-strength = <6>;
1979 bias-disable;
1980 };
1981 };
1982 };
1983
1984 /* SE 11 pin mappings */
1985 qupv3_se11_i2c_pins: qupv3_se11_i2c_pins {
1986 qupv3_se11_i2c_active: qupv3_se11_i2c_active {
1987 mux {
1988 pins = "gpio31", "gpio32";
1989 function = "qup11";
1990 };
1991
1992 config {
1993 pins = "gpio31", "gpio32";
1994 drive-strength = <2>;
1995 bias-disable;
1996 };
1997 };
1998
1999 qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep {
2000 mux {
2001 pins = "gpio31", "gpio32";
2002 function = "gpio";
2003 };
2004
2005 config {
2006 pins = "gpio31", "gpio32";
2007 drive-strength = <2>;
2008 bias-pull-up;
2009 };
2010 };
2011 };
2012
2013 qupv3_se11_spi_pins: qupv3_se11_spi_pins {
2014 qupv3_se11_spi_active: qupv3_se11_spi_active {
2015 mux {
2016 pins = "gpio31", "gpio32", "gpio33",
2017 "gpio34";
2018 function = "qup11";
2019 };
2020
2021 config {
2022 pins = "gpio31", "gpio32", "gpio33",
2023 "gpio34";
2024 drive-strength = <6>;
2025 bias-disable;
2026 };
2027 };
2028
2029 qupv3_se11_spi_sleep: qupv3_se11_spi_sleep {
2030 mux {
2031 pins = "gpio31", "gpio32", "gpio33",
2032 "gpio34";
2033 function = "gpio";
2034 };
2035
2036 config {
2037 pins = "gpio31", "gpio32", "gpio33",
2038 "gpio34";
2039 drive-strength = <6>;
2040 bias-disable;
2041 };
2042 };
2043 };
2044
2045 /* SE 12 pin mappings */
2046 qupv3_se12_i2c_pins: qupv3_se12_i2c_pins {
2047 qupv3_se12_i2c_active: qupv3_se12_i2c_active {
2048 mux {
2049 pins = "gpio49", "gpio50";
2050 function = "qup12";
2051 };
2052
2053 config {
2054 pins = "gpio49", "gpio50";
2055 drive-strength = <2>;
2056 bias-disable;
2057 };
2058 };
2059
2060 qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep {
2061 mux {
2062 pins = "gpio49", "gpio50";
2063 function = "gpio";
2064 };
2065
2066 config {
2067 pins = "gpio49", "gpio50";
2068 drive-strength = <2>;
2069 bias-pull-up;
2070 };
2071 };
2072 };
2073
2074 qupv3_se12_spi_pins: qupv3_se12_spi_pins {
2075 qupv3_se12_spi_active: qupv3_se12_spi_active {
2076 mux {
2077 pins = "gpio49", "gpio50", "gpio51",
2078 "gpio52";
2079 function = "qup12";
2080 };
2081
2082 config {
2083 pins = "gpio49", "gpio50", "gpio51",
2084 "gpio52";
2085 drive-strength = <6>;
2086 bias-disable;
2087 };
2088 };
2089
2090 qupv3_se12_spi_sleep: qupv3_se12_spi_sleep {
2091 mux {
2092 pins = "gpio49", "gpio50", "gpio51",
2093 "gpio52";
2094 function = "gpio";
2095 };
2096
2097 config {
2098 pins = "gpio49", "gpio50", "gpio51",
2099 "gpio52";
2100 drive-strength = <6>;
2101 bias-disable;
2102 };
2103 };
2104 };
2105
2106 /* SE 13 pin mappings */
2107 qupv3_se13_i2c_pins: qupv3_se13_i2c_pins {
2108 qupv3_se13_i2c_active: qupv3_se13_i2c_active {
2109 mux {
2110 pins = "gpio105", "gpio106";
2111 function = "qup13";
2112 };
2113
2114 config {
2115 pins = "gpio105", "gpio106";
2116 drive-strength = <2>;
2117 bias-disable;
2118 };
2119 };
2120
2121 qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep {
2122 mux {
2123 pins = "gpio105", "gpio106";
2124 function = "gpio";
2125 };
2126
2127 config {
2128 pins = "gpio105", "gpio106";
2129 drive-strength = <2>;
2130 bias-pull-up;
2131 };
2132 };
2133 };
2134
2135 qupv3_se13_spi_pins: qupv3_se13_spi_pins {
2136 qupv3_se13_spi_active: qupv3_se13_spi_active {
2137 mux {
2138 pins = "gpio105", "gpio106", "gpio107",
2139 "gpio108";
2140 function = "qup13";
2141 };
2142
2143 config {
2144 pins = "gpio105", "gpio106", "gpio107",
2145 "gpio108";
2146 drive-strength = <6>;
2147 bias-disable;
2148 };
2149 };
2150
2151 qupv3_se13_spi_sleep: qupv3_se13_spi_sleep {
2152 mux {
2153 pins = "gpio105", "gpio106", "gpio107",
2154 "gpio108";
2155 function = "gpio";
2156 };
2157
2158 config {
2159 pins = "gpio105", "gpio106", "gpio107",
2160 "gpio108";
2161 drive-strength = <6>;
2162 bias-disable;
2163 };
2164 };
2165 };
2166
2167 /* SE 14 pin mappings */
2168 qupv3_se14_i2c_pins: qupv3_se14_i2c_pins {
2169 qupv3_se14_i2c_active: qupv3_se14_i2c_active {
2170 mux {
2171 pins = "gpio33", "gpio34";
2172 function = "qup14";
2173 };
2174
2175 config {
2176 pins = "gpio33", "gpio34";
2177 drive-strength = <2>;
2178 bias-disable;
2179 };
2180 };
2181
2182 qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep {
2183 mux {
2184 pins = "gpio33", "gpio34";
2185 function = "gpio";
2186 };
2187
2188 config {
2189 pins = "gpio33", "gpio34";
2190 drive-strength = <2>;
2191 bias-pull-up;
2192 };
2193 };
2194 };
2195
2196 qupv3_se14_spi_pins: qupv3_se14_spi_pins {
2197 qupv3_se14_spi_active: qupv3_se14_spi_active {
2198 mux {
2199 pins = "gpio31", "gpio32", "gpio33",
2200 "gpio34";
2201 function = "qup14";
2202 };
2203
2204 config {
2205 pins = "gpio31", "gpio32", "gpio33",
2206 "gpio34";
2207 drive-strength = <6>;
2208 bias-disable;
2209 };
2210 };
2211
2212 qupv3_se14_spi_sleep: qupv3_se14_spi_sleep {
2213 mux {
2214 pins = "gpio31", "gpio32", "gpio33",
2215 "gpio34";
2216 function = "gpio";
2217 };
2218
2219 config {
2220 pins = "gpio31", "gpio32", "gpio33",
2221 "gpio34";
2222 drive-strength = <6>;
2223 bias-disable;
2224 };
2225 };
2226 };
2227
2228 /* SE 15 pin mappings */
2229 qupv3_se15_i2c_pins: qupv3_se15_i2c_pins {
2230 qupv3_se15_i2c_active: qupv3_se15_i2c_active {
2231 mux {
2232 pins = "gpio81", "gpio82";
2233 function = "qup15";
2234 };
2235
2236 config {
2237 pins = "gpio81", "gpio82";
2238 drive-strength = <2>;
2239 bias-disable;
2240 };
2241 };
2242
2243 qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep {
2244 mux {
2245 pins = "gpio81", "gpio82";
2246 function = "gpio";
2247 };
2248
2249 config {
2250 pins = "gpio81", "gpio82";
2251 drive-strength = <2>;
2252 bias-pull-up;
2253 };
2254 };
2255 };
2256
2257 qupv3_se15_spi_pins: qupv3_se15_spi_pins {
2258 qupv3_se15_spi_active: qupv3_se15_spi_active {
2259 mux {
2260 pins = "gpio81", "gpio82", "gpio83",
2261 "gpio84";
2262 function = "qup15";
2263 };
2264
2265 config {
2266 pins = "gpio81", "gpio82", "gpio83",
2267 "gpio84";
2268 drive-strength = <6>;
2269 bias-disable;
2270 };
2271 };
2272
2273 qupv3_se15_spi_sleep: qupv3_se15_spi_sleep {
2274 mux {
2275 pins = "gpio81", "gpio82", "gpio83",
2276 "gpio84";
2277 function = "gpio";
2278 };
2279
2280 config {
2281 pins = "gpio81", "gpio82", "gpio83",
2282 "gpio84";
2283 drive-strength = <6>;
2284 bias-disable;
2285 };
2286 };
2287 };
Kyle Yan679cbee2016-07-27 16:55:20 -07002288 };
2289};
David Collinsc6686252017-03-31 14:23:09 -07002290
2291&pm8998_gpios {
2292 key_home {
2293 key_home_default: key_home_default {
2294 pins = "gpio5";
2295 function = "normal";
2296 input-enable;
2297 bias-pull-up;
2298 power-source = <0>;
2299 };
2300 };
2301
2302 key_vol_up {
2303 key_vol_up_default: key_vol_up_default {
2304 pins = "gpio6";
2305 function = "normal";
2306 input-enable;
2307 bias-pull-up;
2308 power-source = <0>;
2309 };
2310 };
2311
2312 key_cam_snapshot {
2313 key_cam_snapshot_default: key_cam_snapshot_default {
2314 pins = "gpio7";
2315 function = "normal";
2316 input-enable;
2317 bias-pull-up;
2318 power-source = <0>;
2319 };
2320 };
2321
2322 key_cam_focus {
2323 key_cam_focus_default: key_cam_focus_default {
2324 pins = "gpio8";
2325 function = "normal";
2326 input-enable;
2327 bias-pull-up;
2328 power-source = <0>;
2329 };
2330 };
2331};
Jack Phamc2160c842017-04-05 09:48:59 -07002332
2333&pmi8998_gpios {
2334 usb2_vbus_boost {
2335 usb2_vbus_boost_default: usb2_vbus_boost_default {
2336 pins = "gpio2";
2337 function = "normal";
2338 output-low;
2339 power-source = <0>;
2340 };
2341 };
2342
2343 usb2_vbus_det {
2344 usb2_vbus_det_default: usb2_vbus_det_default {
2345 pins = "gpio8";
2346 function = "normal";
2347 input-enable;
2348 bias-pull-down;
2349 power-source = <1>; /* VPH input supply */
2350 };
2351 };
2352
2353 usb2_id_det {
2354 usb2_id_det_default: usb2_id_det_default {
2355 pins = "gpio9";
2356 function = "normal";
2357 input-enable;
2358 bias-pull-up;
2359 power-source = <0>;
2360 };
2361 };
2362};