blob: d56066bcbb94f32ccd8d6045843bc41e39254d60 [file] [log] [blame]
Grant Likelyca632f52011-06-06 01:16:30 -06001/*
Jassi Brar230d42d2009-11-30 07:39:42 +00002 * Copyright (C) 2009 Samsung Electronics Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#include <linux/init.h>
21#include <linux/module.h>
22#include <linux/workqueue.h>
Mark Brownc2573122011-11-10 10:57:32 +000023#include <linux/interrupt.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000024#include <linux/delay.h>
25#include <linux/clk.h>
26#include <linux/dma-mapping.h>
27#include <linux/platform_device.h>
28#include <linux/spi/spi.h>
29
30#include <mach/dma.h>
Jassi Brare6b873c2010-01-20 13:49:45 -070031#include <plat/s3c64xx-spi.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000032
33/* Registers and bit-fields */
34
35#define S3C64XX_SPI_CH_CFG 0x00
36#define S3C64XX_SPI_CLK_CFG 0x04
37#define S3C64XX_SPI_MODE_CFG 0x08
38#define S3C64XX_SPI_SLAVE_SEL 0x0C
39#define S3C64XX_SPI_INT_EN 0x10
40#define S3C64XX_SPI_STATUS 0x14
41#define S3C64XX_SPI_TX_DATA 0x18
42#define S3C64XX_SPI_RX_DATA 0x1C
43#define S3C64XX_SPI_PACKET_CNT 0x20
44#define S3C64XX_SPI_PENDING_CLR 0x24
45#define S3C64XX_SPI_SWAP_CFG 0x28
46#define S3C64XX_SPI_FB_CLK 0x2C
47
48#define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
49#define S3C64XX_SPI_CH_SW_RST (1<<5)
50#define S3C64XX_SPI_CH_SLAVE (1<<4)
51#define S3C64XX_SPI_CPOL_L (1<<3)
52#define S3C64XX_SPI_CPHA_B (1<<2)
53#define S3C64XX_SPI_CH_RXCH_ON (1<<1)
54#define S3C64XX_SPI_CH_TXCH_ON (1<<0)
55
56#define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
57#define S3C64XX_SPI_CLKSEL_SRCSHFT 9
58#define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
59#define S3C64XX_SPI_PSR_MASK 0xff
60
61#define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
62#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
63#define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
64#define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
65#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
66#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
67#define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
68#define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
69#define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
70#define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
71#define S3C64XX_SPI_MODE_4BURST (1<<0)
72
73#define S3C64XX_SPI_SLAVE_AUTO (1<<1)
74#define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0)
75
76#define S3C64XX_SPI_ACT(c) writel(0, (c)->regs + S3C64XX_SPI_SLAVE_SEL)
77
78#define S3C64XX_SPI_DEACT(c) writel(S3C64XX_SPI_SLAVE_SIG_INACT, \
79 (c)->regs + S3C64XX_SPI_SLAVE_SEL)
80
81#define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
82#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
83#define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
84#define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
85#define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
86#define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
87#define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
88
89#define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
90#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
91#define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
92#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
93#define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
94#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
95
96#define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
97
98#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
99#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
100#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
101#define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
102#define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
103
104#define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
105#define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
106#define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
107#define S3C64XX_SPI_SWAP_RX_EN (1<<4)
108#define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
109#define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
110#define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
111#define S3C64XX_SPI_SWAP_TX_EN (1<<0)
112
113#define S3C64XX_SPI_FBCLK_MSK (3<<0)
114
115#define S3C64XX_SPI_ST_TRLCNTZ(v, i) ((((v) >> (i)->rx_lvl_offset) & \
116 (((i)->fifo_lvl_mask + 1))) \
117 ? 1 : 0)
118
Padmavathi Venna307574142011-07-05 17:14:02 +0900119#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0)
Jassi Brar230d42d2009-11-30 07:39:42 +0000120#define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask)
121#define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask)
122
123#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
124#define S3C64XX_SPI_TRAILCNT_OFF 19
125
126#define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
127
128#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
129
130#define SUSPND (1<<0)
131#define SPIBUSY (1<<1)
132#define RXBUSY (1<<2)
133#define TXBUSY (1<<3)
134
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900135struct s3c64xx_spi_dma_data {
136 unsigned ch;
137 enum dma_data_direction direction;
138 enum dma_ch dmach;
139};
140
Jassi Brar230d42d2009-11-30 07:39:42 +0000141/**
142 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
143 * @clk: Pointer to the spi clock.
Jassi Brarb0d5d6e2010-01-20 13:49:44 -0700144 * @src_clk: Pointer to the clock used to generate SPI signals.
Jassi Brar230d42d2009-11-30 07:39:42 +0000145 * @master: Pointer to the SPI Protocol master.
146 * @workqueue: Work queue for the SPI xfer requests.
147 * @cntrlr_info: Platform specific data for the controller this driver manages.
148 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
149 * @work: Work
150 * @queue: To log SPI xfer requests.
151 * @lock: Controller specific lock.
152 * @state: Set of FLAGS to indicate status.
153 * @rx_dmach: Controller's DMA channel for Rx.
154 * @tx_dmach: Controller's DMA channel for Tx.
155 * @sfr_start: BUS address of SPI controller regs.
156 * @regs: Pointer to ioremap'ed controller registers.
Mark Brownc2573122011-11-10 10:57:32 +0000157 * @irq: interrupt
Jassi Brar230d42d2009-11-30 07:39:42 +0000158 * @xfer_completion: To indicate completion of xfer task.
159 * @cur_mode: Stores the active configuration of the controller.
160 * @cur_bpw: Stores the active bits per word settings.
161 * @cur_speed: Stores the active xfer clock speed.
162 */
163struct s3c64xx_spi_driver_data {
164 void __iomem *regs;
165 struct clk *clk;
Jassi Brarb0d5d6e2010-01-20 13:49:44 -0700166 struct clk *src_clk;
Jassi Brar230d42d2009-11-30 07:39:42 +0000167 struct platform_device *pdev;
168 struct spi_master *master;
169 struct workqueue_struct *workqueue;
Jassi Brarad7de722010-01-20 13:49:44 -0700170 struct s3c64xx_spi_info *cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +0000171 struct spi_device *tgl_spi;
172 struct work_struct work;
173 struct list_head queue;
174 spinlock_t lock;
Jassi Brar230d42d2009-11-30 07:39:42 +0000175 unsigned long sfr_start;
176 struct completion xfer_completion;
177 unsigned state;
178 unsigned cur_mode, cur_bpw;
179 unsigned cur_speed;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900180 struct s3c64xx_spi_dma_data rx_dma;
181 struct s3c64xx_spi_dma_data tx_dma;
Boojin Kim39d3e802011-09-02 09:44:41 +0900182 struct samsung_dma_ops *ops;
Jassi Brar230d42d2009-11-30 07:39:42 +0000183};
184
185static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
186 .name = "samsung-spi-dma",
187};
188
189static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
190{
Jassi Brarad7de722010-01-20 13:49:44 -0700191 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +0000192 void __iomem *regs = sdd->regs;
193 unsigned long loops;
194 u32 val;
195
196 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
197
198 val = readl(regs + S3C64XX_SPI_CH_CFG);
199 val |= S3C64XX_SPI_CH_SW_RST;
200 val &= ~S3C64XX_SPI_CH_HS_EN;
201 writel(val, regs + S3C64XX_SPI_CH_CFG);
202
203 /* Flush TxFIFO*/
204 loops = msecs_to_loops(1);
205 do {
206 val = readl(regs + S3C64XX_SPI_STATUS);
207 } while (TX_FIFO_LVL(val, sci) && loops--);
208
Mark Brownbe7852a2010-08-23 17:40:56 +0100209 if (loops == 0)
210 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
211
Jassi Brar230d42d2009-11-30 07:39:42 +0000212 /* Flush RxFIFO*/
213 loops = msecs_to_loops(1);
214 do {
215 val = readl(regs + S3C64XX_SPI_STATUS);
216 if (RX_FIFO_LVL(val, sci))
217 readl(regs + S3C64XX_SPI_RX_DATA);
218 else
219 break;
220 } while (loops--);
221
Mark Brownbe7852a2010-08-23 17:40:56 +0100222 if (loops == 0)
223 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
224
Jassi Brar230d42d2009-11-30 07:39:42 +0000225 val = readl(regs + S3C64XX_SPI_CH_CFG);
226 val &= ~S3C64XX_SPI_CH_SW_RST;
227 writel(val, regs + S3C64XX_SPI_CH_CFG);
228
229 val = readl(regs + S3C64XX_SPI_MODE_CFG);
230 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
231 writel(val, regs + S3C64XX_SPI_MODE_CFG);
232
233 val = readl(regs + S3C64XX_SPI_CH_CFG);
234 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
235 writel(val, regs + S3C64XX_SPI_CH_CFG);
236}
237
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900238static void s3c64xx_spi_dmacb(void *data)
Boojin Kim39d3e802011-09-02 09:44:41 +0900239{
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900240 struct s3c64xx_spi_driver_data *sdd;
241 struct s3c64xx_spi_dma_data *dma = data;
Boojin Kim39d3e802011-09-02 09:44:41 +0900242 unsigned long flags;
243
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900244 if (dma->direction == DMA_FROM_DEVICE)
245 sdd = container_of(data,
246 struct s3c64xx_spi_driver_data, rx_dma);
247 else
248 sdd = container_of(data,
249 struct s3c64xx_spi_driver_data, tx_dma);
250
Boojin Kim39d3e802011-09-02 09:44:41 +0900251 spin_lock_irqsave(&sdd->lock, flags);
252
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900253 if (dma->direction == DMA_FROM_DEVICE) {
254 sdd->state &= ~RXBUSY;
255 if (!(sdd->state & TXBUSY))
256 complete(&sdd->xfer_completion);
257 } else {
258 sdd->state &= ~TXBUSY;
259 if (!(sdd->state & RXBUSY))
260 complete(&sdd->xfer_completion);
261 }
Boojin Kim39d3e802011-09-02 09:44:41 +0900262
263 spin_unlock_irqrestore(&sdd->lock, flags);
264}
265
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900266static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
267 unsigned len, dma_addr_t buf)
Boojin Kim39d3e802011-09-02 09:44:41 +0900268{
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900269 struct s3c64xx_spi_driver_data *sdd;
270 struct samsung_dma_prep_info info;
Boojin Kim39d3e802011-09-02 09:44:41 +0900271
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900272 if (dma->direction == DMA_FROM_DEVICE)
273 sdd = container_of((void *)dma,
274 struct s3c64xx_spi_driver_data, rx_dma);
275 else
276 sdd = container_of((void *)dma,
277 struct s3c64xx_spi_driver_data, tx_dma);
Boojin Kim39d3e802011-09-02 09:44:41 +0900278
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900279 info.cap = DMA_SLAVE;
280 info.len = len;
281 info.fp = s3c64xx_spi_dmacb;
282 info.fp_param = dma;
283 info.direction = dma->direction;
284 info.buf = buf;
Boojin Kim39d3e802011-09-02 09:44:41 +0900285
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900286 sdd->ops->prepare(dma->ch, &info);
287 sdd->ops->trigger(dma->ch);
288}
289
290static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
291{
292 struct samsung_dma_info info;
293
294 sdd->ops = samsung_dma_get_ops();
295
296 info.cap = DMA_SLAVE;
297 info.client = &s3c64xx_spi_dma_client;
298 info.width = sdd->cur_bpw / 8;
299
300 info.direction = sdd->rx_dma.direction;
301 info.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
302 sdd->rx_dma.ch = sdd->ops->request(sdd->rx_dma.dmach, &info);
303 info.direction = sdd->tx_dma.direction;
304 info.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
305 sdd->tx_dma.ch = sdd->ops->request(sdd->tx_dma.dmach, &info);
306
307 return 1;
Boojin Kim39d3e802011-09-02 09:44:41 +0900308}
309
Jassi Brar230d42d2009-11-30 07:39:42 +0000310static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
311 struct spi_device *spi,
312 struct spi_transfer *xfer, int dma_mode)
313{
Jassi Brarad7de722010-01-20 13:49:44 -0700314 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +0000315 void __iomem *regs = sdd->regs;
316 u32 modecfg, chcfg;
317
318 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
319 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
320
321 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
322 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
323
324 if (dma_mode) {
325 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
326 } else {
327 /* Always shift in data in FIFO, even if xfer is Tx only,
328 * this helps setting PCKT_CNT value for generating clocks
329 * as exactly needed.
330 */
331 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
332 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
333 | S3C64XX_SPI_PACKET_CNT_EN,
334 regs + S3C64XX_SPI_PACKET_CNT);
335 }
336
337 if (xfer->tx_buf != NULL) {
338 sdd->state |= TXBUSY;
339 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
340 if (dma_mode) {
341 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900342 prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma);
Jassi Brar230d42d2009-11-30 07:39:42 +0000343 } else {
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900344 switch (sdd->cur_bpw) {
345 case 32:
346 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
347 xfer->tx_buf, xfer->len / 4);
348 break;
349 case 16:
350 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
351 xfer->tx_buf, xfer->len / 2);
352 break;
353 default:
354 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
355 xfer->tx_buf, xfer->len);
356 break;
357 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000358 }
359 }
360
361 if (xfer->rx_buf != NULL) {
362 sdd->state |= RXBUSY;
363
364 if (sci->high_speed && sdd->cur_speed >= 30000000UL
365 && !(sdd->cur_mode & SPI_CPHA))
366 chcfg |= S3C64XX_SPI_CH_HS_EN;
367
368 if (dma_mode) {
369 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
370 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
371 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
372 | S3C64XX_SPI_PACKET_CNT_EN,
373 regs + S3C64XX_SPI_PACKET_CNT);
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900374 prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma);
Jassi Brar230d42d2009-11-30 07:39:42 +0000375 }
376 }
377
378 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
379 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
380}
381
382static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
383 struct spi_device *spi)
384{
385 struct s3c64xx_spi_csinfo *cs;
386
387 if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
388 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
389 /* Deselect the last toggled device */
390 cs = sdd->tgl_spi->controller_data;
Jassi Brarfa0fcde2010-01-20 13:49:45 -0700391 cs->set_level(cs->line,
392 spi->mode & SPI_CS_HIGH ? 0 : 1);
Jassi Brar230d42d2009-11-30 07:39:42 +0000393 }
394 sdd->tgl_spi = NULL;
395 }
396
397 cs = spi->controller_data;
Jassi Brarfa0fcde2010-01-20 13:49:45 -0700398 cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
Jassi Brar230d42d2009-11-30 07:39:42 +0000399}
400
401static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
402 struct spi_transfer *xfer, int dma_mode)
403{
Jassi Brarad7de722010-01-20 13:49:44 -0700404 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +0000405 void __iomem *regs = sdd->regs;
406 unsigned long val;
407 int ms;
408
409 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
410 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
Mark Brown9d8f86b2010-09-07 16:37:52 +0100411 ms += 10; /* some tolerance */
Jassi Brar230d42d2009-11-30 07:39:42 +0000412
413 if (dma_mode) {
414 val = msecs_to_jiffies(ms) + 10;
415 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
416 } else {
Jassi Brarc3f139b2010-09-03 10:36:46 +0900417 u32 status;
Jassi Brar230d42d2009-11-30 07:39:42 +0000418 val = msecs_to_loops(ms);
419 do {
Jassi Brarc3f139b2010-09-03 10:36:46 +0900420 status = readl(regs + S3C64XX_SPI_STATUS);
421 } while (RX_FIFO_LVL(status, sci) < xfer->len && --val);
Jassi Brar230d42d2009-11-30 07:39:42 +0000422 }
423
424 if (!val)
425 return -EIO;
426
427 if (dma_mode) {
428 u32 status;
429
430 /*
431 * DmaTx returns after simply writing data in the FIFO,
432 * w/o waiting for real transmission on the bus to finish.
433 * DmaRx returns only after Dma read data from FIFO which
434 * needs bus transmission to finish, so we don't worry if
435 * Xfer involved Rx(with or without Tx).
436 */
437 if (xfer->rx_buf == NULL) {
438 val = msecs_to_loops(10);
439 status = readl(regs + S3C64XX_SPI_STATUS);
440 while ((TX_FIFO_LVL(status, sci)
441 || !S3C64XX_SPI_ST_TX_DONE(status, sci))
442 && --val) {
443 cpu_relax();
444 status = readl(regs + S3C64XX_SPI_STATUS);
445 }
446
447 if (!val)
448 return -EIO;
449 }
450 } else {
Jassi Brar230d42d2009-11-30 07:39:42 +0000451 /* If it was only Tx */
452 if (xfer->rx_buf == NULL) {
453 sdd->state &= ~TXBUSY;
454 return 0;
455 }
456
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900457 switch (sdd->cur_bpw) {
458 case 32:
459 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
460 xfer->rx_buf, xfer->len / 4);
461 break;
462 case 16:
463 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
464 xfer->rx_buf, xfer->len / 2);
465 break;
466 default:
467 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
468 xfer->rx_buf, xfer->len);
469 break;
470 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000471 sdd->state &= ~RXBUSY;
472 }
473
474 return 0;
475}
476
477static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
478 struct spi_device *spi)
479{
480 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
481
482 if (sdd->tgl_spi == spi)
483 sdd->tgl_spi = NULL;
484
Jassi Brarfa0fcde2010-01-20 13:49:45 -0700485 cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
Jassi Brar230d42d2009-11-30 07:39:42 +0000486}
487
488static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
489{
Jassi Brarb42a81c2010-09-29 17:31:33 +0900490 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +0000491 void __iomem *regs = sdd->regs;
492 u32 val;
493
494 /* Disable Clock */
Jassi Brarb42a81c2010-09-29 17:31:33 +0900495 if (sci->clk_from_cmu) {
496 clk_disable(sdd->src_clk);
497 } else {
498 val = readl(regs + S3C64XX_SPI_CLK_CFG);
499 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
500 writel(val, regs + S3C64XX_SPI_CLK_CFG);
501 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000502
503 /* Set Polarity and Phase */
504 val = readl(regs + S3C64XX_SPI_CH_CFG);
505 val &= ~(S3C64XX_SPI_CH_SLAVE |
506 S3C64XX_SPI_CPOL_L |
507 S3C64XX_SPI_CPHA_B);
508
509 if (sdd->cur_mode & SPI_CPOL)
510 val |= S3C64XX_SPI_CPOL_L;
511
512 if (sdd->cur_mode & SPI_CPHA)
513 val |= S3C64XX_SPI_CPHA_B;
514
515 writel(val, regs + S3C64XX_SPI_CH_CFG);
516
517 /* Set Channel & DMA Mode */
518 val = readl(regs + S3C64XX_SPI_MODE_CFG);
519 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
520 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
521
522 switch (sdd->cur_bpw) {
523 case 32:
524 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900525 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
Jassi Brar230d42d2009-11-30 07:39:42 +0000526 break;
527 case 16:
528 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900529 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
Jassi Brar230d42d2009-11-30 07:39:42 +0000530 break;
531 default:
532 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900533 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
Jassi Brar230d42d2009-11-30 07:39:42 +0000534 break;
535 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000536
537 writel(val, regs + S3C64XX_SPI_MODE_CFG);
538
Jassi Brarb42a81c2010-09-29 17:31:33 +0900539 if (sci->clk_from_cmu) {
540 /* Configure Clock */
541 /* There is half-multiplier before the SPI */
542 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
543 /* Enable Clock */
544 clk_enable(sdd->src_clk);
545 } else {
546 /* Configure Clock */
547 val = readl(regs + S3C64XX_SPI_CLK_CFG);
548 val &= ~S3C64XX_SPI_PSR_MASK;
549 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
550 & S3C64XX_SPI_PSR_MASK);
551 writel(val, regs + S3C64XX_SPI_CLK_CFG);
Jassi Brar230d42d2009-11-30 07:39:42 +0000552
Jassi Brarb42a81c2010-09-29 17:31:33 +0900553 /* Enable Clock */
554 val = readl(regs + S3C64XX_SPI_CLK_CFG);
555 val |= S3C64XX_SPI_ENCLK_ENABLE;
556 writel(val, regs + S3C64XX_SPI_CLK_CFG);
557 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000558}
559
Jassi Brar230d42d2009-11-30 07:39:42 +0000560#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
561
562static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
563 struct spi_message *msg)
564{
Jassi Brare02ddd42010-09-29 17:31:31 +0900565 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +0000566 struct device *dev = &sdd->pdev->dev;
567 struct spi_transfer *xfer;
568
569 if (msg->is_dma_mapped)
570 return 0;
571
572 /* First mark all xfer unmapped */
573 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
574 xfer->rx_dma = XFER_DMAADDR_INVALID;
575 xfer->tx_dma = XFER_DMAADDR_INVALID;
576 }
577
578 /* Map until end or first fail */
579 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
580
Jassi Brare02ddd42010-09-29 17:31:31 +0900581 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
582 continue;
583
Jassi Brar230d42d2009-11-30 07:39:42 +0000584 if (xfer->tx_buf != NULL) {
Jassi Brar251ee472010-09-03 10:36:26 +0900585 xfer->tx_dma = dma_map_single(dev,
586 (void *)xfer->tx_buf, xfer->len,
587 DMA_TO_DEVICE);
Jassi Brar230d42d2009-11-30 07:39:42 +0000588 if (dma_mapping_error(dev, xfer->tx_dma)) {
589 dev_err(dev, "dma_map_single Tx failed\n");
590 xfer->tx_dma = XFER_DMAADDR_INVALID;
591 return -ENOMEM;
592 }
593 }
594
595 if (xfer->rx_buf != NULL) {
596 xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
597 xfer->len, DMA_FROM_DEVICE);
598 if (dma_mapping_error(dev, xfer->rx_dma)) {
599 dev_err(dev, "dma_map_single Rx failed\n");
600 dma_unmap_single(dev, xfer->tx_dma,
601 xfer->len, DMA_TO_DEVICE);
602 xfer->tx_dma = XFER_DMAADDR_INVALID;
603 xfer->rx_dma = XFER_DMAADDR_INVALID;
604 return -ENOMEM;
605 }
606 }
607 }
608
609 return 0;
610}
611
612static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
613 struct spi_message *msg)
614{
Jassi Brare02ddd42010-09-29 17:31:31 +0900615 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +0000616 struct device *dev = &sdd->pdev->dev;
617 struct spi_transfer *xfer;
618
619 if (msg->is_dma_mapped)
620 return;
621
622 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
623
Jassi Brare02ddd42010-09-29 17:31:31 +0900624 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
625 continue;
626
Jassi Brar230d42d2009-11-30 07:39:42 +0000627 if (xfer->rx_buf != NULL
628 && xfer->rx_dma != XFER_DMAADDR_INVALID)
629 dma_unmap_single(dev, xfer->rx_dma,
630 xfer->len, DMA_FROM_DEVICE);
631
632 if (xfer->tx_buf != NULL
633 && xfer->tx_dma != XFER_DMAADDR_INVALID)
634 dma_unmap_single(dev, xfer->tx_dma,
635 xfer->len, DMA_TO_DEVICE);
636 }
637}
638
639static void handle_msg(struct s3c64xx_spi_driver_data *sdd,
640 struct spi_message *msg)
641{
Jassi Brarad7de722010-01-20 13:49:44 -0700642 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +0000643 struct spi_device *spi = msg->spi;
644 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
645 struct spi_transfer *xfer;
646 int status = 0, cs_toggle = 0;
647 u32 speed;
648 u8 bpw;
649
650 /* If Master's(controller) state differs from that needed by Slave */
651 if (sdd->cur_speed != spi->max_speed_hz
652 || sdd->cur_mode != spi->mode
653 || sdd->cur_bpw != spi->bits_per_word) {
654 sdd->cur_bpw = spi->bits_per_word;
655 sdd->cur_speed = spi->max_speed_hz;
656 sdd->cur_mode = spi->mode;
657 s3c64xx_spi_config(sdd);
658 }
659
660 /* Map all the transfers if needed */
661 if (s3c64xx_spi_map_mssg(sdd, msg)) {
662 dev_err(&spi->dev,
663 "Xfer: Unable to map message buffers!\n");
664 status = -ENOMEM;
665 goto out;
666 }
667
668 /* Configure feedback delay */
669 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
670
671 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
672
673 unsigned long flags;
674 int use_dma;
675
676 INIT_COMPLETION(sdd->xfer_completion);
677
678 /* Only BPW and Speed may change across transfers */
679 bpw = xfer->bits_per_word ? : spi->bits_per_word;
680 speed = xfer->speed_hz ? : spi->max_speed_hz;
681
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900682 if (xfer->len % (bpw / 8)) {
683 dev_err(&spi->dev,
684 "Xfer length(%u) not a multiple of word size(%u)\n",
685 xfer->len, bpw / 8);
686 status = -EIO;
687 goto out;
688 }
689
Jassi Brar230d42d2009-11-30 07:39:42 +0000690 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
691 sdd->cur_bpw = bpw;
692 sdd->cur_speed = speed;
693 s3c64xx_spi_config(sdd);
694 }
695
696 /* Polling method for xfers not bigger than FIFO capacity */
697 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
698 use_dma = 0;
699 else
700 use_dma = 1;
701
702 spin_lock_irqsave(&sdd->lock, flags);
703
704 /* Pending only which is to be done */
705 sdd->state &= ~RXBUSY;
706 sdd->state &= ~TXBUSY;
707
708 enable_datapath(sdd, spi, xfer, use_dma);
709
710 /* Slave Select */
711 enable_cs(sdd, spi);
712
713 /* Start the signals */
714 S3C64XX_SPI_ACT(sdd);
715
716 spin_unlock_irqrestore(&sdd->lock, flags);
717
718 status = wait_for_xfer(sdd, xfer, use_dma);
719
720 /* Quiese the signals */
721 S3C64XX_SPI_DEACT(sdd);
722
723 if (status) {
Joe Perches8a349d42010-02-02 07:22:13 +0000724 dev_err(&spi->dev, "I/O Error: "
725 "rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
Jassi Brar230d42d2009-11-30 07:39:42 +0000726 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
727 (sdd->state & RXBUSY) ? 'f' : 'p',
728 (sdd->state & TXBUSY) ? 'f' : 'p',
729 xfer->len);
730
731 if (use_dma) {
732 if (xfer->tx_buf != NULL
733 && (sdd->state & TXBUSY))
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900734 sdd->ops->stop(sdd->tx_dma.ch);
Jassi Brar230d42d2009-11-30 07:39:42 +0000735 if (xfer->rx_buf != NULL
736 && (sdd->state & RXBUSY))
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900737 sdd->ops->stop(sdd->rx_dma.ch);
Jassi Brar230d42d2009-11-30 07:39:42 +0000738 }
739
740 goto out;
741 }
742
743 if (xfer->delay_usecs)
744 udelay(xfer->delay_usecs);
745
746 if (xfer->cs_change) {
747 /* Hint that the next mssg is gonna be
748 for the same device */
749 if (list_is_last(&xfer->transfer_list,
750 &msg->transfers))
751 cs_toggle = 1;
752 else
753 disable_cs(sdd, spi);
754 }
755
756 msg->actual_length += xfer->len;
757
758 flush_fifo(sdd);
759 }
760
761out:
762 if (!cs_toggle || status)
763 disable_cs(sdd, spi);
764 else
765 sdd->tgl_spi = spi;
766
767 s3c64xx_spi_unmap_mssg(sdd, msg);
768
769 msg->status = status;
770
771 if (msg->complete)
772 msg->complete(msg->context);
773}
774
Jassi Brar230d42d2009-11-30 07:39:42 +0000775static void s3c64xx_spi_work(struct work_struct *work)
776{
777 struct s3c64xx_spi_driver_data *sdd = container_of(work,
778 struct s3c64xx_spi_driver_data, work);
779 unsigned long flags;
780
781 /* Acquire DMA channels */
782 while (!acquire_dma(sdd))
783 msleep(10);
784
785 spin_lock_irqsave(&sdd->lock, flags);
786
787 while (!list_empty(&sdd->queue)
788 && !(sdd->state & SUSPND)) {
789
790 struct spi_message *msg;
791
792 msg = container_of(sdd->queue.next, struct spi_message, queue);
793
794 list_del_init(&msg->queue);
795
796 /* Set Xfer busy flag */
797 sdd->state |= SPIBUSY;
798
799 spin_unlock_irqrestore(&sdd->lock, flags);
800
801 handle_msg(sdd, msg);
802
803 spin_lock_irqsave(&sdd->lock, flags);
804
805 sdd->state &= ~SPIBUSY;
806 }
807
808 spin_unlock_irqrestore(&sdd->lock, flags);
809
810 /* Free DMA channels */
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900811 sdd->ops->release(sdd->rx_dma.ch, &s3c64xx_spi_dma_client);
812 sdd->ops->release(sdd->tx_dma.ch, &s3c64xx_spi_dma_client);
Jassi Brar230d42d2009-11-30 07:39:42 +0000813}
814
815static int s3c64xx_spi_transfer(struct spi_device *spi,
816 struct spi_message *msg)
817{
818 struct s3c64xx_spi_driver_data *sdd;
819 unsigned long flags;
820
821 sdd = spi_master_get_devdata(spi->master);
822
823 spin_lock_irqsave(&sdd->lock, flags);
824
825 if (sdd->state & SUSPND) {
826 spin_unlock_irqrestore(&sdd->lock, flags);
827 return -ESHUTDOWN;
828 }
829
830 msg->status = -EINPROGRESS;
831 msg->actual_length = 0;
832
833 list_add_tail(&msg->queue, &sdd->queue);
834
835 queue_work(sdd->workqueue, &sdd->work);
836
837 spin_unlock_irqrestore(&sdd->lock, flags);
838
839 return 0;
840}
841
842/*
843 * Here we only check the validity of requested configuration
844 * and save the configuration in a local data-structure.
845 * The controller is actually configured only just before we
846 * get a message to transfer.
847 */
848static int s3c64xx_spi_setup(struct spi_device *spi)
849{
850 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
851 struct s3c64xx_spi_driver_data *sdd;
Jassi Brarad7de722010-01-20 13:49:44 -0700852 struct s3c64xx_spi_info *sci;
Jassi Brar230d42d2009-11-30 07:39:42 +0000853 struct spi_message *msg;
Jassi Brar230d42d2009-11-30 07:39:42 +0000854 unsigned long flags;
855 int err = 0;
856
857 if (cs == NULL || cs->set_level == NULL) {
858 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
859 return -ENODEV;
860 }
861
862 sdd = spi_master_get_devdata(spi->master);
863 sci = sdd->cntrlr_info;
864
865 spin_lock_irqsave(&sdd->lock, flags);
866
867 list_for_each_entry(msg, &sdd->queue, queue) {
868 /* Is some mssg is already queued for this device */
869 if (msg->spi == spi) {
870 dev_err(&spi->dev,
871 "setup: attempt while mssg in queue!\n");
872 spin_unlock_irqrestore(&sdd->lock, flags);
873 return -EBUSY;
874 }
875 }
876
877 if (sdd->state & SUSPND) {
878 spin_unlock_irqrestore(&sdd->lock, flags);
879 dev_err(&spi->dev,
880 "setup: SPI-%d not active!\n", spi->master->bus_num);
881 return -ESHUTDOWN;
882 }
883
884 spin_unlock_irqrestore(&sdd->lock, flags);
885
886 if (spi->bits_per_word != 8
887 && spi->bits_per_word != 16
888 && spi->bits_per_word != 32) {
889 dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n",
890 spi->bits_per_word);
891 err = -EINVAL;
892 goto setup_exit;
893 }
894
895 /* Check if we can provide the requested rate */
Jassi Brarb42a81c2010-09-29 17:31:33 +0900896 if (!sci->clk_from_cmu) {
897 u32 psr, speed;
Jassi Brar230d42d2009-11-30 07:39:42 +0000898
Jassi Brarb42a81c2010-09-29 17:31:33 +0900899 /* Max possible */
900 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
Jassi Brar230d42d2009-11-30 07:39:42 +0000901
Jassi Brarb42a81c2010-09-29 17:31:33 +0900902 if (spi->max_speed_hz > speed)
903 spi->max_speed_hz = speed;
Jassi Brar230d42d2009-11-30 07:39:42 +0000904
Jassi Brarb42a81c2010-09-29 17:31:33 +0900905 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
906 psr &= S3C64XX_SPI_PSR_MASK;
907 if (psr == S3C64XX_SPI_PSR_MASK)
908 psr--;
909
910 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
911 if (spi->max_speed_hz < speed) {
912 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
913 psr++;
914 } else {
915 err = -EINVAL;
916 goto setup_exit;
917 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000918 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000919
Jassi Brarb42a81c2010-09-29 17:31:33 +0900920 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
921 if (spi->max_speed_hz >= speed)
922 spi->max_speed_hz = speed;
923 else
924 err = -EINVAL;
925 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000926
927setup_exit:
928
929 /* setup() returns with device de-selected */
930 disable_cs(sdd, spi);
931
932 return err;
933}
934
Mark Brownc2573122011-11-10 10:57:32 +0000935static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
936{
937 struct s3c64xx_spi_driver_data *sdd = data;
938 struct spi_master *spi = sdd->master;
939 unsigned int val;
940
941 val = readl(sdd->regs + S3C64XX_SPI_PENDING_CLR);
942
943 val &= S3C64XX_SPI_PND_RX_OVERRUN_CLR |
944 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
945 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
946 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
947
948 writel(val, sdd->regs + S3C64XX_SPI_PENDING_CLR);
949
950 if (val & S3C64XX_SPI_PND_RX_OVERRUN_CLR)
951 dev_err(&spi->dev, "RX overrun\n");
952 if (val & S3C64XX_SPI_PND_RX_UNDERRUN_CLR)
953 dev_err(&spi->dev, "RX underrun\n");
954 if (val & S3C64XX_SPI_PND_TX_OVERRUN_CLR)
955 dev_err(&spi->dev, "TX overrun\n");
956 if (val & S3C64XX_SPI_PND_TX_UNDERRUN_CLR)
957 dev_err(&spi->dev, "TX underrun\n");
958
959 return IRQ_HANDLED;
960}
961
Jassi Brar230d42d2009-11-30 07:39:42 +0000962static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
963{
Jassi Brarad7de722010-01-20 13:49:44 -0700964 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +0000965 void __iomem *regs = sdd->regs;
966 unsigned int val;
967
968 sdd->cur_speed = 0;
969
970 S3C64XX_SPI_DEACT(sdd);
971
972 /* Disable Interrupts - we use Polling if not DMA mode */
973 writel(0, regs + S3C64XX_SPI_INT_EN);
974
Jassi Brarb42a81c2010-09-29 17:31:33 +0900975 if (!sci->clk_from_cmu)
976 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
Jassi Brar230d42d2009-11-30 07:39:42 +0000977 regs + S3C64XX_SPI_CLK_CFG);
978 writel(0, regs + S3C64XX_SPI_MODE_CFG);
979 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
980
981 /* Clear any irq pending bits */
982 writel(readl(regs + S3C64XX_SPI_PENDING_CLR),
983 regs + S3C64XX_SPI_PENDING_CLR);
984
985 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
986
987 val = readl(regs + S3C64XX_SPI_MODE_CFG);
988 val &= ~S3C64XX_SPI_MODE_4BURST;
989 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
990 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
991 writel(val, regs + S3C64XX_SPI_MODE_CFG);
992
993 flush_fifo(sdd);
994}
995
996static int __init s3c64xx_spi_probe(struct platform_device *pdev)
997{
998 struct resource *mem_res, *dmatx_res, *dmarx_res;
999 struct s3c64xx_spi_driver_data *sdd;
Jassi Brarad7de722010-01-20 13:49:44 -07001000 struct s3c64xx_spi_info *sci;
Jassi Brar230d42d2009-11-30 07:39:42 +00001001 struct spi_master *master;
Mark Brownc2573122011-11-10 10:57:32 +00001002 int ret, irq;
1003 char clk_name[16];
Jassi Brar230d42d2009-11-30 07:39:42 +00001004
1005 if (pdev->id < 0) {
1006 dev_err(&pdev->dev,
1007 "Invalid platform device id-%d\n", pdev->id);
1008 return -ENODEV;
1009 }
1010
1011 if (pdev->dev.platform_data == NULL) {
1012 dev_err(&pdev->dev, "platform_data missing!\n");
1013 return -ENODEV;
1014 }
1015
Mark Browncc0fc0b2010-09-01 08:55:22 -06001016 sci = pdev->dev.platform_data;
1017 if (!sci->src_clk_name) {
1018 dev_err(&pdev->dev,
1019 "Board init must call s3c64xx_spi_set_info()\n");
1020 return -EINVAL;
1021 }
1022
Jassi Brar230d42d2009-11-30 07:39:42 +00001023 /* Check for availability of necessary resource */
1024
1025 dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1026 if (dmatx_res == NULL) {
1027 dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n");
1028 return -ENXIO;
1029 }
1030
1031 dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1032 if (dmarx_res == NULL) {
1033 dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n");
1034 return -ENXIO;
1035 }
1036
1037 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1038 if (mem_res == NULL) {
1039 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1040 return -ENXIO;
1041 }
1042
Mark Brownc2573122011-11-10 10:57:32 +00001043 irq = platform_get_irq(pdev, 0);
1044 if (irq < 0) {
1045 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1046 return irq;
1047 }
1048
Jassi Brar230d42d2009-11-30 07:39:42 +00001049 master = spi_alloc_master(&pdev->dev,
1050 sizeof(struct s3c64xx_spi_driver_data));
1051 if (master == NULL) {
1052 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1053 return -ENOMEM;
1054 }
1055
Jassi Brar230d42d2009-11-30 07:39:42 +00001056 platform_set_drvdata(pdev, master);
1057
1058 sdd = spi_master_get_devdata(master);
1059 sdd->master = master;
1060 sdd->cntrlr_info = sci;
1061 sdd->pdev = pdev;
1062 sdd->sfr_start = mem_res->start;
Boojin Kim82ab8cd2011-09-02 09:44:42 +09001063 sdd->tx_dma.dmach = dmatx_res->start;
1064 sdd->tx_dma.direction = DMA_TO_DEVICE;
1065 sdd->rx_dma.dmach = dmarx_res->start;
1066 sdd->rx_dma.direction = DMA_FROM_DEVICE;
Jassi Brar230d42d2009-11-30 07:39:42 +00001067
1068 sdd->cur_bpw = 8;
1069
1070 master->bus_num = pdev->id;
1071 master->setup = s3c64xx_spi_setup;
1072 master->transfer = s3c64xx_spi_transfer;
1073 master->num_chipselect = sci->num_cs;
1074 master->dma_alignment = 8;
1075 /* the spi->mode bits understood by this driver: */
1076 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1077
1078 if (request_mem_region(mem_res->start,
1079 resource_size(mem_res), pdev->name) == NULL) {
1080 dev_err(&pdev->dev, "Req mem region failed\n");
1081 ret = -ENXIO;
1082 goto err0;
1083 }
1084
1085 sdd->regs = ioremap(mem_res->start, resource_size(mem_res));
1086 if (sdd->regs == NULL) {
1087 dev_err(&pdev->dev, "Unable to remap IO\n");
1088 ret = -ENXIO;
1089 goto err1;
1090 }
1091
1092 if (sci->cfg_gpio == NULL || sci->cfg_gpio(pdev)) {
1093 dev_err(&pdev->dev, "Unable to config gpio\n");
1094 ret = -EBUSY;
1095 goto err2;
1096 }
1097
1098 /* Setup clocks */
1099 sdd->clk = clk_get(&pdev->dev, "spi");
1100 if (IS_ERR(sdd->clk)) {
1101 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1102 ret = PTR_ERR(sdd->clk);
1103 goto err3;
1104 }
1105
1106 if (clk_enable(sdd->clk)) {
1107 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1108 ret = -EBUSY;
1109 goto err4;
1110 }
1111
Jassi Brarb0d5d6e2010-01-20 13:49:44 -07001112 sdd->src_clk = clk_get(&pdev->dev, sci->src_clk_name);
1113 if (IS_ERR(sdd->src_clk)) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001114 dev_err(&pdev->dev,
1115 "Unable to acquire clock '%s'\n", sci->src_clk_name);
Jassi Brarb0d5d6e2010-01-20 13:49:44 -07001116 ret = PTR_ERR(sdd->src_clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001117 goto err5;
1118 }
1119
Jassi Brarb0d5d6e2010-01-20 13:49:44 -07001120 if (clk_enable(sdd->src_clk)) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001121 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n",
1122 sci->src_clk_name);
1123 ret = -EBUSY;
1124 goto err6;
1125 }
1126
1127 sdd->workqueue = create_singlethread_workqueue(
1128 dev_name(master->dev.parent));
1129 if (sdd->workqueue == NULL) {
1130 dev_err(&pdev->dev, "Unable to create workqueue\n");
1131 ret = -ENOMEM;
1132 goto err7;
1133 }
1134
1135 /* Setup Deufult Mode */
1136 s3c64xx_spi_hwinit(sdd, pdev->id);
1137
1138 spin_lock_init(&sdd->lock);
1139 init_completion(&sdd->xfer_completion);
1140 INIT_WORK(&sdd->work, s3c64xx_spi_work);
1141 INIT_LIST_HEAD(&sdd->queue);
1142
Mark Brownc2573122011-11-10 10:57:32 +00001143 ret = request_irq(irq, s3c64xx_spi_irq, 0, "spi-s3c64xx", sdd);
1144 if (ret != 0) {
1145 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1146 irq, ret);
1147 goto err8;
1148 }
1149
1150 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1151 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1152 sdd->regs + S3C64XX_SPI_INT_EN);
1153
Jassi Brar230d42d2009-11-30 07:39:42 +00001154 if (spi_register_master(master)) {
1155 dev_err(&pdev->dev, "cannot register SPI master\n");
1156 ret = -EBUSY;
Mark Brownc2573122011-11-10 10:57:32 +00001157 goto err9;
Jassi Brar230d42d2009-11-30 07:39:42 +00001158 }
1159
Joe Perches8a349d42010-02-02 07:22:13 +00001160 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d "
1161 "with %d Slaves attached\n",
Jassi Brar230d42d2009-11-30 07:39:42 +00001162 pdev->id, master->num_chipselect);
Joe Perches8a349d42010-02-02 07:22:13 +00001163 dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
Jassi Brar230d42d2009-11-30 07:39:42 +00001164 mem_res->end, mem_res->start,
Boojin Kim82ab8cd2011-09-02 09:44:42 +09001165 sdd->rx_dma.dmach, sdd->tx_dma.dmach);
Jassi Brar230d42d2009-11-30 07:39:42 +00001166
1167 return 0;
1168
Mark Brownc2573122011-11-10 10:57:32 +00001169err9:
1170 free_irq(irq, sdd);
Jassi Brar230d42d2009-11-30 07:39:42 +00001171err8:
1172 destroy_workqueue(sdd->workqueue);
1173err7:
Jassi Brarb0d5d6e2010-01-20 13:49:44 -07001174 clk_disable(sdd->src_clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001175err6:
Jassi Brarb0d5d6e2010-01-20 13:49:44 -07001176 clk_put(sdd->src_clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001177err5:
1178 clk_disable(sdd->clk);
1179err4:
1180 clk_put(sdd->clk);
1181err3:
1182err2:
1183 iounmap((void *) sdd->regs);
1184err1:
1185 release_mem_region(mem_res->start, resource_size(mem_res));
1186err0:
1187 platform_set_drvdata(pdev, NULL);
1188 spi_master_put(master);
1189
1190 return ret;
1191}
1192
1193static int s3c64xx_spi_remove(struct platform_device *pdev)
1194{
1195 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1196 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001197 struct resource *mem_res;
1198 unsigned long flags;
1199
1200 spin_lock_irqsave(&sdd->lock, flags);
1201 sdd->state |= SUSPND;
1202 spin_unlock_irqrestore(&sdd->lock, flags);
1203
1204 while (sdd->state & SPIBUSY)
1205 msleep(10);
1206
1207 spi_unregister_master(master);
1208
Mark Brownc2573122011-11-10 10:57:32 +00001209 writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1210
1211 free_irq(platform_get_irq(pdev, 0), sdd);
1212
Jassi Brar230d42d2009-11-30 07:39:42 +00001213 destroy_workqueue(sdd->workqueue);
1214
Jassi Brarb0d5d6e2010-01-20 13:49:44 -07001215 clk_disable(sdd->src_clk);
1216 clk_put(sdd->src_clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001217
1218 clk_disable(sdd->clk);
1219 clk_put(sdd->clk);
1220
1221 iounmap((void *) sdd->regs);
1222
1223 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Jassi Braref6c6802010-01-20 13:49:44 -07001224 if (mem_res != NULL)
1225 release_mem_region(mem_res->start, resource_size(mem_res));
Jassi Brar230d42d2009-11-30 07:39:42 +00001226
1227 platform_set_drvdata(pdev, NULL);
1228 spi_master_put(master);
1229
1230 return 0;
1231}
1232
1233#ifdef CONFIG_PM
1234static int s3c64xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1235{
1236 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1237 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001238 unsigned long flags;
1239
1240 spin_lock_irqsave(&sdd->lock, flags);
1241 sdd->state |= SUSPND;
1242 spin_unlock_irqrestore(&sdd->lock, flags);
1243
1244 while (sdd->state & SPIBUSY)
1245 msleep(10);
1246
1247 /* Disable the clock */
Jassi Brarb0d5d6e2010-01-20 13:49:44 -07001248 clk_disable(sdd->src_clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001249 clk_disable(sdd->clk);
1250
1251 sdd->cur_speed = 0; /* Output Clock is stopped */
1252
1253 return 0;
1254}
1255
1256static int s3c64xx_spi_resume(struct platform_device *pdev)
1257{
1258 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1259 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brarad7de722010-01-20 13:49:44 -07001260 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +00001261 unsigned long flags;
1262
1263 sci->cfg_gpio(pdev);
1264
1265 /* Enable the clock */
Jassi Brarb0d5d6e2010-01-20 13:49:44 -07001266 clk_enable(sdd->src_clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001267 clk_enable(sdd->clk);
1268
1269 s3c64xx_spi_hwinit(sdd, pdev->id);
1270
1271 spin_lock_irqsave(&sdd->lock, flags);
1272 sdd->state &= ~SUSPND;
1273 spin_unlock_irqrestore(&sdd->lock, flags);
1274
1275 return 0;
1276}
1277#else
1278#define s3c64xx_spi_suspend NULL
1279#define s3c64xx_spi_resume NULL
1280#endif /* CONFIG_PM */
1281
1282static struct platform_driver s3c64xx_spi_driver = {
1283 .driver = {
1284 .name = "s3c64xx-spi",
1285 .owner = THIS_MODULE,
1286 },
1287 .remove = s3c64xx_spi_remove,
1288 .suspend = s3c64xx_spi_suspend,
1289 .resume = s3c64xx_spi_resume,
1290};
1291MODULE_ALIAS("platform:s3c64xx-spi");
1292
1293static int __init s3c64xx_spi_init(void)
1294{
1295 return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
1296}
Mark Brownd2a787f2010-09-07 11:29:17 +01001297subsys_initcall(s3c64xx_spi_init);
Jassi Brar230d42d2009-11-30 07:39:42 +00001298
1299static void __exit s3c64xx_spi_exit(void)
1300{
1301 platform_driver_unregister(&s3c64xx_spi_driver);
1302}
1303module_exit(s3c64xx_spi_exit);
1304
1305MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1306MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1307MODULE_LICENSE("GPL");