blob: 58a0ab4923ee64013886fc056a1e63c0fa1192f5 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001
Jeff Garzik6aa20a22006-09-13 13:24:59 -04002/* Advanced Micro Devices Inc. AMD8111E Linux Network Driver
3 * Copyright (C) 2004 Advanced Micro Devices
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 *
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
7 * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
8 * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
9 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
10 * Copyright 1993 United States Government as represented by the
11 * Director, National Security Agency.[ pcnet32.c ]
12 * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
13 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
14 *
Jeff Garzik6aa20a22006-09-13 13:24:59 -040015 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070016 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
Jeff Garzik6aa20a22006-09-13 13:24:59 -040028 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
Linus Torvalds1da177e2005-04-16 15:20:36 -070029 * USA
Jeff Garzik6aa20a22006-09-13 13:24:59 -040030
Linus Torvalds1da177e2005-04-16 15:20:36 -070031Module Name:
32
33 amd8111e.c
34
35Abstract:
Jeff Garzik6aa20a22006-09-13 13:24:59 -040036
37 AMD8111 based 10/100 Ethernet Controller Driver.
Linus Torvalds1da177e2005-04-16 15:20:36 -070038
39Environment:
40
41 Kernel Mode
42
43Revision History:
44 3.0.0
45 Initial Revision.
46 3.0.1
47 1. Dynamic interrupt coalescing.
48 2. Removed prev_stats.
49 3. MII support.
50 4. Dynamic IPG support
51 3.0.2 05/29/2003
52 1. Bug fix: Fixed failure to send jumbo packets larger than 4k.
53 2. Bug fix: Fixed VLAN support failure.
54 3. Bug fix: Fixed receive interrupt coalescing bug.
55 4. Dynamic IPG support is disabled by default.
56 3.0.3 06/05/2003
57 1. Bug fix: Fixed failure to close the interface if SMP is enabled.
58 3.0.4 12/09/2003
59 1. Added set_mac_address routine for bonding driver support.
60 2. Tested the driver for bonding support
Jeff Garzik6aa20a22006-09-13 13:24:59 -040061 3. Bug fix: Fixed mismach in actual receive buffer lenth and lenth
Linus Torvalds1da177e2005-04-16 15:20:36 -070062 indicated to the h/w.
Jeff Garzik6aa20a22006-09-13 13:24:59 -040063 4. Modified amd8111e_rx() routine to receive all the received packets
Linus Torvalds1da177e2005-04-16 15:20:36 -070064 in the first interrupt.
65 5. Bug fix: Corrected rx_errors reported in get_stats() function.
66 3.0.5 03/22/2004
Jeff Garzik6aa20a22006-09-13 13:24:59 -040067 1. Added NAPI support
Linus Torvalds1da177e2005-04-16 15:20:36 -070068
69*/
70
71
Linus Torvalds1da177e2005-04-16 15:20:36 -070072#include <linux/module.h>
73#include <linux/kernel.h>
74#include <linux/types.h>
75#include <linux/compiler.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070076#include <linux/delay.h>
77#include <linux/init.h>
78#include <linux/ioport.h>
79#include <linux/pci.h>
80#include <linux/netdevice.h>
81#include <linux/etherdevice.h>
82#include <linux/skbuff.h>
83#include <linux/ethtool.h>
84#include <linux/mii.h>
85#include <linux/if_vlan.h>
Jeff Garzik6aa20a22006-09-13 13:24:59 -040086#include <linux/ctype.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070087#include <linux/crc32.h>
Tobias Klausercac8c812005-05-16 19:15:11 +020088#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070089
90#include <asm/system.h>
91#include <asm/io.h>
92#include <asm/byteorder.h>
93#include <asm/uaccess.h>
94
95#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
96#define AMD8111E_VLAN_TAG_USED 1
97#else
98#define AMD8111E_VLAN_TAG_USED 0
99#endif
100
101#include "amd8111e.h"
102#define MODULE_NAME "amd8111e"
Francois Romieu6ba33ac2008-07-06 20:55:12 -0700103#define MODULE_VERS "3.0.7"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104MODULE_AUTHOR("Advanced Micro Devices, Inc.");
Francois Romieu6ba33ac2008-07-06 20:55:12 -0700105MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version "MODULE_VERS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106MODULE_LICENSE("GPL");
107MODULE_DEVICE_TABLE(pci, amd8111e_pci_tbl);
108module_param_array(speed_duplex, int, NULL, 0);
109MODULE_PARM_DESC(speed_duplex, "Set device speed and duplex modes, 0: Auto Negotitate, 1: 10Mbps Half Duplex, 2: 10Mbps Full Duplex, 3: 100Mbps Half Duplex, 4: 100Mbps Full Duplex");
110module_param_array(coalesce, bool, NULL, 0);
111MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0: Disable");
112module_param_array(dynamic_ipg, bool, NULL, 0);
113MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable");
114
Alexey Dobriyana3aa1882010-01-07 11:58:11 +0000115static DEFINE_PCI_DEVICE_TABLE(amd8111e_pci_tbl) = {
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400116
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD8111E_7462,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
119 { 0, }
120
121};
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400122/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123This function will read the PHY registers.
124*/
125static int amd8111e_read_phy(struct amd8111e_priv* lp, int phy_id, int reg, u32* val)
126{
127 void __iomem *mmio = lp->mmio;
128 unsigned int reg_val;
129 unsigned int repeat= REPEAT_CNT;
130
131 reg_val = readl(mmio + PHY_ACCESS);
132 while (reg_val & PHY_CMD_ACTIVE)
133 reg_val = readl( mmio + PHY_ACCESS );
134
135 writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) |
136 ((reg & 0x1f) << 16), mmio +PHY_ACCESS);
137 do{
138 reg_val = readl(mmio + PHY_ACCESS);
139 udelay(30); /* It takes 30 us to read/write data */
140 } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
141 if(reg_val & PHY_RD_ERR)
142 goto err_phy_read;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400143
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144 *val = reg_val & 0xffff;
145 return 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400146err_phy_read:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147 *val = 0;
148 return -EINVAL;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400149
Linus Torvalds1da177e2005-04-16 15:20:36 -0700150}
151
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400152/*
153This function will write into PHY registers.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154*/
155static int amd8111e_write_phy(struct amd8111e_priv* lp,int phy_id, int reg, u32 val)
156{
Yoann Padioleau632155e2007-06-01 00:46:35 -0700157 unsigned int repeat = REPEAT_CNT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700158 void __iomem *mmio = lp->mmio;
159 unsigned int reg_val;
160
161 reg_val = readl(mmio + PHY_ACCESS);
162 while (reg_val & PHY_CMD_ACTIVE)
163 reg_val = readl( mmio + PHY_ACCESS );
164
165 writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) |
166 ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS);
167
168 do{
169 reg_val = readl(mmio + PHY_ACCESS);
170 udelay(30); /* It takes 30 us to read/write the data */
171 } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400172
Linus Torvalds1da177e2005-04-16 15:20:36 -0700173 if(reg_val & PHY_RD_ERR)
174 goto err_phy_write;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400175
Linus Torvalds1da177e2005-04-16 15:20:36 -0700176 return 0;
177
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400178err_phy_write:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700179 return -EINVAL;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400180
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181}
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400182/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183This is the mii register read function provided to the mii interface.
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400184*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700185static int amd8111e_mdio_read(struct net_device * dev, int phy_id, int reg_num)
186{
187 struct amd8111e_priv* lp = netdev_priv(dev);
188 unsigned int reg_val;
189
190 amd8111e_read_phy(lp,phy_id,reg_num,&reg_val);
191 return reg_val;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400192
Linus Torvalds1da177e2005-04-16 15:20:36 -0700193}
194
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400195/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196This is the mii register write function provided to the mii interface.
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400197*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700198static void amd8111e_mdio_write(struct net_device * dev, int phy_id, int reg_num, int val)
199{
200 struct amd8111e_priv* lp = netdev_priv(dev);
201
202 amd8111e_write_phy(lp, phy_id, reg_num, val);
203}
204
205/*
206This function will set PHY speed. During initialization sets the original speed to 100 full.
207*/
208static void amd8111e_set_ext_phy(struct net_device *dev)
209{
210 struct amd8111e_priv *lp = netdev_priv(dev);
211 u32 bmcr,advert,tmp;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400212
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213 /* Determine mii register values to set the speed */
214 advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE);
215 tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
216 switch (lp->ext_phy_option){
217
218 default:
219 case SPEED_AUTONEG: /* advertise all values */
220 tmp |= ( ADVERTISE_10HALF|ADVERTISE_10FULL|
221 ADVERTISE_100HALF|ADVERTISE_100FULL) ;
222 break;
223 case SPEED10_HALF:
224 tmp |= ADVERTISE_10HALF;
225 break;
226 case SPEED10_FULL:
227 tmp |= ADVERTISE_10FULL;
228 break;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400229 case SPEED100_HALF:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230 tmp |= ADVERTISE_100HALF;
231 break;
232 case SPEED100_FULL:
233 tmp |= ADVERTISE_100FULL;
234 break;
235 }
236
237 if(advert != tmp)
238 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_ADVERTISE, tmp);
239 /* Restart auto negotiation */
240 bmcr = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_BMCR);
241 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
242 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_BMCR, bmcr);
243
244}
245
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400246/*
247This function will unmap skb->data space and will free
Linus Torvalds1da177e2005-04-16 15:20:36 -0700248all transmit and receive skbuffs.
249*/
250static int amd8111e_free_skbs(struct net_device *dev)
251{
252 struct amd8111e_priv *lp = netdev_priv(dev);
253 struct sk_buff* rx_skbuff;
254 int i;
255
256 /* Freeing transmit skbs */
257 for(i = 0; i < NUM_TX_BUFFERS; i++){
258 if(lp->tx_skbuff[i]){
259 pci_unmap_single(lp->pci_dev,lp->tx_dma_addr[i], lp->tx_skbuff[i]->len,PCI_DMA_TODEVICE);
260 dev_kfree_skb (lp->tx_skbuff[i]);
261 lp->tx_skbuff[i] = NULL;
262 lp->tx_dma_addr[i] = 0;
263 }
264 }
265 /* Freeing previously allocated receive buffers */
266 for (i = 0; i < NUM_RX_BUFFERS; i++){
267 rx_skbuff = lp->rx_skbuff[i];
268 if(rx_skbuff != NULL){
269 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[i],
270 lp->rx_buff_len - 2,PCI_DMA_FROMDEVICE);
271 dev_kfree_skb(lp->rx_skbuff[i]);
272 lp->rx_skbuff[i] = NULL;
273 lp->rx_dma_addr[i] = 0;
274 }
275 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400276
Linus Torvalds1da177e2005-04-16 15:20:36 -0700277 return 0;
278}
279
280/*
281This will set the receive buffer length corresponding to the mtu size of networkinterface.
282*/
283static inline void amd8111e_set_rx_buff_len(struct net_device* dev)
284{
285 struct amd8111e_priv* lp = netdev_priv(dev);
286 unsigned int mtu = dev->mtu;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400287
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288 if (mtu > ETH_DATA_LEN){
289 /* MTU + ethernet header + FCS
290 + optional VLAN tag + skb reserve space 2 */
291
292 lp->rx_buff_len = mtu + ETH_HLEN + 10;
293 lp->options |= OPTION_JUMBO_ENABLE;
294 } else{
295 lp->rx_buff_len = PKT_BUFF_SZ;
296 lp->options &= ~OPTION_JUMBO_ENABLE;
297 }
298}
299
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400300/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301This function will free all the previously allocated buffers, determine new receive buffer length and will allocate new receive buffers. This function also allocates and initializes both the transmitter and receive hardware descriptors.
302 */
303static int amd8111e_init_ring(struct net_device *dev)
304{
305 struct amd8111e_priv *lp = netdev_priv(dev);
306 int i;
307
308 lp->rx_idx = lp->tx_idx = 0;
309 lp->tx_complete_idx = 0;
310 lp->tx_ring_idx = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400311
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312
313 if(lp->opened)
314 /* Free previously allocated transmit and receive skbs */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400315 amd8111e_free_skbs(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700316
317 else{
318 /* allocate the tx and rx descriptors */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400319 if((lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
321 &lp->tx_ring_dma_addr)) == NULL)
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400322
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323 goto err_no_mem;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400324
325 if((lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700326 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
327 &lp->rx_ring_dma_addr)) == NULL)
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400328
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329 goto err_free_tx_ring;
330
331 }
332 /* Set new receive buff size */
333 amd8111e_set_rx_buff_len(dev);
334
335 /* Allocating receive skbs */
336 for (i = 0; i < NUM_RX_BUFFERS; i++) {
337
338 if (!(lp->rx_skbuff[i] = dev_alloc_skb(lp->rx_buff_len))) {
339 /* Release previos allocated skbs */
340 for(--i; i >= 0 ;i--)
341 dev_kfree_skb(lp->rx_skbuff[i]);
342 goto err_free_rx_ring;
343 }
344 skb_reserve(lp->rx_skbuff[i],2);
345 }
346 /* Initilaizing receive descriptors */
347 for (i = 0; i < NUM_RX_BUFFERS; i++) {
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400348 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700349 lp->rx_skbuff[i]->data,lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
350
351 lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]);
352 lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2);
353 wmb();
354 lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
355 }
356
357 /* Initializing transmit descriptors */
358 for (i = 0; i < NUM_TX_RING_DR; i++) {
359 lp->tx_ring[i].buff_phy_addr = 0;
360 lp->tx_ring[i].tx_flags = 0;
361 lp->tx_ring[i].buff_count = 0;
362 }
363
364 return 0;
365
366err_free_rx_ring:
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400367
368 pci_free_consistent(lp->pci_dev,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700369 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,lp->rx_ring,
370 lp->rx_ring_dma_addr);
371
372err_free_tx_ring:
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400373
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374 pci_free_consistent(lp->pci_dev,
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400375 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,lp->tx_ring,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700376 lp->tx_ring_dma_addr);
377
378err_no_mem:
379 return -ENOMEM;
380}
381/* This function will set the interrupt coalescing according to the input arguments */
382static int amd8111e_set_coalesce(struct net_device * dev, enum coal_mode cmod)
383{
384 unsigned int timeout;
385 unsigned int event_count;
386
387 struct amd8111e_priv *lp = netdev_priv(dev);
388 void __iomem *mmio = lp->mmio;
389 struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
390
391
392 switch(cmod)
393 {
394 case RX_INTR_COAL :
395 timeout = coal_conf->rx_timeout;
396 event_count = coal_conf->rx_event_count;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400397 if( timeout > MAX_TIMEOUT ||
398 event_count > MAX_EVENT_COUNT )
Julia Lawall022484c2010-08-05 10:22:20 +0000399 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400401 timeout = timeout * DELAY_TIMER_CONV;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700402 writel(VAL0|STINTEN, mmio+INTEN0);
403 writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout,
404 mmio+DLY_INT_A);
405 break;
406
407 case TX_INTR_COAL :
408 timeout = coal_conf->tx_timeout;
409 event_count = coal_conf->tx_event_count;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400410 if( timeout > MAX_TIMEOUT ||
411 event_count > MAX_EVENT_COUNT )
Julia Lawall022484c2010-08-05 10:22:20 +0000412 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400414
415 timeout = timeout * DELAY_TIMER_CONV;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700416 writel(VAL0|STINTEN,mmio+INTEN0);
417 writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout,
418 mmio+DLY_INT_B);
419 break;
420
421 case DISABLE_COAL:
422 writel(0,mmio+STVAL);
423 writel(STINTEN, mmio+INTEN0);
424 writel(0, mmio +DLY_INT_B);
425 writel(0, mmio+DLY_INT_A);
426 break;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400427 case ENABLE_COAL:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700428 /* Start the timer */
429 writel((u32)SOFT_TIMER_FREQ, mmio+STVAL); /* 0.5 sec */
430 writel(VAL0|STINTEN, mmio+INTEN0);
431 break;
432 default:
433 break;
434
435 }
436 return 0;
437
438}
439
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400440/*
441This function initializes the device registers and starts the device.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700442*/
443static int amd8111e_restart(struct net_device *dev)
444{
445 struct amd8111e_priv *lp = netdev_priv(dev);
446 void __iomem *mmio = lp->mmio;
447 int i,reg_val;
448
449 /* stop the chip */
450 writel(RUN, mmio + CMD0);
451
452 if(amd8111e_init_ring(dev))
453 return -ENOMEM;
454
455 /* enable the port manager and set auto negotiation always */
456 writel((u32) VAL1|EN_PMGR, mmio + CMD3 );
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400457 writel((u32)XPHYANE|XPHYRST , mmio + CTRL2);
458
Linus Torvalds1da177e2005-04-16 15:20:36 -0700459 amd8111e_set_ext_phy(dev);
460
461 /* set control registers */
462 reg_val = readl(mmio + CTRL1);
463 reg_val &= ~XMTSP_MASK;
464 writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 );
465
466 /* enable interrupt */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400467 writel( APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN |
Linus Torvalds1da177e2005-04-16 15:20:36 -0700468 APINT0EN | MIIPDTINTEN | MCCIINTEN | MCCINTEN | MREINTEN |
469 SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0);
470
471 writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
472
473 /* initialize tx and rx ring base addresses */
474 writel((u32)lp->tx_ring_dma_addr,mmio + XMT_RING_BASE_ADDR0);
475 writel((u32)lp->rx_ring_dma_addr,mmio+ RCV_RING_BASE_ADDR0);
476
477 writew((u32)NUM_TX_RING_DR, mmio + XMT_RING_LEN0);
478 writew((u16)NUM_RX_RING_DR, mmio + RCV_RING_LEN0);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400479
Linus Torvalds1da177e2005-04-16 15:20:36 -0700480 /* set default IPG to 96 */
481 writew((u32)DEFAULT_IPG,mmio+IPG);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400482 writew((u32)(DEFAULT_IPG-IFS1_DELTA), mmio + IFS1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700483
484 if(lp->options & OPTION_JUMBO_ENABLE){
485 writel((u32)VAL2|JUMBO, mmio + CMD3);
486 /* Reset REX_UFLO */
487 writel( REX_UFLO, mmio + CMD2);
488 /* Should not set REX_UFLO for jumbo frames */
489 writel( VAL0 | APAD_XMT|REX_RTRY , mmio + CMD2);
490 }else{
491 writel( VAL0 | APAD_XMT | REX_RTRY|REX_UFLO, mmio + CMD2);
492 writel((u32)JUMBO, mmio + CMD3);
493 }
494
495#if AMD8111E_VLAN_TAG_USED
496 writel((u32) VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3);
497#endif
498 writel( VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2 );
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400499
Linus Torvalds1da177e2005-04-16 15:20:36 -0700500 /* Setting the MAC address to the device */
501 for(i = 0; i < ETH_ADDR_LEN; i++)
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400502 writeb( dev->dev_addr[i], mmio + PADR + i );
Linus Torvalds1da177e2005-04-16 15:20:36 -0700503
504 /* Enable interrupt coalesce */
505 if(lp->options & OPTION_INTR_COAL_ENABLE){
506 printk(KERN_INFO "%s: Interrupt Coalescing Enabled.\n",
507 dev->name);
508 amd8111e_set_coalesce(dev,ENABLE_COAL);
509 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400510
Linus Torvalds1da177e2005-04-16 15:20:36 -0700511 /* set RUN bit to start the chip */
512 writel(VAL2 | RDMD0, mmio + CMD0);
513 writel(VAL0 | INTREN | RUN, mmio + CMD0);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400514
Linus Torvalds1da177e2005-04-16 15:20:36 -0700515 /* To avoid PCI posting bug */
516 readl(mmio+CMD0);
517 return 0;
518}
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400519/*
520This function clears necessary the device registers.
521*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700522static void amd8111e_init_hw_default( struct amd8111e_priv* lp)
523{
524 unsigned int reg_val;
525 unsigned int logic_filter[2] ={0,};
526 void __iomem *mmio = lp->mmio;
527
528
529 /* stop the chip */
530 writel(RUN, mmio + CMD0);
531
532 /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
533 writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
534
535 /* Clear RCV_RING_BASE_ADDR */
536 writel(0, mmio + RCV_RING_BASE_ADDR0);
537
538 /* Clear XMT_RING_BASE_ADDR */
539 writel(0, mmio + XMT_RING_BASE_ADDR0);
540 writel(0, mmio + XMT_RING_BASE_ADDR1);
541 writel(0, mmio + XMT_RING_BASE_ADDR2);
542 writel(0, mmio + XMT_RING_BASE_ADDR3);
543
544 /* Clear CMD0 */
545 writel(CMD0_CLEAR,mmio + CMD0);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400546
Linus Torvalds1da177e2005-04-16 15:20:36 -0700547 /* Clear CMD2 */
548 writel(CMD2_CLEAR, mmio +CMD2);
549
550 /* Clear CMD7 */
551 writel(CMD7_CLEAR , mmio + CMD7);
552
553 /* Clear DLY_INT_A and DLY_INT_B */
554 writel(0x0, mmio + DLY_INT_A);
555 writel(0x0, mmio + DLY_INT_B);
556
557 /* Clear FLOW_CONTROL */
558 writel(0x0, mmio + FLOW_CONTROL);
559
560 /* Clear INT0 write 1 to clear register */
561 reg_val = readl(mmio + INT0);
562 writel(reg_val, mmio + INT0);
563
564 /* Clear STVAL */
565 writel(0x0, mmio + STVAL);
566
567 /* Clear INTEN0 */
568 writel( INTEN0_CLEAR, mmio + INTEN0);
569
570 /* Clear LADRF */
571 writel(0x0 , mmio + LADRF);
572
573 /* Set SRAM_SIZE & SRAM_BOUNDARY registers */
574 writel( 0x80010,mmio + SRAM_SIZE);
575
576 /* Clear RCV_RING0_LEN */
577 writel(0x0, mmio + RCV_RING_LEN0);
578
579 /* Clear XMT_RING0/1/2/3_LEN */
580 writel(0x0, mmio + XMT_RING_LEN0);
581 writel(0x0, mmio + XMT_RING_LEN1);
582 writel(0x0, mmio + XMT_RING_LEN2);
583 writel(0x0, mmio + XMT_RING_LEN3);
584
585 /* Clear XMT_RING_LIMIT */
586 writel(0x0, mmio + XMT_RING_LIMIT);
587
588 /* Clear MIB */
589 writew(MIB_CLEAR, mmio + MIB_ADDR);
590
591 /* Clear LARF */
592 amd8111e_writeq(*(u64*)logic_filter,mmio+LADRF);
593
594 /* SRAM_SIZE register */
595 reg_val = readl(mmio + SRAM_SIZE);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400596
Linus Torvalds1da177e2005-04-16 15:20:36 -0700597 if(lp->options & OPTION_JUMBO_ENABLE)
598 writel( VAL2|JUMBO, mmio + CMD3);
599#if AMD8111E_VLAN_TAG_USED
600 writel(VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3 );
601#endif
602 /* Set default value to CTRL1 Register */
603 writel(CTRL1_DEFAULT, mmio + CTRL1);
604
605 /* To avoid PCI posting bug */
606 readl(mmio + CMD2);
607
608}
609
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400610/*
611This function disables the interrupt and clears all the pending
Linus Torvalds1da177e2005-04-16 15:20:36 -0700612interrupts in INT0
613 */
614static void amd8111e_disable_interrupt(struct amd8111e_priv* lp)
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400615{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700616 u32 intr0;
617
618 /* Disable interrupt */
619 writel(INTREN, lp->mmio + CMD0);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400620
Linus Torvalds1da177e2005-04-16 15:20:36 -0700621 /* Clear INT0 */
622 intr0 = readl(lp->mmio + INT0);
623 writel(intr0, lp->mmio + INT0);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400624
Linus Torvalds1da177e2005-04-16 15:20:36 -0700625 /* To avoid PCI posting bug */
626 readl(lp->mmio + INT0);
627
628}
629
630/*
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400631This function stops the chip.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700632*/
633static void amd8111e_stop_chip(struct amd8111e_priv* lp)
634{
635 writel(RUN, lp->mmio + CMD0);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400636
Linus Torvalds1da177e2005-04-16 15:20:36 -0700637 /* To avoid PCI posting bug */
638 readl(lp->mmio + CMD0);
639}
640
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400641/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700642This function frees the transmiter and receiver descriptor rings.
643*/
644static void amd8111e_free_ring(struct amd8111e_priv* lp)
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400645{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700646 /* Free transmit and receive descriptor rings */
647 if(lp->rx_ring){
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400648 pci_free_consistent(lp->pci_dev,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700649 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
650 lp->rx_ring, lp->rx_ring_dma_addr);
651 lp->rx_ring = NULL;
652 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400653
Linus Torvalds1da177e2005-04-16 15:20:36 -0700654 if(lp->tx_ring){
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400655 pci_free_consistent(lp->pci_dev,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700656 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
657 lp->tx_ring, lp->tx_ring_dma_addr);
658
659 lp->tx_ring = NULL;
660 }
661
662}
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400663#if AMD8111E_VLAN_TAG_USED
664/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665This is the receive indication function for packets with vlan tag.
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400666*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700667static int amd8111e_vlan_rx(struct amd8111e_priv *lp, struct sk_buff *skb, u16 vlan_tag)
668{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700669 return vlan_hwaccel_receive_skb(skb, lp->vlgrp,vlan_tag);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700670}
671#endif
672
673/*
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400674This function will free all the transmit skbs that are actually transmitted by the device. It will check the ownership of the skb before freeing the skb.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675*/
676static int amd8111e_tx(struct net_device *dev)
677{
678 struct amd8111e_priv* lp = netdev_priv(dev);
679 int tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
680 int status;
681 /* Complete all the transmit packet */
682 while (lp->tx_complete_idx != lp->tx_idx){
683 tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
684 status = le16_to_cpu(lp->tx_ring[tx_index].tx_flags);
685
686 if(status & OWN_BIT)
687 break; /* It still hasn't been Txed */
688
689 lp->tx_ring[tx_index].buff_phy_addr = 0;
690
691 /* We must free the original skb */
692 if (lp->tx_skbuff[tx_index]) {
693 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[tx_index],
694 lp->tx_skbuff[tx_index]->len,
695 PCI_DMA_TODEVICE);
696 dev_kfree_skb_irq (lp->tx_skbuff[tx_index]);
697 lp->tx_skbuff[tx_index] = NULL;
698 lp->tx_dma_addr[tx_index] = 0;
699 }
700 lp->tx_complete_idx++;
701 /*COAL update tx coalescing parameters */
702 lp->coal_conf.tx_packets++;
Al Viro05d2fec2007-08-22 21:42:28 -0400703 lp->coal_conf.tx_bytes +=
704 le16_to_cpu(lp->tx_ring[tx_index].buff_count);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700705
706 if (netif_queue_stopped(dev) &&
707 lp->tx_complete_idx > lp->tx_idx - NUM_TX_BUFFERS +2){
708 /* The ring is no longer full, clear tbusy. */
709 /* lp->tx_full = 0; */
710 netif_wake_queue (dev);
711 }
712 }
713 return 0;
714}
715
Linus Torvalds1da177e2005-04-16 15:20:36 -0700716/* This function handles the driver receive operation in polling mode */
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700717static int amd8111e_rx_poll(struct napi_struct *napi, int budget)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700718{
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700719 struct amd8111e_priv *lp = container_of(napi, struct amd8111e_priv, napi);
720 struct net_device *dev = lp->amd8111e_net_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700721 int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
722 void __iomem *mmio = lp->mmio;
723 struct sk_buff *skb,*new_skb;
724 int min_pkt_len, status;
725 unsigned int intr0;
726 int num_rx_pkt = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700727 short pkt_len;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400728#if AMD8111E_VLAN_TAG_USED
Linus Torvalds1da177e2005-04-16 15:20:36 -0700729 short vtag;
730#endif
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700731 int rx_pkt_limit = budget;
Liu Taodfa1b732005-05-12 19:40:38 -0400732 unsigned long flags;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400733
734 do{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700735 /* process receive packets until we use the quota*/
736 /* If we own the next entry, it's a new packet. Send it up. */
737 while(1) {
738 status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
739 if (status & OWN_BIT)
740 break;
741
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400742 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700743 * There is a tricky error noted by John Murphy,
744 * <murf@perftech.com> to Russ Nelson: Even with
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400745 * full-sized * buffers it's possible for a
746 * jabber packet to use two buffers, with only
Linus Torvalds1da177e2005-04-16 15:20:36 -0700747 * the last correctly noting the error.
748 */
749
750 if(status & ERR_BIT) {
751 /* reseting flags */
752 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
753 goto err_next_pkt;
754 }
755 /* check for STP and ENP */
756 if(!((status & STP_BIT) && (status & ENP_BIT))){
757 /* reseting flags */
758 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
759 goto err_next_pkt;
760 }
761 pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
762
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400763#if AMD8111E_VLAN_TAG_USED
Linus Torvalds1da177e2005-04-16 15:20:36 -0700764 vtag = status & TT_MASK;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400765 /*MAC will strip vlan tag*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700766 if(lp->vlgrp != NULL && vtag !=0)
767 min_pkt_len =MIN_PKT_LEN - 4;
768 else
769#endif
770 min_pkt_len =MIN_PKT_LEN;
771
772 if (pkt_len < min_pkt_len) {
773 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
774 lp->drv_rx_errors++;
775 goto err_next_pkt;
776 }
777 if(--rx_pkt_limit < 0)
778 goto rx_not_empty;
779 if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400780 /* if allocation fail,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781 ignore that pkt and go to next one */
782 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
783 lp->drv_rx_errors++;
784 goto err_next_pkt;
785 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400786
Linus Torvalds1da177e2005-04-16 15:20:36 -0700787 skb_reserve(new_skb, 2);
788 skb = lp->rx_skbuff[rx_index];
789 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
790 lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
791 skb_put(skb, pkt_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700792 lp->rx_skbuff[rx_index] = new_skb;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700793 lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
794 new_skb->data,
795 lp->rx_buff_len-2,
796 PCI_DMA_FROMDEVICE);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400797
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798 skb->protocol = eth_type_trans(skb, dev);
799
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400800#if AMD8111E_VLAN_TAG_USED
Linus Torvalds1da177e2005-04-16 15:20:36 -0700801 if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
802 amd8111e_vlan_rx(lp, skb,
803 le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
804 } else
805#endif
806 netif_receive_skb(skb);
807 /*COAL update rx coalescing parameters*/
808 lp->coal_conf.rx_packets++;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400809 lp->coal_conf.rx_bytes += pkt_len;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700810 num_rx_pkt++;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400811
812 err_next_pkt:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700813 lp->rx_ring[rx_index].buff_phy_addr
814 = cpu_to_le32(lp->rx_dma_addr[rx_index]);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400815 lp->rx_ring[rx_index].buff_count =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700816 cpu_to_le16(lp->rx_buff_len-2);
817 wmb();
818 lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
819 rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
820 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400821 /* Check the interrupt status register for more packets in the
Linus Torvalds1da177e2005-04-16 15:20:36 -0700822 mean time. Process them since we have not used up our quota.*/
823
824 intr0 = readl(mmio + INT0);
825 /*Ack receive packets */
826 writel(intr0 & RINT0,mmio + INT0);
827
828 } while(intr0 & RINT0);
829
Chris Friesen48e5eca2008-10-28 15:50:54 -0700830 if (rx_pkt_limit > 0) {
831 /* Receive descriptor is empty now */
832 spin_lock_irqsave(&lp->lock, flags);
Ben Hutchings288379f2009-01-19 16:43:59 -0800833 __napi_complete(napi);
Chris Friesen48e5eca2008-10-28 15:50:54 -0700834 writel(VAL0|RINTEN0, mmio + INTEN0);
835 writel(VAL2 | RDMD0, mmio + CMD0);
836 spin_unlock_irqrestore(&lp->lock, flags);
837 }
Liu Taodfa1b732005-05-12 19:40:38 -0400838
Linus Torvalds1da177e2005-04-16 15:20:36 -0700839rx_not_empty:
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700840 return num_rx_pkt;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700841}
842
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400843/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700844This function will indicate the link status to the kernel.
845*/
846static int amd8111e_link_change(struct net_device* dev)
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400847{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700848 struct amd8111e_priv *lp = netdev_priv(dev);
849 int status0,speed;
850
851 /* read the link change */
852 status0 = readl(lp->mmio + STAT0);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400853
Linus Torvalds1da177e2005-04-16 15:20:36 -0700854 if(status0 & LINK_STATS){
855 if(status0 & AUTONEG_COMPLETE)
856 lp->link_config.autoneg = AUTONEG_ENABLE;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400857 else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700858 lp->link_config.autoneg = AUTONEG_DISABLE;
859
860 if(status0 & FULL_DPLX)
861 lp->link_config.duplex = DUPLEX_FULL;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400862 else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700863 lp->link_config.duplex = DUPLEX_HALF;
864 speed = (status0 & SPEED_MASK) >> 7;
865 if(speed == PHY_SPEED_10)
866 lp->link_config.speed = SPEED_10;
867 else if(speed == PHY_SPEED_100)
868 lp->link_config.speed = SPEED_100;
869
870 printk(KERN_INFO "%s: Link is Up. Speed is %s Mbps %s Duplex\n", dev->name,
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400871 (lp->link_config.speed == SPEED_100) ? "100": "10",
872 (lp->link_config.duplex == DUPLEX_FULL)? "Full": "Half");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700873 netif_carrier_on(dev);
874 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400875 else{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876 lp->link_config.speed = SPEED_INVALID;
877 lp->link_config.duplex = DUPLEX_INVALID;
878 lp->link_config.autoneg = AUTONEG_INVALID;
879 printk(KERN_INFO "%s: Link is Down.\n",dev->name);
880 netif_carrier_off(dev);
881 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400882
Linus Torvalds1da177e2005-04-16 15:20:36 -0700883 return 0;
884}
885/*
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400886This function reads the mib counters.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700887*/
888static int amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER)
889{
890 unsigned int status;
891 unsigned int data;
892 unsigned int repeat = REPEAT_CNT;
893
894 writew( MIB_RD_CMD | MIB_COUNTER, mmio + MIB_ADDR);
895 do {
896 status = readw(mmio + MIB_ADDR);
897 udelay(2); /* controller takes MAX 2 us to get mib data */
898 }
899 while (--repeat && (status & MIB_CMD_ACTIVE));
900
901 data = readl(mmio + MIB_DATA);
902 return data;
903}
904
905/*
Eric Dumazetc3227e52010-08-20 03:08:23 +0000906 * This function reads the mib registers and returns the hardware statistics.
907 * It updates previous internal driver statistics with new values.
908 */
909static struct net_device_stats *amd8111e_get_stats(struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700910{
911 struct amd8111e_priv *lp = netdev_priv(dev);
912 void __iomem *mmio = lp->mmio;
913 unsigned long flags;
Eric Dumazetc3227e52010-08-20 03:08:23 +0000914 struct net_device_stats *new_stats = &dev->stats;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400915
Eric Dumazetc3227e52010-08-20 03:08:23 +0000916 if (!lp->opened)
917 return new_stats;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700918 spin_lock_irqsave (&lp->lock, flags);
919
920 /* stats.rx_packets */
921 new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+
922 amd8111e_read_mib(mmio, rcv_multicast_pkts)+
923 amd8111e_read_mib(mmio, rcv_unicast_pkts);
924
925 /* stats.tx_packets */
926 new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets);
927
928 /*stats.rx_bytes */
929 new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets);
930
931 /* stats.tx_bytes */
932 new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets);
933
934 /* stats.rx_errors */
935 /* hw errors + errors driver reported */
936 new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+
937 amd8111e_read_mib(mmio, rcv_fragments)+
938 amd8111e_read_mib(mmio, rcv_jabbers)+
939 amd8111e_read_mib(mmio, rcv_alignment_errors)+
940 amd8111e_read_mib(mmio, rcv_fcs_errors)+
941 amd8111e_read_mib(mmio, rcv_miss_pkts)+
942 lp->drv_rx_errors;
943
944 /* stats.tx_errors */
945 new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
946
947 /* stats.rx_dropped*/
948 new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts);
949
950 /* stats.tx_dropped*/
951 new_stats->tx_dropped = amd8111e_read_mib(mmio, xmt_underrun_pkts);
952
953 /* stats.multicast*/
954 new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts);
955
956 /* stats.collisions*/
957 new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions);
958
959 /* stats.rx_length_errors*/
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400960 new_stats->rx_length_errors =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700961 amd8111e_read_mib(mmio, rcv_undersize_pkts)+
962 amd8111e_read_mib(mmio, rcv_oversize_pkts);
963
964 /* stats.rx_over_errors*/
965 new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
966
967 /* stats.rx_crc_errors*/
968 new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors);
969
970 /* stats.rx_frame_errors*/
971 new_stats->rx_frame_errors =
972 amd8111e_read_mib(mmio, rcv_alignment_errors);
973
974 /* stats.rx_fifo_errors */
975 new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
976
977 /* stats.rx_missed_errors */
978 new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
979
980 /* stats.tx_aborted_errors*/
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400981 new_stats->tx_aborted_errors =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700982 amd8111e_read_mib(mmio, xmt_excessive_collision);
983
984 /* stats.tx_carrier_errors*/
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400985 new_stats->tx_carrier_errors =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700986 amd8111e_read_mib(mmio, xmt_loss_carrier);
987
988 /* stats.tx_fifo_errors*/
989 new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
990
991 /* stats.tx_window_errors*/
992 new_stats->tx_window_errors =
993 amd8111e_read_mib(mmio, xmt_late_collision);
994
995 /* Reset the mibs for collecting new statistics */
996 /* writew(MIB_CLEAR, mmio + MIB_ADDR);*/
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400997
Linus Torvalds1da177e2005-04-16 15:20:36 -0700998 spin_unlock_irqrestore (&lp->lock, flags);
999
1000 return new_stats;
1001}
Robert P. J. Day3a4fa0a2007-10-19 23:10:43 +02001002/* This function recalculate the interrupt coalescing mode on every interrupt
Linus Torvalds1da177e2005-04-16 15:20:36 -07001003according to the datarate and the packet rate.
1004*/
1005static int amd8111e_calc_coalesce(struct net_device *dev)
1006{
1007 struct amd8111e_priv *lp = netdev_priv(dev);
1008 struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
1009 int tx_pkt_rate;
1010 int rx_pkt_rate;
1011 int tx_data_rate;
1012 int rx_data_rate;
1013 int rx_pkt_size;
1014 int tx_pkt_size;
1015
1016 tx_pkt_rate = coal_conf->tx_packets - coal_conf->tx_prev_packets;
1017 coal_conf->tx_prev_packets = coal_conf->tx_packets;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001018
Linus Torvalds1da177e2005-04-16 15:20:36 -07001019 tx_data_rate = coal_conf->tx_bytes - coal_conf->tx_prev_bytes;
1020 coal_conf->tx_prev_bytes = coal_conf->tx_bytes;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001021
Linus Torvalds1da177e2005-04-16 15:20:36 -07001022 rx_pkt_rate = coal_conf->rx_packets - coal_conf->rx_prev_packets;
1023 coal_conf->rx_prev_packets = coal_conf->rx_packets;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001024
Linus Torvalds1da177e2005-04-16 15:20:36 -07001025 rx_data_rate = coal_conf->rx_bytes - coal_conf->rx_prev_bytes;
1026 coal_conf->rx_prev_bytes = coal_conf->rx_bytes;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001027
Linus Torvalds1da177e2005-04-16 15:20:36 -07001028 if(rx_pkt_rate < 800){
1029 if(coal_conf->rx_coal_type != NO_COALESCE){
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001030
Linus Torvalds1da177e2005-04-16 15:20:36 -07001031 coal_conf->rx_timeout = 0x0;
1032 coal_conf->rx_event_count = 0;
1033 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1034 coal_conf->rx_coal_type = NO_COALESCE;
1035 }
1036 }
1037 else{
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001038
Linus Torvalds1da177e2005-04-16 15:20:36 -07001039 rx_pkt_size = rx_data_rate/rx_pkt_rate;
1040 if (rx_pkt_size < 128){
1041 if(coal_conf->rx_coal_type != NO_COALESCE){
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001042
Linus Torvalds1da177e2005-04-16 15:20:36 -07001043 coal_conf->rx_timeout = 0;
1044 coal_conf->rx_event_count = 0;
1045 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1046 coal_conf->rx_coal_type = NO_COALESCE;
1047 }
1048
1049 }
1050 else if ( (rx_pkt_size >= 128) && (rx_pkt_size < 512) ){
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001051
Linus Torvalds1da177e2005-04-16 15:20:36 -07001052 if(coal_conf->rx_coal_type != LOW_COALESCE){
1053 coal_conf->rx_timeout = 1;
1054 coal_conf->rx_event_count = 4;
1055 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1056 coal_conf->rx_coal_type = LOW_COALESCE;
1057 }
1058 }
1059 else if ((rx_pkt_size >= 512) && (rx_pkt_size < 1024)){
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001060
Linus Torvalds1da177e2005-04-16 15:20:36 -07001061 if(coal_conf->rx_coal_type != MEDIUM_COALESCE){
1062 coal_conf->rx_timeout = 1;
1063 coal_conf->rx_event_count = 4;
1064 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1065 coal_conf->rx_coal_type = MEDIUM_COALESCE;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001066 }
1067
Linus Torvalds1da177e2005-04-16 15:20:36 -07001068 }
1069 else if(rx_pkt_size >= 1024){
1070 if(coal_conf->rx_coal_type != HIGH_COALESCE){
1071 coal_conf->rx_timeout = 2;
1072 coal_conf->rx_event_count = 3;
1073 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1074 coal_conf->rx_coal_type = HIGH_COALESCE;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001075 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001076 }
1077 }
1078 /* NOW FOR TX INTR COALESC */
1079 if(tx_pkt_rate < 800){
1080 if(coal_conf->tx_coal_type != NO_COALESCE){
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001081
Linus Torvalds1da177e2005-04-16 15:20:36 -07001082 coal_conf->tx_timeout = 0x0;
1083 coal_conf->tx_event_count = 0;
1084 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1085 coal_conf->tx_coal_type = NO_COALESCE;
1086 }
1087 }
1088 else{
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001089
Linus Torvalds1da177e2005-04-16 15:20:36 -07001090 tx_pkt_size = tx_data_rate/tx_pkt_rate;
1091 if (tx_pkt_size < 128){
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001092
Linus Torvalds1da177e2005-04-16 15:20:36 -07001093 if(coal_conf->tx_coal_type != NO_COALESCE){
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001094
Linus Torvalds1da177e2005-04-16 15:20:36 -07001095 coal_conf->tx_timeout = 0;
1096 coal_conf->tx_event_count = 0;
1097 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1098 coal_conf->tx_coal_type = NO_COALESCE;
1099 }
1100
1101 }
1102 else if ( (tx_pkt_size >= 128) && (tx_pkt_size < 512) ){
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001103
Linus Torvalds1da177e2005-04-16 15:20:36 -07001104 if(coal_conf->tx_coal_type != LOW_COALESCE){
1105 coal_conf->tx_timeout = 1;
1106 coal_conf->tx_event_count = 2;
1107 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1108 coal_conf->tx_coal_type = LOW_COALESCE;
1109
1110 }
1111 }
1112 else if ((tx_pkt_size >= 512) && (tx_pkt_size < 1024)){
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001113
Linus Torvalds1da177e2005-04-16 15:20:36 -07001114 if(coal_conf->tx_coal_type != MEDIUM_COALESCE){
1115 coal_conf->tx_timeout = 2;
1116 coal_conf->tx_event_count = 5;
1117 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1118 coal_conf->tx_coal_type = MEDIUM_COALESCE;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001119 }
1120
Linus Torvalds1da177e2005-04-16 15:20:36 -07001121 }
1122 else if(tx_pkt_size >= 1024){
1123 if (tx_pkt_size >= 1024){
1124 if(coal_conf->tx_coal_type != HIGH_COALESCE){
1125 coal_conf->tx_timeout = 4;
1126 coal_conf->tx_event_count = 8;
1127 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1128 coal_conf->tx_coal_type = HIGH_COALESCE;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001129 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001130 }
1131 }
1132 }
1133 return 0;
1134
1135}
1136/*
1137This is device interrupt function. It handles transmit, receive,link change and hardware timer interrupts.
1138*/
David Howells7d12e782006-10-05 14:55:46 +01001139static irqreturn_t amd8111e_interrupt(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001140{
1141
1142 struct net_device * dev = (struct net_device *) dev_id;
1143 struct amd8111e_priv *lp = netdev_priv(dev);
1144 void __iomem *mmio = lp->mmio;
Liu Taodfa1b732005-05-12 19:40:38 -04001145 unsigned int intr0, intren0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001146 unsigned int handled = 1;
1147
Liu Taodfa1b732005-05-12 19:40:38 -04001148 if(unlikely(dev == NULL))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001149 return IRQ_NONE;
1150
Liu Taodfa1b732005-05-12 19:40:38 -04001151 spin_lock(&lp->lock);
1152
Linus Torvalds1da177e2005-04-16 15:20:36 -07001153 /* disabling interrupt */
1154 writel(INTREN, mmio + CMD0);
1155
1156 /* Read interrupt status */
1157 intr0 = readl(mmio + INT0);
Liu Taodfa1b732005-05-12 19:40:38 -04001158 intren0 = readl(mmio + INTEN0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001159
1160 /* Process all the INT event until INTR bit is clear. */
1161
1162 if (!(intr0 & INTR)){
1163 handled = 0;
1164 goto err_no_interrupt;
1165 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001166
Linus Torvalds1da177e2005-04-16 15:20:36 -07001167 /* Current driver processes 4 interrupts : RINT,TINT,LCINT,STINT */
1168 writel(intr0, mmio + INT0);
1169
1170 /* Check if Receive Interrupt has occurred. */
Francois Romieu6ba33ac2008-07-06 20:55:12 -07001171 if (intr0 & RINT0) {
Ben Hutchings288379f2009-01-19 16:43:59 -08001172 if (napi_schedule_prep(&lp->napi)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001173 /* Disable receive interupts */
1174 writel(RINTEN0, mmio + INTEN0);
1175 /* Schedule a polling routine */
Ben Hutchings288379f2009-01-19 16:43:59 -08001176 __napi_schedule(&lp->napi);
Francois Romieu6ba33ac2008-07-06 20:55:12 -07001177 } else if (intren0 & RINTEN0) {
Joe Perches91e83432010-01-31 10:02:09 +00001178 printk("************Driver bug! interrupt while in poll\n");
Liu Taodfa1b732005-05-12 19:40:38 -04001179 /* Fix by disable receive interrupts */
1180 writel(RINTEN0, mmio + INTEN0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001181 }
1182 }
Francois Romieu6ba33ac2008-07-06 20:55:12 -07001183
Linus Torvalds1da177e2005-04-16 15:20:36 -07001184 /* Check if Transmit Interrupt has occurred. */
Francois Romieu6ba33ac2008-07-06 20:55:12 -07001185 if (intr0 & TINT0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001186 amd8111e_tx(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001187
Linus Torvalds1da177e2005-04-16 15:20:36 -07001188 /* Check if Link Change Interrupt has occurred. */
1189 if (intr0 & LCINT)
1190 amd8111e_link_change(dev);
1191
1192 /* Check if Hardware Timer Interrupt has occurred. */
1193 if (intr0 & STINT)
1194 amd8111e_calc_coalesce(dev);
1195
1196err_no_interrupt:
1197 writel( VAL0 | INTREN,mmio + CMD0);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001198
Liu Taodfa1b732005-05-12 19:40:38 -04001199 spin_unlock(&lp->lock);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001200
Linus Torvalds1da177e2005-04-16 15:20:36 -07001201 return IRQ_RETVAL(handled);
1202}
1203
1204#ifdef CONFIG_NET_POLL_CONTROLLER
1205static void amd8111e_poll(struct net_device *dev)
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001206{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001207 unsigned long flags;
Jiri Kosinab7e36bf2007-02-05 16:29:49 -08001208 local_irq_save(flags);
David Howells7d12e782006-10-05 14:55:46 +01001209 amd8111e_interrupt(0, dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001210 local_irq_restore(flags);
1211}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001212#endif
1213
1214
1215/*
1216This function closes the network interface and updates the statistics so that most recent statistics will be available after the interface is down.
1217*/
1218static int amd8111e_close(struct net_device * dev)
1219{
1220 struct amd8111e_priv *lp = netdev_priv(dev);
1221 netif_stop_queue(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001222
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001223 napi_disable(&lp->napi);
1224
Linus Torvalds1da177e2005-04-16 15:20:36 -07001225 spin_lock_irq(&lp->lock);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001226
Linus Torvalds1da177e2005-04-16 15:20:36 -07001227 amd8111e_disable_interrupt(lp);
1228 amd8111e_stop_chip(lp);
Chunbo Luoe83603f2008-10-28 09:51:46 +08001229
1230 /* Free transmit and receive skbs */
1231 amd8111e_free_skbs(lp->amd8111e_net_dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001232
Linus Torvalds1da177e2005-04-16 15:20:36 -07001233 netif_carrier_off(lp->amd8111e_net_dev);
1234
1235 /* Delete ipg timer */
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001236 if(lp->options & OPTION_DYN_IPG_ENABLE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001237 del_timer_sync(&lp->ipg_data.ipg_timer);
1238
1239 spin_unlock_irq(&lp->lock);
1240 free_irq(dev->irq, dev);
Chunbo Luoe83603f2008-10-28 09:51:46 +08001241 amd8111e_free_ring(lp);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001242
Linus Torvalds1da177e2005-04-16 15:20:36 -07001243 /* Update the statistics before closing */
1244 amd8111e_get_stats(dev);
1245 lp->opened = 0;
1246 return 0;
1247}
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001248/* This function opens new interface.It requests irq for the device, initializes the device,buffers and descriptors, and starts the device.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001249*/
1250static int amd8111e_open(struct net_device * dev )
1251{
1252 struct amd8111e_priv *lp = netdev_priv(dev);
1253
Thomas Gleixner1fb9df52006-07-01 19:29:39 -07001254 if(dev->irq ==0 || request_irq(dev->irq, amd8111e_interrupt, IRQF_SHARED,
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001255 dev->name, dev))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001256 return -EAGAIN;
1257
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001258 napi_enable(&lp->napi);
1259
Linus Torvalds1da177e2005-04-16 15:20:36 -07001260 spin_lock_irq(&lp->lock);
1261
1262 amd8111e_init_hw_default(lp);
1263
1264 if(amd8111e_restart(dev)){
1265 spin_unlock_irq(&lp->lock);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001266 napi_disable(&lp->napi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001267 if (dev->irq)
1268 free_irq(dev->irq, dev);
1269 return -ENOMEM;
1270 }
1271 /* Start ipg timer */
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001272 if(lp->options & OPTION_DYN_IPG_ENABLE){
Linus Torvalds1da177e2005-04-16 15:20:36 -07001273 add_timer(&lp->ipg_data.ipg_timer);
1274 printk(KERN_INFO "%s: Dynamic IPG Enabled.\n",dev->name);
1275 }
1276
1277 lp->opened = 1;
1278
1279 spin_unlock_irq(&lp->lock);
1280
1281 netif_start_queue(dev);
1282
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001283 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001284}
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001285/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001286This function checks if there is any transmit descriptors available to queue more packet.
1287*/
1288static int amd8111e_tx_queue_avail(struct amd8111e_priv* lp )
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001289{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001290 int tx_index = lp->tx_idx & TX_BUFF_MOD_MASK;
Al Viroee41a822007-08-22 21:37:46 -04001291 if (lp->tx_skbuff[tx_index])
Linus Torvalds1da177e2005-04-16 15:20:36 -07001292 return -1;
1293 else
1294 return 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001295
Linus Torvalds1da177e2005-04-16 15:20:36 -07001296}
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001297/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001298This function will queue the transmit packets to the descriptors and will trigger the send operation. It also initializes the transmit descriptors with buffer physical address, byte count, ownership to hardware etc.
1299*/
1300
Stephen Hemminger613573252009-08-31 19:50:58 +00001301static netdev_tx_t amd8111e_start_xmit(struct sk_buff *skb,
1302 struct net_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001303{
1304 struct amd8111e_priv *lp = netdev_priv(dev);
1305 int tx_index;
1306 unsigned long flags;
1307
1308 spin_lock_irqsave(&lp->lock, flags);
1309
1310 tx_index = lp->tx_idx & TX_RING_DR_MOD_MASK;
1311
1312 lp->tx_ring[tx_index].buff_count = cpu_to_le16(skb->len);
1313
1314 lp->tx_skbuff[tx_index] = skb;
1315 lp->tx_ring[tx_index].tx_flags = 0;
1316
1317#if AMD8111E_VLAN_TAG_USED
1318 if((lp->vlgrp != NULL) && vlan_tx_tag_present(skb)){
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001319 lp->tx_ring[tx_index].tag_ctrl_cmd |=
1320 cpu_to_le16(TCC_VLAN_INSERT);
1321 lp->tx_ring[tx_index].tag_ctrl_info =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001322 cpu_to_le16(vlan_tx_tag_get(skb));
1323
1324 }
1325#endif
1326 lp->tx_dma_addr[tx_index] =
1327 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1328 lp->tx_ring[tx_index].buff_phy_addr =
Al Viroee41a822007-08-22 21:37:46 -04001329 cpu_to_le32(lp->tx_dma_addr[tx_index]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001330
1331 /* Set FCS and LTINT bits */
1332 wmb();
1333 lp->tx_ring[tx_index].tx_flags |=
1334 cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT);
1335
1336 lp->tx_idx++;
1337
1338 /* Trigger an immediate send poll. */
1339 writel( VAL1 | TDMD0, lp->mmio + CMD0);
1340 writel( VAL2 | RDMD0,lp->mmio + CMD0);
1341
Linus Torvalds1da177e2005-04-16 15:20:36 -07001342 if(amd8111e_tx_queue_avail(lp) < 0){
1343 netif_stop_queue(dev);
1344 }
1345 spin_unlock_irqrestore(&lp->lock, flags);
Patrick McHardy6ed10652009-06-23 06:03:08 +00001346 return NETDEV_TX_OK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001347}
1348/*
1349This function returns all the memory mapped registers of the device.
1350*/
1351static void amd8111e_read_regs(struct amd8111e_priv *lp, u32 *buf)
1352{
1353 void __iomem *mmio = lp->mmio;
1354 /* Read only necessary registers */
1355 buf[0] = readl(mmio + XMT_RING_BASE_ADDR0);
1356 buf[1] = readl(mmio + XMT_RING_LEN0);
1357 buf[2] = readl(mmio + RCV_RING_BASE_ADDR0);
1358 buf[3] = readl(mmio + RCV_RING_LEN0);
1359 buf[4] = readl(mmio + CMD0);
1360 buf[5] = readl(mmio + CMD2);
1361 buf[6] = readl(mmio + CMD3);
1362 buf[7] = readl(mmio + CMD7);
1363 buf[8] = readl(mmio + INT0);
1364 buf[9] = readl(mmio + INTEN0);
1365 buf[10] = readl(mmio + LADRF);
1366 buf[11] = readl(mmio + LADRF+4);
1367 buf[12] = readl(mmio + STAT0);
1368}
1369
Linus Torvalds1da177e2005-04-16 15:20:36 -07001370
Linus Torvalds1da177e2005-04-16 15:20:36 -07001371/*
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001372This function sets promiscuos mode, all-multi mode or the multicast address
Linus Torvalds1da177e2005-04-16 15:20:36 -07001373list to the device.
1374*/
1375static void amd8111e_set_multicast_list(struct net_device *dev)
1376{
Jiri Pirko22bedad32010-04-01 21:22:57 +00001377 struct netdev_hw_addr *ha;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001378 struct amd8111e_priv *lp = netdev_priv(dev);
1379 u32 mc_filter[2] ;
Jiri Pirko0ddf4772010-02-20 00:13:58 +00001380 int bit_num;
1381
Linus Torvalds1da177e2005-04-16 15:20:36 -07001382 if(dev->flags & IFF_PROMISC){
Linus Torvalds1da177e2005-04-16 15:20:36 -07001383 writel( VAL2 | PROM, lp->mmio + CMD2);
1384 return;
1385 }
1386 else
1387 writel( PROM, lp->mmio + CMD2);
Jiri Pirko4cd24ea2010-02-08 04:30:35 +00001388 if (dev->flags & IFF_ALLMULTI ||
1389 netdev_mc_count(dev) > MAX_FILTER_SIZE) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001390 /* get all multicast packet */
1391 mc_filter[1] = mc_filter[0] = 0xffffffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001392 lp->options |= OPTION_MULTICAST_ENABLE;
1393 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1394 return;
1395 }
Jiri Pirko4cd24ea2010-02-08 04:30:35 +00001396 if (netdev_mc_empty(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001397 /* get only own packets */
1398 mc_filter[1] = mc_filter[0] = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001399 lp->options &= ~OPTION_MULTICAST_ENABLE;
1400 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1401 /* disable promiscous mode */
1402 writel(PROM, lp->mmio + CMD2);
1403 return;
1404 }
1405 /* load all the multicast addresses in the logic filter */
1406 lp->options |= OPTION_MULTICAST_ENABLE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001407 mc_filter[1] = mc_filter[0] = 0;
Jiri Pirko22bedad32010-04-01 21:22:57 +00001408 netdev_for_each_mc_addr(ha, dev) {
1409 bit_num = (ether_crc_le(ETH_ALEN, ha->addr) >> 26) & 0x3f;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001410 mc_filter[bit_num >> 5] |= 1 << (bit_num & 31);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001411 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001412 amd8111e_writeq(*(u64*)mc_filter,lp->mmio+ LADRF);
1413
1414 /* To eliminate PCI posting bug */
1415 readl(lp->mmio + CMD2);
1416
1417}
1418
1419static void amd8111e_get_drvinfo(struct net_device* dev, struct ethtool_drvinfo *info)
1420{
1421 struct amd8111e_priv *lp = netdev_priv(dev);
1422 struct pci_dev *pci_dev = lp->pci_dev;
1423 strcpy (info->driver, MODULE_NAME);
1424 strcpy (info->version, MODULE_VERS);
1425 sprintf(info->fw_version,"%u",chip_version);
1426 strcpy (info->bus_info, pci_name(pci_dev));
1427}
1428
1429static int amd8111e_get_regs_len(struct net_device *dev)
1430{
1431 return AMD8111E_REG_DUMP_LEN;
1432}
1433
1434static void amd8111e_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
1435{
1436 struct amd8111e_priv *lp = netdev_priv(dev);
1437 regs->version = 0;
1438 amd8111e_read_regs(lp, buf);
1439}
1440
1441static int amd8111e_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1442{
1443 struct amd8111e_priv *lp = netdev_priv(dev);
1444 spin_lock_irq(&lp->lock);
1445 mii_ethtool_gset(&lp->mii_if, ecmd);
1446 spin_unlock_irq(&lp->lock);
1447 return 0;
1448}
1449
1450static int amd8111e_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1451{
1452 struct amd8111e_priv *lp = netdev_priv(dev);
1453 int res;
1454 spin_lock_irq(&lp->lock);
1455 res = mii_ethtool_sset(&lp->mii_if, ecmd);
1456 spin_unlock_irq(&lp->lock);
1457 return res;
1458}
1459
1460static int amd8111e_nway_reset(struct net_device *dev)
1461{
1462 struct amd8111e_priv *lp = netdev_priv(dev);
1463 return mii_nway_restart(&lp->mii_if);
1464}
1465
1466static u32 amd8111e_get_link(struct net_device *dev)
1467{
1468 struct amd8111e_priv *lp = netdev_priv(dev);
1469 return mii_link_ok(&lp->mii_if);
1470}
1471
1472static void amd8111e_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1473{
1474 struct amd8111e_priv *lp = netdev_priv(dev);
1475 wol_info->supported = WAKE_MAGIC|WAKE_PHY;
1476 if (lp->options & OPTION_WOL_ENABLE)
1477 wol_info->wolopts = WAKE_MAGIC;
1478}
1479
1480static int amd8111e_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1481{
1482 struct amd8111e_priv *lp = netdev_priv(dev);
1483 if (wol_info->wolopts & ~(WAKE_MAGIC|WAKE_PHY))
1484 return -EINVAL;
1485 spin_lock_irq(&lp->lock);
1486 if (wol_info->wolopts & WAKE_MAGIC)
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001487 lp->options |=
Linus Torvalds1da177e2005-04-16 15:20:36 -07001488 (OPTION_WOL_ENABLE | OPTION_WAKE_MAGIC_ENABLE);
1489 else if(wol_info->wolopts & WAKE_PHY)
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001490 lp->options |=
Linus Torvalds1da177e2005-04-16 15:20:36 -07001491 (OPTION_WOL_ENABLE | OPTION_WAKE_PHY_ENABLE);
1492 else
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001493 lp->options &= ~OPTION_WOL_ENABLE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001494 spin_unlock_irq(&lp->lock);
1495 return 0;
1496}
1497
Jeff Garzik7282d492006-09-13 14:30:00 -04001498static const struct ethtool_ops ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001499 .get_drvinfo = amd8111e_get_drvinfo,
1500 .get_regs_len = amd8111e_get_regs_len,
1501 .get_regs = amd8111e_get_regs,
1502 .get_settings = amd8111e_get_settings,
1503 .set_settings = amd8111e_set_settings,
1504 .nway_reset = amd8111e_nway_reset,
1505 .get_link = amd8111e_get_link,
1506 .get_wol = amd8111e_get_wol,
1507 .set_wol = amd8111e_set_wol,
1508};
1509
1510/*
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001511This function handles all the ethtool ioctls. It gives driver info, gets/sets driver speed, gets memory mapped register values, forces auto negotiation, sets/gets WOL options for ethtool application.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001512*/
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001513
Linus Torvalds1da177e2005-04-16 15:20:36 -07001514static int amd8111e_ioctl(struct net_device * dev , struct ifreq *ifr, int cmd)
1515{
1516 struct mii_ioctl_data *data = if_mii(ifr);
1517 struct amd8111e_priv *lp = netdev_priv(dev);
1518 int err;
1519 u32 mii_regval;
1520
Linus Torvalds1da177e2005-04-16 15:20:36 -07001521 switch(cmd) {
1522 case SIOCGMIIPHY:
1523 data->phy_id = lp->ext_phy_addr;
1524
1525 /* fallthru */
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001526 case SIOCGMIIREG:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001527
1528 spin_lock_irq(&lp->lock);
1529 err = amd8111e_read_phy(lp, data->phy_id,
1530 data->reg_num & PHY_REG_ADDR_MASK, &mii_regval);
1531 spin_unlock_irq(&lp->lock);
1532
1533 data->val_out = mii_regval;
1534 return err;
1535
1536 case SIOCSMIIREG:
1537
1538 spin_lock_irq(&lp->lock);
1539 err = amd8111e_write_phy(lp, data->phy_id,
1540 data->reg_num & PHY_REG_ADDR_MASK, data->val_in);
1541 spin_unlock_irq(&lp->lock);
1542
1543 return err;
1544
1545 default:
1546 /* do nothing */
1547 break;
1548 }
1549 return -EOPNOTSUPP;
1550}
1551static int amd8111e_set_mac_address(struct net_device *dev, void *p)
1552{
1553 struct amd8111e_priv *lp = netdev_priv(dev);
1554 int i;
1555 struct sockaddr *addr = p;
1556
1557 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1558 spin_lock_irq(&lp->lock);
1559 /* Setting the MAC address to the device */
1560 for(i = 0; i < ETH_ADDR_LEN; i++)
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001561 writeb( dev->dev_addr[i], lp->mmio + PADR + i );
1562
Linus Torvalds1da177e2005-04-16 15:20:36 -07001563 spin_unlock_irq(&lp->lock);
1564
1565 return 0;
1566}
1567
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001568/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001569This function changes the mtu of the device. It restarts the device to initialize the descriptor with new receive buffers.
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001570*/
Linus Torvalds1da177e2005-04-16 15:20:36 -07001571static int amd8111e_change_mtu(struct net_device *dev, int new_mtu)
1572{
1573 struct amd8111e_priv *lp = netdev_priv(dev);
1574 int err;
1575
1576 if ((new_mtu < AMD8111E_MIN_MTU) || (new_mtu > AMD8111E_MAX_MTU))
1577 return -EINVAL;
1578
1579 if (!netif_running(dev)) {
1580 /* new_mtu will be used
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001581 when device starts netxt time */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001582 dev->mtu = new_mtu;
1583 return 0;
1584 }
1585
1586 spin_lock_irq(&lp->lock);
1587
1588 /* stop the chip */
1589 writel(RUN, lp->mmio + CMD0);
1590
1591 dev->mtu = new_mtu;
1592
1593 err = amd8111e_restart(dev);
1594 spin_unlock_irq(&lp->lock);
1595 if(!err)
1596 netif_start_queue(dev);
1597 return err;
1598}
1599
1600#if AMD8111E_VLAN_TAG_USED
1601static void amd8111e_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1602{
1603 struct amd8111e_priv *lp = netdev_priv(dev);
1604 spin_lock_irq(&lp->lock);
1605 lp->vlgrp = grp;
1606 spin_unlock_irq(&lp->lock);
1607}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001608#endif
Stephen Hemminger25805dc2007-06-01 09:44:01 -07001609
Linus Torvalds1da177e2005-04-16 15:20:36 -07001610static int amd8111e_enable_magicpkt(struct amd8111e_priv* lp)
1611{
1612 writel( VAL1|MPPLBA, lp->mmio + CMD3);
1613 writel( VAL0|MPEN_SW, lp->mmio + CMD7);
1614
1615 /* To eliminate PCI posting bug */
1616 readl(lp->mmio + CMD7);
1617 return 0;
1618}
1619
1620static int amd8111e_enable_link_change(struct amd8111e_priv* lp)
1621{
1622
1623 /* Adapter is already stoped/suspended/interrupt-disabled */
1624 writel(VAL0|LCMODE_SW,lp->mmio + CMD7);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001625
Linus Torvalds1da177e2005-04-16 15:20:36 -07001626 /* To eliminate PCI posting bug */
1627 readl(lp->mmio + CMD7);
1628 return 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001629}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001630
André Goddard Rosaaf901ca2009-11-14 13:09:05 -02001631/*
1632 * This function is called when a packet transmission fails to complete
1633 * within a reasonable period, on the assumption that an interrupt have
1634 * failed or the interface is locked up. This function will reinitialize
1635 * the hardware.
1636 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001637static void amd8111e_tx_timeout(struct net_device *dev)
1638{
1639 struct amd8111e_priv* lp = netdev_priv(dev);
1640 int err;
1641
1642 printk(KERN_ERR "%s: transmit timed out, resetting\n",
1643 dev->name);
1644 spin_lock_irq(&lp->lock);
1645 err = amd8111e_restart(dev);
1646 spin_unlock_irq(&lp->lock);
1647 if(!err)
1648 netif_wake_queue(dev);
1649}
1650static int amd8111e_suspend(struct pci_dev *pci_dev, pm_message_t state)
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001651{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001652 struct net_device *dev = pci_get_drvdata(pci_dev);
1653 struct amd8111e_priv *lp = netdev_priv(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001654
Linus Torvalds1da177e2005-04-16 15:20:36 -07001655 if (!netif_running(dev))
1656 return 0;
1657
1658 /* disable the interrupt */
1659 spin_lock_irq(&lp->lock);
1660 amd8111e_disable_interrupt(lp);
1661 spin_unlock_irq(&lp->lock);
1662
1663 netif_device_detach(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001664
Linus Torvalds1da177e2005-04-16 15:20:36 -07001665 /* stop chip */
1666 spin_lock_irq(&lp->lock);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001667 if(lp->options & OPTION_DYN_IPG_ENABLE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001668 del_timer_sync(&lp->ipg_data.ipg_timer);
1669 amd8111e_stop_chip(lp);
1670 spin_unlock_irq(&lp->lock);
1671
1672 if(lp->options & OPTION_WOL_ENABLE){
1673 /* enable wol */
1674 if(lp->options & OPTION_WAKE_MAGIC_ENABLE)
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001675 amd8111e_enable_magicpkt(lp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001676 if(lp->options & OPTION_WAKE_PHY_ENABLE)
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001677 amd8111e_enable_link_change(lp);
1678
Linus Torvalds1da177e2005-04-16 15:20:36 -07001679 pci_enable_wake(pci_dev, PCI_D3hot, 1);
1680 pci_enable_wake(pci_dev, PCI_D3cold, 1);
1681
1682 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001683 else{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001684 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1685 pci_enable_wake(pci_dev, PCI_D3cold, 0);
1686 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001687
Linus Torvalds1da177e2005-04-16 15:20:36 -07001688 pci_save_state(pci_dev);
1689 pci_set_power_state(pci_dev, PCI_D3hot);
1690
1691 return 0;
1692}
1693static int amd8111e_resume(struct pci_dev *pci_dev)
1694{
1695 struct net_device *dev = pci_get_drvdata(pci_dev);
1696 struct amd8111e_priv *lp = netdev_priv(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001697
Linus Torvalds1da177e2005-04-16 15:20:36 -07001698 if (!netif_running(dev))
1699 return 0;
1700
1701 pci_set_power_state(pci_dev, PCI_D0);
1702 pci_restore_state(pci_dev);
1703
1704 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1705 pci_enable_wake(pci_dev, PCI_D3cold, 0); /* D3 cold */
1706
1707 netif_device_attach(dev);
1708
1709 spin_lock_irq(&lp->lock);
1710 amd8111e_restart(dev);
1711 /* Restart ipg timer */
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001712 if(lp->options & OPTION_DYN_IPG_ENABLE)
1713 mod_timer(&lp->ipg_data.ipg_timer,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001714 jiffies + IPG_CONVERGE_JIFFIES);
1715 spin_unlock_irq(&lp->lock);
1716
1717 return 0;
1718}
1719
1720
1721static void __devexit amd8111e_remove_one(struct pci_dev *pdev)
1722{
1723 struct net_device *dev = pci_get_drvdata(pdev);
1724 if (dev) {
1725 unregister_netdev(dev);
1726 iounmap(((struct amd8111e_priv *)netdev_priv(dev))->mmio);
1727 free_netdev(dev);
1728 pci_release_regions(pdev);
1729 pci_disable_device(pdev);
1730 pci_set_drvdata(pdev, NULL);
1731 }
1732}
1733static void amd8111e_config_ipg(struct net_device* dev)
1734{
1735 struct amd8111e_priv *lp = netdev_priv(dev);
1736 struct ipg_info* ipg_data = &lp->ipg_data;
1737 void __iomem *mmio = lp->mmio;
1738 unsigned int prev_col_cnt = ipg_data->col_cnt;
1739 unsigned int total_col_cnt;
1740 unsigned int tmp_ipg;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001741
Linus Torvalds1da177e2005-04-16 15:20:36 -07001742 if(lp->link_config.duplex == DUPLEX_FULL){
1743 ipg_data->ipg = DEFAULT_IPG;
1744 return;
1745 }
1746
1747 if(ipg_data->ipg_state == SSTATE){
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001748
Linus Torvalds1da177e2005-04-16 15:20:36 -07001749 if(ipg_data->timer_tick == IPG_STABLE_TIME){
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001750
Linus Torvalds1da177e2005-04-16 15:20:36 -07001751 ipg_data->timer_tick = 0;
1752 ipg_data->ipg = MIN_IPG - IPG_STEP;
1753 ipg_data->current_ipg = MIN_IPG;
1754 ipg_data->diff_col_cnt = 0xFFFFFFFF;
1755 ipg_data->ipg_state = CSTATE;
1756 }
1757 else
1758 ipg_data->timer_tick++;
1759 }
1760
1761 if(ipg_data->ipg_state == CSTATE){
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001762
Linus Torvalds1da177e2005-04-16 15:20:36 -07001763 /* Get the current collision count */
1764
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001765 total_col_cnt = ipg_data->col_cnt =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001766 amd8111e_read_mib(mmio, xmt_collisions);
1767
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001768 if ((total_col_cnt - prev_col_cnt) <
Linus Torvalds1da177e2005-04-16 15:20:36 -07001769 (ipg_data->diff_col_cnt)){
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001770
Linus Torvalds1da177e2005-04-16 15:20:36 -07001771 ipg_data->diff_col_cnt =
1772 total_col_cnt - prev_col_cnt ;
1773
1774 ipg_data->ipg = ipg_data->current_ipg;
1775 }
1776
1777 ipg_data->current_ipg += IPG_STEP;
1778
1779 if (ipg_data->current_ipg <= MAX_IPG)
1780 tmp_ipg = ipg_data->current_ipg;
1781 else{
1782 tmp_ipg = ipg_data->ipg;
1783 ipg_data->ipg_state = SSTATE;
1784 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001785 writew((u32)tmp_ipg, mmio + IPG);
1786 writew((u32)(tmp_ipg - IFS1_DELTA), mmio + IFS1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001787 }
1788 mod_timer(&lp->ipg_data.ipg_timer, jiffies + IPG_CONVERGE_JIFFIES);
1789 return;
1790
1791}
1792
1793static void __devinit amd8111e_probe_ext_phy(struct net_device* dev)
1794{
1795 struct amd8111e_priv *lp = netdev_priv(dev);
1796 int i;
1797
1798 for (i = 0x1e; i >= 0; i--) {
1799 u32 id1, id2;
1800
1801 if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
1802 continue;
1803 if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
1804 continue;
1805 lp->ext_phy_id = (id1 << 16) | id2;
1806 lp->ext_phy_addr = i;
1807 return;
1808 }
1809 lp->ext_phy_id = 0;
1810 lp->ext_phy_addr = 1;
1811}
1812
Stephen Hemminger887e53d2009-01-07 18:09:58 -08001813static const struct net_device_ops amd8111e_netdev_ops = {
1814 .ndo_open = amd8111e_open,
1815 .ndo_stop = amd8111e_close,
1816 .ndo_start_xmit = amd8111e_start_xmit,
1817 .ndo_tx_timeout = amd8111e_tx_timeout,
1818 .ndo_get_stats = amd8111e_get_stats,
1819 .ndo_set_multicast_list = amd8111e_set_multicast_list,
1820 .ndo_validate_addr = eth_validate_addr,
1821 .ndo_set_mac_address = amd8111e_set_mac_address,
1822 .ndo_do_ioctl = amd8111e_ioctl,
1823 .ndo_change_mtu = amd8111e_change_mtu,
1824#if AMD8111E_VLAN_TAG_USED
1825 .ndo_vlan_rx_register = amd8111e_vlan_rx_register,
1826#endif
1827#ifdef CONFIG_NET_POLL_CONTROLLER
1828 .ndo_poll_controller = amd8111e_poll,
1829#endif
1830};
1831
Linus Torvalds1da177e2005-04-16 15:20:36 -07001832static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
1833 const struct pci_device_id *ent)
1834{
1835 int err,i,pm_cap;
1836 unsigned long reg_addr,reg_len;
1837 struct amd8111e_priv* lp;
1838 struct net_device* dev;
1839
1840 err = pci_enable_device(pdev);
1841 if(err){
Joe Perches24500222007-11-19 17:48:28 -08001842 printk(KERN_ERR "amd8111e: Cannot enable new PCI device, "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001843 "exiting.\n");
1844 return err;
1845 }
1846
1847 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)){
Joe Perches24500222007-11-19 17:48:28 -08001848 printk(KERN_ERR "amd8111e: Cannot find PCI base address, "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001849 "exiting.\n");
1850 err = -ENODEV;
1851 goto err_disable_pdev;
1852 }
1853
1854 err = pci_request_regions(pdev, MODULE_NAME);
1855 if(err){
1856 printk(KERN_ERR "amd8111e: Cannot obtain PCI resources, "
1857 "exiting.\n");
1858 goto err_disable_pdev;
1859 }
1860
1861 pci_set_master(pdev);
1862
1863 /* Find power-management capability. */
1864 if((pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM))==0){
1865 printk(KERN_ERR "amd8111e: No Power Management capability, "
1866 "exiting.\n");
1867 goto err_free_reg;
1868 }
1869
1870 /* Initialize DMA */
Yang Hongyang284901a2009-04-06 19:01:15 -07001871 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) < 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001872 printk(KERN_ERR "amd8111e: DMA not supported,"
1873 "exiting.\n");
Tobias Klausercac8c812005-05-16 19:15:11 +02001874 goto err_free_reg;
1875 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001876
Linus Torvalds1da177e2005-04-16 15:20:36 -07001877 reg_addr = pci_resource_start(pdev, 0);
1878 reg_len = pci_resource_len(pdev, 0);
1879
1880 dev = alloc_etherdev(sizeof(struct amd8111e_priv));
1881 if (!dev) {
1882 printk(KERN_ERR "amd8111e: Etherdev alloc failed, exiting.\n");
1883 err = -ENOMEM;
1884 goto err_free_reg;
1885 }
1886
Linus Torvalds1da177e2005-04-16 15:20:36 -07001887 SET_NETDEV_DEV(dev, &pdev->dev);
1888
1889#if AMD8111E_VLAN_TAG_USED
1890 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX ;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001891#endif
1892
Linus Torvalds1da177e2005-04-16 15:20:36 -07001893 lp = netdev_priv(dev);
1894 lp->pci_dev = pdev;
1895 lp->amd8111e_net_dev = dev;
1896 lp->pm_cap = pm_cap;
1897
1898 spin_lock_init(&lp->lock);
1899
1900 lp->mmio = ioremap(reg_addr, reg_len);
Al Viroee41a822007-08-22 21:37:46 -04001901 if (!lp->mmio) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001902 printk(KERN_ERR "amd8111e: Cannot map device registers, "
1903 "exiting\n");
1904 err = -ENOMEM;
1905 goto err_free_dev;
1906 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001907
Linus Torvalds1da177e2005-04-16 15:20:36 -07001908 /* Initializing MAC address */
1909 for(i = 0; i < ETH_ADDR_LEN; i++)
Joe Perches0795af52007-10-03 17:59:30 -07001910 dev->dev_addr[i] = readb(lp->mmio + PADR + i);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001911
Linus Torvalds1da177e2005-04-16 15:20:36 -07001912 /* Setting user defined parametrs */
1913 lp->ext_phy_option = speed_duplex[card_idx];
1914 if(coalesce[card_idx])
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001915 lp->options |= OPTION_INTR_COAL_ENABLE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001916 if(dynamic_ipg[card_idx++])
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001917 lp->options |= OPTION_DYN_IPG_ENABLE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001918
Stephen Hemminger887e53d2009-01-07 18:09:58 -08001919
Linus Torvalds1da177e2005-04-16 15:20:36 -07001920 /* Initialize driver entry points */
Stephen Hemminger887e53d2009-01-07 18:09:58 -08001921 dev->netdev_ops = &amd8111e_netdev_ops;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001922 SET_ETHTOOL_OPS(dev, &ops);
1923 dev->irq =pdev->irq;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001924 dev->watchdog_timeo = AMD8111E_TX_TIMEOUT;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001925 netif_napi_add(dev, &lp->napi, amd8111e_rx_poll, 32);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001926
1927#if AMD8111E_VLAN_TAG_USED
1928 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001929#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001930 /* Probe the external PHY */
1931 amd8111e_probe_ext_phy(dev);
1932
1933 /* setting mii default values */
1934 lp->mii_if.dev = dev;
1935 lp->mii_if.mdio_read = amd8111e_mdio_read;
1936 lp->mii_if.mdio_write = amd8111e_mdio_write;
1937 lp->mii_if.phy_id = lp->ext_phy_addr;
1938
1939 /* Set receive buffer length and set jumbo option*/
1940 amd8111e_set_rx_buff_len(dev);
1941
1942
1943 err = register_netdev(dev);
1944 if (err) {
1945 printk(KERN_ERR "amd8111e: Cannot register net device, "
1946 "exiting.\n");
1947 goto err_iounmap;
1948 }
1949
1950 pci_set_drvdata(pdev, dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001951
Linus Torvalds1da177e2005-04-16 15:20:36 -07001952 /* Initialize software ipg timer */
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001953 if(lp->options & OPTION_DYN_IPG_ENABLE){
Linus Torvalds1da177e2005-04-16 15:20:36 -07001954 init_timer(&lp->ipg_data.ipg_timer);
1955 lp->ipg_data.ipg_timer.data = (unsigned long) dev;
1956 lp->ipg_data.ipg_timer.function = (void *)&amd8111e_config_ipg;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001957 lp->ipg_data.ipg_timer.expires = jiffies +
Linus Torvalds1da177e2005-04-16 15:20:36 -07001958 IPG_CONVERGE_JIFFIES;
1959 lp->ipg_data.ipg = DEFAULT_IPG;
1960 lp->ipg_data.ipg_state = CSTATE;
1961 };
1962
1963 /* display driver and device information */
1964
1965 chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000)>>28;
Joe Perches0795af52007-10-03 17:59:30 -07001966 printk(KERN_INFO "%s: AMD-8111e Driver Version: %s\n",
1967 dev->name,MODULE_VERS);
Johannes Berge1749612008-10-27 15:59:26 -07001968 printk(KERN_INFO "%s: [ Rev %x ] PCI 10/100BaseT Ethernet %pM\n",
1969 dev->name, chip_version, dev->dev_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001970 if (lp->ext_phy_id)
1971 printk(KERN_INFO "%s: Found MII PHY ID 0x%08x at address 0x%02x\n",
1972 dev->name, lp->ext_phy_id, lp->ext_phy_addr);
1973 else
1974 printk(KERN_INFO "%s: Couldn't detect MII PHY, assuming address 0x01\n",
1975 dev->name);
1976 return 0;
1977err_iounmap:
1978 iounmap(lp->mmio);
1979
1980err_free_dev:
1981 free_netdev(dev);
1982
1983err_free_reg:
1984 pci_release_regions(pdev);
1985
1986err_disable_pdev:
1987 pci_disable_device(pdev);
1988 pci_set_drvdata(pdev, NULL);
1989 return err;
1990
1991}
1992
1993static struct pci_driver amd8111e_driver = {
1994 .name = MODULE_NAME,
1995 .id_table = amd8111e_pci_tbl,
1996 .probe = amd8111e_probe_one,
1997 .remove = __devexit_p(amd8111e_remove_one),
1998 .suspend = amd8111e_suspend,
1999 .resume = amd8111e_resume
2000};
2001
2002static int __init amd8111e_init(void)
2003{
Jeff Garzik29917622006-08-19 17:48:59 -04002004 return pci_register_driver(&amd8111e_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002005}
2006
2007static void __exit amd8111e_cleanup(void)
2008{
2009 pci_unregister_driver(&amd8111e_driver);
2010}
2011
2012module_init(amd8111e_init);
2013module_exit(amd8111e_cleanup);