blob: 9872b52332f886a87babc2c9614f2bf5c80ae9a4 [file] [log] [blame]
Yusuke Godafdc50a92010-05-26 14:41:59 -07001/*
2 * MMCIF eMMC driver.
3 *
4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Yusuke Goda <yusuke.goda.sx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
10 *
11 *
12 * TODO
13 * 1. DMA
14 * 2. Power management
15 * 3. Handle MMC errors better
16 *
17 */
18
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +010019/*
20 * The MMCIF driver is now processing MMC requests asynchronously, according
21 * to the Linux MMC API requirement.
22 *
23 * The MMCIF driver processes MMC requests in up to 3 stages: command, optional
24 * data, and optional stop. To achieve asynchronous processing each of these
25 * stages is split into two halves: a top and a bottom half. The top half
26 * initialises the hardware, installs a timeout handler to handle completion
27 * timeouts, and returns. In case of the command stage this immediately returns
28 * control to the caller, leaving all further processing to run asynchronously.
29 * All further request processing is performed by the bottom halves.
30 *
31 * The bottom half further consists of a "hard" IRQ handler, an IRQ handler
32 * thread, a DMA completion callback, if DMA is used, a timeout work, and
33 * request- and stage-specific handler methods.
34 *
35 * Each bottom half run begins with either a hardware interrupt, a DMA callback
36 * invocation, or a timeout work run. In case of an error or a successful
37 * processing completion, the MMC core is informed and the request processing is
38 * finished. In case processing has to continue, i.e., if data has to be read
39 * from or written to the card, or if a stop command has to be sent, the next
40 * top half is called, which performs the necessary hardware handling and
41 * reschedules the timeout work. This returns the driver state machine into the
42 * bottom half waiting state.
43 */
44
Guennadi Liakhovetski86df1742011-11-23 15:52:30 +010045#include <linux/bitops.h>
Guennadi Liakhovetskiaa0787a2010-11-24 10:05:12 +000046#include <linux/clk.h>
47#include <linux/completion.h>
Guennadi Liakhovetskie47bf322010-11-24 10:05:18 +000048#include <linux/delay.h>
Yusuke Godafdc50a92010-05-26 14:41:59 -070049#include <linux/dma-mapping.h>
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +000050#include <linux/dmaengine.h>
Yusuke Godafdc50a92010-05-26 14:41:59 -070051#include <linux/mmc/card.h>
52#include <linux/mmc/core.h>
Guennadi Liakhovetskie47bf322010-11-24 10:05:18 +000053#include <linux/mmc/host.h>
Yusuke Godafdc50a92010-05-26 14:41:59 -070054#include <linux/mmc/mmc.h>
55#include <linux/mmc/sdio.h>
Yusuke Godafdc50a92010-05-26 14:41:59 -070056#include <linux/mmc/sh_mmcif.h>
Guennadi Liakhovetskie4806062012-06-14 14:24:35 +020057#include <linux/mmc/slot-gpio.h>
Guennadi Liakhovetskibf68a812012-05-01 18:18:16 +020058#include <linux/mod_devicetable.h>
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +000059#include <linux/pagemap.h>
Guennadi Liakhovetskie47bf322010-11-24 10:05:18 +000060#include <linux/platform_device.h>
Rafael J. Wysockiefe6a8a2012-03-13 01:02:15 +010061#include <linux/pm_qos.h>
Guennadi Liakhovetskifaca6642011-05-05 16:20:48 +000062#include <linux/pm_runtime.h>
Guennadi Liakhovetski3b0beaf2011-04-15 18:30:47 +000063#include <linux/spinlock.h>
Paul Gortmaker88b47672011-07-03 15:15:51 -040064#include <linux/module.h>
Yusuke Godafdc50a92010-05-26 14:41:59 -070065
66#define DRIVER_NAME "sh_mmcif"
67#define DRIVER_VERSION "2010-04-28"
68
Yusuke Godafdc50a92010-05-26 14:41:59 -070069/* CE_CMD_SET */
70#define CMD_MASK 0x3f000000
71#define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
72#define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
73#define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */
74#define CMD_SET_RBSY (1 << 21) /* R1b */
75#define CMD_SET_CCSEN (1 << 20)
76#define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */
77#define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */
78#define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */
79#define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */
80#define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */
81#define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */
82#define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */
83#define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/
84#define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/
85#define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
86#define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/
87#define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */
88#define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */
89#define CMD_SET_OPDM (1 << 6) /* 1: open/drain */
90#define CMD_SET_CCSH (1 << 5)
91#define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */
92#define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */
93#define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */
94
95/* CE_CMD_CTRL */
96#define CMD_CTRL_BREAK (1 << 0)
97
98/* CE_BLOCK_SET */
99#define BLOCK_SIZE_MASK 0x0000ffff
100
Yusuke Godafdc50a92010-05-26 14:41:59 -0700101/* CE_INT */
102#define INT_CCSDE (1 << 29)
103#define INT_CMD12DRE (1 << 26)
104#define INT_CMD12RBE (1 << 25)
105#define INT_CMD12CRE (1 << 24)
106#define INT_DTRANE (1 << 23)
107#define INT_BUFRE (1 << 22)
108#define INT_BUFWEN (1 << 21)
109#define INT_BUFREN (1 << 20)
110#define INT_CCSRCV (1 << 19)
111#define INT_RBSYE (1 << 17)
112#define INT_CRSPE (1 << 16)
113#define INT_CMDVIO (1 << 15)
114#define INT_BUFVIO (1 << 14)
115#define INT_WDATERR (1 << 11)
116#define INT_RDATERR (1 << 10)
117#define INT_RIDXERR (1 << 9)
118#define INT_RSPERR (1 << 8)
119#define INT_CCSTO (1 << 5)
120#define INT_CRCSTO (1 << 4)
121#define INT_WDATTO (1 << 3)
122#define INT_RDATTO (1 << 2)
123#define INT_RBSYTO (1 << 1)
124#define INT_RSPTO (1 << 0)
125#define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \
126 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
127 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
128 INT_RDATTO | INT_RBSYTO | INT_RSPTO)
129
130/* CE_INT_MASK */
131#define MASK_ALL 0x00000000
132#define MASK_MCCSDE (1 << 29)
133#define MASK_MCMD12DRE (1 << 26)
134#define MASK_MCMD12RBE (1 << 25)
135#define MASK_MCMD12CRE (1 << 24)
136#define MASK_MDTRANE (1 << 23)
137#define MASK_MBUFRE (1 << 22)
138#define MASK_MBUFWEN (1 << 21)
139#define MASK_MBUFREN (1 << 20)
140#define MASK_MCCSRCV (1 << 19)
141#define MASK_MRBSYE (1 << 17)
142#define MASK_MCRSPE (1 << 16)
143#define MASK_MCMDVIO (1 << 15)
144#define MASK_MBUFVIO (1 << 14)
145#define MASK_MWDATERR (1 << 11)
146#define MASK_MRDATERR (1 << 10)
147#define MASK_MRIDXERR (1 << 9)
148#define MASK_MRSPERR (1 << 8)
149#define MASK_MCCSTO (1 << 5)
150#define MASK_MCRCSTO (1 << 4)
151#define MASK_MWDATTO (1 << 3)
152#define MASK_MRDATTO (1 << 2)
153#define MASK_MRBSYTO (1 << 1)
154#define MASK_MRSPTO (1 << 0)
155
Guennadi Liakhovetskiee4b8882011-12-14 19:31:52 +0100156#define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
157 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \
158 MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \
159 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
160
Yusuke Godafdc50a92010-05-26 14:41:59 -0700161/* CE_HOST_STS1 */
162#define STS1_CMDSEQ (1 << 31)
163
164/* CE_HOST_STS2 */
165#define STS2_CRCSTE (1 << 31)
166#define STS2_CRC16E (1 << 30)
167#define STS2_AC12CRCE (1 << 29)
168#define STS2_RSPCRC7E (1 << 28)
169#define STS2_CRCSTEBE (1 << 27)
170#define STS2_RDATEBE (1 << 26)
171#define STS2_AC12REBE (1 << 25)
172#define STS2_RSPEBE (1 << 24)
173#define STS2_AC12IDXE (1 << 23)
174#define STS2_RSPIDXE (1 << 22)
175#define STS2_CCSTO (1 << 15)
176#define STS2_RDATTO (1 << 14)
177#define STS2_DATBSYTO (1 << 13)
178#define STS2_CRCSTTO (1 << 12)
179#define STS2_AC12BSYTO (1 << 11)
180#define STS2_RSPBSYTO (1 << 10)
181#define STS2_AC12RSPTO (1 << 9)
182#define STS2_RSPTO (1 << 8)
183#define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \
184 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
185#define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \
186 STS2_DATBSYTO | STS2_CRCSTTO | \
187 STS2_AC12BSYTO | STS2_RSPBSYTO | \
188 STS2_AC12RSPTO | STS2_RSPTO)
189
Yusuke Godafdc50a92010-05-26 14:41:59 -0700190#define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
191#define CLKDEV_MMC_DATA 20000000 /* 20MHz */
192#define CLKDEV_INIT 400000 /* 400 KHz */
193
Guennadi Liakhovetski3b0beaf2011-04-15 18:30:47 +0000194enum mmcif_state {
195 STATE_IDLE,
196 STATE_REQUEST,
197 STATE_IOS,
198};
199
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100200enum mmcif_wait_for {
201 MMCIF_WAIT_FOR_REQUEST,
202 MMCIF_WAIT_FOR_CMD,
203 MMCIF_WAIT_FOR_MREAD,
204 MMCIF_WAIT_FOR_MWRITE,
205 MMCIF_WAIT_FOR_READ,
206 MMCIF_WAIT_FOR_WRITE,
207 MMCIF_WAIT_FOR_READ_END,
208 MMCIF_WAIT_FOR_WRITE_END,
209 MMCIF_WAIT_FOR_STOP,
210};
211
Yusuke Godafdc50a92010-05-26 14:41:59 -0700212struct sh_mmcif_host {
213 struct mmc_host *mmc;
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100214 struct mmc_request *mrq;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700215 struct platform_device *pd;
216 struct clk *hclk;
217 unsigned int clk;
218 int bus_width;
Guennadi Liakhovetskiaa0787a2010-11-24 10:05:12 +0000219 bool sd_error;
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100220 bool dying;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700221 long timeout;
222 void __iomem *addr;
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100223 u32 *pio_ptr;
Guennadi Liakhovetskiee4b8882011-12-14 19:31:52 +0100224 spinlock_t lock; /* protect sh_mmcif_host::state */
Guennadi Liakhovetski3b0beaf2011-04-15 18:30:47 +0000225 enum mmcif_state state;
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100226 enum mmcif_wait_for wait_for;
227 struct delayed_work timeout_work;
228 size_t blocksize;
229 int sg_idx;
230 int sg_blkidx;
Guennadi Liakhovetskifaca6642011-05-05 16:20:48 +0000231 bool power;
Guennadi Liakhovetskic9b0cef2011-05-26 15:33:30 +0200232 bool card_present;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700233
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000234 /* DMA support */
235 struct dma_chan *chan_rx;
236 struct dma_chan *chan_tx;
237 struct completion dma_complete;
Linus Walleijf38f94c2011-02-10 16:09:50 +0100238 bool dma_active;
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000239};
Yusuke Godafdc50a92010-05-26 14:41:59 -0700240
241static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
242 unsigned int reg, u32 val)
243{
Magnus Damm487d9fc2010-05-18 14:42:51 +0000244 writel(val | readl(host->addr + reg), host->addr + reg);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700245}
246
247static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
248 unsigned int reg, u32 val)
249{
Magnus Damm487d9fc2010-05-18 14:42:51 +0000250 writel(~val & readl(host->addr + reg), host->addr + reg);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700251}
252
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000253static void mmcif_dma_complete(void *arg)
254{
255 struct sh_mmcif_host *host = arg;
Guennadi Liakhovetski69983402011-12-26 12:52:13 -0500256 struct mmc_data *data = host->mrq->data;
257
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000258 dev_dbg(&host->pd->dev, "Command completed\n");
259
Guennadi Liakhovetski69983402011-12-26 12:52:13 -0500260 if (WARN(!data, "%s: NULL data in DMA completion!\n",
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000261 dev_name(&host->pd->dev)))
262 return;
263
Guennadi Liakhovetski69983402011-12-26 12:52:13 -0500264 if (data->flags & MMC_DATA_READ)
Linus Walleij1ed828d2011-02-10 16:09:29 +0100265 dma_unmap_sg(host->chan_rx->device->dev,
Guennadi Liakhovetski69983402011-12-26 12:52:13 -0500266 data->sg, data->sg_len,
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000267 DMA_FROM_DEVICE);
268 else
Linus Walleij1ed828d2011-02-10 16:09:29 +0100269 dma_unmap_sg(host->chan_tx->device->dev,
Guennadi Liakhovetski69983402011-12-26 12:52:13 -0500270 data->sg, data->sg_len,
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000271 DMA_TO_DEVICE);
272
273 complete(&host->dma_complete);
274}
275
276static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
277{
Guennadi Liakhovetski69983402011-12-26 12:52:13 -0500278 struct mmc_data *data = host->mrq->data;
279 struct scatterlist *sg = data->sg;
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000280 struct dma_async_tx_descriptor *desc = NULL;
281 struct dma_chan *chan = host->chan_rx;
282 dma_cookie_t cookie = -EINVAL;
283 int ret;
284
Guennadi Liakhovetski69983402011-12-26 12:52:13 -0500285 ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
Linus Walleij1ed828d2011-02-10 16:09:29 +0100286 DMA_FROM_DEVICE);
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000287 if (ret > 0) {
Linus Walleijf38f94c2011-02-10 16:09:50 +0100288 host->dma_active = true;
Alexandre Bounine16052822012-03-08 16:11:18 -0500289 desc = dmaengine_prep_slave_sg(chan, sg, ret,
Vinod Koul05f57992011-10-14 10:45:11 +0530290 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000291 }
292
293 if (desc) {
294 desc->callback = mmcif_dma_complete;
295 desc->callback_param = host;
Linus Walleija5ece7d2011-02-10 16:10:00 +0100296 cookie = dmaengine_submit(desc);
297 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
298 dma_async_issue_pending(chan);
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000299 }
300 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
Guennadi Liakhovetski69983402011-12-26 12:52:13 -0500301 __func__, data->sg_len, ret, cookie);
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000302
303 if (!desc) {
304 /* DMA failed, fall back to PIO */
305 if (ret >= 0)
306 ret = -EIO;
307 host->chan_rx = NULL;
Linus Walleijf38f94c2011-02-10 16:09:50 +0100308 host->dma_active = false;
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000309 dma_release_channel(chan);
310 /* Free the Tx channel too */
311 chan = host->chan_tx;
312 if (chan) {
313 host->chan_tx = NULL;
314 dma_release_channel(chan);
315 }
316 dev_warn(&host->pd->dev,
317 "DMA failed: %d, falling back to PIO\n", ret);
318 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
319 }
320
321 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
Guennadi Liakhovetski69983402011-12-26 12:52:13 -0500322 desc, cookie, data->sg_len);
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000323}
324
325static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
326{
Guennadi Liakhovetski69983402011-12-26 12:52:13 -0500327 struct mmc_data *data = host->mrq->data;
328 struct scatterlist *sg = data->sg;
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000329 struct dma_async_tx_descriptor *desc = NULL;
330 struct dma_chan *chan = host->chan_tx;
331 dma_cookie_t cookie = -EINVAL;
332 int ret;
333
Guennadi Liakhovetski69983402011-12-26 12:52:13 -0500334 ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
Linus Walleij1ed828d2011-02-10 16:09:29 +0100335 DMA_TO_DEVICE);
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000336 if (ret > 0) {
Linus Walleijf38f94c2011-02-10 16:09:50 +0100337 host->dma_active = true;
Alexandre Bounine16052822012-03-08 16:11:18 -0500338 desc = dmaengine_prep_slave_sg(chan, sg, ret,
Vinod Koul05f57992011-10-14 10:45:11 +0530339 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000340 }
341
342 if (desc) {
343 desc->callback = mmcif_dma_complete;
344 desc->callback_param = host;
Linus Walleija5ece7d2011-02-10 16:10:00 +0100345 cookie = dmaengine_submit(desc);
346 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
347 dma_async_issue_pending(chan);
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000348 }
349 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
Guennadi Liakhovetski69983402011-12-26 12:52:13 -0500350 __func__, data->sg_len, ret, cookie);
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000351
352 if (!desc) {
353 /* DMA failed, fall back to PIO */
354 if (ret >= 0)
355 ret = -EIO;
356 host->chan_tx = NULL;
Linus Walleijf38f94c2011-02-10 16:09:50 +0100357 host->dma_active = false;
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000358 dma_release_channel(chan);
359 /* Free the Rx channel too */
360 chan = host->chan_rx;
361 if (chan) {
362 host->chan_rx = NULL;
363 dma_release_channel(chan);
364 }
365 dev_warn(&host->pd->dev,
366 "DMA failed: %d, falling back to PIO\n", ret);
367 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
368 }
369
370 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__,
371 desc, cookie);
372}
373
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000374static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
375 struct sh_mmcif_plat_data *pdata)
376{
Guennadi Liakhovetski0e79f9a2012-07-05 12:29:43 +0200377 struct resource *res = platform_get_resource(host->pd, IORESOURCE_MEM, 0);
378 struct dma_slave_config cfg;
379 dma_cap_mask_t mask;
380 int ret;
381
Linus Walleijf38f94c2011-02-10 16:09:50 +0100382 host->dma_active = false;
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000383
Guennadi Liakhovetskibf68a812012-05-01 18:18:16 +0200384 if (!pdata)
385 return;
386
Guennadi Liakhovetski0e79f9a2012-07-05 12:29:43 +0200387 if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0)
388 return;
389
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000390 /* We can only either use DMA for both Tx and Rx or not use it at all */
Guennadi Liakhovetski0e79f9a2012-07-05 12:29:43 +0200391 dma_cap_zero(mask);
392 dma_cap_set(DMA_SLAVE, mask);
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000393
Guennadi Liakhovetski0e79f9a2012-07-05 12:29:43 +0200394 host->chan_tx = dma_request_channel(mask, shdma_chan_filter,
395 (void *)pdata->slave_id_tx);
396 dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__,
397 host->chan_tx);
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000398
Guennadi Liakhovetski0e79f9a2012-07-05 12:29:43 +0200399 if (!host->chan_tx)
400 return;
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000401
Guennadi Liakhovetski0e79f9a2012-07-05 12:29:43 +0200402 cfg.slave_id = pdata->slave_id_tx;
403 cfg.direction = DMA_MEM_TO_DEV;
404 cfg.dst_addr = res->start + MMCIF_CE_DATA;
405 cfg.src_addr = 0;
406 ret = dmaengine_slave_config(host->chan_tx, &cfg);
407 if (ret < 0)
408 goto ecfgtx;
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000409
Guennadi Liakhovetski0e79f9a2012-07-05 12:29:43 +0200410 host->chan_rx = dma_request_channel(mask, shdma_chan_filter,
411 (void *)pdata->slave_id_rx);
412 dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__,
413 host->chan_rx);
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000414
Guennadi Liakhovetski0e79f9a2012-07-05 12:29:43 +0200415 if (!host->chan_rx)
416 goto erqrx;
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000417
Guennadi Liakhovetski0e79f9a2012-07-05 12:29:43 +0200418 cfg.slave_id = pdata->slave_id_rx;
419 cfg.direction = DMA_DEV_TO_MEM;
420 cfg.dst_addr = 0;
421 cfg.src_addr = res->start + MMCIF_CE_DATA;
422 ret = dmaengine_slave_config(host->chan_rx, &cfg);
423 if (ret < 0)
424 goto ecfgrx;
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000425
Guennadi Liakhovetski0e79f9a2012-07-05 12:29:43 +0200426 init_completion(&host->dma_complete);
427
428 return;
429
430ecfgrx:
431 dma_release_channel(host->chan_rx);
432 host->chan_rx = NULL;
433erqrx:
434ecfgtx:
435 dma_release_channel(host->chan_tx);
436 host->chan_tx = NULL;
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000437}
438
439static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
440{
441 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
442 /* Descriptors are freed automatically */
443 if (host->chan_tx) {
444 struct dma_chan *chan = host->chan_tx;
445 host->chan_tx = NULL;
446 dma_release_channel(chan);
447 }
448 if (host->chan_rx) {
449 struct dma_chan *chan = host->chan_rx;
450 host->chan_rx = NULL;
451 dma_release_channel(chan);
452 }
453
Linus Walleijf38f94c2011-02-10 16:09:50 +0100454 host->dma_active = false;
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +0000455}
Yusuke Godafdc50a92010-05-26 14:41:59 -0700456
457static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
458{
459 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
Guennadi Liakhovetskibf68a812012-05-01 18:18:16 +0200460 bool sup_pclk = p ? p->sup_pclk : false;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700461
462 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
463 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
464
465 if (!clk)
466 return;
Guennadi Liakhovetskibf68a812012-05-01 18:18:16 +0200467 if (sup_pclk && clk == host->clk)
Yusuke Godafdc50a92010-05-26 14:41:59 -0700468 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
469 else
470 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
Simon Hormanf9388252012-03-28 18:01:09 +0900471 ((fls(DIV_ROUND_UP(host->clk,
472 clk) - 1) - 1) << 16));
Yusuke Godafdc50a92010-05-26 14:41:59 -0700473
474 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
475}
476
477static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
478{
479 u32 tmp;
480
Magnus Damm487d9fc2010-05-18 14:42:51 +0000481 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700482
Magnus Damm487d9fc2010-05-18 14:42:51 +0000483 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
484 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700485 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
486 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
487 /* byte swap on */
488 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
489}
490
491static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
492{
493 u32 state1, state2;
Guennadi Liakhovetskiee4b8882011-12-14 19:31:52 +0100494 int ret, timeout;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700495
Guennadi Liakhovetskiaa0787a2010-11-24 10:05:12 +0000496 host->sd_error = false;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700497
Magnus Damm487d9fc2010-05-18 14:42:51 +0000498 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
499 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
Guennadi Liakhovetskie47bf322010-11-24 10:05:18 +0000500 dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1);
501 dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700502
503 if (state1 & STS1_CMDSEQ) {
504 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
505 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
Guennadi Liakhovetskiee4b8882011-12-14 19:31:52 +0100506 for (timeout = 10000000; timeout; timeout--) {
Magnus Damm487d9fc2010-05-18 14:42:51 +0000507 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
Guennadi Liakhovetskiee4b8882011-12-14 19:31:52 +0100508 & STS1_CMDSEQ))
Yusuke Godafdc50a92010-05-26 14:41:59 -0700509 break;
510 mdelay(1);
511 }
Guennadi Liakhovetskiee4b8882011-12-14 19:31:52 +0100512 if (!timeout) {
513 dev_err(&host->pd->dev,
514 "Forced end of command sequence timeout err\n");
515 return -EIO;
516 }
Yusuke Godafdc50a92010-05-26 14:41:59 -0700517 sh_mmcif_sync_reset(host);
Guennadi Liakhovetskie47bf322010-11-24 10:05:18 +0000518 dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
Yusuke Godafdc50a92010-05-26 14:41:59 -0700519 return -EIO;
520 }
521
522 if (state2 & STS2_CRC_ERR) {
Guennadi Liakhovetskiee4b8882011-12-14 19:31:52 +0100523 dev_dbg(&host->pd->dev, ": CRC error\n");
Yusuke Godafdc50a92010-05-26 14:41:59 -0700524 ret = -EIO;
525 } else if (state2 & STS2_TIMEOUT_ERR) {
Guennadi Liakhovetskiee4b8882011-12-14 19:31:52 +0100526 dev_dbg(&host->pd->dev, ": Timeout\n");
Yusuke Godafdc50a92010-05-26 14:41:59 -0700527 ret = -ETIMEDOUT;
528 } else {
Guennadi Liakhovetskiee4b8882011-12-14 19:31:52 +0100529 dev_dbg(&host->pd->dev, ": End/Index error\n");
Yusuke Godafdc50a92010-05-26 14:41:59 -0700530 ret = -EIO;
531 }
532 return ret;
533}
534
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100535static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p)
Yusuke Godafdc50a92010-05-26 14:41:59 -0700536{
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100537 struct mmc_data *data = host->mrq->data;
538
539 host->sg_blkidx += host->blocksize;
540
541 /* data->sg->length must be a multiple of host->blocksize? */
542 BUG_ON(host->sg_blkidx > data->sg->length);
543
544 if (host->sg_blkidx == data->sg->length) {
545 host->sg_blkidx = 0;
546 if (++host->sg_idx < data->sg_len)
547 host->pio_ptr = sg_virt(++data->sg);
548 } else {
549 host->pio_ptr = p;
550 }
551
552 if (host->sg_idx == data->sg_len)
553 return false;
554
555 return true;
556}
557
558static void sh_mmcif_single_read(struct sh_mmcif_host *host,
559 struct mmc_request *mrq)
560{
561 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
562 BLOCK_SIZE_MASK) + 3;
563
564 host->wait_for = MMCIF_WAIT_FOR_READ;
565 schedule_delayed_work(&host->timeout_work, host->timeout);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700566
Yusuke Godafdc50a92010-05-26 14:41:59 -0700567 /* buf read enable */
568 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100569}
Yusuke Godafdc50a92010-05-26 14:41:59 -0700570
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100571static bool sh_mmcif_read_block(struct sh_mmcif_host *host)
572{
573 struct mmc_data *data = host->mrq->data;
574 u32 *p = sg_virt(data->sg);
575 int i;
576
577 if (host->sd_error) {
578 data->error = sh_mmcif_error_manage(host);
579 return false;
580 }
581
582 for (i = 0; i < host->blocksize / 4; i++)
Magnus Damm487d9fc2010-05-18 14:42:51 +0000583 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700584
585 /* buffer read end */
586 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100587 host->wait_for = MMCIF_WAIT_FOR_READ_END;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700588
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100589 return true;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700590}
591
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100592static void sh_mmcif_multi_read(struct sh_mmcif_host *host,
593 struct mmc_request *mrq)
Yusuke Godafdc50a92010-05-26 14:41:59 -0700594{
595 struct mmc_data *data = mrq->data;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700596
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100597 if (!data->sg_len || !data->sg->length)
598 return;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700599
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100600 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
601 BLOCK_SIZE_MASK;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700602
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100603 host->wait_for = MMCIF_WAIT_FOR_MREAD;
604 host->sg_idx = 0;
605 host->sg_blkidx = 0;
606 host->pio_ptr = sg_virt(data->sg);
607 schedule_delayed_work(&host->timeout_work, host->timeout);
608 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
609}
610
611static bool sh_mmcif_mread_block(struct sh_mmcif_host *host)
612{
613 struct mmc_data *data = host->mrq->data;
614 u32 *p = host->pio_ptr;
615 int i;
616
617 if (host->sd_error) {
618 data->error = sh_mmcif_error_manage(host);
619 return false;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700620 }
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100621
622 BUG_ON(!data->sg->length);
623
624 for (i = 0; i < host->blocksize / 4; i++)
625 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
626
627 if (!sh_mmcif_next_block(host, p))
628 return false;
629
630 schedule_delayed_work(&host->timeout_work, host->timeout);
631 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
632
633 return true;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700634}
635
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100636static void sh_mmcif_single_write(struct sh_mmcif_host *host,
Yusuke Godafdc50a92010-05-26 14:41:59 -0700637 struct mmc_request *mrq)
638{
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100639 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
640 BLOCK_SIZE_MASK) + 3;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700641
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100642 host->wait_for = MMCIF_WAIT_FOR_WRITE;
643 schedule_delayed_work(&host->timeout_work, host->timeout);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700644
645 /* buf write enable */
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100646 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
647}
Yusuke Godafdc50a92010-05-26 14:41:59 -0700648
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100649static bool sh_mmcif_write_block(struct sh_mmcif_host *host)
650{
651 struct mmc_data *data = host->mrq->data;
652 u32 *p = sg_virt(data->sg);
653 int i;
654
655 if (host->sd_error) {
656 data->error = sh_mmcif_error_manage(host);
657 return false;
658 }
659
660 for (i = 0; i < host->blocksize / 4; i++)
Magnus Damm487d9fc2010-05-18 14:42:51 +0000661 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700662
663 /* buffer write end */
664 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100665 host->wait_for = MMCIF_WAIT_FOR_WRITE_END;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700666
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100667 return true;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700668}
669
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100670static void sh_mmcif_multi_write(struct sh_mmcif_host *host,
671 struct mmc_request *mrq)
Yusuke Godafdc50a92010-05-26 14:41:59 -0700672{
673 struct mmc_data *data = mrq->data;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700674
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100675 if (!data->sg_len || !data->sg->length)
676 return;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700677
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100678 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
679 BLOCK_SIZE_MASK;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700680
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100681 host->wait_for = MMCIF_WAIT_FOR_MWRITE;
682 host->sg_idx = 0;
683 host->sg_blkidx = 0;
684 host->pio_ptr = sg_virt(data->sg);
685 schedule_delayed_work(&host->timeout_work, host->timeout);
686 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
687}
Yusuke Godafdc50a92010-05-26 14:41:59 -0700688
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100689static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host)
690{
691 struct mmc_data *data = host->mrq->data;
692 u32 *p = host->pio_ptr;
693 int i;
694
695 if (host->sd_error) {
696 data->error = sh_mmcif_error_manage(host);
697 return false;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700698 }
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100699
700 BUG_ON(!data->sg->length);
701
702 for (i = 0; i < host->blocksize / 4; i++)
703 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
704
705 if (!sh_mmcif_next_block(host, p))
706 return false;
707
708 schedule_delayed_work(&host->timeout_work, host->timeout);
709 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
710
711 return true;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700712}
713
714static void sh_mmcif_get_response(struct sh_mmcif_host *host,
715 struct mmc_command *cmd)
716{
717 if (cmd->flags & MMC_RSP_136) {
Magnus Damm487d9fc2010-05-18 14:42:51 +0000718 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
719 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
720 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
721 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700722 } else
Magnus Damm487d9fc2010-05-18 14:42:51 +0000723 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700724}
725
726static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
727 struct mmc_command *cmd)
728{
Magnus Damm487d9fc2010-05-18 14:42:51 +0000729 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700730}
731
732static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
Guennadi Liakhovetski69983402011-12-26 12:52:13 -0500733 struct mmc_request *mrq)
Yusuke Godafdc50a92010-05-26 14:41:59 -0700734{
Guennadi Liakhovetski69983402011-12-26 12:52:13 -0500735 struct mmc_data *data = mrq->data;
736 struct mmc_command *cmd = mrq->cmd;
737 u32 opc = cmd->opcode;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700738 u32 tmp = 0;
739
740 /* Response Type check */
741 switch (mmc_resp_type(cmd)) {
742 case MMC_RSP_NONE:
743 tmp |= CMD_SET_RTYP_NO;
744 break;
745 case MMC_RSP_R1:
746 case MMC_RSP_R1B:
747 case MMC_RSP_R3:
748 tmp |= CMD_SET_RTYP_6B;
749 break;
750 case MMC_RSP_R2:
751 tmp |= CMD_SET_RTYP_17B;
752 break;
753 default:
Guennadi Liakhovetskie47bf322010-11-24 10:05:18 +0000754 dev_err(&host->pd->dev, "Unsupported response type.\n");
Yusuke Godafdc50a92010-05-26 14:41:59 -0700755 break;
756 }
757 switch (opc) {
758 /* RBSY */
759 case MMC_SWITCH:
760 case MMC_STOP_TRANSMISSION:
761 case MMC_SET_WRITE_PROT:
762 case MMC_CLR_WRITE_PROT:
763 case MMC_ERASE:
Yusuke Godafdc50a92010-05-26 14:41:59 -0700764 tmp |= CMD_SET_RBSY;
765 break;
766 }
767 /* WDAT / DATW */
Guennadi Liakhovetski69983402011-12-26 12:52:13 -0500768 if (data) {
Yusuke Godafdc50a92010-05-26 14:41:59 -0700769 tmp |= CMD_SET_WDAT;
770 switch (host->bus_width) {
771 case MMC_BUS_WIDTH_1:
772 tmp |= CMD_SET_DATW_1;
773 break;
774 case MMC_BUS_WIDTH_4:
775 tmp |= CMD_SET_DATW_4;
776 break;
777 case MMC_BUS_WIDTH_8:
778 tmp |= CMD_SET_DATW_8;
779 break;
780 default:
Guennadi Liakhovetskie47bf322010-11-24 10:05:18 +0000781 dev_err(&host->pd->dev, "Unsupported bus width.\n");
Yusuke Godafdc50a92010-05-26 14:41:59 -0700782 break;
783 }
784 }
785 /* DWEN */
786 if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
787 tmp |= CMD_SET_DWEN;
788 /* CMLTE/CMD12EN */
789 if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
790 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
791 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
Guennadi Liakhovetski69983402011-12-26 12:52:13 -0500792 data->blocks << 16);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700793 }
794 /* RIDXC[1:0] check bits */
795 if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
796 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
797 tmp |= CMD_SET_RIDXC_BITS;
798 /* RCRC7C[1:0] check bits */
799 if (opc == MMC_SEND_OP_COND)
800 tmp |= CMD_SET_CRC7C_BITS;
801 /* RCRC7C[1:0] internal CRC7 */
802 if (opc == MMC_ALL_SEND_CID ||
803 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
804 tmp |= CMD_SET_CRC7C_INTERNAL;
805
Guennadi Liakhovetski69983402011-12-26 12:52:13 -0500806 return (opc << 24) | tmp;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700807}
808
Guennadi Liakhovetskie47bf322010-11-24 10:05:18 +0000809static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100810 struct mmc_request *mrq, u32 opc)
Yusuke Godafdc50a92010-05-26 14:41:59 -0700811{
Yusuke Godafdc50a92010-05-26 14:41:59 -0700812 switch (opc) {
813 case MMC_READ_MULTIPLE_BLOCK:
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100814 sh_mmcif_multi_read(host, mrq);
815 return 0;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700816 case MMC_WRITE_MULTIPLE_BLOCK:
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100817 sh_mmcif_multi_write(host, mrq);
818 return 0;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700819 case MMC_WRITE_BLOCK:
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100820 sh_mmcif_single_write(host, mrq);
821 return 0;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700822 case MMC_READ_SINGLE_BLOCK:
823 case MMC_SEND_EXT_CSD:
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100824 sh_mmcif_single_read(host, mrq);
825 return 0;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700826 default:
Guennadi Liakhovetskie47bf322010-11-24 10:05:18 +0000827 dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc);
Guennadi Liakhovetskiee4b8882011-12-14 19:31:52 +0100828 return -EINVAL;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700829 }
Yusuke Godafdc50a92010-05-26 14:41:59 -0700830}
831
832static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
Guennadi Liakhovetskiee4b8882011-12-14 19:31:52 +0100833 struct mmc_request *mrq)
Yusuke Godafdc50a92010-05-26 14:41:59 -0700834{
Guennadi Liakhovetskiee4b8882011-12-14 19:31:52 +0100835 struct mmc_command *cmd = mrq->cmd;
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100836 u32 opc = cmd->opcode;
837 u32 mask;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700838
Yusuke Godafdc50a92010-05-26 14:41:59 -0700839 switch (opc) {
Guennadi Liakhovetskiee4b8882011-12-14 19:31:52 +0100840 /* response busy check */
Yusuke Godafdc50a92010-05-26 14:41:59 -0700841 case MMC_SWITCH:
842 case MMC_STOP_TRANSMISSION:
843 case MMC_SET_WRITE_PROT:
844 case MMC_CLR_WRITE_PROT:
845 case MMC_ERASE:
Guennadi Liakhovetskiee4b8882011-12-14 19:31:52 +0100846 mask = MASK_START_CMD | MASK_MRBSYE;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700847 break;
848 default:
Guennadi Liakhovetskiee4b8882011-12-14 19:31:52 +0100849 mask = MASK_START_CMD | MASK_MCRSPE;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700850 break;
851 }
Yusuke Godafdc50a92010-05-26 14:41:59 -0700852
Guennadi Liakhovetski69983402011-12-26 12:52:13 -0500853 if (mrq->data) {
Magnus Damm487d9fc2010-05-18 14:42:51 +0000854 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
855 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
856 mrq->data->blksz);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700857 }
Guennadi Liakhovetski69983402011-12-26 12:52:13 -0500858 opc = sh_mmcif_set_cmd(host, mrq);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700859
Magnus Damm487d9fc2010-05-18 14:42:51 +0000860 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
861 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700862 /* set arg */
Magnus Damm487d9fc2010-05-18 14:42:51 +0000863 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700864 /* set cmd */
Magnus Damm487d9fc2010-05-18 14:42:51 +0000865 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700866
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100867 host->wait_for = MMCIF_WAIT_FOR_CMD;
868 schedule_delayed_work(&host->timeout_work, host->timeout);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700869}
870
871static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
Guennadi Liakhovetskiee4b8882011-12-14 19:31:52 +0100872 struct mmc_request *mrq)
Yusuke Godafdc50a92010-05-26 14:41:59 -0700873{
Guennadi Liakhovetski69983402011-12-26 12:52:13 -0500874 switch (mrq->cmd->opcode) {
875 case MMC_READ_MULTIPLE_BLOCK:
Yusuke Godafdc50a92010-05-26 14:41:59 -0700876 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
Guennadi Liakhovetski69983402011-12-26 12:52:13 -0500877 break;
878 case MMC_WRITE_MULTIPLE_BLOCK:
Yusuke Godafdc50a92010-05-26 14:41:59 -0700879 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
Guennadi Liakhovetski69983402011-12-26 12:52:13 -0500880 break;
881 default:
Guennadi Liakhovetskie47bf322010-11-24 10:05:18 +0000882 dev_err(&host->pd->dev, "unsupported stop cmd\n");
Guennadi Liakhovetski69983402011-12-26 12:52:13 -0500883 mrq->stop->error = sh_mmcif_error_manage(host);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700884 return;
885 }
886
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100887 host->wait_for = MMCIF_WAIT_FOR_STOP;
888 schedule_delayed_work(&host->timeout_work, host->timeout);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700889}
890
891static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
892{
893 struct sh_mmcif_host *host = mmc_priv(mmc);
Guennadi Liakhovetski3b0beaf2011-04-15 18:30:47 +0000894 unsigned long flags;
895
896 spin_lock_irqsave(&host->lock, flags);
897 if (host->state != STATE_IDLE) {
898 spin_unlock_irqrestore(&host->lock, flags);
899 mrq->cmd->error = -EAGAIN;
900 mmc_request_done(mmc, mrq);
901 return;
902 }
903
904 host->state = STATE_REQUEST;
905 spin_unlock_irqrestore(&host->lock, flags);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700906
907 switch (mrq->cmd->opcode) {
908 /* MMCIF does not support SD/SDIO command */
Laurent Pinchart7541ca92012-06-12 22:56:09 +0200909 case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */
910 case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
911 if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR)
912 break;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700913 case MMC_APP_CMD:
Guennadi Liakhovetski3b0beaf2011-04-15 18:30:47 +0000914 host->state = STATE_IDLE;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700915 mrq->cmd->error = -ETIMEDOUT;
916 mmc_request_done(mmc, mrq);
917 return;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700918 default:
919 break;
920 }
Yusuke Godafdc50a92010-05-26 14:41:59 -0700921
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100922 host->mrq = mrq;
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +0100923
924 sh_mmcif_start_cmd(host, mrq);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700925}
926
Guennadi Liakhovetskia6609262012-04-19 18:02:50 +0200927static int sh_mmcif_clk_update(struct sh_mmcif_host *host)
928{
929 int ret = clk_enable(host->hclk);
930
931 if (!ret) {
932 host->clk = clk_get_rate(host->hclk);
933 host->mmc->f_max = host->clk / 2;
934 host->mmc->f_min = host->clk / 512;
935 }
936
937 return ret;
938}
939
Guennadi Liakhovetski7d17baa2012-04-20 18:27:13 +0200940static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios)
941{
942 struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data;
943 struct mmc_host *mmc = host->mmc;
944
Guennadi Liakhovetskibf68a812012-05-01 18:18:16 +0200945 if (pd && pd->set_pwr)
Guennadi Liakhovetski7d17baa2012-04-20 18:27:13 +0200946 pd->set_pwr(host->pd, ios->power_mode != MMC_POWER_OFF);
947 if (!IS_ERR(mmc->supply.vmmc))
948 /* Errors ignored... */
949 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
950 ios->power_mode ? ios->vdd : 0);
951}
952
Yusuke Godafdc50a92010-05-26 14:41:59 -0700953static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
954{
955 struct sh_mmcif_host *host = mmc_priv(mmc);
Guennadi Liakhovetski3b0beaf2011-04-15 18:30:47 +0000956 unsigned long flags;
957
958 spin_lock_irqsave(&host->lock, flags);
959 if (host->state != STATE_IDLE) {
960 spin_unlock_irqrestore(&host->lock, flags);
961 return;
962 }
963
964 host->state = STATE_IOS;
965 spin_unlock_irqrestore(&host->lock, flags);
Yusuke Godafdc50a92010-05-26 14:41:59 -0700966
Guennadi Liakhovetskif5e0cec2011-02-25 16:58:38 +0100967 if (ios->power_mode == MMC_POWER_UP) {
Guennadi Liakhovetskic9b0cef2011-05-26 15:33:30 +0200968 if (!host->card_present) {
Guennadi Liakhovetskifaca6642011-05-05 16:20:48 +0000969 /* See if we also get DMA */
970 sh_mmcif_request_dma(host, host->pd->dev.platform_data);
Guennadi Liakhovetskic9b0cef2011-05-26 15:33:30 +0200971 host->card_present = true;
Guennadi Liakhovetskifaca6642011-05-05 16:20:48 +0000972 }
Guennadi Liakhovetski7d17baa2012-04-20 18:27:13 +0200973 sh_mmcif_set_power(host, ios);
Guennadi Liakhovetskif5e0cec2011-02-25 16:58:38 +0100974 } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
975 /* clock stop */
976 sh_mmcif_clock_control(host, 0);
Guennadi Liakhovetskifaca6642011-05-05 16:20:48 +0000977 if (ios->power_mode == MMC_POWER_OFF) {
Guennadi Liakhovetskic9b0cef2011-05-26 15:33:30 +0200978 if (host->card_present) {
Guennadi Liakhovetskifaca6642011-05-05 16:20:48 +0000979 sh_mmcif_release_dma(host);
Guennadi Liakhovetskic9b0cef2011-05-26 15:33:30 +0200980 host->card_present = false;
Guennadi Liakhovetskifaca6642011-05-05 16:20:48 +0000981 }
Guennadi Liakhovetskic9b0cef2011-05-26 15:33:30 +0200982 }
983 if (host->power) {
984 pm_runtime_put(&host->pd->dev);
Guennadi Liakhovetskib2891742012-04-19 18:02:05 +0200985 clk_disable(host->hclk);
Guennadi Liakhovetskic9b0cef2011-05-26 15:33:30 +0200986 host->power = false;
Guennadi Liakhovetski7d17baa2012-04-20 18:27:13 +0200987 if (ios->power_mode == MMC_POWER_OFF)
988 sh_mmcif_set_power(host, ios);
Guennadi Liakhovetskifaca6642011-05-05 16:20:48 +0000989 }
Guennadi Liakhovetski3b0beaf2011-04-15 18:30:47 +0000990 host->state = STATE_IDLE;
Guennadi Liakhovetskif5e0cec2011-02-25 16:58:38 +0100991 return;
Yusuke Godafdc50a92010-05-26 14:41:59 -0700992 }
993
Guennadi Liakhovetskic9b0cef2011-05-26 15:33:30 +0200994 if (ios->clock) {
995 if (!host->power) {
Guennadi Liakhovetskia6609262012-04-19 18:02:50 +0200996 sh_mmcif_clk_update(host);
Guennadi Liakhovetskic9b0cef2011-05-26 15:33:30 +0200997 pm_runtime_get_sync(&host->pd->dev);
998 host->power = true;
999 sh_mmcif_sync_reset(host);
1000 }
Yusuke Godafdc50a92010-05-26 14:41:59 -07001001 sh_mmcif_clock_control(host, ios->clock);
Guennadi Liakhovetskic9b0cef2011-05-26 15:33:30 +02001002 }
Yusuke Godafdc50a92010-05-26 14:41:59 -07001003
1004 host->bus_width = ios->bus_width;
Guennadi Liakhovetski3b0beaf2011-04-15 18:30:47 +00001005 host->state = STATE_IDLE;
Yusuke Godafdc50a92010-05-26 14:41:59 -07001006}
1007
Arnd Hannemann777271d2010-08-24 17:27:01 +02001008static int sh_mmcif_get_cd(struct mmc_host *mmc)
1009{
1010 struct sh_mmcif_host *host = mmc_priv(mmc);
1011 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
Guennadi Liakhovetskie4806062012-06-14 14:24:35 +02001012 int ret = mmc_gpio_get_cd(mmc);
1013
1014 if (ret >= 0)
1015 return ret;
Arnd Hannemann777271d2010-08-24 17:27:01 +02001016
Guennadi Liakhovetskibf68a812012-05-01 18:18:16 +02001017 if (!p || !p->get_cd)
Arnd Hannemann777271d2010-08-24 17:27:01 +02001018 return -ENOSYS;
1019 else
1020 return p->get_cd(host->pd);
1021}
1022
Yusuke Godafdc50a92010-05-26 14:41:59 -07001023static struct mmc_host_ops sh_mmcif_ops = {
1024 .request = sh_mmcif_request,
1025 .set_ios = sh_mmcif_set_ios,
Arnd Hannemann777271d2010-08-24 17:27:01 +02001026 .get_cd = sh_mmcif_get_cd,
Yusuke Godafdc50a92010-05-26 14:41:59 -07001027};
1028
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001029static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host)
1030{
1031 struct mmc_command *cmd = host->mrq->cmd;
Guennadi Liakhovetski69983402011-12-26 12:52:13 -05001032 struct mmc_data *data = host->mrq->data;
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001033 long time;
1034
1035 if (host->sd_error) {
1036 switch (cmd->opcode) {
1037 case MMC_ALL_SEND_CID:
1038 case MMC_SELECT_CARD:
1039 case MMC_APP_CMD:
1040 cmd->error = -ETIMEDOUT;
1041 host->sd_error = false;
1042 break;
1043 default:
1044 cmd->error = sh_mmcif_error_manage(host);
1045 dev_dbg(&host->pd->dev, "Cmd(d'%d) error %d\n",
1046 cmd->opcode, cmd->error);
1047 break;
1048 }
1049 return false;
1050 }
1051 if (!(cmd->flags & MMC_RSP_PRESENT)) {
1052 cmd->error = 0;
1053 return false;
1054 }
1055
1056 sh_mmcif_get_response(host, cmd);
1057
Guennadi Liakhovetski69983402011-12-26 12:52:13 -05001058 if (!data)
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001059 return false;
1060
Guennadi Liakhovetski69983402011-12-26 12:52:13 -05001061 if (data->flags & MMC_DATA_READ) {
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001062 if (host->chan_rx)
1063 sh_mmcif_start_dma_rx(host);
1064 } else {
1065 if (host->chan_tx)
1066 sh_mmcif_start_dma_tx(host);
1067 }
1068
1069 if (!host->dma_active) {
Guennadi Liakhovetski69983402011-12-26 12:52:13 -05001070 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode);
1071 if (!data->error)
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001072 return true;
1073 return false;
1074 }
1075
1076 /* Running in the IRQ thread, can sleep */
1077 time = wait_for_completion_interruptible_timeout(&host->dma_complete,
1078 host->timeout);
1079 if (host->sd_error) {
1080 dev_err(host->mmc->parent,
1081 "Error IRQ while waiting for DMA completion!\n");
1082 /* Woken up by an error IRQ: abort DMA */
Guennadi Liakhovetski69983402011-12-26 12:52:13 -05001083 if (data->flags & MMC_DATA_READ)
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001084 dmaengine_terminate_all(host->chan_rx);
1085 else
1086 dmaengine_terminate_all(host->chan_tx);
Guennadi Liakhovetski69983402011-12-26 12:52:13 -05001087 data->error = sh_mmcif_error_manage(host);
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001088 } else if (!time) {
Guennadi Liakhovetski69983402011-12-26 12:52:13 -05001089 data->error = -ETIMEDOUT;
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001090 } else if (time < 0) {
Guennadi Liakhovetski69983402011-12-26 12:52:13 -05001091 data->error = time;
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001092 }
1093 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
1094 BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
1095 host->dma_active = false;
1096
Guennadi Liakhovetski69983402011-12-26 12:52:13 -05001097 if (data->error)
1098 data->bytes_xfered = 0;
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001099
1100 return false;
1101}
1102
1103static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id)
1104{
1105 struct sh_mmcif_host *host = dev_id;
1106 struct mmc_request *mrq = host->mrq;
Guennadi Liakhovetski69983402011-12-26 12:52:13 -05001107 struct mmc_data *data = mrq->data;
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001108
1109 cancel_delayed_work_sync(&host->timeout_work);
1110
1111 /*
1112 * All handlers return true, if processing continues, and false, if the
1113 * request has to be completed - successfully or not
1114 */
1115 switch (host->wait_for) {
1116 case MMCIF_WAIT_FOR_REQUEST:
1117 /* We're too late, the timeout has already kicked in */
1118 return IRQ_HANDLED;
1119 case MMCIF_WAIT_FOR_CMD:
1120 if (sh_mmcif_end_cmd(host))
1121 /* Wait for data */
1122 return IRQ_HANDLED;
1123 break;
1124 case MMCIF_WAIT_FOR_MREAD:
1125 if (sh_mmcif_mread_block(host))
1126 /* Wait for more data */
1127 return IRQ_HANDLED;
1128 break;
1129 case MMCIF_WAIT_FOR_READ:
1130 if (sh_mmcif_read_block(host))
1131 /* Wait for data end */
1132 return IRQ_HANDLED;
1133 break;
1134 case MMCIF_WAIT_FOR_MWRITE:
1135 if (sh_mmcif_mwrite_block(host))
1136 /* Wait data to write */
1137 return IRQ_HANDLED;
1138 break;
1139 case MMCIF_WAIT_FOR_WRITE:
1140 if (sh_mmcif_write_block(host))
1141 /* Wait for data end */
1142 return IRQ_HANDLED;
1143 break;
1144 case MMCIF_WAIT_FOR_STOP:
1145 if (host->sd_error) {
1146 mrq->stop->error = sh_mmcif_error_manage(host);
1147 break;
1148 }
1149 sh_mmcif_get_cmd12response(host, mrq->stop);
1150 mrq->stop->error = 0;
1151 break;
1152 case MMCIF_WAIT_FOR_READ_END:
1153 case MMCIF_WAIT_FOR_WRITE_END:
1154 if (host->sd_error)
Guennadi Liakhovetski69983402011-12-26 12:52:13 -05001155 data->error = sh_mmcif_error_manage(host);
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001156 break;
1157 default:
1158 BUG();
1159 }
1160
1161 if (host->wait_for != MMCIF_WAIT_FOR_STOP) {
Guennadi Liakhovetski69983402011-12-26 12:52:13 -05001162 if (!mrq->cmd->error && data && !data->error)
1163 data->bytes_xfered =
1164 data->blocks * data->blksz;
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001165
Guennadi Liakhovetski69983402011-12-26 12:52:13 -05001166 if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) {
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001167 sh_mmcif_stop_cmd(host, mrq);
1168 if (!mrq->stop->error)
1169 return IRQ_HANDLED;
1170 }
1171 }
1172
1173 host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1174 host->state = STATE_IDLE;
Guennadi Liakhovetski69983402011-12-26 12:52:13 -05001175 host->mrq = NULL;
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001176 mmc_request_done(host->mmc, mrq);
1177
1178 return IRQ_HANDLED;
1179}
1180
Yusuke Godafdc50a92010-05-26 14:41:59 -07001181static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
1182{
1183 struct sh_mmcif_host *host = dev_id;
Guennadi Liakhovetskiaa0787a2010-11-24 10:05:12 +00001184 u32 state;
Yusuke Godafdc50a92010-05-26 14:41:59 -07001185 int err = 0;
1186
Magnus Damm487d9fc2010-05-18 14:42:51 +00001187 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
Yusuke Godafdc50a92010-05-26 14:41:59 -07001188
Guennadi Liakhovetski8a8284a2011-12-14 19:31:51 +01001189 if (state & INT_ERR_STS) {
1190 /* error interrupts - process first */
1191 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
1192 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
1193 err = 1;
1194 } else if (state & INT_RBSYE) {
Magnus Damm487d9fc2010-05-18 14:42:51 +00001195 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1196 ~(INT_RBSYE | INT_CRSPE));
Yusuke Godafdc50a92010-05-26 14:41:59 -07001197 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
1198 } else if (state & INT_CRSPE) {
Magnus Damm487d9fc2010-05-18 14:42:51 +00001199 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
Yusuke Godafdc50a92010-05-26 14:41:59 -07001200 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
1201 } else if (state & INT_BUFREN) {
Magnus Damm487d9fc2010-05-18 14:42:51 +00001202 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
Yusuke Godafdc50a92010-05-26 14:41:59 -07001203 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
1204 } else if (state & INT_BUFWEN) {
Magnus Damm487d9fc2010-05-18 14:42:51 +00001205 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
Yusuke Godafdc50a92010-05-26 14:41:59 -07001206 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
1207 } else if (state & INT_CMD12DRE) {
Magnus Damm487d9fc2010-05-18 14:42:51 +00001208 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
Yusuke Godafdc50a92010-05-26 14:41:59 -07001209 ~(INT_CMD12DRE | INT_CMD12RBE |
1210 INT_CMD12CRE | INT_BUFRE));
1211 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
1212 } else if (state & INT_BUFRE) {
Magnus Damm487d9fc2010-05-18 14:42:51 +00001213 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
Yusuke Godafdc50a92010-05-26 14:41:59 -07001214 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
1215 } else if (state & INT_DTRANE) {
Guennadi Liakhovetski7a7eb322012-09-18 23:10:24 +00001216 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1217 ~(INT_CMD12DRE | INT_CMD12RBE |
1218 INT_CMD12CRE | INT_DTRANE));
Yusuke Godafdc50a92010-05-26 14:41:59 -07001219 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
1220 } else if (state & INT_CMD12RBE) {
Magnus Damm487d9fc2010-05-18 14:42:51 +00001221 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
Yusuke Godafdc50a92010-05-26 14:41:59 -07001222 ~(INT_CMD12RBE | INT_CMD12CRE));
1223 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
Yusuke Godafdc50a92010-05-26 14:41:59 -07001224 } else {
Guennadi Liakhovetskifaca6642011-05-05 16:20:48 +00001225 dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state);
Magnus Damm487d9fc2010-05-18 14:42:51 +00001226 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
Yusuke Godafdc50a92010-05-26 14:41:59 -07001227 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
1228 err = 1;
1229 }
1230 if (err) {
Guennadi Liakhovetskiaa0787a2010-11-24 10:05:12 +00001231 host->sd_error = true;
Guennadi Liakhovetskie47bf322010-11-24 10:05:18 +00001232 dev_dbg(&host->pd->dev, "int err state = %08x\n", state);
Yusuke Godafdc50a92010-05-26 14:41:59 -07001233 }
Guennadi Liakhovetski8464dd52012-09-18 06:42:42 +00001234 if (host->state == STATE_IDLE) {
1235 dev_info(&host->pd->dev, "Spurious IRQ status 0x%x", state);
1236 return IRQ_HANDLED;
1237 }
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001238 if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) {
1239 if (!host->dma_active)
1240 return IRQ_WAKE_THREAD;
1241 else if (host->sd_error)
1242 mmcif_dma_complete(host);
1243 } else {
Guennadi Liakhovetskiaa0787a2010-11-24 10:05:12 +00001244 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001245 }
Yusuke Godafdc50a92010-05-26 14:41:59 -07001246
1247 return IRQ_HANDLED;
1248}
1249
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001250static void mmcif_timeout_work(struct work_struct *work)
1251{
1252 struct delayed_work *d = container_of(work, struct delayed_work, work);
1253 struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work);
1254 struct mmc_request *mrq = host->mrq;
1255
1256 if (host->dying)
1257 /* Don't run after mmc_remove_host() */
1258 return;
1259
1260 /*
1261 * Handle races with cancel_delayed_work(), unless
1262 * cancel_delayed_work_sync() is used
1263 */
1264 switch (host->wait_for) {
1265 case MMCIF_WAIT_FOR_CMD:
1266 mrq->cmd->error = sh_mmcif_error_manage(host);
1267 break;
1268 case MMCIF_WAIT_FOR_STOP:
1269 mrq->stop->error = sh_mmcif_error_manage(host);
1270 break;
1271 case MMCIF_WAIT_FOR_MREAD:
1272 case MMCIF_WAIT_FOR_MWRITE:
1273 case MMCIF_WAIT_FOR_READ:
1274 case MMCIF_WAIT_FOR_WRITE:
1275 case MMCIF_WAIT_FOR_READ_END:
1276 case MMCIF_WAIT_FOR_WRITE_END:
Guennadi Liakhovetski69983402011-12-26 12:52:13 -05001277 mrq->data->error = sh_mmcif_error_manage(host);
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001278 break;
1279 default:
1280 BUG();
1281 }
1282
1283 host->state = STATE_IDLE;
1284 host->wait_for = MMCIF_WAIT_FOR_REQUEST;
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001285 host->mrq = NULL;
1286 mmc_request_done(host->mmc, mrq);
1287}
1288
Guennadi Liakhovetski7d17baa2012-04-20 18:27:13 +02001289static void sh_mmcif_init_ocr(struct sh_mmcif_host *host)
1290{
1291 struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data;
1292 struct mmc_host *mmc = host->mmc;
1293
1294 mmc_regulator_get_supply(mmc);
1295
Guennadi Liakhovetskibf68a812012-05-01 18:18:16 +02001296 if (!pd)
1297 return;
1298
Guennadi Liakhovetski7d17baa2012-04-20 18:27:13 +02001299 if (!mmc->ocr_avail)
1300 mmc->ocr_avail = pd->ocr;
1301 else if (pd->ocr)
1302 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1303}
1304
Bill Pembertonc3be1ef2012-11-19 13:23:06 -05001305static int sh_mmcif_probe(struct platform_device *pdev)
Yusuke Godafdc50a92010-05-26 14:41:59 -07001306{
1307 int ret = 0, irq[2];
1308 struct mmc_host *mmc;
Guennadi Liakhovetskie47bf322010-11-24 10:05:18 +00001309 struct sh_mmcif_host *host;
Guennadi Liakhovetskie1aae2e2012-04-19 16:15:52 +02001310 struct sh_mmcif_plat_data *pd = pdev->dev.platform_data;
Yusuke Godafdc50a92010-05-26 14:41:59 -07001311 struct resource *res;
1312 void __iomem *reg;
1313 char clk_name[8];
1314
1315 irq[0] = platform_get_irq(pdev, 0);
1316 irq[1] = platform_get_irq(pdev, 1);
1317 if (irq[0] < 0 || irq[1] < 0) {
Guennadi Liakhovetskie47bf322010-11-24 10:05:18 +00001318 dev_err(&pdev->dev, "Get irq error\n");
Yusuke Godafdc50a92010-05-26 14:41:59 -07001319 return -ENXIO;
1320 }
1321 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1322 if (!res) {
1323 dev_err(&pdev->dev, "platform_get_resource error.\n");
1324 return -ENXIO;
1325 }
1326 reg = ioremap(res->start, resource_size(res));
1327 if (!reg) {
1328 dev_err(&pdev->dev, "ioremap error.\n");
1329 return -ENOMEM;
1330 }
Guennadi Liakhovetskie1aae2e2012-04-19 16:15:52 +02001331
Yusuke Godafdc50a92010-05-26 14:41:59 -07001332 mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev);
1333 if (!mmc) {
1334 ret = -ENOMEM;
Guennadi Liakhovetskie1aae2e2012-04-19 16:15:52 +02001335 goto ealloch;
Yusuke Godafdc50a92010-05-26 14:41:59 -07001336 }
1337 host = mmc_priv(mmc);
1338 host->mmc = mmc;
1339 host->addr = reg;
1340 host->timeout = 1000;
1341
Yusuke Godafdc50a92010-05-26 14:41:59 -07001342 host->pd = pdev;
1343
Guennadi Liakhovetski3b0beaf2011-04-15 18:30:47 +00001344 spin_lock_init(&host->lock);
Yusuke Godafdc50a92010-05-26 14:41:59 -07001345
1346 mmc->ops = &sh_mmcif_ops;
Guennadi Liakhovetski7d17baa2012-04-20 18:27:13 +02001347 sh_mmcif_init_ocr(host);
1348
Yusuke Godafdc50a92010-05-26 14:41:59 -07001349 mmc->caps = MMC_CAP_MMC_HIGHSPEED;
Guennadi Liakhovetskibf68a812012-05-01 18:18:16 +02001350 if (pd && pd->caps)
Yusuke Godafdc50a92010-05-26 14:41:59 -07001351 mmc->caps |= pd->caps;
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +00001352 mmc->max_segs = 32;
Yusuke Godafdc50a92010-05-26 14:41:59 -07001353 mmc->max_blk_size = 512;
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +00001354 mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
1355 mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
Yusuke Godafdc50a92010-05-26 14:41:59 -07001356 mmc->max_seg_size = mmc->max_req_size;
1357
Yusuke Godafdc50a92010-05-26 14:41:59 -07001358 platform_set_drvdata(pdev, host);
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +00001359
Guennadi Liakhovetskifaca6642011-05-05 16:20:48 +00001360 pm_runtime_enable(&pdev->dev);
1361 host->power = false;
1362
Guennadi Liakhovetskib2891742012-04-19 18:02:05 +02001363 snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id);
1364 host->hclk = clk_get(&pdev->dev, clk_name);
1365 if (IS_ERR(host->hclk)) {
1366 ret = PTR_ERR(host->hclk);
1367 dev_err(&pdev->dev, "cannot get clock \"%s\": %d\n", clk_name, ret);
1368 goto eclkget;
1369 }
Guennadi Liakhovetskia6609262012-04-19 18:02:50 +02001370 ret = sh_mmcif_clk_update(host);
1371 if (ret < 0)
1372 goto eclkupdate;
Guennadi Liakhovetskib2891742012-04-19 18:02:05 +02001373
Guennadi Liakhovetskifaca6642011-05-05 16:20:48 +00001374 ret = pm_runtime_resume(&pdev->dev);
1375 if (ret < 0)
Guennadi Liakhovetskie1aae2e2012-04-19 16:15:52 +02001376 goto eresume;
Guennadi Liakhovetskia782d682010-11-24 10:05:22 +00001377
Guennadi Liakhovetski5ba85d92012-01-21 00:41:28 +01001378 INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work);
Yusuke Godafdc50a92010-05-26 14:41:59 -07001379
Guennadi Liakhovetskib2891742012-04-19 18:02:05 +02001380 sh_mmcif_sync_reset(host);
Guennadi Liakhovetski3b0beaf2011-04-15 18:30:47 +00001381 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1382
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001383 ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:error", host);
Yusuke Godafdc50a92010-05-26 14:41:59 -07001384 if (ret) {
Guennadi Liakhovetskie47bf322010-11-24 10:05:18 +00001385 dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n");
Guennadi Liakhovetskie1aae2e2012-04-19 16:15:52 +02001386 goto ereqirq0;
Yusuke Godafdc50a92010-05-26 14:41:59 -07001387 }
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001388 ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:int", host);
Yusuke Godafdc50a92010-05-26 14:41:59 -07001389 if (ret) {
Guennadi Liakhovetskie47bf322010-11-24 10:05:18 +00001390 dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
Guennadi Liakhovetskie1aae2e2012-04-19 16:15:52 +02001391 goto ereqirq1;
Yusuke Godafdc50a92010-05-26 14:41:59 -07001392 }
1393
Guennadi Liakhovetskie4806062012-06-14 14:24:35 +02001394 if (pd && pd->use_cd_gpio) {
1395 ret = mmc_gpio_request_cd(mmc, pd->cd_gpio);
1396 if (ret < 0)
1397 goto erqcd;
1398 }
1399
Guennadi Liakhovetskib2891742012-04-19 18:02:05 +02001400 clk_disable(host->hclk);
Guennadi Liakhovetski5ba85d92012-01-21 00:41:28 +01001401 ret = mmc_add_host(mmc);
1402 if (ret < 0)
Guennadi Liakhovetskie1aae2e2012-04-19 16:15:52 +02001403 goto emmcaddh;
Yusuke Godafdc50a92010-05-26 14:41:59 -07001404
Rafael J. Wysockiefe6a8a2012-03-13 01:02:15 +01001405 dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
1406
Guennadi Liakhovetskie47bf322010-11-24 10:05:18 +00001407 dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
1408 dev_dbg(&pdev->dev, "chip ver H'%04x\n",
Magnus Damm487d9fc2010-05-18 14:42:51 +00001409 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
Yusuke Godafdc50a92010-05-26 14:41:59 -07001410 return ret;
1411
Guennadi Liakhovetskie1aae2e2012-04-19 16:15:52 +02001412emmcaddh:
Guennadi Liakhovetskie4806062012-06-14 14:24:35 +02001413 if (pd && pd->use_cd_gpio)
1414 mmc_gpio_free_cd(mmc);
1415erqcd:
Guennadi Liakhovetski5ba85d92012-01-21 00:41:28 +01001416 free_irq(irq[1], host);
Guennadi Liakhovetskie1aae2e2012-04-19 16:15:52 +02001417ereqirq1:
Guennadi Liakhovetski5ba85d92012-01-21 00:41:28 +01001418 free_irq(irq[0], host);
Guennadi Liakhovetskie1aae2e2012-04-19 16:15:52 +02001419ereqirq0:
Guennadi Liakhovetskifaca6642011-05-05 16:20:48 +00001420 pm_runtime_suspend(&pdev->dev);
Guennadi Liakhovetskie1aae2e2012-04-19 16:15:52 +02001421eresume:
Yusuke Godafdc50a92010-05-26 14:41:59 -07001422 clk_disable(host->hclk);
Guennadi Liakhovetskia6609262012-04-19 18:02:50 +02001423eclkupdate:
Guennadi Liakhovetskib2891742012-04-19 18:02:05 +02001424 clk_put(host->hclk);
Guennadi Liakhovetskie1aae2e2012-04-19 16:15:52 +02001425eclkget:
Guennadi Liakhovetskib2891742012-04-19 18:02:05 +02001426 pm_runtime_disable(&pdev->dev);
Yusuke Godafdc50a92010-05-26 14:41:59 -07001427 mmc_free_host(mmc);
Guennadi Liakhovetskie1aae2e2012-04-19 16:15:52 +02001428ealloch:
1429 iounmap(reg);
Yusuke Godafdc50a92010-05-26 14:41:59 -07001430 return ret;
1431}
1432
1433static int __devexit sh_mmcif_remove(struct platform_device *pdev)
1434{
1435 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
Guennadi Liakhovetskie4806062012-06-14 14:24:35 +02001436 struct sh_mmcif_plat_data *pd = pdev->dev.platform_data;
Yusuke Godafdc50a92010-05-26 14:41:59 -07001437 int irq[2];
1438
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001439 host->dying = true;
Guennadi Liakhovetskib2891742012-04-19 18:02:05 +02001440 clk_enable(host->hclk);
Guennadi Liakhovetskifaca6642011-05-05 16:20:48 +00001441 pm_runtime_get_sync(&pdev->dev);
Guennadi Liakhovetskiaa0787a2010-11-24 10:05:12 +00001442
Rafael J. Wysockiefe6a8a2012-03-13 01:02:15 +01001443 dev_pm_qos_hide_latency_limit(&pdev->dev);
1444
Guennadi Liakhovetskie4806062012-06-14 14:24:35 +02001445 if (pd && pd->use_cd_gpio)
1446 mmc_gpio_free_cd(host->mmc);
1447
Guennadi Liakhovetskifaca6642011-05-05 16:20:48 +00001448 mmc_remove_host(host->mmc);
Guennadi Liakhovetski3b0beaf2011-04-15 18:30:47 +00001449 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1450
Guennadi Liakhovetskif985da12011-12-25 21:07:52 +01001451 /*
1452 * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the
1453 * mmc_remove_host() call above. But swapping order doesn't help either
1454 * (a query on the linux-mmc mailing list didn't bring any replies).
1455 */
1456 cancel_delayed_work_sync(&host->timeout_work);
1457
Guennadi Liakhovetskiaa0787a2010-11-24 10:05:12 +00001458 if (host->addr)
1459 iounmap(host->addr);
1460
Yusuke Godafdc50a92010-05-26 14:41:59 -07001461 irq[0] = platform_get_irq(pdev, 0);
1462 irq[1] = platform_get_irq(pdev, 1);
1463
Yusuke Godafdc50a92010-05-26 14:41:59 -07001464 free_irq(irq[0], host);
1465 free_irq(irq[1], host);
1466
Guennadi Liakhovetskiaa0787a2010-11-24 10:05:12 +00001467 platform_set_drvdata(pdev, NULL);
1468
Guennadi Liakhovetskia0d28ba2012-10-23 14:08:52 +02001469 clk_disable(host->hclk);
Yusuke Godafdc50a92010-05-26 14:41:59 -07001470 mmc_free_host(host->mmc);
Guennadi Liakhovetskifaca6642011-05-05 16:20:48 +00001471 pm_runtime_put_sync(&pdev->dev);
1472 pm_runtime_disable(&pdev->dev);
Yusuke Godafdc50a92010-05-26 14:41:59 -07001473
1474 return 0;
1475}
1476
Guennadi Liakhovetskifaca6642011-05-05 16:20:48 +00001477#ifdef CONFIG_PM
1478static int sh_mmcif_suspend(struct device *dev)
1479{
Guennadi Liakhovetskib2891742012-04-19 18:02:05 +02001480 struct sh_mmcif_host *host = dev_get_drvdata(dev);
Guennadi Liakhovetskifaca6642011-05-05 16:20:48 +00001481 int ret = mmc_suspend_host(host->mmc);
1482
Guennadi Liakhovetskib2891742012-04-19 18:02:05 +02001483 if (!ret)
Guennadi Liakhovetskifaca6642011-05-05 16:20:48 +00001484 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
Guennadi Liakhovetskifaca6642011-05-05 16:20:48 +00001485
1486 return ret;
1487}
1488
1489static int sh_mmcif_resume(struct device *dev)
1490{
Guennadi Liakhovetskib2891742012-04-19 18:02:05 +02001491 struct sh_mmcif_host *host = dev_get_drvdata(dev);
Guennadi Liakhovetskifaca6642011-05-05 16:20:48 +00001492
1493 return mmc_resume_host(host->mmc);
1494}
1495#else
1496#define sh_mmcif_suspend NULL
1497#define sh_mmcif_resume NULL
1498#endif /* CONFIG_PM */
1499
Guennadi Liakhovetskibf68a812012-05-01 18:18:16 +02001500static const struct of_device_id mmcif_of_match[] = {
1501 { .compatible = "renesas,sh-mmcif" },
1502 { }
1503};
1504MODULE_DEVICE_TABLE(of, mmcif_of_match);
1505
Guennadi Liakhovetskifaca6642011-05-05 16:20:48 +00001506static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {
1507 .suspend = sh_mmcif_suspend,
1508 .resume = sh_mmcif_resume,
1509};
1510
Yusuke Godafdc50a92010-05-26 14:41:59 -07001511static struct platform_driver sh_mmcif_driver = {
1512 .probe = sh_mmcif_probe,
1513 .remove = sh_mmcif_remove,
1514 .driver = {
1515 .name = DRIVER_NAME,
Guennadi Liakhovetskifaca6642011-05-05 16:20:48 +00001516 .pm = &sh_mmcif_dev_pm_ops,
Guennadi Liakhovetskibf68a812012-05-01 18:18:16 +02001517 .owner = THIS_MODULE,
1518 .of_match_table = mmcif_of_match,
Yusuke Godafdc50a92010-05-26 14:41:59 -07001519 },
1520};
1521
Axel Lind1f81a62011-11-26 12:55:43 +08001522module_platform_driver(sh_mmcif_driver);
Yusuke Godafdc50a92010-05-26 14:41:59 -07001523
1524MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1525MODULE_LICENSE("GPL");
Guennadi Liakhovetskiaa0787a2010-11-24 10:05:12 +00001526MODULE_ALIAS("platform:" DRIVER_NAME);
Yusuke Godafdc50a92010-05-26 14:41:59 -07001527MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");