Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * linux/drivers/video/omap2/dss/dispc.c |
| 3 | * |
| 4 | * Copyright (C) 2009 Nokia Corporation |
| 5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> |
| 6 | * |
| 7 | * Some code and ideas taken from drivers/video/omap/ driver |
| 8 | * by Imre Deak. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify it |
| 11 | * under the terms of the GNU General Public License version 2 as published by |
| 12 | * the Free Software Foundation. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 17 | * more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License along with |
| 20 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 21 | */ |
| 22 | |
| 23 | #define DSS_SUBSYS_NAME "DISPC" |
| 24 | |
| 25 | #include <linux/kernel.h> |
| 26 | #include <linux/dma-mapping.h> |
| 27 | #include <linux/vmalloc.h> |
| 28 | #include <linux/clk.h> |
| 29 | #include <linux/io.h> |
| 30 | #include <linux/jiffies.h> |
| 31 | #include <linux/seq_file.h> |
| 32 | #include <linux/delay.h> |
| 33 | #include <linux/workqueue.h> |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 34 | #include <linux/hardirq.h> |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 35 | #include <linux/interrupt.h> |
Tomi Valkeinen | 24e6289 | 2011-05-23 11:51:18 +0300 | [diff] [blame] | 36 | #include <linux/platform_device.h> |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 37 | #include <linux/pm_runtime.h> |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 38 | |
| 39 | #include <plat/sram.h> |
| 40 | #include <plat/clock.h> |
| 41 | |
Tomi Valkeinen | a0b38cc | 2011-05-11 14:05:07 +0300 | [diff] [blame] | 42 | #include <video/omapdss.h> |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 43 | |
| 44 | #include "dss.h" |
Archit Taneja | a0acb55 | 2010-09-15 19:20:00 +0530 | [diff] [blame] | 45 | #include "dss_features.h" |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 46 | #include "dispc.h" |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 47 | |
| 48 | /* DISPC */ |
Sumit Semwal | 8613b00 | 2010-12-02 11:27:09 +0000 | [diff] [blame] | 49 | #define DISPC_SZ_REGS SZ_4K |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 50 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 51 | #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \ |
| 52 | DISPC_IRQ_OCP_ERR | \ |
| 53 | DISPC_IRQ_VID1_FIFO_UNDERFLOW | \ |
| 54 | DISPC_IRQ_VID2_FIFO_UNDERFLOW | \ |
| 55 | DISPC_IRQ_SYNC_LOST | \ |
| 56 | DISPC_IRQ_SYNC_LOST_DIGIT) |
| 57 | |
| 58 | #define DISPC_MAX_NR_ISRS 8 |
| 59 | |
| 60 | struct omap_dispc_isr_data { |
| 61 | omap_dispc_isr_t isr; |
| 62 | void *arg; |
| 63 | u32 mask; |
| 64 | }; |
| 65 | |
Grazvydas Ignotas | 66be8f6 | 2010-08-24 15:18:43 +0200 | [diff] [blame] | 66 | struct dispc_h_coef { |
| 67 | s8 hc4; |
| 68 | s8 hc3; |
| 69 | u8 hc2; |
| 70 | s8 hc1; |
| 71 | s8 hc0; |
| 72 | }; |
| 73 | |
| 74 | struct dispc_v_coef { |
| 75 | s8 vc22; |
| 76 | s8 vc2; |
| 77 | u8 vc1; |
| 78 | s8 vc0; |
| 79 | s8 vc00; |
| 80 | }; |
| 81 | |
Tomi Valkeinen | 5ed8cf5 | 2011-06-21 09:35:36 +0300 | [diff] [blame] | 82 | enum omap_burst_size { |
| 83 | BURST_SIZE_X2 = 0, |
| 84 | BURST_SIZE_X4 = 1, |
| 85 | BURST_SIZE_X8 = 2, |
| 86 | }; |
| 87 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 88 | #define REG_GET(idx, start, end) \ |
| 89 | FLD_GET(dispc_read_reg(idx), start, end) |
| 90 | |
| 91 | #define REG_FLD_MOD(idx, val, start, end) \ |
| 92 | dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end)) |
| 93 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 94 | struct dispc_irq_stats { |
| 95 | unsigned long last_reset; |
| 96 | unsigned irq_count; |
| 97 | unsigned irqs[32]; |
| 98 | }; |
| 99 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 100 | static struct { |
Senthilvadivu Guruswamy | 060b6d9 | 2011-01-24 06:22:00 +0000 | [diff] [blame] | 101 | struct platform_device *pdev; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 102 | void __iomem *base; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 103 | |
| 104 | int ctx_loss_cnt; |
| 105 | |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 106 | int irq; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 107 | struct clk *dss_clk; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 108 | |
Archit Taneja | e13a138 | 2011-08-05 19:06:04 +0530 | [diff] [blame] | 109 | u32 fifo_size[MAX_DSS_OVERLAYS]; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 110 | |
| 111 | spinlock_t irq_lock; |
| 112 | u32 irq_error_mask; |
| 113 | struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS]; |
| 114 | u32 error_irqs; |
| 115 | struct work_struct error_work; |
| 116 | |
Tomi Valkeinen | 49ea86f | 2011-06-01 15:54:06 +0300 | [diff] [blame] | 117 | bool ctx_valid; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 118 | u32 ctx[DISPC_SZ_REGS / sizeof(u32)]; |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 119 | |
| 120 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 121 | spinlock_t irq_stats_lock; |
| 122 | struct dispc_irq_stats irq_stats; |
| 123 | #endif |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 124 | } dispc; |
| 125 | |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 126 | enum omap_color_component { |
| 127 | /* used for all color formats for OMAP3 and earlier |
| 128 | * and for RGB and Y color component on OMAP4 |
| 129 | */ |
| 130 | DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0, |
| 131 | /* used for UV component for |
| 132 | * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12 |
| 133 | * color formats on OMAP4 |
| 134 | */ |
| 135 | DISPC_COLOR_COMPONENT_UV = 1 << 1, |
| 136 | }; |
| 137 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 138 | static void _omap_dispc_set_irqs(void); |
| 139 | |
Archit Taneja | 55978cc | 2011-05-06 11:45:51 +0530 | [diff] [blame] | 140 | static inline void dispc_write_reg(const u16 idx, u32 val) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 141 | { |
Archit Taneja | 55978cc | 2011-05-06 11:45:51 +0530 | [diff] [blame] | 142 | __raw_writel(val, dispc.base + idx); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 143 | } |
| 144 | |
Archit Taneja | 55978cc | 2011-05-06 11:45:51 +0530 | [diff] [blame] | 145 | static inline u32 dispc_read_reg(const u16 idx) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 146 | { |
Archit Taneja | 55978cc | 2011-05-06 11:45:51 +0530 | [diff] [blame] | 147 | return __raw_readl(dispc.base + idx); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 148 | } |
| 149 | |
Tomi Valkeinen | 49ea86f | 2011-06-01 15:54:06 +0300 | [diff] [blame] | 150 | static int dispc_get_ctx_loss_count(void) |
| 151 | { |
| 152 | struct device *dev = &dispc.pdev->dev; |
| 153 | struct omap_display_platform_data *pdata = dev->platform_data; |
| 154 | struct omap_dss_board_info *board_data = pdata->board_data; |
| 155 | int cnt; |
| 156 | |
| 157 | if (!board_data->get_context_loss_count) |
| 158 | return -ENOENT; |
| 159 | |
| 160 | cnt = board_data->get_context_loss_count(dev); |
| 161 | |
| 162 | WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt); |
| 163 | |
| 164 | return cnt; |
| 165 | } |
| 166 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 167 | #define SR(reg) \ |
Archit Taneja | 55978cc | 2011-05-06 11:45:51 +0530 | [diff] [blame] | 168 | dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 169 | #define RR(reg) \ |
Archit Taneja | 55978cc | 2011-05-06 11:45:51 +0530 | [diff] [blame] | 170 | dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)]) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 171 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 172 | static void dispc_save_context(void) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 173 | { |
Archit Taneja | c6104b8 | 2011-08-05 19:06:02 +0530 | [diff] [blame] | 174 | int i, j; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 175 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 176 | DSSDBG("dispc_save_context\n"); |
| 177 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 178 | SR(IRQENABLE); |
| 179 | SR(CONTROL); |
| 180 | SR(CONFIG); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 181 | SR(LINE_NUMBER); |
Tomi Valkeinen | 332e9d7 | 2011-05-27 14:22:16 +0300 | [diff] [blame] | 182 | if (dss_has_feature(FEAT_GLOBAL_ALPHA)) |
| 183 | SR(GLOBAL_ALPHA); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 184 | if (dss_has_feature(FEAT_MGR_LCD2)) { |
| 185 | SR(CONTROL2); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 186 | SR(CONFIG2); |
| 187 | } |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 188 | |
Archit Taneja | c6104b8 | 2011-08-05 19:06:02 +0530 | [diff] [blame] | 189 | for (i = 0; i < dss_feat_get_num_mgrs(); i++) { |
| 190 | SR(DEFAULT_COLOR(i)); |
| 191 | SR(TRANS_COLOR(i)); |
| 192 | SR(SIZE_MGR(i)); |
| 193 | if (i == OMAP_DSS_CHANNEL_DIGIT) |
| 194 | continue; |
| 195 | SR(TIMING_H(i)); |
| 196 | SR(TIMING_V(i)); |
| 197 | SR(POL_FREQ(i)); |
| 198 | SR(DIVISORo(i)); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 199 | |
Archit Taneja | c6104b8 | 2011-08-05 19:06:02 +0530 | [diff] [blame] | 200 | SR(DATA_CYCLE1(i)); |
| 201 | SR(DATA_CYCLE2(i)); |
| 202 | SR(DATA_CYCLE3(i)); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 203 | |
Tomi Valkeinen | 332e9d7 | 2011-05-27 14:22:16 +0300 | [diff] [blame] | 204 | if (dss_has_feature(FEAT_CPR)) { |
Archit Taneja | c6104b8 | 2011-08-05 19:06:02 +0530 | [diff] [blame] | 205 | SR(CPR_COEF_R(i)); |
| 206 | SR(CPR_COEF_G(i)); |
| 207 | SR(CPR_COEF_B(i)); |
| 208 | } |
| 209 | } |
| 210 | |
| 211 | for (i = 0; i < dss_feat_get_num_ovls(); i++) { |
| 212 | SR(OVL_BA0(i)); |
| 213 | SR(OVL_BA1(i)); |
| 214 | SR(OVL_POSITION(i)); |
| 215 | SR(OVL_SIZE(i)); |
| 216 | SR(OVL_ATTRIBUTES(i)); |
| 217 | SR(OVL_FIFO_THRESHOLD(i)); |
| 218 | SR(OVL_ROW_INC(i)); |
| 219 | SR(OVL_PIXEL_INC(i)); |
| 220 | if (dss_has_feature(FEAT_PRELOAD)) |
| 221 | SR(OVL_PRELOAD(i)); |
| 222 | if (i == OMAP_DSS_GFX) { |
| 223 | SR(OVL_WINDOW_SKIP(i)); |
| 224 | SR(OVL_TABLE_BA(i)); |
| 225 | continue; |
| 226 | } |
| 227 | SR(OVL_FIR(i)); |
| 228 | SR(OVL_PICTURE_SIZE(i)); |
| 229 | SR(OVL_ACCU0(i)); |
| 230 | SR(OVL_ACCU1(i)); |
| 231 | |
| 232 | for (j = 0; j < 8; j++) |
| 233 | SR(OVL_FIR_COEF_H(i, j)); |
| 234 | |
| 235 | for (j = 0; j < 8; j++) |
| 236 | SR(OVL_FIR_COEF_HV(i, j)); |
| 237 | |
| 238 | for (j = 0; j < 5; j++) |
| 239 | SR(OVL_CONV_COEF(i, j)); |
| 240 | |
| 241 | if (dss_has_feature(FEAT_FIR_COEF_V)) { |
| 242 | for (j = 0; j < 8; j++) |
| 243 | SR(OVL_FIR_COEF_V(i, j)); |
Tomi Valkeinen | 332e9d7 | 2011-05-27 14:22:16 +0300 | [diff] [blame] | 244 | } |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 245 | |
Archit Taneja | c6104b8 | 2011-08-05 19:06:02 +0530 | [diff] [blame] | 246 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { |
| 247 | SR(OVL_BA0_UV(i)); |
| 248 | SR(OVL_BA1_UV(i)); |
| 249 | SR(OVL_FIR2(i)); |
| 250 | SR(OVL_ACCU2_0(i)); |
| 251 | SR(OVL_ACCU2_1(i)); |
| 252 | |
| 253 | for (j = 0; j < 8; j++) |
| 254 | SR(OVL_FIR_COEF_H2(i, j)); |
| 255 | |
| 256 | for (j = 0; j < 8; j++) |
| 257 | SR(OVL_FIR_COEF_HV2(i, j)); |
| 258 | |
| 259 | for (j = 0; j < 8; j++) |
| 260 | SR(OVL_FIR_COEF_V2(i, j)); |
| 261 | } |
| 262 | if (dss_has_feature(FEAT_ATTR2)) |
| 263 | SR(OVL_ATTRIBUTES2(i)); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 264 | } |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 265 | |
Murthy, Raghuveer | 0cf35df | 2011-03-03 09:28:00 -0600 | [diff] [blame] | 266 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) |
| 267 | SR(DIVISOR); |
Tomi Valkeinen | 49ea86f | 2011-06-01 15:54:06 +0300 | [diff] [blame] | 268 | |
| 269 | dispc.ctx_loss_cnt = dispc_get_ctx_loss_count(); |
| 270 | dispc.ctx_valid = true; |
| 271 | |
| 272 | DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 273 | } |
| 274 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 275 | static void dispc_restore_context(void) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 276 | { |
Archit Taneja | c6104b8 | 2011-08-05 19:06:02 +0530 | [diff] [blame] | 277 | int i, j, ctx; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 278 | |
| 279 | DSSDBG("dispc_restore_context\n"); |
| 280 | |
Tomi Valkeinen | 49ea86f | 2011-06-01 15:54:06 +0300 | [diff] [blame] | 281 | if (!dispc.ctx_valid) |
| 282 | return; |
| 283 | |
| 284 | ctx = dispc_get_ctx_loss_count(); |
| 285 | |
| 286 | if (ctx >= 0 && ctx == dispc.ctx_loss_cnt) |
| 287 | return; |
| 288 | |
| 289 | DSSDBG("ctx_loss_count: saved %d, current %d\n", |
| 290 | dispc.ctx_loss_cnt, ctx); |
| 291 | |
Ville Syrjälä | 75c7d59 | 2010-03-05 01:13:11 +0200 | [diff] [blame] | 292 | /*RR(IRQENABLE);*/ |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 293 | /*RR(CONTROL);*/ |
| 294 | RR(CONFIG); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 295 | RR(LINE_NUMBER); |
Tomi Valkeinen | 332e9d7 | 2011-05-27 14:22:16 +0300 | [diff] [blame] | 296 | if (dss_has_feature(FEAT_GLOBAL_ALPHA)) |
| 297 | RR(GLOBAL_ALPHA); |
Archit Taneja | c6104b8 | 2011-08-05 19:06:02 +0530 | [diff] [blame] | 298 | if (dss_has_feature(FEAT_MGR_LCD2)) |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 299 | RR(CONFIG2); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 300 | |
Archit Taneja | c6104b8 | 2011-08-05 19:06:02 +0530 | [diff] [blame] | 301 | for (i = 0; i < dss_feat_get_num_mgrs(); i++) { |
| 302 | RR(DEFAULT_COLOR(i)); |
| 303 | RR(TRANS_COLOR(i)); |
| 304 | RR(SIZE_MGR(i)); |
| 305 | if (i == OMAP_DSS_CHANNEL_DIGIT) |
| 306 | continue; |
| 307 | RR(TIMING_H(i)); |
| 308 | RR(TIMING_V(i)); |
| 309 | RR(POL_FREQ(i)); |
| 310 | RR(DIVISORo(i)); |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 311 | |
Archit Taneja | c6104b8 | 2011-08-05 19:06:02 +0530 | [diff] [blame] | 312 | RR(DATA_CYCLE1(i)); |
| 313 | RR(DATA_CYCLE2(i)); |
| 314 | RR(DATA_CYCLE3(i)); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 315 | |
Tomi Valkeinen | 332e9d7 | 2011-05-27 14:22:16 +0300 | [diff] [blame] | 316 | if (dss_has_feature(FEAT_CPR)) { |
Archit Taneja | c6104b8 | 2011-08-05 19:06:02 +0530 | [diff] [blame] | 317 | RR(CPR_COEF_R(i)); |
| 318 | RR(CPR_COEF_G(i)); |
| 319 | RR(CPR_COEF_B(i)); |
Tomi Valkeinen | 332e9d7 | 2011-05-27 14:22:16 +0300 | [diff] [blame] | 320 | } |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 321 | } |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 322 | |
Archit Taneja | c6104b8 | 2011-08-05 19:06:02 +0530 | [diff] [blame] | 323 | for (i = 0; i < dss_feat_get_num_ovls(); i++) { |
| 324 | RR(OVL_BA0(i)); |
| 325 | RR(OVL_BA1(i)); |
| 326 | RR(OVL_POSITION(i)); |
| 327 | RR(OVL_SIZE(i)); |
| 328 | RR(OVL_ATTRIBUTES(i)); |
| 329 | RR(OVL_FIFO_THRESHOLD(i)); |
| 330 | RR(OVL_ROW_INC(i)); |
| 331 | RR(OVL_PIXEL_INC(i)); |
| 332 | if (dss_has_feature(FEAT_PRELOAD)) |
| 333 | RR(OVL_PRELOAD(i)); |
| 334 | if (i == OMAP_DSS_GFX) { |
| 335 | RR(OVL_WINDOW_SKIP(i)); |
| 336 | RR(OVL_TABLE_BA(i)); |
| 337 | continue; |
| 338 | } |
| 339 | RR(OVL_FIR(i)); |
| 340 | RR(OVL_PICTURE_SIZE(i)); |
| 341 | RR(OVL_ACCU0(i)); |
| 342 | RR(OVL_ACCU1(i)); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 343 | |
Archit Taneja | c6104b8 | 2011-08-05 19:06:02 +0530 | [diff] [blame] | 344 | for (j = 0; j < 8; j++) |
| 345 | RR(OVL_FIR_COEF_H(i, j)); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 346 | |
Archit Taneja | c6104b8 | 2011-08-05 19:06:02 +0530 | [diff] [blame] | 347 | for (j = 0; j < 8; j++) |
| 348 | RR(OVL_FIR_COEF_HV(i, j)); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 349 | |
Archit Taneja | c6104b8 | 2011-08-05 19:06:02 +0530 | [diff] [blame] | 350 | for (j = 0; j < 5; j++) |
| 351 | RR(OVL_CONV_COEF(i, j)); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 352 | |
Archit Taneja | c6104b8 | 2011-08-05 19:06:02 +0530 | [diff] [blame] | 353 | if (dss_has_feature(FEAT_FIR_COEF_V)) { |
| 354 | for (j = 0; j < 8; j++) |
| 355 | RR(OVL_FIR_COEF_V(i, j)); |
| 356 | } |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 357 | |
Archit Taneja | c6104b8 | 2011-08-05 19:06:02 +0530 | [diff] [blame] | 358 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { |
| 359 | RR(OVL_BA0_UV(i)); |
| 360 | RR(OVL_BA1_UV(i)); |
| 361 | RR(OVL_FIR2(i)); |
| 362 | RR(OVL_ACCU2_0(i)); |
| 363 | RR(OVL_ACCU2_1(i)); |
| 364 | |
| 365 | for (j = 0; j < 8; j++) |
| 366 | RR(OVL_FIR_COEF_H2(i, j)); |
| 367 | |
| 368 | for (j = 0; j < 8; j++) |
| 369 | RR(OVL_FIR_COEF_HV2(i, j)); |
| 370 | |
| 371 | for (j = 0; j < 8; j++) |
| 372 | RR(OVL_FIR_COEF_V2(i, j)); |
| 373 | } |
| 374 | if (dss_has_feature(FEAT_ATTR2)) |
| 375 | RR(OVL_ATTRIBUTES2(i)); |
Tomi Valkeinen | 332e9d7 | 2011-05-27 14:22:16 +0300 | [diff] [blame] | 376 | } |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 377 | |
Murthy, Raghuveer | 0cf35df | 2011-03-03 09:28:00 -0600 | [diff] [blame] | 378 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) |
| 379 | RR(DIVISOR); |
| 380 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 381 | /* enable last, because LCD & DIGIT enable are here */ |
| 382 | RR(CONTROL); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 383 | if (dss_has_feature(FEAT_MGR_LCD2)) |
| 384 | RR(CONTROL2); |
Ville Syrjälä | 75c7d59 | 2010-03-05 01:13:11 +0200 | [diff] [blame] | 385 | /* clear spurious SYNC_LOST_DIGIT interrupts */ |
| 386 | dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT); |
| 387 | |
| 388 | /* |
| 389 | * enable last so IRQs won't trigger before |
| 390 | * the context is fully restored |
| 391 | */ |
| 392 | RR(IRQENABLE); |
Tomi Valkeinen | 49ea86f | 2011-06-01 15:54:06 +0300 | [diff] [blame] | 393 | |
| 394 | DSSDBG("context restored\n"); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 395 | } |
| 396 | |
| 397 | #undef SR |
| 398 | #undef RR |
| 399 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 400 | int dispc_runtime_get(void) |
| 401 | { |
| 402 | int r; |
| 403 | |
| 404 | DSSDBG("dispc_runtime_get\n"); |
| 405 | |
| 406 | r = pm_runtime_get_sync(&dispc.pdev->dev); |
| 407 | WARN_ON(r < 0); |
| 408 | return r < 0 ? r : 0; |
| 409 | } |
| 410 | |
| 411 | void dispc_runtime_put(void) |
| 412 | { |
| 413 | int r; |
| 414 | |
| 415 | DSSDBG("dispc_runtime_put\n"); |
| 416 | |
| 417 | r = pm_runtime_put(&dispc.pdev->dev); |
| 418 | WARN_ON(r < 0); |
| 419 | } |
| 420 | |
| 421 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 422 | bool dispc_mgr_go_busy(enum omap_channel channel) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 423 | { |
| 424 | int bit; |
| 425 | |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 426 | if (channel == OMAP_DSS_CHANNEL_LCD || |
| 427 | channel == OMAP_DSS_CHANNEL_LCD2) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 428 | bit = 5; /* GOLCD */ |
| 429 | else |
| 430 | bit = 6; /* GODIGIT */ |
| 431 | |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 432 | if (channel == OMAP_DSS_CHANNEL_LCD2) |
| 433 | return REG_GET(DISPC_CONTROL2, bit, bit) == 1; |
| 434 | else |
| 435 | return REG_GET(DISPC_CONTROL, bit, bit) == 1; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 436 | } |
| 437 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 438 | void dispc_mgr_go(enum omap_channel channel) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 439 | { |
| 440 | int bit; |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 441 | bool enable_bit, go_bit; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 442 | |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 443 | if (channel == OMAP_DSS_CHANNEL_LCD || |
| 444 | channel == OMAP_DSS_CHANNEL_LCD2) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 445 | bit = 0; /* LCDENABLE */ |
| 446 | else |
| 447 | bit = 1; /* DIGITALENABLE */ |
| 448 | |
| 449 | /* if the channel is not enabled, we don't need GO */ |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 450 | if (channel == OMAP_DSS_CHANNEL_LCD2) |
| 451 | enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1; |
| 452 | else |
| 453 | enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1; |
| 454 | |
| 455 | if (!enable_bit) |
Tomi Valkeinen | e6d80f9 | 2011-05-19 14:12:26 +0300 | [diff] [blame] | 456 | return; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 457 | |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 458 | if (channel == OMAP_DSS_CHANNEL_LCD || |
| 459 | channel == OMAP_DSS_CHANNEL_LCD2) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 460 | bit = 5; /* GOLCD */ |
| 461 | else |
| 462 | bit = 6; /* GODIGIT */ |
| 463 | |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 464 | if (channel == OMAP_DSS_CHANNEL_LCD2) |
| 465 | go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1; |
| 466 | else |
| 467 | go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1; |
| 468 | |
| 469 | if (go_bit) { |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 470 | DSSERR("GO bit not down for channel %d\n", channel); |
Tomi Valkeinen | e6d80f9 | 2011-05-19 14:12:26 +0300 | [diff] [blame] | 471 | return; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 472 | } |
| 473 | |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 474 | DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : |
| 475 | (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT")); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 476 | |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 477 | if (channel == OMAP_DSS_CHANNEL_LCD2) |
| 478 | REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit); |
| 479 | else |
| 480 | REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 481 | } |
| 482 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 483 | static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 484 | { |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 485 | dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 486 | } |
| 487 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 488 | static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 489 | { |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 490 | dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 491 | } |
| 492 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 493 | static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 494 | { |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 495 | dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 496 | } |
| 497 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 498 | static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value) |
Amber Jain | ab5ca07 | 2011-05-19 19:47:53 +0530 | [diff] [blame] | 499 | { |
| 500 | BUG_ON(plane == OMAP_DSS_GFX); |
| 501 | |
| 502 | dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value); |
| 503 | } |
| 504 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 505 | static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg, |
| 506 | u32 value) |
Amber Jain | ab5ca07 | 2011-05-19 19:47:53 +0530 | [diff] [blame] | 507 | { |
| 508 | BUG_ON(plane == OMAP_DSS_GFX); |
| 509 | |
| 510 | dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value); |
| 511 | } |
| 512 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 513 | static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value) |
Amber Jain | ab5ca07 | 2011-05-19 19:47:53 +0530 | [diff] [blame] | 514 | { |
| 515 | BUG_ON(plane == OMAP_DSS_GFX); |
| 516 | |
| 517 | dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value); |
| 518 | } |
| 519 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 520 | static void dispc_ovl_set_scale_coef(enum omap_plane plane, int hscaleup, |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 521 | int vscaleup, int five_taps, |
| 522 | enum omap_color_component color_comp) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 523 | { |
| 524 | /* Coefficients for horizontal up-sampling */ |
Grazvydas Ignotas | 66be8f6 | 2010-08-24 15:18:43 +0200 | [diff] [blame] | 525 | static const struct dispc_h_coef coef_hup[8] = { |
| 526 | { 0, 0, 128, 0, 0 }, |
| 527 | { -1, 13, 124, -8, 0 }, |
| 528 | { -2, 30, 112, -11, -1 }, |
| 529 | { -5, 51, 95, -11, -2 }, |
| 530 | { 0, -9, 73, 73, -9 }, |
| 531 | { -2, -11, 95, 51, -5 }, |
| 532 | { -1, -11, 112, 30, -2 }, |
| 533 | { 0, -8, 124, 13, -1 }, |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 534 | }; |
| 535 | |
| 536 | /* Coefficients for vertical up-sampling */ |
Grazvydas Ignotas | 66be8f6 | 2010-08-24 15:18:43 +0200 | [diff] [blame] | 537 | static const struct dispc_v_coef coef_vup_3tap[8] = { |
| 538 | { 0, 0, 128, 0, 0 }, |
| 539 | { 0, 3, 123, 2, 0 }, |
| 540 | { 0, 12, 111, 5, 0 }, |
| 541 | { 0, 32, 89, 7, 0 }, |
| 542 | { 0, 0, 64, 64, 0 }, |
| 543 | { 0, 7, 89, 32, 0 }, |
| 544 | { 0, 5, 111, 12, 0 }, |
| 545 | { 0, 2, 123, 3, 0 }, |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 546 | }; |
| 547 | |
Grazvydas Ignotas | 66be8f6 | 2010-08-24 15:18:43 +0200 | [diff] [blame] | 548 | static const struct dispc_v_coef coef_vup_5tap[8] = { |
| 549 | { 0, 0, 128, 0, 0 }, |
| 550 | { -1, 13, 124, -8, 0 }, |
| 551 | { -2, 30, 112, -11, -1 }, |
| 552 | { -5, 51, 95, -11, -2 }, |
| 553 | { 0, -9, 73, 73, -9 }, |
| 554 | { -2, -11, 95, 51, -5 }, |
| 555 | { -1, -11, 112, 30, -2 }, |
| 556 | { 0, -8, 124, 13, -1 }, |
| 557 | }; |
| 558 | |
| 559 | /* Coefficients for horizontal down-sampling */ |
| 560 | static const struct dispc_h_coef coef_hdown[8] = { |
| 561 | { 0, 36, 56, 36, 0 }, |
| 562 | { 4, 40, 55, 31, -2 }, |
| 563 | { 8, 44, 54, 27, -5 }, |
| 564 | { 12, 48, 53, 22, -7 }, |
| 565 | { -9, 17, 52, 51, 17 }, |
| 566 | { -7, 22, 53, 48, 12 }, |
| 567 | { -5, 27, 54, 44, 8 }, |
| 568 | { -2, 31, 55, 40, 4 }, |
| 569 | }; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 570 | |
| 571 | /* Coefficients for vertical down-sampling */ |
Grazvydas Ignotas | 66be8f6 | 2010-08-24 15:18:43 +0200 | [diff] [blame] | 572 | static const struct dispc_v_coef coef_vdown_3tap[8] = { |
| 573 | { 0, 36, 56, 36, 0 }, |
| 574 | { 0, 40, 57, 31, 0 }, |
| 575 | { 0, 45, 56, 27, 0 }, |
| 576 | { 0, 50, 55, 23, 0 }, |
| 577 | { 0, 18, 55, 55, 0 }, |
| 578 | { 0, 23, 55, 50, 0 }, |
| 579 | { 0, 27, 56, 45, 0 }, |
| 580 | { 0, 31, 57, 40, 0 }, |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 581 | }; |
| 582 | |
Grazvydas Ignotas | 66be8f6 | 2010-08-24 15:18:43 +0200 | [diff] [blame] | 583 | static const struct dispc_v_coef coef_vdown_5tap[8] = { |
| 584 | { 0, 36, 56, 36, 0 }, |
| 585 | { 4, 40, 55, 31, -2 }, |
| 586 | { 8, 44, 54, 27, -5 }, |
| 587 | { 12, 48, 53, 22, -7 }, |
| 588 | { -9, 17, 52, 51, 17 }, |
| 589 | { -7, 22, 53, 48, 12 }, |
| 590 | { -5, 27, 54, 44, 8 }, |
| 591 | { -2, 31, 55, 40, 4 }, |
| 592 | }; |
| 593 | |
| 594 | const struct dispc_h_coef *h_coef; |
| 595 | const struct dispc_v_coef *v_coef; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 596 | int i; |
| 597 | |
| 598 | if (hscaleup) |
| 599 | h_coef = coef_hup; |
| 600 | else |
| 601 | h_coef = coef_hdown; |
| 602 | |
Grazvydas Ignotas | 66be8f6 | 2010-08-24 15:18:43 +0200 | [diff] [blame] | 603 | if (vscaleup) |
| 604 | v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap; |
| 605 | else |
| 606 | v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 607 | |
| 608 | for (i = 0; i < 8; i++) { |
| 609 | u32 h, hv; |
| 610 | |
Grazvydas Ignotas | 66be8f6 | 2010-08-24 15:18:43 +0200 | [diff] [blame] | 611 | h = FLD_VAL(h_coef[i].hc0, 7, 0) |
| 612 | | FLD_VAL(h_coef[i].hc1, 15, 8) |
| 613 | | FLD_VAL(h_coef[i].hc2, 23, 16) |
| 614 | | FLD_VAL(h_coef[i].hc3, 31, 24); |
| 615 | hv = FLD_VAL(h_coef[i].hc4, 7, 0) |
| 616 | | FLD_VAL(v_coef[i].vc0, 15, 8) |
| 617 | | FLD_VAL(v_coef[i].vc1, 23, 16) |
| 618 | | FLD_VAL(v_coef[i].vc2, 31, 24); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 619 | |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 620 | if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 621 | dispc_ovl_write_firh_reg(plane, i, h); |
| 622 | dispc_ovl_write_firhv_reg(plane, i, hv); |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 623 | } else { |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 624 | dispc_ovl_write_firh2_reg(plane, i, h); |
| 625 | dispc_ovl_write_firhv2_reg(plane, i, hv); |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 626 | } |
| 627 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 628 | } |
| 629 | |
Grazvydas Ignotas | 66be8f6 | 2010-08-24 15:18:43 +0200 | [diff] [blame] | 630 | if (five_taps) { |
| 631 | for (i = 0; i < 8; i++) { |
| 632 | u32 v; |
| 633 | v = FLD_VAL(v_coef[i].vc00, 7, 0) |
| 634 | | FLD_VAL(v_coef[i].vc22, 15, 8); |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 635 | if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 636 | dispc_ovl_write_firv_reg(plane, i, v); |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 637 | else |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 638 | dispc_ovl_write_firv2_reg(plane, i, v); |
Grazvydas Ignotas | 66be8f6 | 2010-08-24 15:18:43 +0200 | [diff] [blame] | 639 | } |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 640 | } |
| 641 | } |
| 642 | |
| 643 | static void _dispc_setup_color_conv_coef(void) |
| 644 | { |
Archit Taneja | ac01c29 | 2011-08-05 19:06:03 +0530 | [diff] [blame] | 645 | int i; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 646 | const struct color_conv_coef { |
| 647 | int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb; |
| 648 | int full_range; |
| 649 | } ctbl_bt601_5 = { |
| 650 | 298, 409, 0, 298, -208, -100, 298, 0, 517, 0, |
| 651 | }; |
| 652 | |
| 653 | const struct color_conv_coef *ct; |
| 654 | |
| 655 | #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0)) |
| 656 | |
| 657 | ct = &ctbl_bt601_5; |
| 658 | |
Archit Taneja | ac01c29 | 2011-08-05 19:06:03 +0530 | [diff] [blame] | 659 | for (i = 1; i < dss_feat_get_num_ovls(); i++) { |
| 660 | dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0), |
| 661 | CVAL(ct->rcr, ct->ry)); |
| 662 | dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1), |
| 663 | CVAL(ct->gy, ct->rcb)); |
| 664 | dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2), |
| 665 | CVAL(ct->gcb, ct->gcr)); |
| 666 | dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3), |
| 667 | CVAL(ct->bcr, ct->by)); |
| 668 | dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4), |
| 669 | CVAL(0, ct->bcb)); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 670 | |
Archit Taneja | ac01c29 | 2011-08-05 19:06:03 +0530 | [diff] [blame] | 671 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range, |
| 672 | 11, 11); |
| 673 | } |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 674 | |
| 675 | #undef CVAL |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 676 | } |
| 677 | |
| 678 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 679 | static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 680 | { |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 681 | dispc_write_reg(DISPC_OVL_BA0(plane), paddr); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 682 | } |
| 683 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 684 | static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 685 | { |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 686 | dispc_write_reg(DISPC_OVL_BA1(plane), paddr); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 687 | } |
| 688 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 689 | static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr) |
Amber Jain | ab5ca07 | 2011-05-19 19:47:53 +0530 | [diff] [blame] | 690 | { |
| 691 | dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr); |
| 692 | } |
| 693 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 694 | static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr) |
Amber Jain | ab5ca07 | 2011-05-19 19:47:53 +0530 | [diff] [blame] | 695 | { |
| 696 | dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr); |
| 697 | } |
| 698 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 699 | static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 700 | { |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 701 | u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0); |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 702 | |
| 703 | dispc_write_reg(DISPC_OVL_POSITION(plane), val); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 704 | } |
| 705 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 706 | static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 707 | { |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 708 | u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 709 | |
| 710 | if (plane == OMAP_DSS_GFX) |
| 711 | dispc_write_reg(DISPC_OVL_SIZE(plane), val); |
| 712 | else |
| 713 | dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 714 | } |
| 715 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 716 | static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 717 | { |
| 718 | u32 val; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 719 | |
| 720 | BUG_ON(plane == OMAP_DSS_GFX); |
| 721 | |
| 722 | val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 723 | |
| 724 | dispc_write_reg(DISPC_OVL_SIZE(plane), val); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 725 | } |
| 726 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 727 | static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable) |
Rajkumar N | fd28a39 | 2010-11-04 12:28:42 +0100 | [diff] [blame] | 728 | { |
Tomi Valkeinen | f6dc815 | 2011-08-15 15:18:20 +0300 | [diff] [blame] | 729 | struct omap_overlay *ovl = omap_dss_get_overlay(plane); |
Rajkumar N | fd28a39 | 2010-11-04 12:28:42 +0100 | [diff] [blame] | 730 | |
Tomi Valkeinen | f6dc815 | 2011-08-15 15:18:20 +0300 | [diff] [blame] | 731 | if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0) |
Rajkumar N | fd28a39 | 2010-11-04 12:28:42 +0100 | [diff] [blame] | 732 | return; |
| 733 | |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 734 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); |
Rajkumar N | fd28a39 | 2010-11-04 12:28:42 +0100 | [diff] [blame] | 735 | } |
| 736 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 737 | static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 738 | { |
Tomi Valkeinen | fe3cc9d | 2011-08-15 11:51:50 +0300 | [diff] [blame] | 739 | static const unsigned shifts[] = { 0, 8, 16, }; |
| 740 | int shift; |
Tomi Valkeinen | f6dc815 | 2011-08-15 15:18:20 +0300 | [diff] [blame] | 741 | struct omap_overlay *ovl = omap_dss_get_overlay(plane); |
Tomi Valkeinen | fe3cc9d | 2011-08-15 11:51:50 +0300 | [diff] [blame] | 742 | |
Tomi Valkeinen | f6dc815 | 2011-08-15 15:18:20 +0300 | [diff] [blame] | 743 | if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0) |
Rajkumar N | fd28a39 | 2010-11-04 12:28:42 +0100 | [diff] [blame] | 744 | return; |
Archit Taneja | a0acb55 | 2010-09-15 19:20:00 +0530 | [diff] [blame] | 745 | |
Tomi Valkeinen | fe3cc9d | 2011-08-15 11:51:50 +0300 | [diff] [blame] | 746 | shift = shifts[plane]; |
| 747 | REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 748 | } |
| 749 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 750 | static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 751 | { |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 752 | dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 753 | } |
| 754 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 755 | static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 756 | { |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 757 | dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 758 | } |
| 759 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 760 | static void dispc_ovl_set_color_mode(enum omap_plane plane, |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 761 | enum omap_color_mode color_mode) |
| 762 | { |
| 763 | u32 m = 0; |
Amber Jain | f20e422 | 2011-05-19 19:47:50 +0530 | [diff] [blame] | 764 | if (plane != OMAP_DSS_GFX) { |
| 765 | switch (color_mode) { |
| 766 | case OMAP_DSS_COLOR_NV12: |
| 767 | m = 0x0; break; |
| 768 | case OMAP_DSS_COLOR_RGB12U: |
| 769 | m = 0x1; break; |
| 770 | case OMAP_DSS_COLOR_RGBA16: |
| 771 | m = 0x2; break; |
| 772 | case OMAP_DSS_COLOR_RGBX16: |
| 773 | m = 0x4; break; |
| 774 | case OMAP_DSS_COLOR_ARGB16: |
| 775 | m = 0x5; break; |
| 776 | case OMAP_DSS_COLOR_RGB16: |
| 777 | m = 0x6; break; |
| 778 | case OMAP_DSS_COLOR_ARGB16_1555: |
| 779 | m = 0x7; break; |
| 780 | case OMAP_DSS_COLOR_RGB24U: |
| 781 | m = 0x8; break; |
| 782 | case OMAP_DSS_COLOR_RGB24P: |
| 783 | m = 0x9; break; |
| 784 | case OMAP_DSS_COLOR_YUV2: |
| 785 | m = 0xa; break; |
| 786 | case OMAP_DSS_COLOR_UYVY: |
| 787 | m = 0xb; break; |
| 788 | case OMAP_DSS_COLOR_ARGB32: |
| 789 | m = 0xc; break; |
| 790 | case OMAP_DSS_COLOR_RGBA32: |
| 791 | m = 0xd; break; |
| 792 | case OMAP_DSS_COLOR_RGBX32: |
| 793 | m = 0xe; break; |
| 794 | case OMAP_DSS_COLOR_XRGB16_1555: |
| 795 | m = 0xf; break; |
| 796 | default: |
| 797 | BUG(); break; |
| 798 | } |
| 799 | } else { |
| 800 | switch (color_mode) { |
| 801 | case OMAP_DSS_COLOR_CLUT1: |
| 802 | m = 0x0; break; |
| 803 | case OMAP_DSS_COLOR_CLUT2: |
| 804 | m = 0x1; break; |
| 805 | case OMAP_DSS_COLOR_CLUT4: |
| 806 | m = 0x2; break; |
| 807 | case OMAP_DSS_COLOR_CLUT8: |
| 808 | m = 0x3; break; |
| 809 | case OMAP_DSS_COLOR_RGB12U: |
| 810 | m = 0x4; break; |
| 811 | case OMAP_DSS_COLOR_ARGB16: |
| 812 | m = 0x5; break; |
| 813 | case OMAP_DSS_COLOR_RGB16: |
| 814 | m = 0x6; break; |
| 815 | case OMAP_DSS_COLOR_ARGB16_1555: |
| 816 | m = 0x7; break; |
| 817 | case OMAP_DSS_COLOR_RGB24U: |
| 818 | m = 0x8; break; |
| 819 | case OMAP_DSS_COLOR_RGB24P: |
| 820 | m = 0x9; break; |
| 821 | case OMAP_DSS_COLOR_YUV2: |
| 822 | m = 0xa; break; |
| 823 | case OMAP_DSS_COLOR_UYVY: |
| 824 | m = 0xb; break; |
| 825 | case OMAP_DSS_COLOR_ARGB32: |
| 826 | m = 0xc; break; |
| 827 | case OMAP_DSS_COLOR_RGBA32: |
| 828 | m = 0xd; break; |
| 829 | case OMAP_DSS_COLOR_RGBX32: |
| 830 | m = 0xe; break; |
| 831 | case OMAP_DSS_COLOR_XRGB16_1555: |
| 832 | m = 0xf; break; |
| 833 | default: |
| 834 | BUG(); break; |
| 835 | } |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 836 | } |
| 837 | |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 838 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 839 | } |
| 840 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 841 | static void dispc_ovl_set_channel_out(enum omap_plane plane, |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 842 | enum omap_channel channel) |
| 843 | { |
| 844 | int shift; |
| 845 | u32 val; |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 846 | int chan = 0, chan2 = 0; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 847 | |
| 848 | switch (plane) { |
| 849 | case OMAP_DSS_GFX: |
| 850 | shift = 8; |
| 851 | break; |
| 852 | case OMAP_DSS_VIDEO1: |
| 853 | case OMAP_DSS_VIDEO2: |
| 854 | shift = 16; |
| 855 | break; |
| 856 | default: |
| 857 | BUG(); |
| 858 | return; |
| 859 | } |
| 860 | |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 861 | val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 862 | if (dss_has_feature(FEAT_MGR_LCD2)) { |
| 863 | switch (channel) { |
| 864 | case OMAP_DSS_CHANNEL_LCD: |
| 865 | chan = 0; |
| 866 | chan2 = 0; |
| 867 | break; |
| 868 | case OMAP_DSS_CHANNEL_DIGIT: |
| 869 | chan = 1; |
| 870 | chan2 = 0; |
| 871 | break; |
| 872 | case OMAP_DSS_CHANNEL_LCD2: |
| 873 | chan = 0; |
| 874 | chan2 = 1; |
| 875 | break; |
| 876 | default: |
| 877 | BUG(); |
| 878 | } |
| 879 | |
| 880 | val = FLD_MOD(val, chan, shift, shift); |
| 881 | val = FLD_MOD(val, chan2, 31, 30); |
| 882 | } else { |
| 883 | val = FLD_MOD(val, channel, shift, shift); |
| 884 | } |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 885 | dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 886 | } |
| 887 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 888 | static void dispc_ovl_set_burst_size(enum omap_plane plane, |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 889 | enum omap_burst_size burst_size) |
| 890 | { |
Tomi Valkeinen | fe3cc9d | 2011-08-15 11:51:50 +0300 | [diff] [blame] | 891 | static const unsigned shifts[] = { 6, 14, 14, }; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 892 | int shift; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 893 | |
Tomi Valkeinen | fe3cc9d | 2011-08-15 11:51:50 +0300 | [diff] [blame] | 894 | shift = shifts[plane]; |
Tomi Valkeinen | 5ed8cf5 | 2011-06-21 09:35:36 +0300 | [diff] [blame] | 895 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 896 | } |
| 897 | |
Tomi Valkeinen | 5ed8cf5 | 2011-06-21 09:35:36 +0300 | [diff] [blame] | 898 | static void dispc_configure_burst_sizes(void) |
| 899 | { |
| 900 | int i; |
| 901 | const int burst_size = BURST_SIZE_X8; |
| 902 | |
| 903 | /* Configure burst size always to maximum size */ |
| 904 | for (i = 0; i < omap_dss_get_num_overlays(); ++i) |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 905 | dispc_ovl_set_burst_size(i, burst_size); |
Tomi Valkeinen | 5ed8cf5 | 2011-06-21 09:35:36 +0300 | [diff] [blame] | 906 | } |
| 907 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 908 | u32 dispc_ovl_get_burst_size(enum omap_plane plane) |
Tomi Valkeinen | 5ed8cf5 | 2011-06-21 09:35:36 +0300 | [diff] [blame] | 909 | { |
| 910 | unsigned unit = dss_feat_get_burst_size_unit(); |
| 911 | /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */ |
| 912 | return unit * 8; |
| 913 | } |
| 914 | |
Mythri P K | d386261 | 2011-03-11 18:02:49 +0530 | [diff] [blame] | 915 | void dispc_enable_gamma_table(bool enable) |
| 916 | { |
| 917 | /* |
| 918 | * This is partially implemented to support only disabling of |
| 919 | * the gamma table. |
| 920 | */ |
| 921 | if (enable) { |
| 922 | DSSWARN("Gamma table enabling for TV not yet supported"); |
| 923 | return; |
| 924 | } |
| 925 | |
| 926 | REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9); |
| 927 | } |
| 928 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 929 | void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable) |
Tomi Valkeinen | 3c07cae | 2011-06-21 09:34:30 +0300 | [diff] [blame] | 930 | { |
| 931 | u16 reg; |
| 932 | |
| 933 | if (channel == OMAP_DSS_CHANNEL_LCD) |
| 934 | reg = DISPC_CONFIG; |
| 935 | else if (channel == OMAP_DSS_CHANNEL_LCD2) |
| 936 | reg = DISPC_CONFIG2; |
| 937 | else |
| 938 | return; |
| 939 | |
| 940 | REG_FLD_MOD(reg, enable, 15, 15); |
| 941 | } |
| 942 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 943 | void dispc_mgr_set_cpr_coef(enum omap_channel channel, |
Tomi Valkeinen | 3c07cae | 2011-06-21 09:34:30 +0300 | [diff] [blame] | 944 | struct omap_dss_cpr_coefs *coefs) |
| 945 | { |
| 946 | u32 coef_r, coef_g, coef_b; |
| 947 | |
| 948 | if (channel != OMAP_DSS_CHANNEL_LCD && channel != OMAP_DSS_CHANNEL_LCD2) |
| 949 | return; |
| 950 | |
| 951 | coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) | |
| 952 | FLD_VAL(coefs->rb, 9, 0); |
| 953 | coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) | |
| 954 | FLD_VAL(coefs->gb, 9, 0); |
| 955 | coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) | |
| 956 | FLD_VAL(coefs->bb, 9, 0); |
| 957 | |
| 958 | dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r); |
| 959 | dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g); |
| 960 | dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b); |
| 961 | } |
| 962 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 963 | static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 964 | { |
| 965 | u32 val; |
| 966 | |
| 967 | BUG_ON(plane == OMAP_DSS_GFX); |
| 968 | |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 969 | val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 970 | val = FLD_MOD(val, enable, 9, 9); |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 971 | dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 972 | } |
| 973 | |
Archit Taneja | c3d92529 | 2011-09-14 11:52:54 +0530 | [diff] [blame^] | 974 | static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 975 | { |
Tomi Valkeinen | fe3cc9d | 2011-08-15 11:51:50 +0300 | [diff] [blame] | 976 | static const unsigned shifts[] = { 5, 10, 10 }; |
| 977 | int shift; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 978 | |
Tomi Valkeinen | fe3cc9d | 2011-08-15 11:51:50 +0300 | [diff] [blame] | 979 | shift = shifts[plane]; |
| 980 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 981 | } |
| 982 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 983 | void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 984 | { |
| 985 | u32 val; |
| 986 | BUG_ON((width > (1 << 11)) || (height > (1 << 11))); |
| 987 | val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); |
Archit Taneja | 702d144 | 2011-05-06 11:45:50 +0530 | [diff] [blame] | 988 | dispc_write_reg(DISPC_SIZE_MGR(channel), val); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 989 | } |
| 990 | |
| 991 | void dispc_set_digit_size(u16 width, u16 height) |
| 992 | { |
| 993 | u32 val; |
| 994 | BUG_ON((width > (1 << 11)) || (height > (1 << 11))); |
| 995 | val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); |
Archit Taneja | 702d144 | 2011-05-06 11:45:50 +0530 | [diff] [blame] | 996 | dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 997 | } |
| 998 | |
| 999 | static void dispc_read_plane_fifo_sizes(void) |
| 1000 | { |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1001 | u32 size; |
| 1002 | int plane; |
Archit Taneja | a0acb55 | 2010-09-15 19:20:00 +0530 | [diff] [blame] | 1003 | u8 start, end; |
Tomi Valkeinen | 5ed8cf5 | 2011-06-21 09:35:36 +0300 | [diff] [blame] | 1004 | u32 unit; |
| 1005 | |
| 1006 | unit = dss_feat_get_buffer_size_unit(); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1007 | |
Archit Taneja | a0acb55 | 2010-09-15 19:20:00 +0530 | [diff] [blame] | 1008 | dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1009 | |
Archit Taneja | e13a138 | 2011-08-05 19:06:04 +0530 | [diff] [blame] | 1010 | for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) { |
Tomi Valkeinen | 5ed8cf5 | 2011-06-21 09:35:36 +0300 | [diff] [blame] | 1011 | size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end); |
| 1012 | size *= unit; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1013 | dispc.fifo_size[plane] = size; |
| 1014 | } |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1015 | } |
| 1016 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 1017 | u32 dispc_ovl_get_fifo_size(enum omap_plane plane) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1018 | { |
| 1019 | return dispc.fifo_size[plane]; |
| 1020 | } |
| 1021 | |
Archit Taneja | c3d92529 | 2011-09-14 11:52:54 +0530 | [diff] [blame^] | 1022 | static void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, |
| 1023 | u32 high) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1024 | { |
Archit Taneja | a0acb55 | 2010-09-15 19:20:00 +0530 | [diff] [blame] | 1025 | u8 hi_start, hi_end, lo_start, lo_end; |
Tomi Valkeinen | 5ed8cf5 | 2011-06-21 09:35:36 +0300 | [diff] [blame] | 1026 | u32 unit; |
| 1027 | |
| 1028 | unit = dss_feat_get_buffer_size_unit(); |
| 1029 | |
| 1030 | WARN_ON(low % unit != 0); |
| 1031 | WARN_ON(high % unit != 0); |
| 1032 | |
| 1033 | low /= unit; |
| 1034 | high /= unit; |
Archit Taneja | a0acb55 | 2010-09-15 19:20:00 +0530 | [diff] [blame] | 1035 | |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 1036 | dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end); |
| 1037 | dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end); |
| 1038 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1039 | DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n", |
| 1040 | plane, |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 1041 | REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), |
| 1042 | lo_start, lo_end), |
| 1043 | REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), |
| 1044 | hi_start, hi_end), |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1045 | low, high); |
| 1046 | |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 1047 | dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane), |
Archit Taneja | a0acb55 | 2010-09-15 19:20:00 +0530 | [diff] [blame] | 1048 | FLD_VAL(high, hi_start, hi_end) | |
| 1049 | FLD_VAL(low, lo_start, lo_end)); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1050 | } |
| 1051 | |
| 1052 | void dispc_enable_fifomerge(bool enable) |
| 1053 | { |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1054 | DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled"); |
| 1055 | REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1056 | } |
| 1057 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 1058 | static void dispc_ovl_set_fir(enum omap_plane plane, |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 1059 | int hinc, int vinc, |
| 1060 | enum omap_color_component color_comp) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1061 | { |
| 1062 | u32 val; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1063 | |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 1064 | if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { |
| 1065 | u8 hinc_start, hinc_end, vinc_start, vinc_end; |
Archit Taneja | a0acb55 | 2010-09-15 19:20:00 +0530 | [diff] [blame] | 1066 | |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 1067 | dss_feat_get_reg_field(FEAT_REG_FIRHINC, |
| 1068 | &hinc_start, &hinc_end); |
| 1069 | dss_feat_get_reg_field(FEAT_REG_FIRVINC, |
| 1070 | &vinc_start, &vinc_end); |
| 1071 | val = FLD_VAL(vinc, vinc_start, vinc_end) | |
| 1072 | FLD_VAL(hinc, hinc_start, hinc_end); |
Archit Taneja | a0acb55 | 2010-09-15 19:20:00 +0530 | [diff] [blame] | 1073 | |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 1074 | dispc_write_reg(DISPC_OVL_FIR(plane), val); |
| 1075 | } else { |
| 1076 | val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0); |
| 1077 | dispc_write_reg(DISPC_OVL_FIR2(plane), val); |
| 1078 | } |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1079 | } |
| 1080 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 1081 | static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1082 | { |
| 1083 | u32 val; |
Archit Taneja | 87a7484 | 2011-03-02 11:19:50 +0530 | [diff] [blame] | 1084 | u8 hor_start, hor_end, vert_start, vert_end; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1085 | |
Archit Taneja | 87a7484 | 2011-03-02 11:19:50 +0530 | [diff] [blame] | 1086 | dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); |
| 1087 | dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); |
| 1088 | |
| 1089 | val = FLD_VAL(vaccu, vert_start, vert_end) | |
| 1090 | FLD_VAL(haccu, hor_start, hor_end); |
| 1091 | |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 1092 | dispc_write_reg(DISPC_OVL_ACCU0(plane), val); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1093 | } |
| 1094 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 1095 | static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1096 | { |
| 1097 | u32 val; |
Archit Taneja | 87a7484 | 2011-03-02 11:19:50 +0530 | [diff] [blame] | 1098 | u8 hor_start, hor_end, vert_start, vert_end; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1099 | |
Archit Taneja | 87a7484 | 2011-03-02 11:19:50 +0530 | [diff] [blame] | 1100 | dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); |
| 1101 | dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); |
| 1102 | |
| 1103 | val = FLD_VAL(vaccu, vert_start, vert_end) | |
| 1104 | FLD_VAL(haccu, hor_start, hor_end); |
| 1105 | |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 1106 | dispc_write_reg(DISPC_OVL_ACCU1(plane), val); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1107 | } |
| 1108 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 1109 | static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu, |
| 1110 | int vaccu) |
Amber Jain | ab5ca07 | 2011-05-19 19:47:53 +0530 | [diff] [blame] | 1111 | { |
| 1112 | u32 val; |
| 1113 | |
| 1114 | val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); |
| 1115 | dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val); |
| 1116 | } |
| 1117 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 1118 | static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu, |
| 1119 | int vaccu) |
Amber Jain | ab5ca07 | 2011-05-19 19:47:53 +0530 | [diff] [blame] | 1120 | { |
| 1121 | u32 val; |
| 1122 | |
| 1123 | val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); |
| 1124 | dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val); |
| 1125 | } |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1126 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 1127 | static void dispc_ovl_set_scale_param(enum omap_plane plane, |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1128 | u16 orig_width, u16 orig_height, |
| 1129 | u16 out_width, u16 out_height, |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 1130 | bool five_taps, u8 rotation, |
| 1131 | enum omap_color_component color_comp) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1132 | { |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 1133 | int fir_hinc, fir_vinc; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1134 | int hscaleup, vscaleup; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1135 | |
| 1136 | hscaleup = orig_width <= out_width; |
| 1137 | vscaleup = orig_height <= out_height; |
| 1138 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 1139 | dispc_ovl_set_scale_coef(plane, hscaleup, vscaleup, five_taps, |
| 1140 | color_comp); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1141 | |
Amber Jain | ed14a3c | 2011-05-19 19:47:51 +0530 | [diff] [blame] | 1142 | fir_hinc = 1024 * orig_width / out_width; |
| 1143 | fir_vinc = 1024 * orig_height / out_height; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1144 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 1145 | dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp); |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 1146 | } |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1147 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 1148 | static void dispc_ovl_set_scaling_common(enum omap_plane plane, |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 1149 | u16 orig_width, u16 orig_height, |
| 1150 | u16 out_width, u16 out_height, |
| 1151 | bool ilace, bool five_taps, |
| 1152 | bool fieldmode, enum omap_color_mode color_mode, |
| 1153 | u8 rotation) |
| 1154 | { |
| 1155 | int accu0 = 0; |
| 1156 | int accu1 = 0; |
| 1157 | u32 l; |
| 1158 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 1159 | dispc_ovl_set_scale_param(plane, orig_width, orig_height, |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 1160 | out_width, out_height, five_taps, |
| 1161 | rotation, DISPC_COLOR_COMPONENT_RGB_Y); |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 1162 | l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1163 | |
Archit Taneja | 87a7484 | 2011-03-02 11:19:50 +0530 | [diff] [blame] | 1164 | /* RESIZEENABLE and VERTICALTAPS */ |
| 1165 | l &= ~((0x3 << 5) | (0x1 << 21)); |
Amber Jain | ed14a3c | 2011-05-19 19:47:51 +0530 | [diff] [blame] | 1166 | l |= (orig_width != out_width) ? (1 << 5) : 0; |
| 1167 | l |= (orig_height != out_height) ? (1 << 6) : 0; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1168 | l |= five_taps ? (1 << 21) : 0; |
Archit Taneja | 87a7484 | 2011-03-02 11:19:50 +0530 | [diff] [blame] | 1169 | |
| 1170 | /* VRESIZECONF and HRESIZECONF */ |
| 1171 | if (dss_has_feature(FEAT_RESIZECONF)) { |
| 1172 | l &= ~(0x3 << 7); |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 1173 | l |= (orig_width <= out_width) ? 0 : (1 << 7); |
| 1174 | l |= (orig_height <= out_height) ? 0 : (1 << 8); |
Archit Taneja | 87a7484 | 2011-03-02 11:19:50 +0530 | [diff] [blame] | 1175 | } |
| 1176 | |
| 1177 | /* LINEBUFFERSPLIT */ |
| 1178 | if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) { |
| 1179 | l &= ~(0x1 << 22); |
| 1180 | l |= five_taps ? (1 << 22) : 0; |
| 1181 | } |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1182 | |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 1183 | dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1184 | |
| 1185 | /* |
| 1186 | * field 0 = even field = bottom field |
| 1187 | * field 1 = odd field = top field |
| 1188 | */ |
| 1189 | if (ilace && !fieldmode) { |
| 1190 | accu1 = 0; |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 1191 | accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1192 | if (accu0 >= 1024/2) { |
| 1193 | accu1 = 1024/2; |
| 1194 | accu0 -= accu1; |
| 1195 | } |
| 1196 | } |
| 1197 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 1198 | dispc_ovl_set_vid_accu0(plane, 0, accu0); |
| 1199 | dispc_ovl_set_vid_accu1(plane, 0, accu1); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1200 | } |
| 1201 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 1202 | static void dispc_ovl_set_scaling_uv(enum omap_plane plane, |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 1203 | u16 orig_width, u16 orig_height, |
| 1204 | u16 out_width, u16 out_height, |
| 1205 | bool ilace, bool five_taps, |
| 1206 | bool fieldmode, enum omap_color_mode color_mode, |
| 1207 | u8 rotation) |
| 1208 | { |
| 1209 | int scale_x = out_width != orig_width; |
| 1210 | int scale_y = out_height != orig_height; |
| 1211 | |
| 1212 | if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) |
| 1213 | return; |
| 1214 | if ((color_mode != OMAP_DSS_COLOR_YUV2 && |
| 1215 | color_mode != OMAP_DSS_COLOR_UYVY && |
| 1216 | color_mode != OMAP_DSS_COLOR_NV12)) { |
| 1217 | /* reset chroma resampling for RGB formats */ |
| 1218 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8); |
| 1219 | return; |
| 1220 | } |
| 1221 | switch (color_mode) { |
| 1222 | case OMAP_DSS_COLOR_NV12: |
| 1223 | /* UV is subsampled by 2 vertically*/ |
| 1224 | orig_height >>= 1; |
| 1225 | /* UV is subsampled by 2 horz.*/ |
| 1226 | orig_width >>= 1; |
| 1227 | break; |
| 1228 | case OMAP_DSS_COLOR_YUV2: |
| 1229 | case OMAP_DSS_COLOR_UYVY: |
| 1230 | /*For YUV422 with 90/270 rotation, |
| 1231 | *we don't upsample chroma |
| 1232 | */ |
| 1233 | if (rotation == OMAP_DSS_ROT_0 || |
| 1234 | rotation == OMAP_DSS_ROT_180) |
| 1235 | /* UV is subsampled by 2 hrz*/ |
| 1236 | orig_width >>= 1; |
| 1237 | /* must use FIR for YUV422 if rotated */ |
| 1238 | if (rotation != OMAP_DSS_ROT_0) |
| 1239 | scale_x = scale_y = true; |
| 1240 | break; |
| 1241 | default: |
| 1242 | BUG(); |
| 1243 | } |
| 1244 | |
| 1245 | if (out_width != orig_width) |
| 1246 | scale_x = true; |
| 1247 | if (out_height != orig_height) |
| 1248 | scale_y = true; |
| 1249 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 1250 | dispc_ovl_set_scale_param(plane, orig_width, orig_height, |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 1251 | out_width, out_height, five_taps, |
| 1252 | rotation, DISPC_COLOR_COMPONENT_UV); |
| 1253 | |
| 1254 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), |
| 1255 | (scale_x || scale_y) ? 1 : 0, 8, 8); |
| 1256 | /* set H scaling */ |
| 1257 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5); |
| 1258 | /* set V scaling */ |
| 1259 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6); |
| 1260 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 1261 | dispc_ovl_set_vid_accu2_0(plane, 0x80, 0); |
| 1262 | dispc_ovl_set_vid_accu2_1(plane, 0x80, 0); |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 1263 | } |
| 1264 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 1265 | static void dispc_ovl_set_scaling(enum omap_plane plane, |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 1266 | u16 orig_width, u16 orig_height, |
| 1267 | u16 out_width, u16 out_height, |
| 1268 | bool ilace, bool five_taps, |
| 1269 | bool fieldmode, enum omap_color_mode color_mode, |
| 1270 | u8 rotation) |
| 1271 | { |
| 1272 | BUG_ON(plane == OMAP_DSS_GFX); |
| 1273 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 1274 | dispc_ovl_set_scaling_common(plane, |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 1275 | orig_width, orig_height, |
| 1276 | out_width, out_height, |
| 1277 | ilace, five_taps, |
| 1278 | fieldmode, color_mode, |
| 1279 | rotation); |
| 1280 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 1281 | dispc_ovl_set_scaling_uv(plane, |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 1282 | orig_width, orig_height, |
| 1283 | out_width, out_height, |
| 1284 | ilace, five_taps, |
| 1285 | fieldmode, color_mode, |
| 1286 | rotation); |
| 1287 | } |
| 1288 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 1289 | static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation, |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1290 | bool mirroring, enum omap_color_mode color_mode) |
| 1291 | { |
Archit Taneja | 87a7484 | 2011-03-02 11:19:50 +0530 | [diff] [blame] | 1292 | bool row_repeat = false; |
| 1293 | int vidrot = 0; |
| 1294 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1295 | if (color_mode == OMAP_DSS_COLOR_YUV2 || |
| 1296 | color_mode == OMAP_DSS_COLOR_UYVY) { |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1297 | |
| 1298 | if (mirroring) { |
| 1299 | switch (rotation) { |
| 1300 | case OMAP_DSS_ROT_0: |
| 1301 | vidrot = 2; |
| 1302 | break; |
| 1303 | case OMAP_DSS_ROT_90: |
| 1304 | vidrot = 1; |
| 1305 | break; |
| 1306 | case OMAP_DSS_ROT_180: |
| 1307 | vidrot = 0; |
| 1308 | break; |
| 1309 | case OMAP_DSS_ROT_270: |
| 1310 | vidrot = 3; |
| 1311 | break; |
| 1312 | } |
| 1313 | } else { |
| 1314 | switch (rotation) { |
| 1315 | case OMAP_DSS_ROT_0: |
| 1316 | vidrot = 0; |
| 1317 | break; |
| 1318 | case OMAP_DSS_ROT_90: |
| 1319 | vidrot = 1; |
| 1320 | break; |
| 1321 | case OMAP_DSS_ROT_180: |
| 1322 | vidrot = 2; |
| 1323 | break; |
| 1324 | case OMAP_DSS_ROT_270: |
| 1325 | vidrot = 3; |
| 1326 | break; |
| 1327 | } |
| 1328 | } |
| 1329 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1330 | if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270) |
Archit Taneja | 87a7484 | 2011-03-02 11:19:50 +0530 | [diff] [blame] | 1331 | row_repeat = true; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1332 | else |
Archit Taneja | 87a7484 | 2011-03-02 11:19:50 +0530 | [diff] [blame] | 1333 | row_repeat = false; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1334 | } |
Archit Taneja | 87a7484 | 2011-03-02 11:19:50 +0530 | [diff] [blame] | 1335 | |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 1336 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); |
Archit Taneja | 87a7484 | 2011-03-02 11:19:50 +0530 | [diff] [blame] | 1337 | if (dss_has_feature(FEAT_ROWREPEATENABLE)) |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 1338 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), |
| 1339 | row_repeat ? 1 : 0, 18, 18); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1340 | } |
| 1341 | |
| 1342 | static int color_mode_to_bpp(enum omap_color_mode color_mode) |
| 1343 | { |
| 1344 | switch (color_mode) { |
| 1345 | case OMAP_DSS_COLOR_CLUT1: |
| 1346 | return 1; |
| 1347 | case OMAP_DSS_COLOR_CLUT2: |
| 1348 | return 2; |
| 1349 | case OMAP_DSS_COLOR_CLUT4: |
| 1350 | return 4; |
| 1351 | case OMAP_DSS_COLOR_CLUT8: |
Amber Jain | f20e422 | 2011-05-19 19:47:50 +0530 | [diff] [blame] | 1352 | case OMAP_DSS_COLOR_NV12: |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1353 | return 8; |
| 1354 | case OMAP_DSS_COLOR_RGB12U: |
| 1355 | case OMAP_DSS_COLOR_RGB16: |
| 1356 | case OMAP_DSS_COLOR_ARGB16: |
| 1357 | case OMAP_DSS_COLOR_YUV2: |
| 1358 | case OMAP_DSS_COLOR_UYVY: |
Amber Jain | f20e422 | 2011-05-19 19:47:50 +0530 | [diff] [blame] | 1359 | case OMAP_DSS_COLOR_RGBA16: |
| 1360 | case OMAP_DSS_COLOR_RGBX16: |
| 1361 | case OMAP_DSS_COLOR_ARGB16_1555: |
| 1362 | case OMAP_DSS_COLOR_XRGB16_1555: |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1363 | return 16; |
| 1364 | case OMAP_DSS_COLOR_RGB24P: |
| 1365 | return 24; |
| 1366 | case OMAP_DSS_COLOR_RGB24U: |
| 1367 | case OMAP_DSS_COLOR_ARGB32: |
| 1368 | case OMAP_DSS_COLOR_RGBA32: |
| 1369 | case OMAP_DSS_COLOR_RGBX32: |
| 1370 | return 32; |
| 1371 | default: |
| 1372 | BUG(); |
| 1373 | } |
| 1374 | } |
| 1375 | |
| 1376 | static s32 pixinc(int pixels, u8 ps) |
| 1377 | { |
| 1378 | if (pixels == 1) |
| 1379 | return 1; |
| 1380 | else if (pixels > 1) |
| 1381 | return 1 + (pixels - 1) * ps; |
| 1382 | else if (pixels < 0) |
| 1383 | return 1 - (-pixels + 1) * ps; |
| 1384 | else |
| 1385 | BUG(); |
| 1386 | } |
| 1387 | |
| 1388 | static void calc_vrfb_rotation_offset(u8 rotation, bool mirror, |
| 1389 | u16 screen_width, |
| 1390 | u16 width, u16 height, |
| 1391 | enum omap_color_mode color_mode, bool fieldmode, |
| 1392 | unsigned int field_offset, |
| 1393 | unsigned *offset0, unsigned *offset1, |
| 1394 | s32 *row_inc, s32 *pix_inc) |
| 1395 | { |
| 1396 | u8 ps; |
| 1397 | |
| 1398 | /* FIXME CLUT formats */ |
| 1399 | switch (color_mode) { |
| 1400 | case OMAP_DSS_COLOR_CLUT1: |
| 1401 | case OMAP_DSS_COLOR_CLUT2: |
| 1402 | case OMAP_DSS_COLOR_CLUT4: |
| 1403 | case OMAP_DSS_COLOR_CLUT8: |
| 1404 | BUG(); |
| 1405 | return; |
| 1406 | case OMAP_DSS_COLOR_YUV2: |
| 1407 | case OMAP_DSS_COLOR_UYVY: |
| 1408 | ps = 4; |
| 1409 | break; |
| 1410 | default: |
| 1411 | ps = color_mode_to_bpp(color_mode) / 8; |
| 1412 | break; |
| 1413 | } |
| 1414 | |
| 1415 | DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width, |
| 1416 | width, height); |
| 1417 | |
| 1418 | /* |
| 1419 | * field 0 = even field = bottom field |
| 1420 | * field 1 = odd field = top field |
| 1421 | */ |
| 1422 | switch (rotation + mirror * 4) { |
| 1423 | case OMAP_DSS_ROT_0: |
| 1424 | case OMAP_DSS_ROT_180: |
| 1425 | /* |
| 1426 | * If the pixel format is YUV or UYVY divide the width |
| 1427 | * of the image by 2 for 0 and 180 degree rotation. |
| 1428 | */ |
| 1429 | if (color_mode == OMAP_DSS_COLOR_YUV2 || |
| 1430 | color_mode == OMAP_DSS_COLOR_UYVY) |
| 1431 | width = width >> 1; |
| 1432 | case OMAP_DSS_ROT_90: |
| 1433 | case OMAP_DSS_ROT_270: |
| 1434 | *offset1 = 0; |
| 1435 | if (field_offset) |
| 1436 | *offset0 = field_offset * screen_width * ps; |
| 1437 | else |
| 1438 | *offset0 = 0; |
| 1439 | |
| 1440 | *row_inc = pixinc(1 + (screen_width - width) + |
| 1441 | (fieldmode ? screen_width : 0), |
| 1442 | ps); |
| 1443 | *pix_inc = pixinc(1, ps); |
| 1444 | break; |
| 1445 | |
| 1446 | case OMAP_DSS_ROT_0 + 4: |
| 1447 | case OMAP_DSS_ROT_180 + 4: |
| 1448 | /* If the pixel format is YUV or UYVY divide the width |
| 1449 | * of the image by 2 for 0 degree and 180 degree |
| 1450 | */ |
| 1451 | if (color_mode == OMAP_DSS_COLOR_YUV2 || |
| 1452 | color_mode == OMAP_DSS_COLOR_UYVY) |
| 1453 | width = width >> 1; |
| 1454 | case OMAP_DSS_ROT_90 + 4: |
| 1455 | case OMAP_DSS_ROT_270 + 4: |
| 1456 | *offset1 = 0; |
| 1457 | if (field_offset) |
| 1458 | *offset0 = field_offset * screen_width * ps; |
| 1459 | else |
| 1460 | *offset0 = 0; |
| 1461 | *row_inc = pixinc(1 - (screen_width + width) - |
| 1462 | (fieldmode ? screen_width : 0), |
| 1463 | ps); |
| 1464 | *pix_inc = pixinc(1, ps); |
| 1465 | break; |
| 1466 | |
| 1467 | default: |
| 1468 | BUG(); |
| 1469 | } |
| 1470 | } |
| 1471 | |
| 1472 | static void calc_dma_rotation_offset(u8 rotation, bool mirror, |
| 1473 | u16 screen_width, |
| 1474 | u16 width, u16 height, |
| 1475 | enum omap_color_mode color_mode, bool fieldmode, |
| 1476 | unsigned int field_offset, |
| 1477 | unsigned *offset0, unsigned *offset1, |
| 1478 | s32 *row_inc, s32 *pix_inc) |
| 1479 | { |
| 1480 | u8 ps; |
| 1481 | u16 fbw, fbh; |
| 1482 | |
| 1483 | /* FIXME CLUT formats */ |
| 1484 | switch (color_mode) { |
| 1485 | case OMAP_DSS_COLOR_CLUT1: |
| 1486 | case OMAP_DSS_COLOR_CLUT2: |
| 1487 | case OMAP_DSS_COLOR_CLUT4: |
| 1488 | case OMAP_DSS_COLOR_CLUT8: |
| 1489 | BUG(); |
| 1490 | return; |
| 1491 | default: |
| 1492 | ps = color_mode_to_bpp(color_mode) / 8; |
| 1493 | break; |
| 1494 | } |
| 1495 | |
| 1496 | DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width, |
| 1497 | width, height); |
| 1498 | |
| 1499 | /* width & height are overlay sizes, convert to fb sizes */ |
| 1500 | |
| 1501 | if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) { |
| 1502 | fbw = width; |
| 1503 | fbh = height; |
| 1504 | } else { |
| 1505 | fbw = height; |
| 1506 | fbh = width; |
| 1507 | } |
| 1508 | |
| 1509 | /* |
| 1510 | * field 0 = even field = bottom field |
| 1511 | * field 1 = odd field = top field |
| 1512 | */ |
| 1513 | switch (rotation + mirror * 4) { |
| 1514 | case OMAP_DSS_ROT_0: |
| 1515 | *offset1 = 0; |
| 1516 | if (field_offset) |
| 1517 | *offset0 = *offset1 + field_offset * screen_width * ps; |
| 1518 | else |
| 1519 | *offset0 = *offset1; |
| 1520 | *row_inc = pixinc(1 + (screen_width - fbw) + |
| 1521 | (fieldmode ? screen_width : 0), |
| 1522 | ps); |
| 1523 | *pix_inc = pixinc(1, ps); |
| 1524 | break; |
| 1525 | case OMAP_DSS_ROT_90: |
| 1526 | *offset1 = screen_width * (fbh - 1) * ps; |
| 1527 | if (field_offset) |
| 1528 | *offset0 = *offset1 + field_offset * ps; |
| 1529 | else |
| 1530 | *offset0 = *offset1; |
| 1531 | *row_inc = pixinc(screen_width * (fbh - 1) + 1 + |
| 1532 | (fieldmode ? 1 : 0), ps); |
| 1533 | *pix_inc = pixinc(-screen_width, ps); |
| 1534 | break; |
| 1535 | case OMAP_DSS_ROT_180: |
| 1536 | *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; |
| 1537 | if (field_offset) |
| 1538 | *offset0 = *offset1 - field_offset * screen_width * ps; |
| 1539 | else |
| 1540 | *offset0 = *offset1; |
| 1541 | *row_inc = pixinc(-1 - |
| 1542 | (screen_width - fbw) - |
| 1543 | (fieldmode ? screen_width : 0), |
| 1544 | ps); |
| 1545 | *pix_inc = pixinc(-1, ps); |
| 1546 | break; |
| 1547 | case OMAP_DSS_ROT_270: |
| 1548 | *offset1 = (fbw - 1) * ps; |
| 1549 | if (field_offset) |
| 1550 | *offset0 = *offset1 - field_offset * ps; |
| 1551 | else |
| 1552 | *offset0 = *offset1; |
| 1553 | *row_inc = pixinc(-screen_width * (fbh - 1) - 1 - |
| 1554 | (fieldmode ? 1 : 0), ps); |
| 1555 | *pix_inc = pixinc(screen_width, ps); |
| 1556 | break; |
| 1557 | |
| 1558 | /* mirroring */ |
| 1559 | case OMAP_DSS_ROT_0 + 4: |
| 1560 | *offset1 = (fbw - 1) * ps; |
| 1561 | if (field_offset) |
| 1562 | *offset0 = *offset1 + field_offset * screen_width * ps; |
| 1563 | else |
| 1564 | *offset0 = *offset1; |
| 1565 | *row_inc = pixinc(screen_width * 2 - 1 + |
| 1566 | (fieldmode ? screen_width : 0), |
| 1567 | ps); |
| 1568 | *pix_inc = pixinc(-1, ps); |
| 1569 | break; |
| 1570 | |
| 1571 | case OMAP_DSS_ROT_90 + 4: |
| 1572 | *offset1 = 0; |
| 1573 | if (field_offset) |
| 1574 | *offset0 = *offset1 + field_offset * ps; |
| 1575 | else |
| 1576 | *offset0 = *offset1; |
| 1577 | *row_inc = pixinc(-screen_width * (fbh - 1) + 1 + |
| 1578 | (fieldmode ? 1 : 0), |
| 1579 | ps); |
| 1580 | *pix_inc = pixinc(screen_width, ps); |
| 1581 | break; |
| 1582 | |
| 1583 | case OMAP_DSS_ROT_180 + 4: |
| 1584 | *offset1 = screen_width * (fbh - 1) * ps; |
| 1585 | if (field_offset) |
| 1586 | *offset0 = *offset1 - field_offset * screen_width * ps; |
| 1587 | else |
| 1588 | *offset0 = *offset1; |
| 1589 | *row_inc = pixinc(1 - screen_width * 2 - |
| 1590 | (fieldmode ? screen_width : 0), |
| 1591 | ps); |
| 1592 | *pix_inc = pixinc(1, ps); |
| 1593 | break; |
| 1594 | |
| 1595 | case OMAP_DSS_ROT_270 + 4: |
| 1596 | *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; |
| 1597 | if (field_offset) |
| 1598 | *offset0 = *offset1 - field_offset * ps; |
| 1599 | else |
| 1600 | *offset0 = *offset1; |
| 1601 | *row_inc = pixinc(screen_width * (fbh - 1) - 1 - |
| 1602 | (fieldmode ? 1 : 0), |
| 1603 | ps); |
| 1604 | *pix_inc = pixinc(-screen_width, ps); |
| 1605 | break; |
| 1606 | |
| 1607 | default: |
| 1608 | BUG(); |
| 1609 | } |
| 1610 | } |
| 1611 | |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 1612 | static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width, |
| 1613 | u16 height, u16 out_width, u16 out_height, |
| 1614 | enum omap_color_mode color_mode) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1615 | { |
| 1616 | u32 fclk = 0; |
| 1617 | /* FIXME venc pclk? */ |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 1618 | u64 tmp, pclk = dispc_mgr_pclk_rate(channel); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1619 | |
| 1620 | if (height > out_height) { |
| 1621 | /* FIXME get real display PPL */ |
| 1622 | unsigned int ppl = 800; |
| 1623 | |
| 1624 | tmp = pclk * height * out_width; |
| 1625 | do_div(tmp, 2 * out_height * ppl); |
| 1626 | fclk = tmp; |
| 1627 | |
Ville Syrjälä | 2d9c559 | 2010-01-08 11:56:41 +0200 | [diff] [blame] | 1628 | if (height > 2 * out_height) { |
| 1629 | if (ppl == out_width) |
| 1630 | return 0; |
| 1631 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1632 | tmp = pclk * (height - 2 * out_height) * out_width; |
| 1633 | do_div(tmp, 2 * out_height * (ppl - out_width)); |
| 1634 | fclk = max(fclk, (u32) tmp); |
| 1635 | } |
| 1636 | } |
| 1637 | |
| 1638 | if (width > out_width) { |
| 1639 | tmp = pclk * width; |
| 1640 | do_div(tmp, out_width); |
| 1641 | fclk = max(fclk, (u32) tmp); |
| 1642 | |
| 1643 | if (color_mode == OMAP_DSS_COLOR_RGB24U) |
| 1644 | fclk <<= 1; |
| 1645 | } |
| 1646 | |
| 1647 | return fclk; |
| 1648 | } |
| 1649 | |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 1650 | static unsigned long calc_fclk(enum omap_channel channel, u16 width, |
| 1651 | u16 height, u16 out_width, u16 out_height) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1652 | { |
| 1653 | unsigned int hf, vf; |
| 1654 | |
| 1655 | /* |
| 1656 | * FIXME how to determine the 'A' factor |
| 1657 | * for the no downscaling case ? |
| 1658 | */ |
| 1659 | |
| 1660 | if (width > 3 * out_width) |
| 1661 | hf = 4; |
| 1662 | else if (width > 2 * out_width) |
| 1663 | hf = 3; |
| 1664 | else if (width > out_width) |
| 1665 | hf = 2; |
| 1666 | else |
| 1667 | hf = 1; |
| 1668 | |
| 1669 | if (height > out_height) |
| 1670 | vf = 2; |
| 1671 | else |
| 1672 | vf = 1; |
| 1673 | |
| 1674 | /* FIXME venc pclk? */ |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 1675 | return dispc_mgr_pclk_rate(channel) * vf * hf; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1676 | } |
| 1677 | |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1678 | int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi, |
Archit Taneja | c3d92529 | 2011-09-14 11:52:54 +0530 | [diff] [blame^] | 1679 | bool ilace, enum omap_channel channel, bool replication, |
| 1680 | u32 fifo_low, u32 fifo_high) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1681 | { |
| 1682 | const int maxdownscale = cpu_is_omap34xx() ? 4 : 2; |
| 1683 | bool five_taps = 0; |
| 1684 | bool fieldmode = 0; |
| 1685 | int cconv = 0; |
| 1686 | unsigned offset0, offset1; |
| 1687 | s32 row_inc; |
| 1688 | s32 pix_inc; |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1689 | u16 frame_height = oi->height; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1690 | unsigned int field_offset = 0; |
| 1691 | |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1692 | DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> " |
Archit Taneja | c3d92529 | 2011-09-14 11:52:54 +0530 | [diff] [blame^] | 1693 | "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d " |
| 1694 | "fifo_low %d fifo high %d\n", plane, oi->paddr, oi->p_uv_addr, |
| 1695 | oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height, |
| 1696 | oi->out_width, oi->out_height, oi->color_mode, oi->rotation, |
| 1697 | oi->mirror, ilace, channel, replication, fifo_low, fifo_high); |
Tomi Valkeinen | e6d80f9 | 2011-05-19 14:12:26 +0300 | [diff] [blame] | 1698 | |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1699 | if (oi->paddr == 0) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1700 | return -EINVAL; |
| 1701 | |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1702 | if (ilace && oi->height == oi->out_height) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1703 | fieldmode = 1; |
| 1704 | |
| 1705 | if (ilace) { |
| 1706 | if (fieldmode) |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1707 | oi->height /= 2; |
| 1708 | oi->pos_y /= 2; |
| 1709 | oi->out_height /= 2; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1710 | |
| 1711 | DSSDBG("adjusting for ilace: height %d, pos_y %d, " |
| 1712 | "out_height %d\n", |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1713 | oi->height, oi->pos_y, oi->out_height); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1714 | } |
| 1715 | |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1716 | if (!dss_feat_color_mode_supported(plane, oi->color_mode)) |
Archit Taneja | 8dad2ab | 2010-11-25 17:58:10 +0530 | [diff] [blame] | 1717 | return -EINVAL; |
| 1718 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1719 | if (plane == OMAP_DSS_GFX) { |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1720 | if (oi->width != oi->out_width || oi->height != oi->out_height) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1721 | return -EINVAL; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1722 | } else { |
| 1723 | /* video plane */ |
| 1724 | |
| 1725 | unsigned long fclk = 0; |
| 1726 | |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1727 | if (oi->out_width < oi->width / maxdownscale || |
| 1728 | oi->out_width > oi->width * 8) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1729 | return -EINVAL; |
| 1730 | |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1731 | if (oi->out_height < oi->height / maxdownscale || |
| 1732 | oi->out_height > oi->height * 8) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1733 | return -EINVAL; |
| 1734 | |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1735 | if (oi->color_mode == OMAP_DSS_COLOR_YUV2 || |
| 1736 | oi->color_mode == OMAP_DSS_COLOR_UYVY || |
| 1737 | oi->color_mode == OMAP_DSS_COLOR_NV12) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1738 | cconv = 1; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1739 | |
| 1740 | /* Must use 5-tap filter? */ |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1741 | five_taps = oi->height > oi->out_height * 2; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1742 | |
| 1743 | if (!five_taps) { |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1744 | fclk = calc_fclk(channel, oi->width, oi->height, |
| 1745 | oi->out_width, oi->out_height); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1746 | |
| 1747 | /* Try 5-tap filter if 3-tap fclk is too high */ |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1748 | if (cpu_is_omap34xx() && oi->height > oi->out_height && |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1749 | fclk > dispc_fclk_rate()) |
| 1750 | five_taps = true; |
| 1751 | } |
| 1752 | |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1753 | if (oi->width > (2048 >> five_taps)) { |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1754 | DSSERR("failed to set up scaling, fclk too low\n"); |
| 1755 | return -EINVAL; |
| 1756 | } |
| 1757 | |
| 1758 | if (five_taps) |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1759 | fclk = calc_fclk_five_taps(channel, oi->width, |
| 1760 | oi->height, oi->out_width, |
| 1761 | oi->out_height, oi->color_mode); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1762 | |
| 1763 | DSSDBG("required fclk rate = %lu Hz\n", fclk); |
| 1764 | DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate()); |
| 1765 | |
Ville Syrjälä | 2d9c559 | 2010-01-08 11:56:41 +0200 | [diff] [blame] | 1766 | if (!fclk || fclk > dispc_fclk_rate()) { |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1767 | DSSERR("failed to set up scaling, " |
| 1768 | "required fclk rate = %lu Hz, " |
| 1769 | "current fclk rate = %lu Hz\n", |
| 1770 | fclk, dispc_fclk_rate()); |
| 1771 | return -EINVAL; |
| 1772 | } |
| 1773 | } |
| 1774 | |
| 1775 | if (ilace && !fieldmode) { |
| 1776 | /* |
| 1777 | * when downscaling the bottom field may have to start several |
| 1778 | * source lines below the top field. Unfortunately ACCUI |
| 1779 | * registers will only hold the fractional part of the offset |
| 1780 | * so the integer part must be added to the base address of the |
| 1781 | * bottom field. |
| 1782 | */ |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1783 | if (!oi->height || oi->height == oi->out_height) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1784 | field_offset = 0; |
| 1785 | else |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1786 | field_offset = oi->height / oi->out_height / 2; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1787 | } |
| 1788 | |
| 1789 | /* Fields are independent but interleaved in memory. */ |
| 1790 | if (fieldmode) |
| 1791 | field_offset = 1; |
| 1792 | |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1793 | if (oi->rotation_type == OMAP_DSS_ROT_DMA) |
| 1794 | calc_dma_rotation_offset(oi->rotation, oi->mirror, |
| 1795 | oi->screen_width, oi->width, frame_height, |
| 1796 | oi->color_mode, fieldmode, field_offset, |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1797 | &offset0, &offset1, &row_inc, &pix_inc); |
| 1798 | else |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1799 | calc_vrfb_rotation_offset(oi->rotation, oi->mirror, |
| 1800 | oi->screen_width, oi->width, frame_height, |
| 1801 | oi->color_mode, fieldmode, field_offset, |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1802 | &offset0, &offset1, &row_inc, &pix_inc); |
| 1803 | |
| 1804 | DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n", |
| 1805 | offset0, offset1, row_inc, pix_inc); |
| 1806 | |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1807 | dispc_ovl_set_color_mode(plane, oi->color_mode); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1808 | |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1809 | dispc_ovl_set_ba0(plane, oi->paddr + offset0); |
| 1810 | dispc_ovl_set_ba1(plane, oi->paddr + offset1); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1811 | |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1812 | if (OMAP_DSS_COLOR_NV12 == oi->color_mode) { |
| 1813 | dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0); |
| 1814 | dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1); |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 1815 | } |
| 1816 | |
| 1817 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 1818 | dispc_ovl_set_row_inc(plane, row_inc); |
| 1819 | dispc_ovl_set_pix_inc(plane, pix_inc); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1820 | |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1821 | DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, oi->width, |
| 1822 | oi->height, oi->out_width, oi->out_height); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1823 | |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1824 | dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1825 | |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1826 | dispc_ovl_set_pic_size(plane, oi->width, oi->height); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1827 | |
| 1828 | if (plane != OMAP_DSS_GFX) { |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1829 | dispc_ovl_set_scaling(plane, oi->width, oi->height, |
| 1830 | oi->out_width, oi->out_height, |
Amber Jain | 0d66cbb | 2011-05-19 19:47:54 +0530 | [diff] [blame] | 1831 | ilace, five_taps, fieldmode, |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1832 | oi->color_mode, oi->rotation); |
| 1833 | dispc_ovl_set_vid_size(plane, oi->out_width, oi->out_height); |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 1834 | dispc_ovl_set_vid_color_conv(plane, cconv); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1835 | } |
| 1836 | |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1837 | dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror, |
| 1838 | oi->color_mode); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1839 | |
Archit Taneja | a4273b7 | 2011-09-14 11:10:10 +0530 | [diff] [blame] | 1840 | dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha); |
| 1841 | dispc_ovl_setup_global_alpha(plane, oi->global_alpha); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1842 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 1843 | dispc_ovl_set_channel_out(plane, channel); |
Tomi Valkeinen | 8fa8031 | 2011-08-16 12:56:19 +0300 | [diff] [blame] | 1844 | |
Archit Taneja | c3d92529 | 2011-09-14 11:52:54 +0530 | [diff] [blame^] | 1845 | dispc_ovl_enable_replication(plane, replication); |
| 1846 | dispc_ovl_set_fifo_threshold(plane, fifo_low, fifo_high); |
| 1847 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1848 | return 0; |
| 1849 | } |
| 1850 | |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 1851 | int dispc_ovl_enable(enum omap_plane plane, bool enable) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1852 | { |
Tomi Valkeinen | e6d80f9 | 2011-05-19 14:12:26 +0300 | [diff] [blame] | 1853 | DSSDBG("dispc_enable_plane %d, %d\n", plane, enable); |
| 1854 | |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 1855 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0); |
Tomi Valkeinen | e6d80f9 | 2011-05-19 14:12:26 +0300 | [diff] [blame] | 1856 | |
| 1857 | return 0; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1858 | } |
| 1859 | |
| 1860 | static void dispc_disable_isr(void *data, u32 mask) |
| 1861 | { |
| 1862 | struct completion *compl = data; |
| 1863 | complete(compl); |
| 1864 | } |
| 1865 | |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 1866 | static void _enable_lcd_out(enum omap_channel channel, bool enable) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1867 | { |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 1868 | if (channel == OMAP_DSS_CHANNEL_LCD2) |
| 1869 | REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0); |
| 1870 | else |
| 1871 | REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1872 | } |
| 1873 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 1874 | static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1875 | { |
| 1876 | struct completion frame_done_completion; |
| 1877 | bool is_on; |
| 1878 | int r; |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 1879 | u32 irq; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1880 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1881 | /* When we disable LCD output, we need to wait until frame is done. |
| 1882 | * Otherwise the DSS is still working, and turning off the clocks |
| 1883 | * prevents DSS from going to OFF mode */ |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 1884 | is_on = channel == OMAP_DSS_CHANNEL_LCD2 ? |
| 1885 | REG_GET(DISPC_CONTROL2, 0, 0) : |
| 1886 | REG_GET(DISPC_CONTROL, 0, 0); |
| 1887 | |
| 1888 | irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 : |
| 1889 | DISPC_IRQ_FRAMEDONE; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1890 | |
| 1891 | if (!enable && is_on) { |
| 1892 | init_completion(&frame_done_completion); |
| 1893 | |
| 1894 | r = omap_dispc_register_isr(dispc_disable_isr, |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 1895 | &frame_done_completion, irq); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1896 | |
| 1897 | if (r) |
| 1898 | DSSERR("failed to register FRAMEDONE isr\n"); |
| 1899 | } |
| 1900 | |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 1901 | _enable_lcd_out(channel, enable); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1902 | |
| 1903 | if (!enable && is_on) { |
| 1904 | if (!wait_for_completion_timeout(&frame_done_completion, |
| 1905 | msecs_to_jiffies(100))) |
| 1906 | DSSERR("timeout waiting for FRAME DONE\n"); |
| 1907 | |
| 1908 | r = omap_dispc_unregister_isr(dispc_disable_isr, |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 1909 | &frame_done_completion, irq); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1910 | |
| 1911 | if (r) |
| 1912 | DSSERR("failed to unregister FRAMEDONE isr\n"); |
| 1913 | } |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1914 | } |
| 1915 | |
| 1916 | static void _enable_digit_out(bool enable) |
| 1917 | { |
| 1918 | REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1); |
| 1919 | } |
| 1920 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 1921 | static void dispc_mgr_enable_digit_out(bool enable) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1922 | { |
| 1923 | struct completion frame_done_completion; |
Tomi Valkeinen | e82b090 | 2011-08-31 14:42:49 +0300 | [diff] [blame] | 1924 | enum dss_hdmi_venc_clk_source_select src; |
| 1925 | int r, i; |
| 1926 | u32 irq_mask; |
| 1927 | int num_irqs; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1928 | |
Tomi Valkeinen | e6d80f9 | 2011-05-19 14:12:26 +0300 | [diff] [blame] | 1929 | if (REG_GET(DISPC_CONTROL, 1, 1) == enable) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1930 | return; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1931 | |
Tomi Valkeinen | e82b090 | 2011-08-31 14:42:49 +0300 | [diff] [blame] | 1932 | src = dss_get_hdmi_venc_clk_source(); |
| 1933 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1934 | if (enable) { |
| 1935 | unsigned long flags; |
| 1936 | /* When we enable digit output, we'll get an extra digit |
| 1937 | * sync lost interrupt, that we need to ignore */ |
| 1938 | spin_lock_irqsave(&dispc.irq_lock, flags); |
| 1939 | dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT; |
| 1940 | _omap_dispc_set_irqs(); |
| 1941 | spin_unlock_irqrestore(&dispc.irq_lock, flags); |
| 1942 | } |
| 1943 | |
| 1944 | /* When we disable digit output, we need to wait until fields are done. |
| 1945 | * Otherwise the DSS is still working, and turning off the clocks |
| 1946 | * prevents DSS from going to OFF mode. And when enabling, we need to |
| 1947 | * wait for the extra sync losts */ |
| 1948 | init_completion(&frame_done_completion); |
| 1949 | |
Tomi Valkeinen | e82b090 | 2011-08-31 14:42:49 +0300 | [diff] [blame] | 1950 | if (src == DSS_HDMI_M_PCLK && enable == false) { |
| 1951 | irq_mask = DISPC_IRQ_FRAMEDONETV; |
| 1952 | num_irqs = 1; |
| 1953 | } else { |
| 1954 | irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD; |
| 1955 | /* XXX I understand from TRM that we should only wait for the |
| 1956 | * current field to complete. But it seems we have to wait for |
| 1957 | * both fields */ |
| 1958 | num_irqs = 2; |
| 1959 | } |
| 1960 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1961 | r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion, |
Tomi Valkeinen | e82b090 | 2011-08-31 14:42:49 +0300 | [diff] [blame] | 1962 | irq_mask); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1963 | if (r) |
Tomi Valkeinen | e82b090 | 2011-08-31 14:42:49 +0300 | [diff] [blame] | 1964 | DSSERR("failed to register %x isr\n", irq_mask); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1965 | |
| 1966 | _enable_digit_out(enable); |
| 1967 | |
Tomi Valkeinen | e82b090 | 2011-08-31 14:42:49 +0300 | [diff] [blame] | 1968 | for (i = 0; i < num_irqs; ++i) { |
| 1969 | if (!wait_for_completion_timeout(&frame_done_completion, |
| 1970 | msecs_to_jiffies(100))) |
| 1971 | DSSERR("timeout waiting for digit out to %s\n", |
| 1972 | enable ? "start" : "stop"); |
| 1973 | } |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1974 | |
Tomi Valkeinen | e82b090 | 2011-08-31 14:42:49 +0300 | [diff] [blame] | 1975 | r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion, |
| 1976 | irq_mask); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1977 | if (r) |
Tomi Valkeinen | e82b090 | 2011-08-31 14:42:49 +0300 | [diff] [blame] | 1978 | DSSERR("failed to unregister %x isr\n", irq_mask); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1979 | |
| 1980 | if (enable) { |
| 1981 | unsigned long flags; |
| 1982 | spin_lock_irqsave(&dispc.irq_lock, flags); |
Tomi Valkeinen | e82b090 | 2011-08-31 14:42:49 +0300 | [diff] [blame] | 1983 | dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1984 | dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT); |
| 1985 | _omap_dispc_set_irqs(); |
| 1986 | spin_unlock_irqrestore(&dispc.irq_lock, flags); |
| 1987 | } |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 1988 | } |
| 1989 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 1990 | bool dispc_mgr_is_enabled(enum omap_channel channel) |
Tomi Valkeinen | a2faee8 | 2010-01-08 17:14:53 +0200 | [diff] [blame] | 1991 | { |
| 1992 | if (channel == OMAP_DSS_CHANNEL_LCD) |
| 1993 | return !!REG_GET(DISPC_CONTROL, 0, 0); |
| 1994 | else if (channel == OMAP_DSS_CHANNEL_DIGIT) |
| 1995 | return !!REG_GET(DISPC_CONTROL, 1, 1); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 1996 | else if (channel == OMAP_DSS_CHANNEL_LCD2) |
| 1997 | return !!REG_GET(DISPC_CONTROL2, 0, 0); |
Tomi Valkeinen | a2faee8 | 2010-01-08 17:14:53 +0200 | [diff] [blame] | 1998 | else |
| 1999 | BUG(); |
| 2000 | } |
| 2001 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2002 | void dispc_mgr_enable(enum omap_channel channel, bool enable) |
Tomi Valkeinen | a2faee8 | 2010-01-08 17:14:53 +0200 | [diff] [blame] | 2003 | { |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2004 | if (channel == OMAP_DSS_CHANNEL_LCD || |
| 2005 | channel == OMAP_DSS_CHANNEL_LCD2) |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2006 | dispc_mgr_enable_lcd_out(channel, enable); |
Tomi Valkeinen | a2faee8 | 2010-01-08 17:14:53 +0200 | [diff] [blame] | 2007 | else if (channel == OMAP_DSS_CHANNEL_DIGIT) |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2008 | dispc_mgr_enable_digit_out(enable); |
Tomi Valkeinen | a2faee8 | 2010-01-08 17:14:53 +0200 | [diff] [blame] | 2009 | else |
| 2010 | BUG(); |
| 2011 | } |
| 2012 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2013 | void dispc_lcd_enable_signal_polarity(bool act_high) |
| 2014 | { |
Archit Taneja | 6ced40b | 2010-12-02 11:27:13 +0000 | [diff] [blame] | 2015 | if (!dss_has_feature(FEAT_LCDENABLEPOL)) |
| 2016 | return; |
| 2017 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2018 | REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2019 | } |
| 2020 | |
| 2021 | void dispc_lcd_enable_signal(bool enable) |
| 2022 | { |
Archit Taneja | 6ced40b | 2010-12-02 11:27:13 +0000 | [diff] [blame] | 2023 | if (!dss_has_feature(FEAT_LCDENABLESIGNAL)) |
| 2024 | return; |
| 2025 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2026 | REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2027 | } |
| 2028 | |
| 2029 | void dispc_pck_free_enable(bool enable) |
| 2030 | { |
Archit Taneja | 6ced40b | 2010-12-02 11:27:13 +0000 | [diff] [blame] | 2031 | if (!dss_has_feature(FEAT_PCKFREEENABLE)) |
| 2032 | return; |
| 2033 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2034 | REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2035 | } |
| 2036 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2037 | void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2038 | { |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2039 | if (channel == OMAP_DSS_CHANNEL_LCD2) |
| 2040 | REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16); |
| 2041 | else |
| 2042 | REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2043 | } |
| 2044 | |
| 2045 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2046 | void dispc_mgr_set_lcd_display_type(enum omap_channel channel, |
Sumit Semwal | 64ba4f7 | 2010-12-02 11:27:10 +0000 | [diff] [blame] | 2047 | enum omap_lcd_display_type type) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2048 | { |
| 2049 | int mode; |
| 2050 | |
| 2051 | switch (type) { |
| 2052 | case OMAP_DSS_LCD_DISPLAY_STN: |
| 2053 | mode = 0; |
| 2054 | break; |
| 2055 | |
| 2056 | case OMAP_DSS_LCD_DISPLAY_TFT: |
| 2057 | mode = 1; |
| 2058 | break; |
| 2059 | |
| 2060 | default: |
| 2061 | BUG(); |
| 2062 | return; |
| 2063 | } |
| 2064 | |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2065 | if (channel == OMAP_DSS_CHANNEL_LCD2) |
| 2066 | REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3); |
| 2067 | else |
| 2068 | REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2069 | } |
| 2070 | |
| 2071 | void dispc_set_loadmode(enum omap_dss_load_mode mode) |
| 2072 | { |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2073 | REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2074 | } |
| 2075 | |
| 2076 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2077 | void dispc_mgr_set_default_color(enum omap_channel channel, u32 color) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2078 | { |
Sumit Semwal | 8613b00 | 2010-12-02 11:27:09 +0000 | [diff] [blame] | 2079 | dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2080 | } |
| 2081 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2082 | u32 dispc_mgr_get_default_color(enum omap_channel channel) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2083 | { |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2084 | u32 l; |
| 2085 | |
| 2086 | BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT && |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2087 | channel != OMAP_DSS_CHANNEL_LCD && |
| 2088 | channel != OMAP_DSS_CHANNEL_LCD2); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2089 | |
Sumit Semwal | 8613b00 | 2010-12-02 11:27:09 +0000 | [diff] [blame] | 2090 | l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel)); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2091 | |
| 2092 | return l; |
| 2093 | } |
| 2094 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2095 | void dispc_mgr_set_trans_key(enum omap_channel ch, |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2096 | enum omap_dss_trans_key_type type, |
| 2097 | u32 trans_key) |
| 2098 | { |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2099 | if (ch == OMAP_DSS_CHANNEL_LCD) |
| 2100 | REG_FLD_MOD(DISPC_CONFIG, type, 11, 11); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2101 | else if (ch == OMAP_DSS_CHANNEL_DIGIT) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2102 | REG_FLD_MOD(DISPC_CONFIG, type, 13, 13); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2103 | else /* OMAP_DSS_CHANNEL_LCD2 */ |
| 2104 | REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2105 | |
Sumit Semwal | 8613b00 | 2010-12-02 11:27:09 +0000 | [diff] [blame] | 2106 | dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2107 | } |
| 2108 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2109 | void dispc_mgr_get_trans_key(enum omap_channel ch, |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2110 | enum omap_dss_trans_key_type *type, |
| 2111 | u32 *trans_key) |
| 2112 | { |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2113 | if (type) { |
| 2114 | if (ch == OMAP_DSS_CHANNEL_LCD) |
| 2115 | *type = REG_GET(DISPC_CONFIG, 11, 11); |
| 2116 | else if (ch == OMAP_DSS_CHANNEL_DIGIT) |
| 2117 | *type = REG_GET(DISPC_CONFIG, 13, 13); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2118 | else if (ch == OMAP_DSS_CHANNEL_LCD2) |
| 2119 | *type = REG_GET(DISPC_CONFIG2, 11, 11); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2120 | else |
| 2121 | BUG(); |
| 2122 | } |
| 2123 | |
| 2124 | if (trans_key) |
Sumit Semwal | 8613b00 | 2010-12-02 11:27:09 +0000 | [diff] [blame] | 2125 | *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch)); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2126 | } |
| 2127 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2128 | void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2129 | { |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2130 | if (ch == OMAP_DSS_CHANNEL_LCD) |
| 2131 | REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2132 | else if (ch == OMAP_DSS_CHANNEL_DIGIT) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2133 | REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2134 | else /* OMAP_DSS_CHANNEL_LCD2 */ |
| 2135 | REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2136 | } |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2137 | void dispc_mgr_enable_alpha_blending(enum omap_channel ch, bool enable) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2138 | { |
Archit Taneja | a0acb55 | 2010-09-15 19:20:00 +0530 | [diff] [blame] | 2139 | if (!dss_has_feature(FEAT_GLOBAL_ALPHA)) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2140 | return; |
| 2141 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2142 | if (ch == OMAP_DSS_CHANNEL_LCD) |
| 2143 | REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2144 | else if (ch == OMAP_DSS_CHANNEL_DIGIT) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2145 | REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2146 | else /* OMAP_DSS_CHANNEL_LCD2 */ |
| 2147 | REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2148 | } |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2149 | bool dispc_mgr_alpha_blending_enabled(enum omap_channel ch) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2150 | { |
| 2151 | bool enabled; |
| 2152 | |
Archit Taneja | a0acb55 | 2010-09-15 19:20:00 +0530 | [diff] [blame] | 2153 | if (!dss_has_feature(FEAT_GLOBAL_ALPHA)) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2154 | return false; |
| 2155 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2156 | if (ch == OMAP_DSS_CHANNEL_LCD) |
| 2157 | enabled = REG_GET(DISPC_CONFIG, 18, 18); |
| 2158 | else if (ch == OMAP_DSS_CHANNEL_DIGIT) |
Archit Taneja | 712247a | 2010-11-08 12:56:21 +0100 | [diff] [blame] | 2159 | enabled = REG_GET(DISPC_CONFIG, 19, 19); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2160 | else if (ch == OMAP_DSS_CHANNEL_LCD2) |
| 2161 | enabled = REG_GET(DISPC_CONFIG2, 18, 18); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2162 | else |
| 2163 | BUG(); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2164 | |
| 2165 | return enabled; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2166 | } |
| 2167 | |
| 2168 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2169 | bool dispc_mgr_trans_key_enabled(enum omap_channel ch) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2170 | { |
| 2171 | bool enabled; |
| 2172 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2173 | if (ch == OMAP_DSS_CHANNEL_LCD) |
| 2174 | enabled = REG_GET(DISPC_CONFIG, 10, 10); |
| 2175 | else if (ch == OMAP_DSS_CHANNEL_DIGIT) |
| 2176 | enabled = REG_GET(DISPC_CONFIG, 12, 12); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2177 | else if (ch == OMAP_DSS_CHANNEL_LCD2) |
| 2178 | enabled = REG_GET(DISPC_CONFIG2, 10, 10); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2179 | else |
| 2180 | BUG(); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2181 | |
| 2182 | return enabled; |
| 2183 | } |
| 2184 | |
| 2185 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2186 | void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2187 | { |
| 2188 | int code; |
| 2189 | |
| 2190 | switch (data_lines) { |
| 2191 | case 12: |
| 2192 | code = 0; |
| 2193 | break; |
| 2194 | case 16: |
| 2195 | code = 1; |
| 2196 | break; |
| 2197 | case 18: |
| 2198 | code = 2; |
| 2199 | break; |
| 2200 | case 24: |
| 2201 | code = 3; |
| 2202 | break; |
| 2203 | default: |
| 2204 | BUG(); |
| 2205 | return; |
| 2206 | } |
| 2207 | |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2208 | if (channel == OMAP_DSS_CHANNEL_LCD2) |
| 2209 | REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8); |
| 2210 | else |
| 2211 | REG_FLD_MOD(DISPC_CONTROL, code, 9, 8); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2212 | } |
| 2213 | |
Archit Taneja | 569969d | 2011-08-22 17:41:57 +0530 | [diff] [blame] | 2214 | void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2215 | { |
| 2216 | u32 l; |
Archit Taneja | 569969d | 2011-08-22 17:41:57 +0530 | [diff] [blame] | 2217 | int gpout0, gpout1; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2218 | |
| 2219 | switch (mode) { |
Archit Taneja | 569969d | 2011-08-22 17:41:57 +0530 | [diff] [blame] | 2220 | case DSS_IO_PAD_MODE_RESET: |
| 2221 | gpout0 = 0; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2222 | gpout1 = 0; |
| 2223 | break; |
Archit Taneja | 569969d | 2011-08-22 17:41:57 +0530 | [diff] [blame] | 2224 | case DSS_IO_PAD_MODE_RFBI: |
| 2225 | gpout0 = 1; |
| 2226 | gpout1 = 0; |
| 2227 | break; |
| 2228 | case DSS_IO_PAD_MODE_BYPASS: |
| 2229 | gpout0 = 1; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2230 | gpout1 = 1; |
| 2231 | break; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2232 | default: |
| 2233 | BUG(); |
| 2234 | return; |
| 2235 | } |
| 2236 | |
Archit Taneja | 569969d | 2011-08-22 17:41:57 +0530 | [diff] [blame] | 2237 | l = dispc_read_reg(DISPC_CONTROL); |
| 2238 | l = FLD_MOD(l, gpout0, 15, 15); |
| 2239 | l = FLD_MOD(l, gpout1, 16, 16); |
| 2240 | dispc_write_reg(DISPC_CONTROL, l); |
| 2241 | } |
| 2242 | |
| 2243 | void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable) |
| 2244 | { |
| 2245 | if (channel == OMAP_DSS_CHANNEL_LCD2) |
| 2246 | REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11); |
| 2247 | else |
| 2248 | REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2249 | } |
| 2250 | |
| 2251 | static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp, |
| 2252 | int vsw, int vfp, int vbp) |
| 2253 | { |
| 2254 | if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) { |
| 2255 | if (hsw < 1 || hsw > 64 || |
| 2256 | hfp < 1 || hfp > 256 || |
| 2257 | hbp < 1 || hbp > 256 || |
| 2258 | vsw < 1 || vsw > 64 || |
| 2259 | vfp < 0 || vfp > 255 || |
| 2260 | vbp < 0 || vbp > 255) |
| 2261 | return false; |
| 2262 | } else { |
| 2263 | if (hsw < 1 || hsw > 256 || |
| 2264 | hfp < 1 || hfp > 4096 || |
| 2265 | hbp < 1 || hbp > 4096 || |
| 2266 | vsw < 1 || vsw > 256 || |
| 2267 | vfp < 0 || vfp > 4095 || |
| 2268 | vbp < 0 || vbp > 4095) |
| 2269 | return false; |
| 2270 | } |
| 2271 | |
| 2272 | return true; |
| 2273 | } |
| 2274 | |
| 2275 | bool dispc_lcd_timings_ok(struct omap_video_timings *timings) |
| 2276 | { |
| 2277 | return _dispc_lcd_timings_ok(timings->hsw, timings->hfp, |
| 2278 | timings->hbp, timings->vsw, |
| 2279 | timings->vfp, timings->vbp); |
| 2280 | } |
| 2281 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2282 | static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw, |
Sumit Semwal | 64ba4f7 | 2010-12-02 11:27:10 +0000 | [diff] [blame] | 2283 | int hfp, int hbp, int vsw, int vfp, int vbp) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2284 | { |
| 2285 | u32 timing_h, timing_v; |
| 2286 | |
| 2287 | if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) { |
| 2288 | timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) | |
| 2289 | FLD_VAL(hbp-1, 27, 20); |
| 2290 | |
| 2291 | timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) | |
| 2292 | FLD_VAL(vbp, 27, 20); |
| 2293 | } else { |
| 2294 | timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) | |
| 2295 | FLD_VAL(hbp-1, 31, 20); |
| 2296 | |
| 2297 | timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) | |
| 2298 | FLD_VAL(vbp, 31, 20); |
| 2299 | } |
| 2300 | |
Sumit Semwal | 64ba4f7 | 2010-12-02 11:27:10 +0000 | [diff] [blame] | 2301 | dispc_write_reg(DISPC_TIMING_H(channel), timing_h); |
| 2302 | dispc_write_reg(DISPC_TIMING_V(channel), timing_v); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2303 | } |
| 2304 | |
| 2305 | /* change name to mode? */ |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2306 | void dispc_mgr_set_lcd_timings(enum omap_channel channel, |
Sumit Semwal | 64ba4f7 | 2010-12-02 11:27:10 +0000 | [diff] [blame] | 2307 | struct omap_video_timings *timings) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2308 | { |
| 2309 | unsigned xtot, ytot; |
| 2310 | unsigned long ht, vt; |
| 2311 | |
| 2312 | if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp, |
| 2313 | timings->hbp, timings->vsw, |
| 2314 | timings->vfp, timings->vbp)) |
| 2315 | BUG(); |
| 2316 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2317 | _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp, |
Sumit Semwal | 64ba4f7 | 2010-12-02 11:27:10 +0000 | [diff] [blame] | 2318 | timings->hbp, timings->vsw, timings->vfp, |
| 2319 | timings->vbp); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2320 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2321 | dispc_mgr_set_lcd_size(channel, timings->x_res, timings->y_res); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2322 | |
| 2323 | xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp; |
| 2324 | ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp; |
| 2325 | |
| 2326 | ht = (timings->pixel_clock * 1000) / xtot; |
| 2327 | vt = (timings->pixel_clock * 1000) / xtot / ytot; |
| 2328 | |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2329 | DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res, |
| 2330 | timings->y_res); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2331 | DSSDBG("pck %u\n", timings->pixel_clock); |
| 2332 | DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n", |
| 2333 | timings->hsw, timings->hfp, timings->hbp, |
| 2334 | timings->vsw, timings->vfp, timings->vbp); |
| 2335 | |
| 2336 | DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt); |
| 2337 | } |
| 2338 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2339 | static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div, |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 2340 | u16 pck_div) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2341 | { |
| 2342 | BUG_ON(lck_div < 1); |
Tomi Valkeinen | 9eaaf20 | 2011-08-29 15:56:04 +0300 | [diff] [blame] | 2343 | BUG_ON(pck_div < 1); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2344 | |
Murthy, Raghuveer | ce7fa5e | 2011-03-03 09:27:59 -0600 | [diff] [blame] | 2345 | dispc_write_reg(DISPC_DIVISORo(channel), |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2346 | FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0)); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2347 | } |
| 2348 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2349 | static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div, |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2350 | int *pck_div) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2351 | { |
| 2352 | u32 l; |
Murthy, Raghuveer | ce7fa5e | 2011-03-03 09:27:59 -0600 | [diff] [blame] | 2353 | l = dispc_read_reg(DISPC_DIVISORo(channel)); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2354 | *lck_div = FLD_GET(l, 23, 16); |
| 2355 | *pck_div = FLD_GET(l, 7, 0); |
| 2356 | } |
| 2357 | |
| 2358 | unsigned long dispc_fclk_rate(void) |
| 2359 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2360 | struct platform_device *dsidev; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2361 | unsigned long r = 0; |
| 2362 | |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 2363 | switch (dss_get_dispc_clk_source()) { |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 2364 | case OMAP_DSS_CLK_SRC_FCK: |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 2365 | r = clk_get_rate(dispc.dss_clk); |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 2366 | break; |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 2367 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2368 | dsidev = dsi_get_dsidev_from_id(0); |
| 2369 | r = dsi_get_pll_hsdiv_dispc_rate(dsidev); |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 2370 | break; |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 2371 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: |
| 2372 | dsidev = dsi_get_dsidev_from_id(1); |
| 2373 | r = dsi_get_pll_hsdiv_dispc_rate(dsidev); |
| 2374 | break; |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 2375 | default: |
| 2376 | BUG(); |
| 2377 | } |
| 2378 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2379 | return r; |
| 2380 | } |
| 2381 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2382 | unsigned long dispc_mgr_lclk_rate(enum omap_channel channel) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2383 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2384 | struct platform_device *dsidev; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2385 | int lcd; |
| 2386 | unsigned long r; |
| 2387 | u32 l; |
| 2388 | |
Murthy, Raghuveer | ce7fa5e | 2011-03-03 09:27:59 -0600 | [diff] [blame] | 2389 | l = dispc_read_reg(DISPC_DIVISORo(channel)); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2390 | |
| 2391 | lcd = FLD_GET(l, 23, 16); |
| 2392 | |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 2393 | switch (dss_get_lcd_clk_source(channel)) { |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 2394 | case OMAP_DSS_CLK_SRC_FCK: |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 2395 | r = clk_get_rate(dispc.dss_clk); |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 2396 | break; |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 2397 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2398 | dsidev = dsi_get_dsidev_from_id(0); |
| 2399 | r = dsi_get_pll_hsdiv_dispc_rate(dsidev); |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 2400 | break; |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 2401 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: |
| 2402 | dsidev = dsi_get_dsidev_from_id(1); |
| 2403 | r = dsi_get_pll_hsdiv_dispc_rate(dsidev); |
| 2404 | break; |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 2405 | default: |
| 2406 | BUG(); |
| 2407 | } |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2408 | |
| 2409 | return r / lcd; |
| 2410 | } |
| 2411 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2412 | unsigned long dispc_mgr_pclk_rate(enum omap_channel channel) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2413 | { |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 2414 | int pcd; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2415 | unsigned long r; |
| 2416 | u32 l; |
| 2417 | |
Murthy, Raghuveer | ce7fa5e | 2011-03-03 09:27:59 -0600 | [diff] [blame] | 2418 | l = dispc_read_reg(DISPC_DIVISORo(channel)); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2419 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2420 | pcd = FLD_GET(l, 7, 0); |
| 2421 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2422 | r = dispc_mgr_lclk_rate(channel); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2423 | |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 2424 | return r / pcd; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2425 | } |
| 2426 | |
| 2427 | void dispc_dump_clocks(struct seq_file *s) |
| 2428 | { |
| 2429 | int lcd, pcd; |
Murthy, Raghuveer | 0cf35df | 2011-03-03 09:28:00 -0600 | [diff] [blame] | 2430 | u32 l; |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 2431 | enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source(); |
| 2432 | enum omap_dss_clk_source lcd_clk_src; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2433 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 2434 | if (dispc_runtime_get()) |
| 2435 | return; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2436 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2437 | seq_printf(s, "- DISPC -\n"); |
| 2438 | |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 2439 | seq_printf(s, "dispc fclk source = %s (%s)\n", |
| 2440 | dss_get_generic_clk_source_name(dispc_clk_src), |
| 2441 | dss_feat_get_clk_source_name(dispc_clk_src)); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2442 | |
| 2443 | seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate()); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2444 | |
Murthy, Raghuveer | 0cf35df | 2011-03-03 09:28:00 -0600 | [diff] [blame] | 2445 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) { |
| 2446 | seq_printf(s, "- DISPC-CORE-CLK -\n"); |
| 2447 | l = dispc_read_reg(DISPC_DIVISOR); |
| 2448 | lcd = FLD_GET(l, 23, 16); |
| 2449 | |
| 2450 | seq_printf(s, "lck\t\t%-16lulck div\t%u\n", |
| 2451 | (dispc_fclk_rate()/lcd), lcd); |
| 2452 | } |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2453 | seq_printf(s, "- LCD1 -\n"); |
| 2454 | |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 2455 | lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD); |
| 2456 | |
| 2457 | seq_printf(s, "lcd1_clk source = %s (%s)\n", |
| 2458 | dss_get_generic_clk_source_name(lcd_clk_src), |
| 2459 | dss_feat_get_clk_source_name(lcd_clk_src)); |
| 2460 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2461 | dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2462 | |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 2463 | seq_printf(s, "lck\t\t%-16lulck div\t%u\n", |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2464 | dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd); |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 2465 | seq_printf(s, "pck\t\t%-16lupck div\t%u\n", |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2466 | dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2467 | if (dss_has_feature(FEAT_MGR_LCD2)) { |
| 2468 | seq_printf(s, "- LCD2 -\n"); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2469 | |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 2470 | lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2); |
| 2471 | |
| 2472 | seq_printf(s, "lcd2_clk source = %s (%s)\n", |
| 2473 | dss_get_generic_clk_source_name(lcd_clk_src), |
| 2474 | dss_feat_get_clk_source_name(lcd_clk_src)); |
| 2475 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2476 | dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2477 | |
| 2478 | seq_printf(s, "lck\t\t%-16lulck div\t%u\n", |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2479 | dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2480 | seq_printf(s, "pck\t\t%-16lupck div\t%u\n", |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2481 | dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2482 | } |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 2483 | |
| 2484 | dispc_runtime_put(); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2485 | } |
| 2486 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 2487 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 2488 | void dispc_dump_irqs(struct seq_file *s) |
| 2489 | { |
| 2490 | unsigned long flags; |
| 2491 | struct dispc_irq_stats stats; |
| 2492 | |
| 2493 | spin_lock_irqsave(&dispc.irq_stats_lock, flags); |
| 2494 | |
| 2495 | stats = dispc.irq_stats; |
| 2496 | memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats)); |
| 2497 | dispc.irq_stats.last_reset = jiffies; |
| 2498 | |
| 2499 | spin_unlock_irqrestore(&dispc.irq_stats_lock, flags); |
| 2500 | |
| 2501 | seq_printf(s, "period %u ms\n", |
| 2502 | jiffies_to_msecs(jiffies - stats.last_reset)); |
| 2503 | |
| 2504 | seq_printf(s, "irqs %d\n", stats.irq_count); |
| 2505 | #define PIS(x) \ |
| 2506 | seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]); |
| 2507 | |
| 2508 | PIS(FRAMEDONE); |
| 2509 | PIS(VSYNC); |
| 2510 | PIS(EVSYNC_EVEN); |
| 2511 | PIS(EVSYNC_ODD); |
| 2512 | PIS(ACBIAS_COUNT_STAT); |
| 2513 | PIS(PROG_LINE_NUM); |
| 2514 | PIS(GFX_FIFO_UNDERFLOW); |
| 2515 | PIS(GFX_END_WIN); |
| 2516 | PIS(PAL_GAMMA_MASK); |
| 2517 | PIS(OCP_ERR); |
| 2518 | PIS(VID1_FIFO_UNDERFLOW); |
| 2519 | PIS(VID1_END_WIN); |
| 2520 | PIS(VID2_FIFO_UNDERFLOW); |
| 2521 | PIS(VID2_END_WIN); |
| 2522 | PIS(SYNC_LOST); |
| 2523 | PIS(SYNC_LOST_DIGIT); |
| 2524 | PIS(WAKEUP); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2525 | if (dss_has_feature(FEAT_MGR_LCD2)) { |
| 2526 | PIS(FRAMEDONE2); |
| 2527 | PIS(VSYNC2); |
| 2528 | PIS(ACBIAS_COUNT_STAT2); |
| 2529 | PIS(SYNC_LOST2); |
| 2530 | } |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 2531 | #undef PIS |
| 2532 | } |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 2533 | #endif |
| 2534 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2535 | void dispc_dump_regs(struct seq_file *s) |
| 2536 | { |
Archit Taneja | 4dd2da1 | 2011-08-05 19:06:01 +0530 | [diff] [blame] | 2537 | int i, j; |
| 2538 | const char *mgr_names[] = { |
| 2539 | [OMAP_DSS_CHANNEL_LCD] = "LCD", |
| 2540 | [OMAP_DSS_CHANNEL_DIGIT] = "TV", |
| 2541 | [OMAP_DSS_CHANNEL_LCD2] = "LCD2", |
| 2542 | }; |
| 2543 | const char *ovl_names[] = { |
| 2544 | [OMAP_DSS_GFX] = "GFX", |
| 2545 | [OMAP_DSS_VIDEO1] = "VID1", |
| 2546 | [OMAP_DSS_VIDEO2] = "VID2", |
| 2547 | }; |
| 2548 | const char **p_names; |
| 2549 | |
Archit Taneja | 9b372c2 | 2011-05-06 11:45:49 +0530 | [diff] [blame] | 2550 | #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r)) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2551 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 2552 | if (dispc_runtime_get()) |
| 2553 | return; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2554 | |
Archit Taneja | 5010be8 | 2011-08-05 19:06:00 +0530 | [diff] [blame] | 2555 | /* DISPC common registers */ |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2556 | DUMPREG(DISPC_REVISION); |
| 2557 | DUMPREG(DISPC_SYSCONFIG); |
| 2558 | DUMPREG(DISPC_SYSSTATUS); |
| 2559 | DUMPREG(DISPC_IRQSTATUS); |
| 2560 | DUMPREG(DISPC_IRQENABLE); |
| 2561 | DUMPREG(DISPC_CONTROL); |
| 2562 | DUMPREG(DISPC_CONFIG); |
| 2563 | DUMPREG(DISPC_CAPABLE); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2564 | DUMPREG(DISPC_LINE_STATUS); |
| 2565 | DUMPREG(DISPC_LINE_NUMBER); |
Tomi Valkeinen | 332e9d7 | 2011-05-27 14:22:16 +0300 | [diff] [blame] | 2566 | if (dss_has_feature(FEAT_GLOBAL_ALPHA)) |
| 2567 | DUMPREG(DISPC_GLOBAL_ALPHA); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2568 | if (dss_has_feature(FEAT_MGR_LCD2)) { |
| 2569 | DUMPREG(DISPC_CONTROL2); |
| 2570 | DUMPREG(DISPC_CONFIG2); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2571 | } |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2572 | |
Archit Taneja | 5010be8 | 2011-08-05 19:06:00 +0530 | [diff] [blame] | 2573 | #undef DUMPREG |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2574 | |
Archit Taneja | 5010be8 | 2011-08-05 19:06:00 +0530 | [diff] [blame] | 2575 | #define DISPC_REG(i, name) name(i) |
Archit Taneja | 4dd2da1 | 2011-08-05 19:06:01 +0530 | [diff] [blame] | 2576 | #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \ |
| 2577 | 48 - strlen(#r) - strlen(p_names[i]), " ", \ |
Archit Taneja | 5010be8 | 2011-08-05 19:06:00 +0530 | [diff] [blame] | 2578 | dispc_read_reg(DISPC_REG(i, r))) |
| 2579 | |
Archit Taneja | 4dd2da1 | 2011-08-05 19:06:01 +0530 | [diff] [blame] | 2580 | p_names = mgr_names; |
Archit Taneja | 5010be8 | 2011-08-05 19:06:00 +0530 | [diff] [blame] | 2581 | |
Archit Taneja | 4dd2da1 | 2011-08-05 19:06:01 +0530 | [diff] [blame] | 2582 | /* DISPC channel specific registers */ |
| 2583 | for (i = 0; i < dss_feat_get_num_mgrs(); i++) { |
| 2584 | DUMPREG(i, DISPC_DEFAULT_COLOR); |
| 2585 | DUMPREG(i, DISPC_TRANS_COLOR); |
| 2586 | DUMPREG(i, DISPC_SIZE_MGR); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2587 | |
Archit Taneja | 4dd2da1 | 2011-08-05 19:06:01 +0530 | [diff] [blame] | 2588 | if (i == OMAP_DSS_CHANNEL_DIGIT) |
| 2589 | continue; |
Archit Taneja | 5010be8 | 2011-08-05 19:06:00 +0530 | [diff] [blame] | 2590 | |
Archit Taneja | 4dd2da1 | 2011-08-05 19:06:01 +0530 | [diff] [blame] | 2591 | DUMPREG(i, DISPC_DEFAULT_COLOR); |
| 2592 | DUMPREG(i, DISPC_TRANS_COLOR); |
| 2593 | DUMPREG(i, DISPC_TIMING_H); |
| 2594 | DUMPREG(i, DISPC_TIMING_V); |
| 2595 | DUMPREG(i, DISPC_POL_FREQ); |
| 2596 | DUMPREG(i, DISPC_DIVISORo); |
| 2597 | DUMPREG(i, DISPC_SIZE_MGR); |
Archit Taneja | 5010be8 | 2011-08-05 19:06:00 +0530 | [diff] [blame] | 2598 | |
Archit Taneja | 4dd2da1 | 2011-08-05 19:06:01 +0530 | [diff] [blame] | 2599 | DUMPREG(i, DISPC_DATA_CYCLE1); |
| 2600 | DUMPREG(i, DISPC_DATA_CYCLE2); |
| 2601 | DUMPREG(i, DISPC_DATA_CYCLE3); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2602 | |
Tomi Valkeinen | 332e9d7 | 2011-05-27 14:22:16 +0300 | [diff] [blame] | 2603 | if (dss_has_feature(FEAT_CPR)) { |
Archit Taneja | 4dd2da1 | 2011-08-05 19:06:01 +0530 | [diff] [blame] | 2604 | DUMPREG(i, DISPC_CPR_COEF_R); |
| 2605 | DUMPREG(i, DISPC_CPR_COEF_G); |
| 2606 | DUMPREG(i, DISPC_CPR_COEF_B); |
Tomi Valkeinen | 332e9d7 | 2011-05-27 14:22:16 +0300 | [diff] [blame] | 2607 | } |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2608 | } |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2609 | |
Archit Taneja | 4dd2da1 | 2011-08-05 19:06:01 +0530 | [diff] [blame] | 2610 | p_names = ovl_names; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2611 | |
Archit Taneja | 4dd2da1 | 2011-08-05 19:06:01 +0530 | [diff] [blame] | 2612 | for (i = 0; i < dss_feat_get_num_ovls(); i++) { |
| 2613 | DUMPREG(i, DISPC_OVL_BA0); |
| 2614 | DUMPREG(i, DISPC_OVL_BA1); |
| 2615 | DUMPREG(i, DISPC_OVL_POSITION); |
| 2616 | DUMPREG(i, DISPC_OVL_SIZE); |
| 2617 | DUMPREG(i, DISPC_OVL_ATTRIBUTES); |
| 2618 | DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD); |
| 2619 | DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS); |
| 2620 | DUMPREG(i, DISPC_OVL_ROW_INC); |
| 2621 | DUMPREG(i, DISPC_OVL_PIXEL_INC); |
| 2622 | if (dss_has_feature(FEAT_PRELOAD)) |
| 2623 | DUMPREG(i, DISPC_OVL_PRELOAD); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2624 | |
Archit Taneja | 4dd2da1 | 2011-08-05 19:06:01 +0530 | [diff] [blame] | 2625 | if (i == OMAP_DSS_GFX) { |
| 2626 | DUMPREG(i, DISPC_OVL_WINDOW_SKIP); |
| 2627 | DUMPREG(i, DISPC_OVL_TABLE_BA); |
| 2628 | continue; |
| 2629 | } |
| 2630 | |
| 2631 | DUMPREG(i, DISPC_OVL_FIR); |
| 2632 | DUMPREG(i, DISPC_OVL_PICTURE_SIZE); |
| 2633 | DUMPREG(i, DISPC_OVL_ACCU0); |
| 2634 | DUMPREG(i, DISPC_OVL_ACCU1); |
| 2635 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { |
| 2636 | DUMPREG(i, DISPC_OVL_BA0_UV); |
| 2637 | DUMPREG(i, DISPC_OVL_BA1_UV); |
| 2638 | DUMPREG(i, DISPC_OVL_FIR2); |
| 2639 | DUMPREG(i, DISPC_OVL_ACCU2_0); |
| 2640 | DUMPREG(i, DISPC_OVL_ACCU2_1); |
| 2641 | } |
| 2642 | if (dss_has_feature(FEAT_ATTR2)) |
| 2643 | DUMPREG(i, DISPC_OVL_ATTRIBUTES2); |
| 2644 | if (dss_has_feature(FEAT_PRELOAD)) |
| 2645 | DUMPREG(i, DISPC_OVL_PRELOAD); |
Archit Taneja | 5010be8 | 2011-08-05 19:06:00 +0530 | [diff] [blame] | 2646 | } |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2647 | |
Archit Taneja | 5010be8 | 2011-08-05 19:06:00 +0530 | [diff] [blame] | 2648 | #undef DISPC_REG |
| 2649 | #undef DUMPREG |
| 2650 | |
| 2651 | #define DISPC_REG(plane, name, i) name(plane, i) |
| 2652 | #define DUMPREG(plane, name, i) \ |
Archit Taneja | 4dd2da1 | 2011-08-05 19:06:01 +0530 | [diff] [blame] | 2653 | seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \ |
| 2654 | 46 - strlen(#name) - strlen(p_names[plane]), " ", \ |
Archit Taneja | 5010be8 | 2011-08-05 19:06:00 +0530 | [diff] [blame] | 2655 | dispc_read_reg(DISPC_REG(plane, name, i))) |
| 2656 | |
Archit Taneja | 4dd2da1 | 2011-08-05 19:06:01 +0530 | [diff] [blame] | 2657 | /* Video pipeline coefficient registers */ |
Archit Taneja | 5010be8 | 2011-08-05 19:06:00 +0530 | [diff] [blame] | 2658 | |
Archit Taneja | 4dd2da1 | 2011-08-05 19:06:01 +0530 | [diff] [blame] | 2659 | /* start from OMAP_DSS_VIDEO1 */ |
| 2660 | for (i = 1; i < dss_feat_get_num_ovls(); i++) { |
| 2661 | for (j = 0; j < 8; j++) |
| 2662 | DUMPREG(i, DISPC_OVL_FIR_COEF_H, j); |
Archit Taneja | 5010be8 | 2011-08-05 19:06:00 +0530 | [diff] [blame] | 2663 | |
Archit Taneja | 4dd2da1 | 2011-08-05 19:06:01 +0530 | [diff] [blame] | 2664 | for (j = 0; j < 8; j++) |
| 2665 | DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j); |
Archit Taneja | 5010be8 | 2011-08-05 19:06:00 +0530 | [diff] [blame] | 2666 | |
Archit Taneja | 4dd2da1 | 2011-08-05 19:06:01 +0530 | [diff] [blame] | 2667 | for (j = 0; j < 5; j++) |
| 2668 | DUMPREG(i, DISPC_OVL_CONV_COEF, j); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2669 | |
Archit Taneja | 4dd2da1 | 2011-08-05 19:06:01 +0530 | [diff] [blame] | 2670 | if (dss_has_feature(FEAT_FIR_COEF_V)) { |
| 2671 | for (j = 0; j < 8; j++) |
| 2672 | DUMPREG(i, DISPC_OVL_FIR_COEF_V, j); |
| 2673 | } |
Amber Jain | ab5ca07 | 2011-05-19 19:47:53 +0530 | [diff] [blame] | 2674 | |
Archit Taneja | 4dd2da1 | 2011-08-05 19:06:01 +0530 | [diff] [blame] | 2675 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { |
| 2676 | for (j = 0; j < 8; j++) |
| 2677 | DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j); |
Amber Jain | ab5ca07 | 2011-05-19 19:47:53 +0530 | [diff] [blame] | 2678 | |
Archit Taneja | 4dd2da1 | 2011-08-05 19:06:01 +0530 | [diff] [blame] | 2679 | for (j = 0; j < 8; j++) |
| 2680 | DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j); |
Amber Jain | ab5ca07 | 2011-05-19 19:47:53 +0530 | [diff] [blame] | 2681 | |
Archit Taneja | 4dd2da1 | 2011-08-05 19:06:01 +0530 | [diff] [blame] | 2682 | for (j = 0; j < 8; j++) |
| 2683 | DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j); |
| 2684 | } |
Tomi Valkeinen | 332e9d7 | 2011-05-27 14:22:16 +0300 | [diff] [blame] | 2685 | } |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2686 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 2687 | dispc_runtime_put(); |
Archit Taneja | 5010be8 | 2011-08-05 19:06:00 +0530 | [diff] [blame] | 2688 | |
| 2689 | #undef DISPC_REG |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2690 | #undef DUMPREG |
| 2691 | } |
| 2692 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2693 | static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff, |
| 2694 | bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, |
| 2695 | u8 acb) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2696 | { |
| 2697 | u32 l = 0; |
| 2698 | |
| 2699 | DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n", |
| 2700 | onoff, rf, ieo, ipc, ihs, ivs, acbi, acb); |
| 2701 | |
| 2702 | l |= FLD_VAL(onoff, 17, 17); |
| 2703 | l |= FLD_VAL(rf, 16, 16); |
| 2704 | l |= FLD_VAL(ieo, 15, 15); |
| 2705 | l |= FLD_VAL(ipc, 14, 14); |
| 2706 | l |= FLD_VAL(ihs, 13, 13); |
| 2707 | l |= FLD_VAL(ivs, 12, 12); |
| 2708 | l |= FLD_VAL(acbi, 11, 8); |
| 2709 | l |= FLD_VAL(acb, 7, 0); |
| 2710 | |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 2711 | dispc_write_reg(DISPC_POL_FREQ(channel), l); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2712 | } |
| 2713 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2714 | void dispc_mgr_set_pol_freq(enum omap_channel channel, |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 2715 | enum omap_panel_config config, u8 acbi, u8 acb) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2716 | { |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2717 | _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0, |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2718 | (config & OMAP_DSS_LCD_RF) != 0, |
| 2719 | (config & OMAP_DSS_LCD_IEO) != 0, |
| 2720 | (config & OMAP_DSS_LCD_IPC) != 0, |
| 2721 | (config & OMAP_DSS_LCD_IHS) != 0, |
| 2722 | (config & OMAP_DSS_LCD_IVS) != 0, |
| 2723 | acbi, acb); |
| 2724 | } |
| 2725 | |
| 2726 | /* with fck as input clock rate, find dispc dividers that produce req_pck */ |
| 2727 | void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck, |
| 2728 | struct dispc_clock_info *cinfo) |
| 2729 | { |
Tomi Valkeinen | 9eaaf20 | 2011-08-29 15:56:04 +0300 | [diff] [blame] | 2730 | u16 pcd_min, pcd_max; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2731 | unsigned long best_pck; |
| 2732 | u16 best_ld, cur_ld; |
| 2733 | u16 best_pd, cur_pd; |
| 2734 | |
Tomi Valkeinen | 9eaaf20 | 2011-08-29 15:56:04 +0300 | [diff] [blame] | 2735 | pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD); |
| 2736 | pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD); |
| 2737 | |
| 2738 | if (!is_tft) |
| 2739 | pcd_min = 3; |
| 2740 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2741 | best_pck = 0; |
| 2742 | best_ld = 0; |
| 2743 | best_pd = 0; |
| 2744 | |
| 2745 | for (cur_ld = 1; cur_ld <= 255; ++cur_ld) { |
| 2746 | unsigned long lck = fck / cur_ld; |
| 2747 | |
Tomi Valkeinen | 9eaaf20 | 2011-08-29 15:56:04 +0300 | [diff] [blame] | 2748 | for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) { |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2749 | unsigned long pck = lck / cur_pd; |
| 2750 | long old_delta = abs(best_pck - req_pck); |
| 2751 | long new_delta = abs(pck - req_pck); |
| 2752 | |
| 2753 | if (best_pck == 0 || new_delta < old_delta) { |
| 2754 | best_pck = pck; |
| 2755 | best_ld = cur_ld; |
| 2756 | best_pd = cur_pd; |
| 2757 | |
| 2758 | if (pck == req_pck) |
| 2759 | goto found; |
| 2760 | } |
| 2761 | |
| 2762 | if (pck < req_pck) |
| 2763 | break; |
| 2764 | } |
| 2765 | |
| 2766 | if (lck / pcd_min < req_pck) |
| 2767 | break; |
| 2768 | } |
| 2769 | |
| 2770 | found: |
| 2771 | cinfo->lck_div = best_ld; |
| 2772 | cinfo->pck_div = best_pd; |
| 2773 | cinfo->lck = fck / cinfo->lck_div; |
| 2774 | cinfo->pck = cinfo->lck / cinfo->pck_div; |
| 2775 | } |
| 2776 | |
| 2777 | /* calculate clock rates using dividers in cinfo */ |
| 2778 | int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, |
| 2779 | struct dispc_clock_info *cinfo) |
| 2780 | { |
| 2781 | if (cinfo->lck_div > 255 || cinfo->lck_div == 0) |
| 2782 | return -EINVAL; |
Tomi Valkeinen | 9eaaf20 | 2011-08-29 15:56:04 +0300 | [diff] [blame] | 2783 | if (cinfo->pck_div < 1 || cinfo->pck_div > 255) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2784 | return -EINVAL; |
| 2785 | |
| 2786 | cinfo->lck = dispc_fclk_rate / cinfo->lck_div; |
| 2787 | cinfo->pck = cinfo->lck / cinfo->pck_div; |
| 2788 | |
| 2789 | return 0; |
| 2790 | } |
| 2791 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2792 | int dispc_mgr_set_clock_div(enum omap_channel channel, |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 2793 | struct dispc_clock_info *cinfo) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2794 | { |
| 2795 | DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div); |
| 2796 | DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div); |
| 2797 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2798 | dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2799 | |
| 2800 | return 0; |
| 2801 | } |
| 2802 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 2803 | int dispc_mgr_get_clock_div(enum omap_channel channel, |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 2804 | struct dispc_clock_info *cinfo) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2805 | { |
| 2806 | unsigned long fck; |
| 2807 | |
| 2808 | fck = dispc_fclk_rate(); |
| 2809 | |
Murthy, Raghuveer | ce7fa5e | 2011-03-03 09:27:59 -0600 | [diff] [blame] | 2810 | cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16); |
| 2811 | cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2812 | |
| 2813 | cinfo->lck = fck / cinfo->lck_div; |
| 2814 | cinfo->pck = cinfo->lck / cinfo->pck_div; |
| 2815 | |
| 2816 | return 0; |
| 2817 | } |
| 2818 | |
| 2819 | /* dispc.irq_lock has to be locked by the caller */ |
| 2820 | static void _omap_dispc_set_irqs(void) |
| 2821 | { |
| 2822 | u32 mask; |
| 2823 | u32 old_mask; |
| 2824 | int i; |
| 2825 | struct omap_dispc_isr_data *isr_data; |
| 2826 | |
| 2827 | mask = dispc.irq_error_mask; |
| 2828 | |
| 2829 | for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { |
| 2830 | isr_data = &dispc.registered_isr[i]; |
| 2831 | |
| 2832 | if (isr_data->isr == NULL) |
| 2833 | continue; |
| 2834 | |
| 2835 | mask |= isr_data->mask; |
| 2836 | } |
| 2837 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2838 | old_mask = dispc_read_reg(DISPC_IRQENABLE); |
| 2839 | /* clear the irqstatus for newly enabled irqs */ |
| 2840 | dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask); |
| 2841 | |
| 2842 | dispc_write_reg(DISPC_IRQENABLE, mask); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2843 | } |
| 2844 | |
| 2845 | int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask) |
| 2846 | { |
| 2847 | int i; |
| 2848 | int ret; |
| 2849 | unsigned long flags; |
| 2850 | struct omap_dispc_isr_data *isr_data; |
| 2851 | |
| 2852 | if (isr == NULL) |
| 2853 | return -EINVAL; |
| 2854 | |
| 2855 | spin_lock_irqsave(&dispc.irq_lock, flags); |
| 2856 | |
| 2857 | /* check for duplicate entry */ |
| 2858 | for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { |
| 2859 | isr_data = &dispc.registered_isr[i]; |
| 2860 | if (isr_data->isr == isr && isr_data->arg == arg && |
| 2861 | isr_data->mask == mask) { |
| 2862 | ret = -EINVAL; |
| 2863 | goto err; |
| 2864 | } |
| 2865 | } |
| 2866 | |
| 2867 | isr_data = NULL; |
| 2868 | ret = -EBUSY; |
| 2869 | |
| 2870 | for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { |
| 2871 | isr_data = &dispc.registered_isr[i]; |
| 2872 | |
| 2873 | if (isr_data->isr != NULL) |
| 2874 | continue; |
| 2875 | |
| 2876 | isr_data->isr = isr; |
| 2877 | isr_data->arg = arg; |
| 2878 | isr_data->mask = mask; |
| 2879 | ret = 0; |
| 2880 | |
| 2881 | break; |
| 2882 | } |
| 2883 | |
Tomi Valkeinen | b9cb098 | 2011-03-04 18:19:54 +0200 | [diff] [blame] | 2884 | if (ret) |
| 2885 | goto err; |
| 2886 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2887 | _omap_dispc_set_irqs(); |
| 2888 | |
| 2889 | spin_unlock_irqrestore(&dispc.irq_lock, flags); |
| 2890 | |
| 2891 | return 0; |
| 2892 | err: |
| 2893 | spin_unlock_irqrestore(&dispc.irq_lock, flags); |
| 2894 | |
| 2895 | return ret; |
| 2896 | } |
| 2897 | EXPORT_SYMBOL(omap_dispc_register_isr); |
| 2898 | |
| 2899 | int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask) |
| 2900 | { |
| 2901 | int i; |
| 2902 | unsigned long flags; |
| 2903 | int ret = -EINVAL; |
| 2904 | struct omap_dispc_isr_data *isr_data; |
| 2905 | |
| 2906 | spin_lock_irqsave(&dispc.irq_lock, flags); |
| 2907 | |
| 2908 | for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { |
| 2909 | isr_data = &dispc.registered_isr[i]; |
| 2910 | if (isr_data->isr != isr || isr_data->arg != arg || |
| 2911 | isr_data->mask != mask) |
| 2912 | continue; |
| 2913 | |
| 2914 | /* found the correct isr */ |
| 2915 | |
| 2916 | isr_data->isr = NULL; |
| 2917 | isr_data->arg = NULL; |
| 2918 | isr_data->mask = 0; |
| 2919 | |
| 2920 | ret = 0; |
| 2921 | break; |
| 2922 | } |
| 2923 | |
| 2924 | if (ret == 0) |
| 2925 | _omap_dispc_set_irqs(); |
| 2926 | |
| 2927 | spin_unlock_irqrestore(&dispc.irq_lock, flags); |
| 2928 | |
| 2929 | return ret; |
| 2930 | } |
| 2931 | EXPORT_SYMBOL(omap_dispc_unregister_isr); |
| 2932 | |
| 2933 | #ifdef DEBUG |
| 2934 | static void print_irq_status(u32 status) |
| 2935 | { |
| 2936 | if ((status & dispc.irq_error_mask) == 0) |
| 2937 | return; |
| 2938 | |
| 2939 | printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status); |
| 2940 | |
| 2941 | #define PIS(x) \ |
| 2942 | if (status & DISPC_IRQ_##x) \ |
| 2943 | printk(#x " "); |
| 2944 | PIS(GFX_FIFO_UNDERFLOW); |
| 2945 | PIS(OCP_ERR); |
| 2946 | PIS(VID1_FIFO_UNDERFLOW); |
| 2947 | PIS(VID2_FIFO_UNDERFLOW); |
| 2948 | PIS(SYNC_LOST); |
| 2949 | PIS(SYNC_LOST_DIGIT); |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 2950 | if (dss_has_feature(FEAT_MGR_LCD2)) |
| 2951 | PIS(SYNC_LOST2); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2952 | #undef PIS |
| 2953 | |
| 2954 | printk("\n"); |
| 2955 | } |
| 2956 | #endif |
| 2957 | |
| 2958 | /* Called from dss.c. Note that we don't touch clocks here, |
| 2959 | * but we presume they are on because we got an IRQ. However, |
| 2960 | * an irq handler may turn the clocks off, so we may not have |
| 2961 | * clock later in the function. */ |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 2962 | static irqreturn_t omap_dispc_irq_handler(int irq, void *arg) |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2963 | { |
| 2964 | int i; |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 2965 | u32 irqstatus, irqenable; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2966 | u32 handledirqs = 0; |
| 2967 | u32 unhandled_errors; |
| 2968 | struct omap_dispc_isr_data *isr_data; |
| 2969 | struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS]; |
| 2970 | |
| 2971 | spin_lock(&dispc.irq_lock); |
| 2972 | |
| 2973 | irqstatus = dispc_read_reg(DISPC_IRQSTATUS); |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 2974 | irqenable = dispc_read_reg(DISPC_IRQENABLE); |
| 2975 | |
| 2976 | /* IRQ is not for us */ |
| 2977 | if (!(irqstatus & irqenable)) { |
| 2978 | spin_unlock(&dispc.irq_lock); |
| 2979 | return IRQ_NONE; |
| 2980 | } |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2981 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 2982 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 2983 | spin_lock(&dispc.irq_stats_lock); |
| 2984 | dispc.irq_stats.irq_count++; |
| 2985 | dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs); |
| 2986 | spin_unlock(&dispc.irq_stats_lock); |
| 2987 | #endif |
| 2988 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 2989 | #ifdef DEBUG |
| 2990 | if (dss_debug) |
| 2991 | print_irq_status(irqstatus); |
| 2992 | #endif |
| 2993 | /* Ack the interrupt. Do it here before clocks are possibly turned |
| 2994 | * off */ |
| 2995 | dispc_write_reg(DISPC_IRQSTATUS, irqstatus); |
| 2996 | /* flush posted write */ |
| 2997 | dispc_read_reg(DISPC_IRQSTATUS); |
| 2998 | |
| 2999 | /* make a copy and unlock, so that isrs can unregister |
| 3000 | * themselves */ |
| 3001 | memcpy(registered_isr, dispc.registered_isr, |
| 3002 | sizeof(registered_isr)); |
| 3003 | |
| 3004 | spin_unlock(&dispc.irq_lock); |
| 3005 | |
| 3006 | for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { |
| 3007 | isr_data = ®istered_isr[i]; |
| 3008 | |
| 3009 | if (!isr_data->isr) |
| 3010 | continue; |
| 3011 | |
| 3012 | if (isr_data->mask & irqstatus) { |
| 3013 | isr_data->isr(isr_data->arg, irqstatus); |
| 3014 | handledirqs |= isr_data->mask; |
| 3015 | } |
| 3016 | } |
| 3017 | |
| 3018 | spin_lock(&dispc.irq_lock); |
| 3019 | |
| 3020 | unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask; |
| 3021 | |
| 3022 | if (unhandled_errors) { |
| 3023 | dispc.error_irqs |= unhandled_errors; |
| 3024 | |
| 3025 | dispc.irq_error_mask &= ~unhandled_errors; |
| 3026 | _omap_dispc_set_irqs(); |
| 3027 | |
| 3028 | schedule_work(&dispc.error_work); |
| 3029 | } |
| 3030 | |
| 3031 | spin_unlock(&dispc.irq_lock); |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 3032 | |
| 3033 | return IRQ_HANDLED; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 3034 | } |
| 3035 | |
| 3036 | static void dispc_error_worker(struct work_struct *work) |
| 3037 | { |
| 3038 | int i; |
| 3039 | u32 errors; |
| 3040 | unsigned long flags; |
Tomi Valkeinen | fe3cc9d | 2011-08-15 11:51:50 +0300 | [diff] [blame] | 3041 | static const unsigned fifo_underflow_bits[] = { |
| 3042 | DISPC_IRQ_GFX_FIFO_UNDERFLOW, |
| 3043 | DISPC_IRQ_VID1_FIFO_UNDERFLOW, |
| 3044 | DISPC_IRQ_VID2_FIFO_UNDERFLOW, |
| 3045 | }; |
| 3046 | |
| 3047 | static const unsigned sync_lost_bits[] = { |
| 3048 | DISPC_IRQ_SYNC_LOST, |
| 3049 | DISPC_IRQ_SYNC_LOST_DIGIT, |
| 3050 | DISPC_IRQ_SYNC_LOST2, |
| 3051 | }; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 3052 | |
| 3053 | spin_lock_irqsave(&dispc.irq_lock, flags); |
| 3054 | errors = dispc.error_irqs; |
| 3055 | dispc.error_irqs = 0; |
| 3056 | spin_unlock_irqrestore(&dispc.irq_lock, flags); |
| 3057 | |
Dima Zavin | 13eae1f | 2011-06-27 10:31:05 -0700 | [diff] [blame] | 3058 | dispc_runtime_get(); |
| 3059 | |
Tomi Valkeinen | fe3cc9d | 2011-08-15 11:51:50 +0300 | [diff] [blame] | 3060 | for (i = 0; i < omap_dss_get_num_overlays(); ++i) { |
| 3061 | struct omap_overlay *ovl; |
| 3062 | unsigned bit; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 3063 | |
Tomi Valkeinen | fe3cc9d | 2011-08-15 11:51:50 +0300 | [diff] [blame] | 3064 | ovl = omap_dss_get_overlay(i); |
| 3065 | bit = fifo_underflow_bits[i]; |
| 3066 | |
| 3067 | if (bit & errors) { |
| 3068 | DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n", |
| 3069 | ovl->name); |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 3070 | dispc_ovl_enable(ovl->id, false); |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 3071 | dispc_mgr_go(ovl->manager->id); |
Tomi Valkeinen | fe3cc9d | 2011-08-15 11:51:50 +0300 | [diff] [blame] | 3072 | mdelay(50); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 3073 | } |
| 3074 | } |
| 3075 | |
Tomi Valkeinen | fe3cc9d | 2011-08-15 11:51:50 +0300 | [diff] [blame] | 3076 | for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) { |
| 3077 | struct omap_overlay_manager *mgr; |
| 3078 | unsigned bit; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 3079 | |
Tomi Valkeinen | fe3cc9d | 2011-08-15 11:51:50 +0300 | [diff] [blame] | 3080 | mgr = omap_dss_get_overlay_manager(i); |
| 3081 | bit = sync_lost_bits[i]; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 3082 | |
Tomi Valkeinen | fe3cc9d | 2011-08-15 11:51:50 +0300 | [diff] [blame] | 3083 | if (bit & errors) { |
| 3084 | struct omap_dss_device *dssdev = mgr->device; |
| 3085 | bool enable; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 3086 | |
Tomi Valkeinen | fe3cc9d | 2011-08-15 11:51:50 +0300 | [diff] [blame] | 3087 | DSSERR("SYNC_LOST on channel %s, restarting the output " |
| 3088 | "with video overlays disabled\n", |
| 3089 | mgr->name); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 3090 | |
Tomi Valkeinen | fe3cc9d | 2011-08-15 11:51:50 +0300 | [diff] [blame] | 3091 | enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE; |
| 3092 | dssdev->driver->disable(dssdev); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 3093 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 3094 | for (i = 0; i < omap_dss_get_num_overlays(); ++i) { |
| 3095 | struct omap_overlay *ovl; |
| 3096 | ovl = omap_dss_get_overlay(i); |
| 3097 | |
Tomi Valkeinen | fe3cc9d | 2011-08-15 11:51:50 +0300 | [diff] [blame] | 3098 | if (ovl->id != OMAP_DSS_GFX && |
| 3099 | ovl->manager == mgr) |
Tomi Valkeinen | f0e5caa | 2011-08-16 13:25:00 +0300 | [diff] [blame] | 3100 | dispc_ovl_enable(ovl->id, false); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 3101 | } |
| 3102 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 3103 | dispc_mgr_go(mgr->id); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 3104 | mdelay(50); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 3105 | |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 3106 | if (enable) |
| 3107 | dssdev->driver->enable(dssdev); |
| 3108 | } |
| 3109 | } |
| 3110 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 3111 | if (errors & DISPC_IRQ_OCP_ERR) { |
| 3112 | DSSERR("OCP_ERR\n"); |
| 3113 | for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) { |
| 3114 | struct omap_overlay_manager *mgr; |
| 3115 | mgr = omap_dss_get_overlay_manager(i); |
Tomi Valkeinen | 4a9e78a | 2011-08-15 11:22:21 +0300 | [diff] [blame] | 3116 | mgr->device->driver->disable(mgr->device); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 3117 | } |
| 3118 | } |
| 3119 | |
| 3120 | spin_lock_irqsave(&dispc.irq_lock, flags); |
| 3121 | dispc.irq_error_mask |= errors; |
| 3122 | _omap_dispc_set_irqs(); |
| 3123 | spin_unlock_irqrestore(&dispc.irq_lock, flags); |
Dima Zavin | 13eae1f | 2011-06-27 10:31:05 -0700 | [diff] [blame] | 3124 | |
| 3125 | dispc_runtime_put(); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 3126 | } |
| 3127 | |
| 3128 | int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout) |
| 3129 | { |
| 3130 | void dispc_irq_wait_handler(void *data, u32 mask) |
| 3131 | { |
| 3132 | complete((struct completion *)data); |
| 3133 | } |
| 3134 | |
| 3135 | int r; |
| 3136 | DECLARE_COMPLETION_ONSTACK(completion); |
| 3137 | |
| 3138 | r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion, |
| 3139 | irqmask); |
| 3140 | |
| 3141 | if (r) |
| 3142 | return r; |
| 3143 | |
| 3144 | timeout = wait_for_completion_timeout(&completion, timeout); |
| 3145 | |
| 3146 | omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask); |
| 3147 | |
| 3148 | if (timeout == 0) |
| 3149 | return -ETIMEDOUT; |
| 3150 | |
| 3151 | if (timeout == -ERESTARTSYS) |
| 3152 | return -ERESTARTSYS; |
| 3153 | |
| 3154 | return 0; |
| 3155 | } |
| 3156 | |
| 3157 | int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask, |
| 3158 | unsigned long timeout) |
| 3159 | { |
| 3160 | void dispc_irq_wait_handler(void *data, u32 mask) |
| 3161 | { |
| 3162 | complete((struct completion *)data); |
| 3163 | } |
| 3164 | |
| 3165 | int r; |
| 3166 | DECLARE_COMPLETION_ONSTACK(completion); |
| 3167 | |
| 3168 | r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion, |
| 3169 | irqmask); |
| 3170 | |
| 3171 | if (r) |
| 3172 | return r; |
| 3173 | |
| 3174 | timeout = wait_for_completion_interruptible_timeout(&completion, |
| 3175 | timeout); |
| 3176 | |
| 3177 | omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask); |
| 3178 | |
| 3179 | if (timeout == 0) |
| 3180 | return -ETIMEDOUT; |
| 3181 | |
| 3182 | if (timeout == -ERESTARTSYS) |
| 3183 | return -ERESTARTSYS; |
| 3184 | |
| 3185 | return 0; |
| 3186 | } |
| 3187 | |
| 3188 | #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC |
| 3189 | void dispc_fake_vsync_irq(void) |
| 3190 | { |
| 3191 | u32 irqstatus = DISPC_IRQ_VSYNC; |
| 3192 | int i; |
| 3193 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 3194 | WARN_ON(!in_interrupt()); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 3195 | |
| 3196 | for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { |
| 3197 | struct omap_dispc_isr_data *isr_data; |
| 3198 | isr_data = &dispc.registered_isr[i]; |
| 3199 | |
| 3200 | if (!isr_data->isr) |
| 3201 | continue; |
| 3202 | |
| 3203 | if (isr_data->mask & irqstatus) |
| 3204 | isr_data->isr(isr_data->arg, irqstatus); |
| 3205 | } |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 3206 | } |
| 3207 | #endif |
| 3208 | |
| 3209 | static void _omap_dispc_initialize_irq(void) |
| 3210 | { |
| 3211 | unsigned long flags; |
| 3212 | |
| 3213 | spin_lock_irqsave(&dispc.irq_lock, flags); |
| 3214 | |
| 3215 | memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr)); |
| 3216 | |
| 3217 | dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR; |
Sumit Semwal | 2a205f3 | 2010-12-02 11:27:12 +0000 | [diff] [blame] | 3218 | if (dss_has_feature(FEAT_MGR_LCD2)) |
| 3219 | dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2; |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 3220 | |
| 3221 | /* there's SYNC_LOST_DIGIT waiting after enabling the DSS, |
| 3222 | * so clear it */ |
| 3223 | dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS)); |
| 3224 | |
| 3225 | _omap_dispc_set_irqs(); |
| 3226 | |
| 3227 | spin_unlock_irqrestore(&dispc.irq_lock, flags); |
| 3228 | } |
| 3229 | |
| 3230 | void dispc_enable_sidle(void) |
| 3231 | { |
| 3232 | REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */ |
| 3233 | } |
| 3234 | |
| 3235 | void dispc_disable_sidle(void) |
| 3236 | { |
| 3237 | REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ |
| 3238 | } |
| 3239 | |
| 3240 | static void _omap_dispc_initial_config(void) |
| 3241 | { |
| 3242 | u32 l; |
| 3243 | |
Murthy, Raghuveer | 0cf35df | 2011-03-03 09:28:00 -0600 | [diff] [blame] | 3244 | /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */ |
| 3245 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) { |
| 3246 | l = dispc_read_reg(DISPC_DIVISOR); |
| 3247 | /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */ |
| 3248 | l = FLD_MOD(l, 1, 0, 0); |
| 3249 | l = FLD_MOD(l, 1, 23, 16); |
| 3250 | dispc_write_reg(DISPC_DIVISOR, l); |
| 3251 | } |
| 3252 | |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 3253 | /* FUNCGATED */ |
Archit Taneja | 6ced40b | 2010-12-02 11:27:13 +0000 | [diff] [blame] | 3254 | if (dss_has_feature(FEAT_FUNCGATED)) |
| 3255 | REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 3256 | |
| 3257 | /* L3 firewall setting: enable access to OCM RAM */ |
| 3258 | /* XXX this should be somewhere in plat-omap */ |
| 3259 | if (cpu_is_omap24xx()) |
| 3260 | __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0)); |
| 3261 | |
| 3262 | _dispc_setup_color_conv_coef(); |
| 3263 | |
| 3264 | dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY); |
| 3265 | |
| 3266 | dispc_read_plane_fifo_sizes(); |
Tomi Valkeinen | 5ed8cf5 | 2011-06-21 09:35:36 +0300 | [diff] [blame] | 3267 | |
| 3268 | dispc_configure_burst_sizes(); |
Tomi Valkeinen | 80c3971 | 2009-11-12 11:41:42 +0200 | [diff] [blame] | 3269 | } |
| 3270 | |
Senthilvadivu Guruswamy | 060b6d9 | 2011-01-24 06:22:00 +0000 | [diff] [blame] | 3271 | /* DISPC HW IP initialisation */ |
| 3272 | static int omap_dispchw_probe(struct platform_device *pdev) |
| 3273 | { |
| 3274 | u32 rev; |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 3275 | int r = 0; |
Senthilvadivu Guruswamy | ea9da36 | 2011-01-24 06:22:04 +0000 | [diff] [blame] | 3276 | struct resource *dispc_mem; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 3277 | struct clk *clk; |
Senthilvadivu Guruswamy | ea9da36 | 2011-01-24 06:22:04 +0000 | [diff] [blame] | 3278 | |
Senthilvadivu Guruswamy | 060b6d9 | 2011-01-24 06:22:00 +0000 | [diff] [blame] | 3279 | dispc.pdev = pdev; |
| 3280 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 3281 | clk = clk_get(&pdev->dev, "fck"); |
| 3282 | if (IS_ERR(clk)) { |
| 3283 | DSSERR("can't get fck\n"); |
| 3284 | r = PTR_ERR(clk); |
| 3285 | goto err_get_clk; |
| 3286 | } |
| 3287 | |
| 3288 | dispc.dss_clk = clk; |
| 3289 | |
Senthilvadivu Guruswamy | 060b6d9 | 2011-01-24 06:22:00 +0000 | [diff] [blame] | 3290 | spin_lock_init(&dispc.irq_lock); |
| 3291 | |
| 3292 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 3293 | spin_lock_init(&dispc.irq_stats_lock); |
| 3294 | dispc.irq_stats.last_reset = jiffies; |
| 3295 | #endif |
| 3296 | |
| 3297 | INIT_WORK(&dispc.error_work, dispc_error_worker); |
| 3298 | |
Senthilvadivu Guruswamy | ea9da36 | 2011-01-24 06:22:04 +0000 | [diff] [blame] | 3299 | dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0); |
| 3300 | if (!dispc_mem) { |
| 3301 | DSSERR("can't get IORESOURCE_MEM DISPC\n"); |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 3302 | r = -EINVAL; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 3303 | goto err_ioremap; |
Senthilvadivu Guruswamy | ea9da36 | 2011-01-24 06:22:04 +0000 | [diff] [blame] | 3304 | } |
| 3305 | dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem)); |
Senthilvadivu Guruswamy | 060b6d9 | 2011-01-24 06:22:00 +0000 | [diff] [blame] | 3306 | if (!dispc.base) { |
| 3307 | DSSERR("can't ioremap DISPC\n"); |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 3308 | r = -ENOMEM; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 3309 | goto err_ioremap; |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 3310 | } |
| 3311 | dispc.irq = platform_get_irq(dispc.pdev, 0); |
| 3312 | if (dispc.irq < 0) { |
| 3313 | DSSERR("platform_get_irq failed\n"); |
| 3314 | r = -ENODEV; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 3315 | goto err_irq; |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 3316 | } |
| 3317 | |
| 3318 | r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED, |
| 3319 | "OMAP DISPC", dispc.pdev); |
| 3320 | if (r < 0) { |
| 3321 | DSSERR("request_irq failed\n"); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 3322 | goto err_irq; |
Senthilvadivu Guruswamy | 060b6d9 | 2011-01-24 06:22:00 +0000 | [diff] [blame] | 3323 | } |
| 3324 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 3325 | pm_runtime_enable(&pdev->dev); |
| 3326 | |
| 3327 | r = dispc_runtime_get(); |
| 3328 | if (r) |
| 3329 | goto err_runtime_get; |
Senthilvadivu Guruswamy | 060b6d9 | 2011-01-24 06:22:00 +0000 | [diff] [blame] | 3330 | |
| 3331 | _omap_dispc_initial_config(); |
| 3332 | |
| 3333 | _omap_dispc_initialize_irq(); |
| 3334 | |
Senthilvadivu Guruswamy | 060b6d9 | 2011-01-24 06:22:00 +0000 | [diff] [blame] | 3335 | rev = dispc_read_reg(DISPC_REVISION); |
Sumit Semwal | a06b62f | 2011-01-24 06:22:03 +0000 | [diff] [blame] | 3336 | dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n", |
Senthilvadivu Guruswamy | 060b6d9 | 2011-01-24 06:22:00 +0000 | [diff] [blame] | 3337 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
| 3338 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 3339 | dispc_runtime_put(); |
Senthilvadivu Guruswamy | 060b6d9 | 2011-01-24 06:22:00 +0000 | [diff] [blame] | 3340 | |
| 3341 | return 0; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 3342 | |
| 3343 | err_runtime_get: |
| 3344 | pm_runtime_disable(&pdev->dev); |
| 3345 | free_irq(dispc.irq, dispc.pdev); |
| 3346 | err_irq: |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 3347 | iounmap(dispc.base); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 3348 | err_ioremap: |
| 3349 | clk_put(dispc.dss_clk); |
| 3350 | err_get_clk: |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 3351 | return r; |
Senthilvadivu Guruswamy | 060b6d9 | 2011-01-24 06:22:00 +0000 | [diff] [blame] | 3352 | } |
| 3353 | |
| 3354 | static int omap_dispchw_remove(struct platform_device *pdev) |
| 3355 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 3356 | pm_runtime_disable(&pdev->dev); |
| 3357 | |
| 3358 | clk_put(dispc.dss_clk); |
| 3359 | |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 3360 | free_irq(dispc.irq, dispc.pdev); |
Senthilvadivu Guruswamy | 060b6d9 | 2011-01-24 06:22:00 +0000 | [diff] [blame] | 3361 | iounmap(dispc.base); |
| 3362 | return 0; |
| 3363 | } |
| 3364 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 3365 | static int dispc_runtime_suspend(struct device *dev) |
| 3366 | { |
| 3367 | dispc_save_context(); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 3368 | dss_runtime_put(); |
| 3369 | |
| 3370 | return 0; |
| 3371 | } |
| 3372 | |
| 3373 | static int dispc_runtime_resume(struct device *dev) |
| 3374 | { |
| 3375 | int r; |
| 3376 | |
| 3377 | r = dss_runtime_get(); |
| 3378 | if (r < 0) |
| 3379 | return r; |
| 3380 | |
Tomi Valkeinen | 49ea86f | 2011-06-01 15:54:06 +0300 | [diff] [blame] | 3381 | dispc_restore_context(); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 3382 | |
| 3383 | return 0; |
| 3384 | } |
| 3385 | |
| 3386 | static const struct dev_pm_ops dispc_pm_ops = { |
| 3387 | .runtime_suspend = dispc_runtime_suspend, |
| 3388 | .runtime_resume = dispc_runtime_resume, |
| 3389 | }; |
| 3390 | |
Senthilvadivu Guruswamy | 060b6d9 | 2011-01-24 06:22:00 +0000 | [diff] [blame] | 3391 | static struct platform_driver omap_dispchw_driver = { |
| 3392 | .probe = omap_dispchw_probe, |
| 3393 | .remove = omap_dispchw_remove, |
| 3394 | .driver = { |
| 3395 | .name = "omapdss_dispc", |
| 3396 | .owner = THIS_MODULE, |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 3397 | .pm = &dispc_pm_ops, |
Senthilvadivu Guruswamy | 060b6d9 | 2011-01-24 06:22:00 +0000 | [diff] [blame] | 3398 | }, |
| 3399 | }; |
| 3400 | |
| 3401 | int dispc_init_platform_driver(void) |
| 3402 | { |
| 3403 | return platform_driver_register(&omap_dispchw_driver); |
| 3404 | } |
| 3405 | |
| 3406 | void dispc_uninit_platform_driver(void) |
| 3407 | { |
| 3408 | return platform_driver_unregister(&omap_dispchw_driver); |
| 3409 | } |