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Yuval Mintz4ad79e12015-07-22 09:16:23 +03001/* bnx2x_ethtool.c: QLogic Everest network driver.
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002 *
Yuval Mintz247fa822013-01-14 05:11:50 +00003 * Copyright (c) 2007-2013 Broadcom Corporation
Yuval Mintz4ad79e12015-07-22 09:16:23 +03004 * Copyright (c) 2014 QLogic Corporation
5 * All rights reserved
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
10 *
Ariel Elior08f6dd82014-05-27 13:11:36 +030011 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +000012 * Written by: Eliezer Tamir
13 * Based on code from Michael Chan's bnx2 driver
14 * UDP CSUM errata workaround by Arik Gendelman
15 * Slowpath and fastpath rework by Vladislav Zolotarov
16 * Statistics and Link management by Yitchak Gertner
17 *
18 */
Joe Perchesf1deab52011-08-14 12:16:21 +000019
20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +000022#include <linux/ethtool.h>
23#include <linux/netdevice.h>
24#include <linux/types.h>
25#include <linux/sched.h>
26#include <linux/crc32.h>
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +000027#include "bnx2x.h"
28#include "bnx2x_cmn.h"
29#include "bnx2x_dump.h"
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +000030#include "bnx2x_init.h"
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +000031
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +000032/* Note: in the format strings below %s is replaced by the queue-name which is
33 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
34 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
35 */
36#define MAX_QUEUE_NAME_LEN 4
37static const struct {
38 long offset;
39 int size;
40 char string[ETH_GSTRING_LEN];
41} bnx2x_q_stats_arr[] = {
42/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +000043 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
44 8, "[%s]: rx_ucast_packets" },
45 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
46 8, "[%s]: rx_mcast_packets" },
47 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
48 8, "[%s]: rx_bcast_packets" },
49 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
50 { Q_STATS_OFFSET32(rx_err_discard_pkt),
51 4, "[%s]: rx_phy_ip_err_discards"},
52 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
53 4, "[%s]: rx_skb_alloc_discard" },
54 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
Yuval Mintz6a531192015-11-19 17:04:35 +020055 { Q_STATS_OFFSET32(driver_xoff), 4, "[%s]: tx_exhaustion_events" },
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +030056 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
57/* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +000058 8, "[%s]: tx_ucast_packets" },
59 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
60 8, "[%s]: tx_mcast_packets" },
61 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +030062 8, "[%s]: tx_bcast_packets" },
63 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
64 8, "[%s]: tpa_aggregations" },
65 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
66 8, "[%s]: tpa_aggregated_frames"},
Dmitry Kravkovc96bdc02012-12-02 04:05:48 +000067 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
68 { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
69 4, "[%s]: driver_filtered_tx_pkt" }
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +000070};
71
72#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
73
74static const struct {
75 long offset;
76 int size;
Michal Schmidt44c33c62015-12-04 17:22:36 +010077 bool is_port_stat;
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +000078 char string[ETH_GSTRING_LEN];
79} bnx2x_stats_arr[] = {
80/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +010081 8, false, "rx_bytes" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +000082 { STATS_OFFSET32(error_bytes_received_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +010083 8, false, "rx_error_bytes" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +000084 { STATS_OFFSET32(total_unicast_packets_received_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +010085 8, false, "rx_ucast_packets" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +000086 { STATS_OFFSET32(total_multicast_packets_received_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +010087 8, false, "rx_mcast_packets" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +000088 { STATS_OFFSET32(total_broadcast_packets_received_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +010089 8, false, "rx_bcast_packets" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +000090 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +010091 8, true, "rx_crc_errors" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +000092 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +010093 8, true, "rx_align_errors" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +000094 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +010095 8, true, "rx_undersize_packets" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +000096 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +010097 8, true, "rx_oversize_packets" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +000098/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +010099 8, true, "rx_fragments" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000100 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100101 8, true, "rx_jabbers" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000102 { STATS_OFFSET32(no_buff_discard_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100103 8, false, "rx_discards" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000104 { STATS_OFFSET32(mac_filter_discard),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100105 4, true, "rx_filtered_packets" },
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +0300106 { STATS_OFFSET32(mf_tag_discard),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100107 4, true, "rx_mf_tag_discard" },
Barak Witkowski0e898dd2011-12-05 21:52:22 +0000108 { STATS_OFFSET32(pfc_frames_received_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100109 8, true, "pfc_frames_received" },
Barak Witkowski0e898dd2011-12-05 21:52:22 +0000110 { STATS_OFFSET32(pfc_frames_sent_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100111 8, true, "pfc_frames_sent" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000112 { STATS_OFFSET32(brb_drop_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100113 8, true, "rx_brb_discard" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000114 { STATS_OFFSET32(brb_truncate_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100115 8, true, "rx_brb_truncate" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000116 { STATS_OFFSET32(pause_frames_received_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100117 8, true, "rx_pause_frames" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000118 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100119 8, true, "rx_mac_ctrl_frames" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000120 { STATS_OFFSET32(nig_timer_max),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100121 4, true, "rx_constant_pause_events" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000122/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100123 4, false, "rx_phy_ip_err_discards"},
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000124 { STATS_OFFSET32(rx_skb_alloc_failed),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100125 4, false, "rx_skb_alloc_discard" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000126 { STATS_OFFSET32(hw_csum_err),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100127 4, false, "rx_csum_offload_errors" },
Yuval Mintz6a531192015-11-19 17:04:35 +0200128 { STATS_OFFSET32(driver_xoff),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100129 4, false, "tx_exhaustion_events" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000130 { STATS_OFFSET32(total_bytes_transmitted_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100131 8, false, "tx_bytes" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000132 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100133 8, true, "tx_error_bytes" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000134 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100135 8, false, "tx_ucast_packets" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000136 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100137 8, false, "tx_mcast_packets" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000138 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100139 8, false, "tx_bcast_packets" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000140 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100141 8, true, "tx_mac_errors" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000142 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100143 8, true, "tx_carrier_errors" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000144/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100145 8, true, "tx_single_collisions" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000146 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100147 8, true, "tx_multi_collisions" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000148 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100149 8, true, "tx_deferred" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000150 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100151 8, true, "tx_excess_collisions" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000152 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100153 8, true, "tx_late_collisions" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000154 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100155 8, true, "tx_total_collisions" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000156 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100157 8, true, "tx_64_byte_packets" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000158 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100159 8, true, "tx_65_to_127_byte_packets" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000160 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100161 8, true, "tx_128_to_255_byte_packets" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000162 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100163 8, true, "tx_256_to_511_byte_packets" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000164/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100165 8, true, "tx_512_to_1023_byte_packets" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000166 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100167 8, true, "tx_1024_to_1522_byte_packets" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000168 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100169 8, true, "tx_1523_to_9022_byte_packets" },
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000170 { STATS_OFFSET32(pause_frames_sent_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100171 8, true, "tx_pause_frames" },
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +0300172 { STATS_OFFSET32(total_tpa_aggregations_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100173 8, false, "tpa_aggregations" },
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +0300174 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100175 8, false, "tpa_aggregated_frames"},
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +0300176 { STATS_OFFSET32(total_tpa_bytes_hi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100177 8, false, "tpa_bytes"},
Ariel Elior7a752992012-01-26 06:01:53 +0000178 { STATS_OFFSET32(recoverable_error),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100179 4, false, "recoverable_errors" },
Ariel Elior7a752992012-01-26 06:01:53 +0000180 { STATS_OFFSET32(unrecoverable_error),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100181 4, false, "unrecoverable_errors" },
Dmitry Kravkovc96bdc02012-12-02 04:05:48 +0000182 { STATS_OFFSET32(driver_filtered_tx_pkt),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100183 4, false, "driver_filtered_tx_pkt" },
Yuval Mintze9939c82012-06-06 17:13:08 +0000184 { STATS_OFFSET32(eee_tx_lpi),
Michal Schmidt44c33c62015-12-04 17:22:36 +0100185 4, true, "Tx LPI entry count"}
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000186};
187
188#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000189
Yaniv Rosner1ac9e422011-05-31 21:26:11 +0000190static int bnx2x_get_port_type(struct bnx2x *bp)
191{
192 int port_type;
193 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
194 switch (bp->link_params.phy[phy_idx].media_type) {
Yuval Mintzdbef8072012-06-20 19:05:22 +0000195 case ETH_PHY_SFPP_10G_FIBER:
196 case ETH_PHY_SFP_1G_FIBER:
Yaniv Rosner1ac9e422011-05-31 21:26:11 +0000197 case ETH_PHY_XFP_FIBER:
198 case ETH_PHY_KR:
199 case ETH_PHY_CX4:
200 port_type = PORT_FIBRE;
201 break;
202 case ETH_PHY_DA_TWINAX:
203 port_type = PORT_DA;
204 break;
205 case ETH_PHY_BASE_T:
206 port_type = PORT_TP;
207 break;
208 case ETH_PHY_NOT_PRESENT:
209 port_type = PORT_NONE;
210 break;
211 case ETH_PHY_UNSPECIFIED:
212 default:
213 port_type = PORT_OTHER;
214 break;
215 }
216 return port_type;
217}
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +0000218
Dmitry Kravkov6495d152014-06-26 14:31:04 +0300219static int bnx2x_get_vf_settings(struct net_device *dev,
220 struct ethtool_cmd *cmd)
221{
222 struct bnx2x *bp = netdev_priv(dev);
223
224 if (bp->state == BNX2X_STATE_OPEN) {
225 if (test_bit(BNX2X_LINK_REPORT_FD,
226 &bp->vf_link_vars.link_report_flags))
227 cmd->duplex = DUPLEX_FULL;
228 else
229 cmd->duplex = DUPLEX_HALF;
230
231 ethtool_cmd_speed_set(cmd, bp->vf_link_vars.line_speed);
232 } else {
233 cmd->duplex = DUPLEX_UNKNOWN;
234 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
235 }
236
237 cmd->port = PORT_OTHER;
238 cmd->phy_address = 0;
239 cmd->transceiver = XCVR_INTERNAL;
240 cmd->autoneg = AUTONEG_DISABLE;
241 cmd->maxtxpkt = 0;
242 cmd->maxrxpkt = 0;
243
244 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
245 " supported 0x%x advertising 0x%x speed %u\n"
246 " duplex %d port %d phy_address %d transceiver %d\n"
247 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
248 cmd->cmd, cmd->supported, cmd->advertising,
249 ethtool_cmd_speed(cmd),
250 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
251 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
252
253 return 0;
254}
255
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000256static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
257{
258 struct bnx2x *bp = netdev_priv(dev);
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000259 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
Yuval Mintz5d67c1c2015-06-25 15:19:22 +0300260 u32 media_type;
David Decotignyb3337e42011-04-14 16:11:34 +0000261
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000262 /* Dual Media boards present all available port types */
263 cmd->supported = bp->port.supported[cfg_idx] |
264 (bp->port.supported[cfg_idx ^ 1] &
265 (SUPPORTED_TP | SUPPORTED_FIBRE));
266 cmd->advertising = bp->port.advertising[cfg_idx];
Yuval Mintz5d67c1c2015-06-25 15:19:22 +0300267 media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type;
268 if (media_type == ETH_PHY_SFP_1G_FIBER) {
Yuval Mintzdbef8072012-06-20 19:05:22 +0000269 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
270 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
271 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000272
Yuval Mintz59694f02012-12-02 04:05:49 +0000273 if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
274 !(bp->flags & MF_FUNC_DIS)) {
Yuval Mintz2de67432013-01-23 03:21:43 +0000275 cmd->duplex = bp->link_vars.duplex;
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000276
Yuval Mintz38298462012-03-12 08:53:12 +0000277 if (IS_MF(bp) && !BP_NOMCP(bp))
278 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
Yuval Mintz59694f02012-12-02 04:05:49 +0000279 else
280 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
Yuval Mintz38298462012-03-12 08:53:12 +0000281 } else {
282 cmd->duplex = DUPLEX_UNKNOWN;
283 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
284 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000285
Yaniv Rosner1ac9e422011-05-31 21:26:11 +0000286 cmd->port = bnx2x_get_port_type(bp);
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000287
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000288 cmd->phy_address = bp->mdio.prtad;
289 cmd->transceiver = XCVR_INTERNAL;
290
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000291 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000292 cmd->autoneg = AUTONEG_ENABLE;
293 else
294 cmd->autoneg = AUTONEG_DISABLE;
295
Mintz Yuval9e7e8392012-02-15 02:10:24 +0000296 /* Publish LP advertised speeds and FC */
297 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
298 u32 status = bp->link_vars.link_status;
299
300 cmd->lp_advertising |= ADVERTISED_Autoneg;
301 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
302 cmd->lp_advertising |= ADVERTISED_Pause;
303 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
304 cmd->lp_advertising |= ADVERTISED_Asym_Pause;
305
306 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
307 cmd->lp_advertising |= ADVERTISED_10baseT_Half;
308 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
309 cmd->lp_advertising |= ADVERTISED_10baseT_Full;
310 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
311 cmd->lp_advertising |= ADVERTISED_100baseT_Half;
312 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
313 cmd->lp_advertising |= ADVERTISED_100baseT_Full;
314 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
315 cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
Yuval Mintz5d67c1c2015-06-25 15:19:22 +0300316 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) {
317 if (media_type == ETH_PHY_KR) {
318 cmd->lp_advertising |=
319 ADVERTISED_1000baseKX_Full;
320 } else {
321 cmd->lp_advertising |=
322 ADVERTISED_1000baseT_Full;
323 }
324 }
Mintz Yuval9e7e8392012-02-15 02:10:24 +0000325 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
326 cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
Yuval Mintz5d67c1c2015-06-25 15:19:22 +0300327 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) {
328 if (media_type == ETH_PHY_KR) {
329 cmd->lp_advertising |=
330 ADVERTISED_10000baseKR_Full;
331 } else {
332 cmd->lp_advertising |=
333 ADVERTISED_10000baseT_Full;
334 }
335 }
Yaniv Rosnerbe94bea2013-02-27 13:06:45 +0000336 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
337 cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full;
Mintz Yuval9e7e8392012-02-15 02:10:24 +0000338 }
339
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000340 cmd->maxtxpkt = 0;
341 cmd->maxrxpkt = 0;
342
Merav Sicron51c1a582012-03-18 10:33:38 +0000343 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
Joe Perchesf1deab52011-08-14 12:16:21 +0000344 " supported 0x%x advertising 0x%x speed %u\n"
345 " duplex %d port %d phy_address %d transceiver %d\n"
346 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
David Decotignyb3337e42011-04-14 16:11:34 +0000347 cmd->cmd, cmd->supported, cmd->advertising,
348 ethtool_cmd_speed(cmd),
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000349 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
350 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
351
352 return 0;
353}
354
355static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
356{
357 struct bnx2x *bp = netdev_priv(dev);
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000358 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
Yuval Mintzdbef8072012-06-20 19:05:22 +0000359 u32 speed, phy_idx;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000360
Dmitry Kravkov0793f83f2010-12-01 12:39:28 -0800361 if (IS_MF_SD(bp))
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000362 return 0;
363
Merav Sicron51c1a582012-03-18 10:33:38 +0000364 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
David Decotignyb3337e42011-04-14 16:11:34 +0000365 " supported 0x%x advertising 0x%x speed %u\n"
Dmitry Kravkov0793f83f2010-12-01 12:39:28 -0800366 " duplex %d port %d phy_address %d transceiver %d\n"
367 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
David Decotignyb3337e42011-04-14 16:11:34 +0000368 cmd->cmd, cmd->supported, cmd->advertising,
369 ethtool_cmd_speed(cmd),
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000370 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
371 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
372
David Decotignyb3337e42011-04-14 16:11:34 +0000373 speed = ethtool_cmd_speed(cmd);
Dmitry Kravkov0793f83f2010-12-01 12:39:28 -0800374
Yuval Mintz16a5fd92013-06-02 00:06:18 +0000375 /* If received a request for an unknown duplex, assume full*/
Yuval Mintz38298462012-03-12 08:53:12 +0000376 if (cmd->duplex == DUPLEX_UNKNOWN)
377 cmd->duplex = DUPLEX_FULL;
378
Dmitry Kravkov0793f83f2010-12-01 12:39:28 -0800379 if (IS_MF_SI(bp)) {
Dmitry Kravkove3835b92011-03-06 10:50:44 +0000380 u32 part;
Dmitry Kravkov0793f83f2010-12-01 12:39:28 -0800381 u32 line_speed = bp->link_vars.line_speed;
382
383 /* use 10G if no link detected */
384 if (!line_speed)
385 line_speed = 10000;
386
387 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
Merav Sicron51c1a582012-03-18 10:33:38 +0000388 DP(BNX2X_MSG_ETHTOOL,
389 "To set speed BC %X or higher is required, please upgrade BC\n",
390 REQ_BC_VER_4_SET_MF_BW);
Dmitry Kravkov0793f83f2010-12-01 12:39:28 -0800391 return -EINVAL;
392 }
Dmitry Kravkove3835b92011-03-06 10:50:44 +0000393
Dmitry Kravkovfaa6fcb2011-02-28 03:37:20 +0000394 part = (speed * 100) / line_speed;
Dmitry Kravkove3835b92011-03-06 10:50:44 +0000395
Dmitry Kravkovfaa6fcb2011-02-28 03:37:20 +0000396 if (line_speed < speed || !part) {
Merav Sicron51c1a582012-03-18 10:33:38 +0000397 DP(BNX2X_MSG_ETHTOOL,
398 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
Dmitry Kravkov0793f83f2010-12-01 12:39:28 -0800399 return -EINVAL;
400 }
Dmitry Kravkov0793f83f2010-12-01 12:39:28 -0800401
Dmitry Kravkove3835b92011-03-06 10:50:44 +0000402 if (bp->state != BNX2X_STATE_OPEN)
403 /* store value for following "load" */
404 bp->pending_max = part;
405 else
406 bnx2x_update_max_mf_config(bp, part);
Dmitry Kravkov0793f83f2010-12-01 12:39:28 -0800407
Dmitry Kravkov0793f83f2010-12-01 12:39:28 -0800408 return 0;
409 }
410
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000411 cfg_idx = bnx2x_get_link_cfg_idx(bp);
412 old_multi_phy_config = bp->link_params.multi_phy_config;
Yaniv Rosner33f9e6f2014-01-28 17:28:51 +0200413 if (cmd->port != bnx2x_get_port_type(bp)) {
414 switch (cmd->port) {
415 case PORT_TP:
416 if (!(bp->port.supported[0] & SUPPORTED_TP ||
417 bp->port.supported[1] & SUPPORTED_TP)) {
418 DP(BNX2X_MSG_ETHTOOL,
419 "Unsupported port type\n");
420 return -EINVAL;
421 }
422 bp->link_params.multi_phy_config &=
423 ~PORT_HW_CFG_PHY_SELECTION_MASK;
424 if (bp->link_params.multi_phy_config &
425 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
426 bp->link_params.multi_phy_config |=
427 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
428 else
429 bp->link_params.multi_phy_config |=
430 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
431 break;
432 case PORT_FIBRE:
433 case PORT_DA:
Yaniv Rosner042d7652014-07-23 22:12:57 +0300434 case PORT_NONE:
Yaniv Rosner33f9e6f2014-01-28 17:28:51 +0200435 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
436 bp->port.supported[1] & SUPPORTED_FIBRE)) {
437 DP(BNX2X_MSG_ETHTOOL,
438 "Unsupported port type\n");
439 return -EINVAL;
440 }
441 bp->link_params.multi_phy_config &=
442 ~PORT_HW_CFG_PHY_SELECTION_MASK;
443 if (bp->link_params.multi_phy_config &
444 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
445 bp->link_params.multi_phy_config |=
446 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
447 else
448 bp->link_params.multi_phy_config |=
449 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
450 break;
451 default:
Merav Sicron51c1a582012-03-18 10:33:38 +0000452 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000453 return -EINVAL;
454 }
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000455 }
Yuval Mintz2de67432013-01-23 03:21:43 +0000456 /* Save new config in case command complete successfully */
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000457 new_multi_phy_config = bp->link_params.multi_phy_config;
458 /* Get the new cfg_idx */
459 cfg_idx = bnx2x_get_link_cfg_idx(bp);
460 /* Restore old config in case command failed */
461 bp->link_params.multi_phy_config = old_multi_phy_config;
Merav Sicron51c1a582012-03-18 10:33:38 +0000462 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000463
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000464 if (cmd->autoneg == AUTONEG_ENABLE) {
Yaniv Rosner75318322012-01-17 02:33:27 +0000465 u32 an_supported_speed = bp->port.supported[cfg_idx];
466 if (bp->link_params.phy[EXT_PHY1].type ==
467 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
468 an_supported_speed |= (SUPPORTED_100baseT_Half |
469 SUPPORTED_100baseT_Full);
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000470 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
Merav Sicron51c1a582012-03-18 10:33:38 +0000471 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000472 return -EINVAL;
473 }
474
475 /* advertise the requested speed and duplex if supported */
Yaniv Rosner75318322012-01-17 02:33:27 +0000476 if (cmd->advertising & ~an_supported_speed) {
Merav Sicron51c1a582012-03-18 10:33:38 +0000477 DP(BNX2X_MSG_ETHTOOL,
478 "Advertisement parameters are not supported\n");
David S. Miller8decf862011-09-22 03:23:13 -0400479 return -EINVAL;
480 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000481
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000482 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
David S. Miller8decf862011-09-22 03:23:13 -0400483 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
484 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000485 cmd->advertising);
David S. Miller8decf862011-09-22 03:23:13 -0400486 if (cmd->advertising) {
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000487
David S. Miller8decf862011-09-22 03:23:13 -0400488 bp->link_params.speed_cap_mask[cfg_idx] = 0;
489 if (cmd->advertising & ADVERTISED_10baseT_Half) {
490 bp->link_params.speed_cap_mask[cfg_idx] |=
491 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
492 }
493 if (cmd->advertising & ADVERTISED_10baseT_Full)
494 bp->link_params.speed_cap_mask[cfg_idx] |=
495 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
496
497 if (cmd->advertising & ADVERTISED_100baseT_Full)
498 bp->link_params.speed_cap_mask[cfg_idx] |=
499 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
500
501 if (cmd->advertising & ADVERTISED_100baseT_Half) {
502 bp->link_params.speed_cap_mask[cfg_idx] |=
503 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
504 }
505 if (cmd->advertising & ADVERTISED_1000baseT_Half) {
506 bp->link_params.speed_cap_mask[cfg_idx] |=
507 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
508 }
509 if (cmd->advertising & (ADVERTISED_1000baseT_Full |
510 ADVERTISED_1000baseKX_Full))
511 bp->link_params.speed_cap_mask[cfg_idx] |=
512 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
513
514 if (cmd->advertising & (ADVERTISED_10000baseT_Full |
515 ADVERTISED_10000baseKX4_Full |
516 ADVERTISED_10000baseKR_Full))
517 bp->link_params.speed_cap_mask[cfg_idx] |=
518 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
Yaniv Rosnerbe94bea2013-02-27 13:06:45 +0000519
520 if (cmd->advertising & ADVERTISED_20000baseKR2_Full)
521 bp->link_params.speed_cap_mask[cfg_idx] |=
522 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
David S. Miller8decf862011-09-22 03:23:13 -0400523 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000524 } else { /* forced speed */
525 /* advertise the requested speed and duplex if supported */
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000526 switch (speed) {
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000527 case SPEED_10:
528 if (cmd->duplex == DUPLEX_FULL) {
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000529 if (!(bp->port.supported[cfg_idx] &
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000530 SUPPORTED_10baseT_Full)) {
Merav Sicron51c1a582012-03-18 10:33:38 +0000531 DP(BNX2X_MSG_ETHTOOL,
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000532 "10M full not supported\n");
533 return -EINVAL;
534 }
535
536 advertising = (ADVERTISED_10baseT_Full |
537 ADVERTISED_TP);
538 } else {
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000539 if (!(bp->port.supported[cfg_idx] &
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000540 SUPPORTED_10baseT_Half)) {
Merav Sicron51c1a582012-03-18 10:33:38 +0000541 DP(BNX2X_MSG_ETHTOOL,
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000542 "10M half not supported\n");
543 return -EINVAL;
544 }
545
546 advertising = (ADVERTISED_10baseT_Half |
547 ADVERTISED_TP);
548 }
549 break;
550
551 case SPEED_100:
552 if (cmd->duplex == DUPLEX_FULL) {
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000553 if (!(bp->port.supported[cfg_idx] &
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000554 SUPPORTED_100baseT_Full)) {
Merav Sicron51c1a582012-03-18 10:33:38 +0000555 DP(BNX2X_MSG_ETHTOOL,
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000556 "100M full not supported\n");
557 return -EINVAL;
558 }
559
560 advertising = (ADVERTISED_100baseT_Full |
561 ADVERTISED_TP);
562 } else {
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000563 if (!(bp->port.supported[cfg_idx] &
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000564 SUPPORTED_100baseT_Half)) {
Merav Sicron51c1a582012-03-18 10:33:38 +0000565 DP(BNX2X_MSG_ETHTOOL,
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000566 "100M half not supported\n");
567 return -EINVAL;
568 }
569
570 advertising = (ADVERTISED_100baseT_Half |
571 ADVERTISED_TP);
572 }
573 break;
574
575 case SPEED_1000:
576 if (cmd->duplex != DUPLEX_FULL) {
Merav Sicron51c1a582012-03-18 10:33:38 +0000577 DP(BNX2X_MSG_ETHTOOL,
578 "1G half not supported\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000579 return -EINVAL;
580 }
581
Yuval Mintz5d67c1c2015-06-25 15:19:22 +0300582 if (bp->port.supported[cfg_idx] &
583 SUPPORTED_1000baseT_Full) {
584 advertising = (ADVERTISED_1000baseT_Full |
585 ADVERTISED_TP);
586
587 } else if (bp->port.supported[cfg_idx] &
588 SUPPORTED_1000baseKX_Full) {
589 advertising = ADVERTISED_1000baseKX_Full;
590 } else {
Merav Sicron51c1a582012-03-18 10:33:38 +0000591 DP(BNX2X_MSG_ETHTOOL,
592 "1G full not supported\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000593 return -EINVAL;
594 }
595
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000596 break;
597
598 case SPEED_2500:
599 if (cmd->duplex != DUPLEX_FULL) {
Merav Sicron51c1a582012-03-18 10:33:38 +0000600 DP(BNX2X_MSG_ETHTOOL,
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000601 "2.5G half not supported\n");
602 return -EINVAL;
603 }
604
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000605 if (!(bp->port.supported[cfg_idx]
606 & SUPPORTED_2500baseX_Full)) {
Merav Sicron51c1a582012-03-18 10:33:38 +0000607 DP(BNX2X_MSG_ETHTOOL,
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000608 "2.5G full not supported\n");
609 return -EINVAL;
610 }
611
612 advertising = (ADVERTISED_2500baseX_Full |
613 ADVERTISED_TP);
614 break;
615
616 case SPEED_10000:
617 if (cmd->duplex != DUPLEX_FULL) {
Merav Sicron51c1a582012-03-18 10:33:38 +0000618 DP(BNX2X_MSG_ETHTOOL,
619 "10G half not supported\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000620 return -EINVAL;
621 }
Yuval Mintzdbef8072012-06-20 19:05:22 +0000622 phy_idx = bnx2x_get_cur_phy_idx(bp);
Yuval Mintz5d67c1c2015-06-25 15:19:22 +0300623 if ((bp->port.supported[cfg_idx] &
624 SUPPORTED_10000baseT_Full) &&
625 (bp->link_params.phy[phy_idx].media_type !=
Yuval Mintzdbef8072012-06-20 19:05:22 +0000626 ETH_PHY_SFP_1G_FIBER)) {
Yuval Mintz5d67c1c2015-06-25 15:19:22 +0300627 advertising = (ADVERTISED_10000baseT_Full |
628 ADVERTISED_FIBRE);
629 } else if (bp->port.supported[cfg_idx] &
630 SUPPORTED_10000baseKR_Full) {
631 advertising = (ADVERTISED_10000baseKR_Full |
632 ADVERTISED_FIBRE);
633 } else {
Merav Sicron51c1a582012-03-18 10:33:38 +0000634 DP(BNX2X_MSG_ETHTOOL,
635 "10G full not supported\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000636 return -EINVAL;
637 }
638
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000639 break;
640
641 default:
Merav Sicron51c1a582012-03-18 10:33:38 +0000642 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000643 return -EINVAL;
644 }
645
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000646 bp->link_params.req_line_speed[cfg_idx] = speed;
647 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
648 bp->port.advertising[cfg_idx] = advertising;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000649 }
650
Merav Sicron51c1a582012-03-18 10:33:38 +0000651 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
Joe Perchesf1deab52011-08-14 12:16:21 +0000652 " req_duplex %d advertising 0x%x\n",
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000653 bp->link_params.req_line_speed[cfg_idx],
654 bp->link_params.req_duplex[cfg_idx],
655 bp->port.advertising[cfg_idx]);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000656
Yaniv Rosnera22f0782010-09-07 11:41:20 +0000657 /* Set new config */
658 bp->link_params.multi_phy_config = new_multi_phy_config;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000659 if (netif_running(dev)) {
660 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
Ariel Eliordc6a20a2015-06-25 15:19:27 +0300661 bnx2x_force_link_reset(bp);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000662 bnx2x_link_set(bp);
663 }
664
665 return 0;
666}
667
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000668#define DUMP_ALL_PRESETS 0x1FFF
669#define DUMP_MAX_PRESETS 13
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000670
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000671static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000672{
673 if (CHIP_IS_E1(bp))
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000674 return dump_num_registers[0][preset-1];
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000675 else if (CHIP_IS_E1H(bp))
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000676 return dump_num_registers[1][preset-1];
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000677 else if (CHIP_IS_E2(bp))
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000678 return dump_num_registers[2][preset-1];
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000679 else if (CHIP_IS_E3A0(bp))
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000680 return dump_num_registers[3][preset-1];
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000681 else if (CHIP_IS_E3B0(bp))
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000682 return dump_num_registers[4][preset-1];
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000683 else
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000684 return 0;
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000685}
686
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000687static int __bnx2x_get_regs_len(struct bnx2x *bp)
688{
689 u32 preset_idx;
690 int regdump_len = 0;
691
692 /* Calculate the total preset regs length */
693 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
694 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
695
696 return regdump_len;
697}
698
699static int bnx2x_get_regs_len(struct net_device *dev)
700{
701 struct bnx2x *bp = netdev_priv(dev);
702 int regdump_len = 0;
703
Yuval Mintz75543742013-09-28 08:46:08 +0300704 if (IS_VF(bp))
705 return 0;
706
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000707 regdump_len = __bnx2x_get_regs_len(bp);
708 regdump_len *= 4;
709 regdump_len += sizeof(struct dump_header);
710
711 return regdump_len;
712}
713
714#define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
715#define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
716#define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
717#define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
718#define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
719
720#define IS_REG_IN_PRESET(presets, idx) \
721 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
722
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000723/******* Paged registers info selectors ********/
Eric Dumazet1191cb82012-04-27 21:39:21 +0000724static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000725{
726 if (CHIP_IS_E2(bp))
727 return page_vals_e2;
728 else if (CHIP_IS_E3(bp))
729 return page_vals_e3;
730 else
731 return NULL;
732}
733
Eric Dumazet1191cb82012-04-27 21:39:21 +0000734static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000735{
736 if (CHIP_IS_E2(bp))
737 return PAGE_MODE_VALUES_E2;
738 else if (CHIP_IS_E3(bp))
739 return PAGE_MODE_VALUES_E3;
740 else
741 return 0;
742}
743
Eric Dumazet1191cb82012-04-27 21:39:21 +0000744static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000745{
746 if (CHIP_IS_E2(bp))
747 return page_write_regs_e2;
748 else if (CHIP_IS_E3(bp))
749 return page_write_regs_e3;
750 else
751 return NULL;
752}
753
Eric Dumazet1191cb82012-04-27 21:39:21 +0000754static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000755{
756 if (CHIP_IS_E2(bp))
757 return PAGE_WRITE_REGS_E2;
758 else if (CHIP_IS_E3(bp))
759 return PAGE_WRITE_REGS_E3;
760 else
761 return 0;
762}
763
Eric Dumazet1191cb82012-04-27 21:39:21 +0000764static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000765{
766 if (CHIP_IS_E2(bp))
767 return page_read_regs_e2;
768 else if (CHIP_IS_E3(bp))
769 return page_read_regs_e3;
770 else
771 return NULL;
772}
773
Eric Dumazet1191cb82012-04-27 21:39:21 +0000774static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000775{
776 if (CHIP_IS_E2(bp))
777 return PAGE_READ_REGS_E2;
778 else if (CHIP_IS_E3(bp))
779 return PAGE_READ_REGS_E3;
780 else
781 return 0;
782}
783
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000784static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
785 const struct reg_addr *reg_info)
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000786{
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000787 if (CHIP_IS_E1(bp))
788 return IS_E1_REG(reg_info->chips);
789 else if (CHIP_IS_E1H(bp))
790 return IS_E1H_REG(reg_info->chips);
791 else if (CHIP_IS_E2(bp))
792 return IS_E2_REG(reg_info->chips);
793 else if (CHIP_IS_E3A0(bp))
794 return IS_E3A0_REG(reg_info->chips);
795 else if (CHIP_IS_E3B0(bp))
796 return IS_E3B0_REG(reg_info->chips);
797 else
798 return false;
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000799}
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000800
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000801static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
802 const struct wreg_addr *wreg_info)
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000803{
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000804 if (CHIP_IS_E1(bp))
805 return IS_E1_REG(wreg_info->chips);
806 else if (CHIP_IS_E1H(bp))
807 return IS_E1H_REG(wreg_info->chips);
808 else if (CHIP_IS_E2(bp))
809 return IS_E2_REG(wreg_info->chips);
810 else if (CHIP_IS_E3A0(bp))
811 return IS_E3A0_REG(wreg_info->chips);
812 else if (CHIP_IS_E3B0(bp))
813 return IS_E3B0_REG(wreg_info->chips);
814 else
815 return false;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000816}
817
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000818/**
819 * bnx2x_read_pages_regs - read "paged" registers
820 *
821 * @bp device handle
822 * @p output buffer
823 *
Yuval Mintz2de67432013-01-23 03:21:43 +0000824 * Reads "paged" memories: memories that may only be read by first writing to a
825 * specific address ("write address") and then reading from a specific address
826 * ("read address"). There may be more than one write address per "page" and
827 * more than one read address per write address.
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000828 */
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000829static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000830{
831 u32 i, j, k, n;
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000832
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000833 /* addresses of the paged registers */
834 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
835 /* number of paged registers */
836 int num_pages = __bnx2x_get_page_reg_num(bp);
837 /* write addresses */
838 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
839 /* number of write addresses */
840 int write_num = __bnx2x_get_page_write_num(bp);
841 /* read addresses info */
842 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
843 /* number of read addresses */
844 int read_num = __bnx2x_get_page_read_num(bp);
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000845 u32 addr, size;
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000846
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000847 for (i = 0; i < num_pages; i++) {
848 for (j = 0; j < write_num; j++) {
849 REG_WR(bp, write_addr[j], page_addr[i]);
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000850
851 for (k = 0; k < read_num; k++) {
852 if (IS_REG_IN_PRESET(read_addr[k].presets,
853 preset)) {
854 size = read_addr[k].size;
855 for (n = 0; n < size; n++) {
856 addr = read_addr[k].addr + n*4;
857 *p++ = REG_RD(bp, addr);
858 }
859 }
860 }
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000861 }
862 }
863}
864
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000865static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000866{
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000867 u32 i, j, addr;
868 const struct wreg_addr *wreg_addr_p = NULL;
869
870 if (CHIP_IS_E1(bp))
871 wreg_addr_p = &wreg_addr_e1;
872 else if (CHIP_IS_E1H(bp))
873 wreg_addr_p = &wreg_addr_e1h;
874 else if (CHIP_IS_E2(bp))
875 wreg_addr_p = &wreg_addr_e2;
876 else if (CHIP_IS_E3A0(bp))
877 wreg_addr_p = &wreg_addr_e3;
878 else if (CHIP_IS_E3B0(bp))
879 wreg_addr_p = &wreg_addr_e3b0;
880
881 /* Read the idle_chk registers */
882 for (i = 0; i < IDLE_REGS_COUNT; i++) {
883 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
884 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
885 for (j = 0; j < idle_reg_addrs[i].size; j++)
886 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
887 }
888 }
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000889
890 /* Read the regular registers */
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000891 for (i = 0; i < REGS_COUNT; i++) {
892 if (bnx2x_is_reg_in_chip(bp, &reg_addrs[i]) &&
893 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000894 for (j = 0; j < reg_addrs[i].size; j++)
895 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000896 }
897 }
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000898
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000899 /* Read the CAM registers */
900 if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
901 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
902 for (i = 0; i < wreg_addr_p->size; i++) {
903 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
904
905 /* In case of wreg_addr register, read additional
906 registers from read_regs array
907 */
908 for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
909 addr = *(wreg_addr_p->read_regs);
910 *p++ = REG_RD(bp, addr + j*4);
911 }
912 }
913 }
914
915 /* Paged registers are supported in E2 & E3 only */
916 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
Yuval Mintz16a5fd92013-06-02 00:06:18 +0000917 /* Read "paged" registers */
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000918 bnx2x_read_pages_regs(bp, p, preset);
919 }
920
921 return 0;
922}
923
924static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
925{
926 u32 preset_idx;
927
928 /* Read all registers, by reading all preset registers */
929 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
930 /* Skip presets with IOR */
931 if ((preset_idx == 2) ||
932 (preset_idx == 5) ||
933 (preset_idx == 8) ||
934 (preset_idx == 11))
935 continue;
936 __bnx2x_get_preset_regs(bp, p, preset_idx);
937 p += __bnx2x_get_preset_regs_len(bp, preset_idx);
938 }
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000939}
940
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000941static void bnx2x_get_regs(struct net_device *dev,
942 struct ethtool_regs *regs, void *_p)
943{
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000944 u32 *p = _p;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000945 struct bnx2x *bp = netdev_priv(dev);
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000946 struct dump_header dump_hdr = {0};
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000947
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000948 regs->version = 2;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000949 memset(p, 0, regs->len);
950
951 if (!netif_running(bp->dev))
952 return;
953
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000954 /* Disable parity attentions as long as following dump may
955 * cause false alarms by reading never written registers. We
956 * will re-enable parity attentions right after the dump.
957 */
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000958
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000959 bnx2x_disable_blocks_parity(bp);
960
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000961 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
962 dump_hdr.preset = DUMP_ALL_PRESETS;
963 dump_hdr.version = BNX2X_DUMP_VERSION;
964
965 /* dump_meta_data presents OR of CHIP and PATH. */
966 if (CHIP_IS_E1(bp)) {
967 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
968 } else if (CHIP_IS_E1H(bp)) {
969 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
970 } else if (CHIP_IS_E2(bp)) {
971 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
972 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
973 } else if (CHIP_IS_E3A0(bp)) {
974 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
975 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
976 } else if (CHIP_IS_E3B0(bp)) {
977 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
978 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
979 }
980
981 memcpy(p, &dump_hdr, sizeof(struct dump_header));
982 p += dump_hdr.header_size + 1;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000983
Yuval Mintze56270f2016-02-16 18:08:01 +0200984 /* This isn't really an error, but since attention handling is going
985 * to print the GRC timeouts using this macro, we use the same.
986 */
987 BNX2X_ERR("Generating register dump. Might trigger harmless GRC timeouts\n");
988
Vladislav Zolotarov0fea29c2011-07-21 07:57:23 +0000989 /* Actually read the registers */
990 __bnx2x_get_regs(bp, p);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +0000991
Dmitry Kravkov4293b9f2013-10-20 16:51:33 +0200992 /* Re-enable parity attentions */
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000993 bnx2x_clear_blocks_parity(bp);
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +0000994 bnx2x_enable_blocks_parity(bp);
Miriam Shitrit07ba6af2013-01-14 05:11:46 +0000995}
996
997static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
998{
999 struct bnx2x *bp = netdev_priv(dev);
1000 int regdump_len = 0;
1001
1002 regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
1003 regdump_len *= 4;
1004 regdump_len += sizeof(struct dump_header);
1005
1006 return regdump_len;
1007}
1008
1009static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
1010{
1011 struct bnx2x *bp = netdev_priv(dev);
1012
1013 /* Use the ethtool_dump "flag" field as the dump preset index */
Michal Schmidt5bb680d2013-07-01 17:23:06 +02001014 if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS)
1015 return -EINVAL;
1016
Miriam Shitrit07ba6af2013-01-14 05:11:46 +00001017 bp->dump_preset_idx = val->flag;
1018 return 0;
1019}
1020
1021static int bnx2x_get_dump_flag(struct net_device *dev,
1022 struct ethtool_dump *dump)
1023{
1024 struct bnx2x *bp = netdev_priv(dev);
1025
Michal Schmidt8cc2d922013-07-01 17:23:20 +02001026 dump->version = BNX2X_DUMP_VERSION;
1027 dump->flag = bp->dump_preset_idx;
Miriam Shitrit07ba6af2013-01-14 05:11:46 +00001028 /* Calculate the requested preset idx length */
1029 dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
1030 DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
1031 bp->dump_preset_idx, dump->len);
Miriam Shitrit07ba6af2013-01-14 05:11:46 +00001032 return 0;
1033}
1034
1035static int bnx2x_get_dump_data(struct net_device *dev,
1036 struct ethtool_dump *dump,
1037 void *buffer)
1038{
1039 u32 *p = buffer;
1040 struct bnx2x *bp = netdev_priv(dev);
1041 struct dump_header dump_hdr = {0};
1042
Miriam Shitrit07ba6af2013-01-14 05:11:46 +00001043 /* Disable parity attentions as long as following dump may
1044 * cause false alarms by reading never written registers. We
1045 * will re-enable parity attentions right after the dump.
1046 */
1047
Miriam Shitrit07ba6af2013-01-14 05:11:46 +00001048 bnx2x_disable_blocks_parity(bp);
1049
Miriam Shitrit07ba6af2013-01-14 05:11:46 +00001050 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1051 dump_hdr.preset = bp->dump_preset_idx;
1052 dump_hdr.version = BNX2X_DUMP_VERSION;
1053
1054 DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1055
1056 /* dump_meta_data presents OR of CHIP and PATH. */
1057 if (CHIP_IS_E1(bp)) {
1058 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1059 } else if (CHIP_IS_E1H(bp)) {
1060 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1061 } else if (CHIP_IS_E2(bp)) {
1062 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1063 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1064 } else if (CHIP_IS_E3A0(bp)) {
1065 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1066 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1067 } else if (CHIP_IS_E3B0(bp)) {
1068 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1069 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1070 }
1071
1072 memcpy(p, &dump_hdr, sizeof(struct dump_header));
1073 p += dump_hdr.header_size + 1;
1074
1075 /* Actually read the registers */
1076 __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1077
Dmitry Kravkov4293b9f2013-10-20 16:51:33 +02001078 /* Re-enable parity attentions */
Miriam Shitrit07ba6af2013-01-14 05:11:46 +00001079 bnx2x_clear_blocks_parity(bp);
1080 bnx2x_enable_blocks_parity(bp);
1081
Miriam Shitrit07ba6af2013-01-14 05:11:46 +00001082 return 0;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001083}
1084
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001085static void bnx2x_get_drvinfo(struct net_device *dev,
1086 struct ethtool_drvinfo *info)
1087{
1088 struct bnx2x *bp = netdev_priv(dev);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001089
Rick Jones68aad782011-11-07 13:29:27 +00001090 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1091 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001092
Ariel Elior8ca5e172013-01-01 05:22:34 +00001093 bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
1094
Rick Jones68aad782011-11-07 13:29:27 +00001095 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001096}
1097
1098static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1099{
1100 struct bnx2x *bp = netdev_priv(dev);
1101
1102 if (bp->flags & NO_WOL_FLAG) {
1103 wol->supported = 0;
1104 wol->wolopts = 0;
1105 } else {
1106 wol->supported = WAKE_MAGIC;
1107 if (bp->wol)
1108 wol->wolopts = WAKE_MAGIC;
1109 else
1110 wol->wolopts = 0;
1111 }
1112 memset(&wol->sopass, 0, sizeof(wol->sopass));
1113}
1114
1115static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1116{
1117 struct bnx2x *bp = netdev_priv(dev);
1118
Merav Sicron51c1a582012-03-18 10:33:38 +00001119 if (wol->wolopts & ~WAKE_MAGIC) {
Yuval Mintz2de67432013-01-23 03:21:43 +00001120 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001121 return -EINVAL;
Merav Sicron51c1a582012-03-18 10:33:38 +00001122 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001123
1124 if (wol->wolopts & WAKE_MAGIC) {
Merav Sicron51c1a582012-03-18 10:33:38 +00001125 if (bp->flags & NO_WOL_FLAG) {
Yuval Mintz2de67432013-01-23 03:21:43 +00001126 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001127 return -EINVAL;
Merav Sicron51c1a582012-03-18 10:33:38 +00001128 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001129 bp->wol = 1;
1130 } else
1131 bp->wol = 0;
1132
Yuval Mintz230d00e2015-07-22 09:16:25 +03001133 if (SHMEM2_HAS(bp, curr_cfg))
1134 SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS);
1135
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001136 return 0;
1137}
1138
1139static u32 bnx2x_get_msglevel(struct net_device *dev)
1140{
1141 struct bnx2x *bp = netdev_priv(dev);
1142
1143 return bp->msg_enable;
1144}
1145
1146static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1147{
1148 struct bnx2x *bp = netdev_priv(dev);
1149
Dmitry Kravkov7a25cc72011-06-14 01:33:25 +00001150 if (capable(CAP_NET_ADMIN)) {
1151 /* dump MCP trace */
Ariel Eliorad5afc82013-01-01 05:22:26 +00001152 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
Dmitry Kravkov7a25cc72011-06-14 01:33:25 +00001153 bnx2x_fw_dump_lvl(bp, KERN_INFO);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001154 bp->msg_enable = level;
Dmitry Kravkov7a25cc72011-06-14 01:33:25 +00001155 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001156}
1157
1158static int bnx2x_nway_reset(struct net_device *dev)
1159{
1160 struct bnx2x *bp = netdev_priv(dev);
1161
1162 if (!bp->port.pmf)
1163 return 0;
1164
1165 if (netif_running(dev)) {
1166 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
Yuval Mintz5d07d862012-09-13 02:56:21 +00001167 bnx2x_force_link_reset(bp);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001168 bnx2x_link_set(bp);
1169 }
1170
1171 return 0;
1172}
1173
1174static u32 bnx2x_get_link(struct net_device *dev)
1175{
1176 struct bnx2x *bp = netdev_priv(dev);
1177
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00001178 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001179 return 0;
1180
Dmitry Kravkov6495d152014-06-26 14:31:04 +03001181 if (IS_VF(bp))
1182 return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1183 &bp->vf_link_vars.link_report_flags);
1184
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001185 return bp->link_vars.link_up;
1186}
1187
1188static int bnx2x_get_eeprom_len(struct net_device *dev)
1189{
1190 struct bnx2x *bp = netdev_priv(dev);
1191
1192 return bp->common.flash_size;
1193}
1194
Yuval Mintz16a5fd92013-06-02 00:06:18 +00001195/* Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1196 * had we done things the other way around, if two pfs from the same port would
Ariel Eliorf16da432012-01-26 06:01:50 +00001197 * attempt to access nvram at the same time, we could run into a scenario such
1198 * as:
1199 * pf A takes the port lock.
1200 * pf B succeeds in taking the same lock since they are from the same port.
1201 * pf A takes the per pf misc lock. Performs eeprom access.
1202 * pf A finishes. Unlocks the per pf misc lock.
1203 * Pf B takes the lock and proceeds to perform it's own access.
1204 * pf A unlocks the per port lock, while pf B is still working (!).
1205 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
Yuval Mintz2de67432013-01-23 03:21:43 +00001206 * access corrupted by pf B)
Ariel Eliorf16da432012-01-26 06:01:50 +00001207 */
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001208static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1209{
1210 int port = BP_PORT(bp);
1211 int count, i;
Ariel Eliorf16da432012-01-26 06:01:50 +00001212 u32 val;
1213
1214 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1215 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001216
1217 /* adjust timeout for emulation/FPGA */
Dmitry Kravkov754a2f52011-06-14 01:34:02 +00001218 count = BNX2X_NVRAM_TIMEOUT_COUNT;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001219 if (CHIP_REV_IS_SLOW(bp))
1220 count *= 100;
1221
1222 /* request access to nvram interface */
1223 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1224 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1225
1226 for (i = 0; i < count*10; i++) {
1227 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1228 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1229 break;
1230
1231 udelay(5);
1232 }
1233
1234 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
Merav Sicron51c1a582012-03-18 10:33:38 +00001235 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1236 "cannot get access to nvram interface\n");
Yuval Mintzefd38b82015-06-25 15:19:28 +03001237 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001238 return -EBUSY;
1239 }
1240
1241 return 0;
1242}
1243
1244static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1245{
1246 int port = BP_PORT(bp);
1247 int count, i;
Ariel Eliorf16da432012-01-26 06:01:50 +00001248 u32 val;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001249
1250 /* adjust timeout for emulation/FPGA */
Dmitry Kravkov754a2f52011-06-14 01:34:02 +00001251 count = BNX2X_NVRAM_TIMEOUT_COUNT;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001252 if (CHIP_REV_IS_SLOW(bp))
1253 count *= 100;
1254
1255 /* relinquish nvram interface */
1256 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1257 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1258
1259 for (i = 0; i < count*10; i++) {
1260 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1261 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1262 break;
1263
1264 udelay(5);
1265 }
1266
1267 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
Merav Sicron51c1a582012-03-18 10:33:38 +00001268 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1269 "cannot free access to nvram interface\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001270 return -EBUSY;
1271 }
1272
Ariel Eliorf16da432012-01-26 06:01:50 +00001273 /* release HW lock: protect against other PFs in PF Direct Assignment */
1274 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001275 return 0;
1276}
1277
1278static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1279{
1280 u32 val;
1281
1282 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1283
1284 /* enable both bits, even on read */
1285 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1286 (val | MCPR_NVM_ACCESS_ENABLE_EN |
1287 MCPR_NVM_ACCESS_ENABLE_WR_EN));
1288}
1289
1290static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1291{
1292 u32 val;
1293
1294 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1295
1296 /* disable both bits, even after read */
1297 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1298 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1299 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1300}
1301
1302static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1303 u32 cmd_flags)
1304{
1305 int count, i, rc;
1306 u32 val;
1307
1308 /* build the command word */
1309 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1310
1311 /* need to clear DONE bit separately */
1312 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1313
1314 /* address of the NVRAM to read from */
1315 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1316 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1317
1318 /* issue a read command */
1319 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1320
1321 /* adjust timeout for emulation/FPGA */
Dmitry Kravkov754a2f52011-06-14 01:34:02 +00001322 count = BNX2X_NVRAM_TIMEOUT_COUNT;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001323 if (CHIP_REV_IS_SLOW(bp))
1324 count *= 100;
1325
1326 /* wait for completion */
1327 *ret_val = 0;
1328 rc = -EBUSY;
1329 for (i = 0; i < count; i++) {
1330 udelay(5);
1331 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1332
1333 if (val & MCPR_NVM_COMMAND_DONE) {
1334 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1335 /* we read nvram data in cpu order
1336 * but ethtool sees it as an array of bytes
Miriam Shitrit07ba6af2013-01-14 05:11:46 +00001337 * converting to big-endian will do the work
1338 */
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001339 *ret_val = cpu_to_be32(val);
1340 rc = 0;
1341 break;
1342 }
1343 }
Merav Sicron51c1a582012-03-18 10:33:38 +00001344 if (rc == -EBUSY)
1345 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1346 "nvram read timeout expired\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001347 return rc;
1348}
1349
Yuval Mintz97ac4ef2015-08-04 09:37:29 +03001350int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1351 int buf_size)
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001352{
1353 int rc;
1354 u32 cmd_flags;
1355 __be32 val;
1356
1357 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
Merav Sicron51c1a582012-03-18 10:33:38 +00001358 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001359 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1360 offset, buf_size);
1361 return -EINVAL;
1362 }
1363
1364 if (offset + buf_size > bp->common.flash_size) {
Merav Sicron51c1a582012-03-18 10:33:38 +00001365 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1366 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001367 offset, buf_size, bp->common.flash_size);
1368 return -EINVAL;
1369 }
1370
1371 /* request access to nvram interface */
1372 rc = bnx2x_acquire_nvram_lock(bp);
1373 if (rc)
1374 return rc;
1375
1376 /* enable access to nvram interface */
1377 bnx2x_enable_nvram_access(bp);
1378
1379 /* read the first word(s) */
1380 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1381 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1382 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1383 memcpy(ret_buf, &val, 4);
1384
1385 /* advance to the next dword */
1386 offset += sizeof(u32);
1387 ret_buf += sizeof(u32);
1388 buf_size -= sizeof(u32);
1389 cmd_flags = 0;
1390 }
1391
1392 if (rc == 0) {
1393 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1394 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1395 memcpy(ret_buf, &val, 4);
1396 }
1397
1398 /* disable access to nvram interface */
1399 bnx2x_disable_nvram_access(bp);
1400 bnx2x_release_nvram_lock(bp);
1401
1402 return rc;
1403}
1404
Dmitry Kravkov85640952013-04-22 03:48:06 +00001405static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf,
1406 int buf_size)
1407{
1408 int rc;
1409
1410 rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size);
1411
1412 if (!rc) {
1413 __be32 *be = (__be32 *)buf;
1414
1415 while ((buf_size -= 4) >= 0)
1416 *buf++ = be32_to_cpu(*be++);
1417 }
1418
1419 return rc;
1420}
1421
Yuval Mintz3fb43eb2013-05-27 04:08:31 +00001422static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
1423{
1424 int rc = 1;
1425 u16 pm = 0;
1426 struct net_device *dev = pci_get_drvdata(bp->pdev);
1427
Jon Mason29ed74c2013-09-11 11:22:39 -07001428 if (bp->pdev->pm_cap)
Yuval Mintz3fb43eb2013-05-27 04:08:31 +00001429 rc = pci_read_config_word(bp->pdev,
Jon Mason29ed74c2013-09-11 11:22:39 -07001430 bp->pdev->pm_cap + PCI_PM_CTRL, &pm);
Yuval Mintz3fb43eb2013-05-27 04:08:31 +00001431
Yuval Mintz829a5072013-06-01 23:02:26 +00001432 if ((rc && !netif_running(dev)) ||
Yuval Mintzc957d092013-06-25 08:50:11 +03001433 (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0)))
Yuval Mintz3fb43eb2013-05-27 04:08:31 +00001434 return false;
1435
1436 return true;
1437}
1438
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001439static int bnx2x_get_eeprom(struct net_device *dev,
1440 struct ethtool_eeprom *eeprom, u8 *eebuf)
1441{
1442 struct bnx2x *bp = netdev_priv(dev);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001443
Yuval Mintz3fb43eb2013-05-27 04:08:31 +00001444 if (!bnx2x_is_nvm_accessible(bp)) {
Merav Sicron51c1a582012-03-18 10:33:38 +00001445 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1446 "cannot access eeprom when the interface is down\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001447 return -EAGAIN;
Merav Sicron51c1a582012-03-18 10:33:38 +00001448 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001449
Merav Sicron51c1a582012-03-18 10:33:38 +00001450 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
Joe Perchesf1deab52011-08-14 12:16:21 +00001451 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001452 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1453 eeprom->len, eeprom->len);
1454
1455 /* parameters already validated in ethtool_get_eeprom */
1456
Dmitry Kravkovf1691dc2013-04-22 03:48:08 +00001457 return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001458}
1459
Yuval Mintz24ea8182012-06-20 19:05:23 +00001460static int bnx2x_get_module_eeprom(struct net_device *dev,
1461 struct ethtool_eeprom *ee,
1462 u8 *data)
1463{
1464 struct bnx2x *bp = netdev_priv(dev);
Yaniv Rosner669d69962013-03-27 01:05:18 +00001465 int rc = -EINVAL, phy_idx;
Yuval Mintz24ea8182012-06-20 19:05:23 +00001466 u8 *user_data = data;
Yaniv Rosner669d69962013-03-27 01:05:18 +00001467 unsigned int start_addr = ee->offset, xfer_size = 0;
Yuval Mintz24ea8182012-06-20 19:05:23 +00001468
Yuval Mintz3fb43eb2013-05-27 04:08:31 +00001469 if (!bnx2x_is_nvm_accessible(bp)) {
Yuval Mintz24ea8182012-06-20 19:05:23 +00001470 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1471 "cannot access eeprom when the interface is down\n");
1472 return -EAGAIN;
1473 }
1474
1475 phy_idx = bnx2x_get_cur_phy_idx(bp);
Yaniv Rosner669d69962013-03-27 01:05:18 +00001476
1477 /* Read A0 section */
1478 if (start_addr < ETH_MODULE_SFF_8079_LEN) {
1479 /* Limit transfer size to the A0 section boundary */
1480 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN)
1481 xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr;
1482 else
1483 xfer_size = ee->len;
1484 bnx2x_acquire_phy_lock(bp);
Yuval Mintz24ea8182012-06-20 19:05:23 +00001485 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1486 &bp->link_params,
Yaniv Rosner669d69962013-03-27 01:05:18 +00001487 I2C_DEV_ADDR_A0,
1488 start_addr,
Yuval Mintz24ea8182012-06-20 19:05:23 +00001489 xfer_size,
1490 user_data);
Yaniv Rosner669d69962013-03-27 01:05:18 +00001491 bnx2x_release_phy_lock(bp);
1492 if (rc) {
1493 DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n");
1494
1495 return -EINVAL;
1496 }
Yuval Mintz24ea8182012-06-20 19:05:23 +00001497 user_data += xfer_size;
Yaniv Rosner669d69962013-03-27 01:05:18 +00001498 start_addr += xfer_size;
Yuval Mintz24ea8182012-06-20 19:05:23 +00001499 }
1500
Yaniv Rosner669d69962013-03-27 01:05:18 +00001501 /* Read A2 section */
1502 if ((start_addr >= ETH_MODULE_SFF_8079_LEN) &&
1503 (start_addr < ETH_MODULE_SFF_8472_LEN)) {
1504 xfer_size = ee->len - xfer_size;
1505 /* Limit transfer size to the A2 section boundary */
1506 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN)
1507 xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr;
1508 start_addr -= ETH_MODULE_SFF_8079_LEN;
1509 bnx2x_acquire_phy_lock(bp);
1510 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1511 &bp->link_params,
1512 I2C_DEV_ADDR_A2,
1513 start_addr,
1514 xfer_size,
1515 user_data);
1516 bnx2x_release_phy_lock(bp);
1517 if (rc) {
1518 DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n");
1519 return -EINVAL;
1520 }
1521 }
Yuval Mintz24ea8182012-06-20 19:05:23 +00001522 return rc;
1523}
1524
1525static int bnx2x_get_module_info(struct net_device *dev,
1526 struct ethtool_modinfo *modinfo)
1527{
1528 struct bnx2x *bp = netdev_priv(dev);
Yaniv Rosner669d69962013-03-27 01:05:18 +00001529 int phy_idx, rc;
1530 u8 sff8472_comp, diag_type;
1531
Yuval Mintz3fb43eb2013-05-27 04:08:31 +00001532 if (!bnx2x_is_nvm_accessible(bp)) {
Yaniv Rosner669d69962013-03-27 01:05:18 +00001533 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
Yuval Mintz24ea8182012-06-20 19:05:23 +00001534 "cannot access eeprom when the interface is down\n");
1535 return -EAGAIN;
1536 }
Yuval Mintz24ea8182012-06-20 19:05:23 +00001537 phy_idx = bnx2x_get_cur_phy_idx(bp);
Yaniv Rosner669d69962013-03-27 01:05:18 +00001538 bnx2x_acquire_phy_lock(bp);
1539 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1540 &bp->link_params,
1541 I2C_DEV_ADDR_A0,
1542 SFP_EEPROM_SFF_8472_COMP_ADDR,
1543 SFP_EEPROM_SFF_8472_COMP_SIZE,
1544 &sff8472_comp);
1545 bnx2x_release_phy_lock(bp);
1546 if (rc) {
1547 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n");
1548 return -EINVAL;
1549 }
1550
1551 bnx2x_acquire_phy_lock(bp);
1552 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1553 &bp->link_params,
1554 I2C_DEV_ADDR_A0,
1555 SFP_EEPROM_DIAG_TYPE_ADDR,
1556 SFP_EEPROM_DIAG_TYPE_SIZE,
1557 &diag_type);
1558 bnx2x_release_phy_lock(bp);
1559 if (rc) {
1560 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n");
1561 return -EINVAL;
1562 }
1563
1564 if (!sff8472_comp ||
Mauro S. M. Rodrigues4fd07ae2019-06-13 16:25:40 -03001565 (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ) ||
1566 !(diag_type & SFP_EEPROM_DDM_IMPLEMENTED)) {
Yuval Mintz24ea8182012-06-20 19:05:23 +00001567 modinfo->type = ETH_MODULE_SFF_8079;
1568 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
Yaniv Rosner669d69962013-03-27 01:05:18 +00001569 } else {
1570 modinfo->type = ETH_MODULE_SFF_8472;
1571 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
Yuval Mintz24ea8182012-06-20 19:05:23 +00001572 }
Yaniv Rosner669d69962013-03-27 01:05:18 +00001573 return 0;
Yuval Mintz24ea8182012-06-20 19:05:23 +00001574}
1575
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001576static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1577 u32 cmd_flags)
1578{
1579 int count, i, rc;
1580
1581 /* build the command word */
1582 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1583
1584 /* need to clear DONE bit separately */
1585 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1586
1587 /* write the data */
1588 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1589
1590 /* address of the NVRAM to write to */
1591 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1592 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1593
1594 /* issue the write command */
1595 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1596
1597 /* adjust timeout for emulation/FPGA */
Dmitry Kravkov754a2f52011-06-14 01:34:02 +00001598 count = BNX2X_NVRAM_TIMEOUT_COUNT;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001599 if (CHIP_REV_IS_SLOW(bp))
1600 count *= 100;
1601
1602 /* wait for completion */
1603 rc = -EBUSY;
1604 for (i = 0; i < count; i++) {
1605 udelay(5);
1606 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1607 if (val & MCPR_NVM_COMMAND_DONE) {
1608 rc = 0;
1609 break;
1610 }
1611 }
1612
Merav Sicron51c1a582012-03-18 10:33:38 +00001613 if (rc == -EBUSY)
1614 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1615 "nvram write timeout expired\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001616 return rc;
1617}
1618
1619#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1620
1621static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1622 int buf_size)
1623{
1624 int rc;
Dmitry Kravkov30c20b62013-04-22 03:48:07 +00001625 u32 cmd_flags, align_offset, val;
1626 __be32 val_be;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001627
1628 if (offset + buf_size > bp->common.flash_size) {
Merav Sicron51c1a582012-03-18 10:33:38 +00001629 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1630 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001631 offset, buf_size, bp->common.flash_size);
1632 return -EINVAL;
1633 }
1634
1635 /* request access to nvram interface */
1636 rc = bnx2x_acquire_nvram_lock(bp);
1637 if (rc)
1638 return rc;
1639
1640 /* enable access to nvram interface */
1641 bnx2x_enable_nvram_access(bp);
1642
1643 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1644 align_offset = (offset & ~0x03);
Dmitry Kravkov30c20b62013-04-22 03:48:07 +00001645 rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001646
1647 if (rc == 0) {
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001648 /* nvram data is returned as an array of bytes
Miriam Shitrit07ba6af2013-01-14 05:11:46 +00001649 * convert it back to cpu order
1650 */
Dmitry Kravkov30c20b62013-04-22 03:48:07 +00001651 val = be32_to_cpu(val_be);
1652
Yuval Mintzc957d092013-06-25 08:50:11 +03001653 val &= ~le32_to_cpu((__force __le32)
1654 (0xff << BYTE_OFFSET(offset)));
1655 val |= le32_to_cpu((__force __le32)
1656 (*data_buf << BYTE_OFFSET(offset)));
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001657
1658 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1659 cmd_flags);
1660 }
1661
1662 /* disable access to nvram interface */
1663 bnx2x_disable_nvram_access(bp);
1664 bnx2x_release_nvram_lock(bp);
1665
1666 return rc;
1667}
1668
1669static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1670 int buf_size)
1671{
1672 int rc;
1673 u32 cmd_flags;
1674 u32 val;
1675 u32 written_so_far;
1676
1677 if (buf_size == 1) /* ethtool */
1678 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1679
1680 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
Merav Sicron51c1a582012-03-18 10:33:38 +00001681 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001682 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1683 offset, buf_size);
1684 return -EINVAL;
1685 }
1686
1687 if (offset + buf_size > bp->common.flash_size) {
Merav Sicron51c1a582012-03-18 10:33:38 +00001688 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1689 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001690 offset, buf_size, bp->common.flash_size);
1691 return -EINVAL;
1692 }
1693
1694 /* request access to nvram interface */
1695 rc = bnx2x_acquire_nvram_lock(bp);
1696 if (rc)
1697 return rc;
1698
1699 /* enable access to nvram interface */
1700 bnx2x_enable_nvram_access(bp);
1701
1702 written_so_far = 0;
1703 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1704 while ((written_so_far < buf_size) && (rc == 0)) {
1705 if (written_so_far == (buf_size - sizeof(u32)))
1706 cmd_flags |= MCPR_NVM_COMMAND_LAST;
Dmitry Kravkov754a2f52011-06-14 01:34:02 +00001707 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001708 cmd_flags |= MCPR_NVM_COMMAND_LAST;
Dmitry Kravkov754a2f52011-06-14 01:34:02 +00001709 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001710 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1711
1712 memcpy(&val, data_buf, 4);
1713
Yuval Mintz68bf5a12013-12-26 09:57:09 +02001714 /* Notice unlike bnx2x_nvram_read_dword() this will not
1715 * change val using be32_to_cpu(), which causes data to flip
1716 * if the eeprom is read and then written back. This is due
1717 * to tools utilizing this functionality that would break
1718 * if this would be resolved.
1719 */
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001720 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1721
1722 /* advance to the next dword */
1723 offset += sizeof(u32);
1724 data_buf += sizeof(u32);
1725 written_so_far += sizeof(u32);
Yuval Mintz0ea853d2015-08-10 12:49:36 +03001726
1727 /* At end of each 4Kb page, release nvram lock to allow MFW
1728 * chance to take it for its own use.
1729 */
1730 if ((cmd_flags & MCPR_NVM_COMMAND_LAST) &&
1731 (written_so_far < buf_size)) {
1732 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1733 "Releasing NVM lock after offset 0x%x\n",
1734 (u32)(offset - sizeof(u32)));
1735 bnx2x_release_nvram_lock(bp);
1736 usleep_range(1000, 2000);
1737 rc = bnx2x_acquire_nvram_lock(bp);
1738 if (rc)
1739 return rc;
1740 }
1741
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001742 cmd_flags = 0;
1743 }
1744
1745 /* disable access to nvram interface */
1746 bnx2x_disable_nvram_access(bp);
1747 bnx2x_release_nvram_lock(bp);
1748
1749 return rc;
1750}
1751
1752static int bnx2x_set_eeprom(struct net_device *dev,
1753 struct ethtool_eeprom *eeprom, u8 *eebuf)
1754{
1755 struct bnx2x *bp = netdev_priv(dev);
1756 int port = BP_PORT(bp);
1757 int rc = 0;
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001758 u32 ext_phy_config;
Yuval Mintz3fb43eb2013-05-27 04:08:31 +00001759
1760 if (!bnx2x_is_nvm_accessible(bp)) {
Merav Sicron51c1a582012-03-18 10:33:38 +00001761 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1762 "cannot access eeprom when the interface is down\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001763 return -EAGAIN;
Merav Sicron51c1a582012-03-18 10:33:38 +00001764 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001765
Merav Sicron51c1a582012-03-18 10:33:38 +00001766 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
Joe Perchesf1deab52011-08-14 12:16:21 +00001767 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001768 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1769 eeprom->len, eeprom->len);
1770
1771 /* parameters already validated in ethtool_set_eeprom */
1772
1773 /* PHY eeprom can be accessed only by the PMF */
1774 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
Merav Sicron51c1a582012-03-18 10:33:38 +00001775 !bp->port.pmf) {
1776 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1777 "wrong magic or interface is not pmf\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001778 return -EINVAL;
Merav Sicron51c1a582012-03-18 10:33:38 +00001779 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001780
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001781 ext_phy_config =
1782 SHMEM_RD(bp,
1783 dev_info.port_hw_config[port].external_phy_config);
1784
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001785 if (eeprom->magic == 0x50485950) {
1786 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1787 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1788
1789 bnx2x_acquire_phy_lock(bp);
1790 rc |= bnx2x_link_reset(&bp->link_params,
1791 &bp->link_vars, 0);
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001792 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001793 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1794 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1795 MISC_REGISTERS_GPIO_HIGH, port);
1796 bnx2x_release_phy_lock(bp);
1797 bnx2x_link_report(bp);
1798
1799 } else if (eeprom->magic == 0x50485952) {
1800 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1801 if (bp->state == BNX2X_STATE_OPEN) {
1802 bnx2x_acquire_phy_lock(bp);
1803 rc |= bnx2x_link_reset(&bp->link_params,
1804 &bp->link_vars, 1);
1805
1806 rc |= bnx2x_phy_init(&bp->link_params,
1807 &bp->link_vars);
1808 bnx2x_release_phy_lock(bp);
1809 bnx2x_calc_fc_adv(bp);
1810 }
1811 } else if (eeprom->magic == 0x53985943) {
1812 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001813 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001814 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001815
1816 /* DSP Remove Download Mode */
1817 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1818 MISC_REGISTERS_GPIO_LOW, port);
1819
1820 bnx2x_acquire_phy_lock(bp);
1821
Yaniv Rosnere10bc842010-09-07 11:40:50 +00001822 bnx2x_sfx7101_sp_sw_reset(bp,
1823 &bp->link_params.phy[EXT_PHY1]);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001824
1825 /* wait 0.5 sec to allow it to run */
1826 msleep(500);
1827 bnx2x_ext_phy_hw_reset(bp, port);
1828 msleep(500);
1829 bnx2x_release_phy_lock(bp);
1830 }
1831 } else
1832 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1833
1834 return rc;
1835}
Dmitry Kravkovf85582f2010-10-06 03:34:21 +00001836
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001837static int bnx2x_get_coalesce(struct net_device *dev,
1838 struct ethtool_coalesce *coal)
1839{
1840 struct bnx2x *bp = netdev_priv(dev);
1841
1842 memset(coal, 0, sizeof(struct ethtool_coalesce));
1843
1844 coal->rx_coalesce_usecs = bp->rx_ticks;
1845 coal->tx_coalesce_usecs = bp->tx_ticks;
1846
1847 return 0;
1848}
1849
1850static int bnx2x_set_coalesce(struct net_device *dev,
1851 struct ethtool_coalesce *coal)
1852{
1853 struct bnx2x *bp = netdev_priv(dev);
1854
1855 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1856 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1857 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1858
1859 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1860 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1861 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1862
1863 if (netif_running(dev))
1864 bnx2x_update_coalesce(bp);
1865
1866 return 0;
1867}
1868
1869static void bnx2x_get_ringparam(struct net_device *dev,
1870 struct ethtool_ringparam *ering)
1871{
1872 struct bnx2x *bp = netdev_priv(dev);
1873
1874 ering->rx_max_pending = MAX_RX_AVAIL;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001875
Mintz, Yuval65870fa2016-12-04 15:30:17 +02001876 /* If size isn't already set, we give an estimation of the number
1877 * of buffers we'll have. We're neglecting some possible conditions
1878 * [we couldn't know for certain at this point if number of queues
1879 * might shrink] but the number would be correct for the likely
1880 * scenario.
1881 */
Dmitry Kravkov25141582010-09-12 05:48:28 +00001882 if (bp->rx_ring_size)
1883 ering->rx_pending = bp->rx_ring_size;
Mintz, Yuval65870fa2016-12-04 15:30:17 +02001884 else if (BNX2X_NUM_RX_QUEUES(bp))
1885 ering->rx_pending = MAX_RX_AVAIL / BNX2X_NUM_RX_QUEUES(bp);
Dmitry Kravkov25141582010-09-12 05:48:28 +00001886 else
David S. Miller8decf862011-09-22 03:23:13 -04001887 ering->rx_pending = MAX_RX_AVAIL;
Dmitry Kravkov25141582010-09-12 05:48:28 +00001888
Barak Witkowskia3348722012-04-23 03:04:46 +00001889 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001890 ering->tx_pending = bp->tx_ring_size;
1891}
1892
1893static int bnx2x_set_ringparam(struct net_device *dev,
1894 struct ethtool_ringparam *ering)
1895{
1896 struct bnx2x *bp = netdev_priv(dev);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001897
Yuval Mintz04c46732013-01-23 03:21:46 +00001898 DP(BNX2X_MSG_ETHTOOL,
1899 "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1900 ering->rx_pending, ering->tx_pending);
1901
Yuval Mintz909d9fa2015-04-22 12:47:32 +03001902 if (pci_num_vf(bp->pdev)) {
1903 DP(BNX2X_MSG_IOV,
1904 "VFs are enabled, can not change ring parameters\n");
1905 return -EPERM;
1906 }
1907
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001908 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
Merav Sicron51c1a582012-03-18 10:33:38 +00001909 DP(BNX2X_MSG_ETHTOOL,
1910 "Handling parity error recovery. Try again later\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001911 return -EAGAIN;
1912 }
1913
1914 if ((ering->rx_pending > MAX_RX_AVAIL) ||
Dmitry Kravkovb3b83c32011-05-04 23:50:33 +00001915 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1916 MIN_RX_SIZE_TPA)) ||
Dmitry Kravkov2e98ffc2014-09-17 16:24:36 +03001917 (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) ||
Merav Sicron51c1a582012-03-18 10:33:38 +00001918 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1919 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001920 return -EINVAL;
Merav Sicron51c1a582012-03-18 10:33:38 +00001921 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001922
1923 bp->rx_ring_size = ering->rx_pending;
1924 bp->tx_ring_size = ering->tx_pending;
1925
Dmitry Kravkova9fccec2011-06-14 01:33:30 +00001926 return bnx2x_reload_if_running(dev);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001927}
1928
1929static void bnx2x_get_pauseparam(struct net_device *dev,
1930 struct ethtool_pauseparam *epause)
1931{
1932 struct bnx2x *bp = netdev_priv(dev);
Yaniv Rosnera22f0782010-09-07 11:41:20 +00001933 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
Mintz Yuval9e7e8392012-02-15 02:10:24 +00001934 int cfg_reg;
1935
Yaniv Rosnera22f0782010-09-07 11:41:20 +00001936 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1937 BNX2X_FLOW_CTRL_AUTO);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001938
Mintz Yuval9e7e8392012-02-15 02:10:24 +00001939 if (!epause->autoneg)
Yuval Mintz241fb5d2012-03-12 08:53:13 +00001940 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
Mintz Yuval9e7e8392012-02-15 02:10:24 +00001941 else
1942 cfg_reg = bp->link_params.req_fc_auto_adv;
1943
1944 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001945 BNX2X_FLOW_CTRL_RX);
Mintz Yuval9e7e8392012-02-15 02:10:24 +00001946 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001947 BNX2X_FLOW_CTRL_TX);
1948
Merav Sicron51c1a582012-03-18 10:33:38 +00001949 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
Joe Perchesf1deab52011-08-14 12:16:21 +00001950 " autoneg %d rx_pause %d tx_pause %d\n",
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001951 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1952}
1953
1954static int bnx2x_set_pauseparam(struct net_device *dev,
1955 struct ethtool_pauseparam *epause)
1956{
1957 struct bnx2x *bp = netdev_priv(dev);
Yaniv Rosnera22f0782010-09-07 11:41:20 +00001958 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
Dmitry Kravkovfb3bff12010-10-06 03:26:40 +00001959 if (IS_MF(bp))
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001960 return 0;
1961
Merav Sicron51c1a582012-03-18 10:33:38 +00001962 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
Joe Perchesf1deab52011-08-14 12:16:21 +00001963 " autoneg %d rx_pause %d tx_pause %d\n",
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001964 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1965
Yaniv Rosnera22f0782010-09-07 11:41:20 +00001966 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001967
1968 if (epause->rx_pause)
Yaniv Rosnera22f0782010-09-07 11:41:20 +00001969 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001970
1971 if (epause->tx_pause)
Yaniv Rosnera22f0782010-09-07 11:41:20 +00001972 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001973
Yaniv Rosnera22f0782010-09-07 11:41:20 +00001974 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1975 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001976
1977 if (epause->autoneg) {
Yaniv Rosnera22f0782010-09-07 11:41:20 +00001978 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
Merav Sicron51c1a582012-03-18 10:33:38 +00001979 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001980 return -EINVAL;
1981 }
1982
Yaniv Rosnera22f0782010-09-07 11:41:20 +00001983 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1984 bp->link_params.req_flow_ctrl[cfg_idx] =
1985 BNX2X_FLOW_CTRL_AUTO;
1986 }
Yaniv Rosnerba35a0f2013-04-24 01:44:59 +00001987 bp->link_params.req_fc_auto_adv = 0;
Yaniv Rosner5cd75f02012-09-11 04:34:12 +00001988 if (epause->rx_pause)
1989 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1990
1991 if (epause->tx_pause)
1992 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
Yaniv Rosnerba35a0f2013-04-24 01:44:59 +00001993
1994 if (!bp->link_params.req_fc_auto_adv)
1995 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00001996 }
1997
Merav Sicron51c1a582012-03-18 10:33:38 +00001998 DP(BNX2X_MSG_ETHTOOL,
Yaniv Rosnera22f0782010-09-07 11:41:20 +00001999 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002000
2001 if (netif_running(dev)) {
2002 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
Ariel Eliordc6a20a2015-06-25 15:19:27 +03002003 bnx2x_force_link_reset(bp);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002004 bnx2x_link_set(bp);
2005 }
2006
2007 return 0;
2008}
2009
Merav Sicron58893352012-09-23 03:12:23 +00002010static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
Merav Sicroncf2c1df62012-06-19 07:48:23 +00002011 "register_test (offline) ",
2012 "memory_test (offline) ",
2013 "int_loopback_test (offline)",
2014 "ext_loopback_test (offline)",
2015 "nvram_test (online) ",
2016 "interrupt_test (online) ",
2017 "link_test (online) "
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002018};
2019
Yuval Mintz3521b4192013-05-22 21:21:49 +00002020enum {
2021 BNX2X_PRI_FLAG_ISCSI,
2022 BNX2X_PRI_FLAG_FCOE,
2023 BNX2X_PRI_FLAG_STORAGE,
2024 BNX2X_PRI_FLAG_LEN,
2025};
2026
2027static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = {
2028 "iSCSI offload support",
2029 "FCoE offload support",
2030 "Storage only interface"
2031};
2032
Yuval Mintze9939c82012-06-06 17:13:08 +00002033static u32 bnx2x_eee_to_adv(u32 eee_adv)
2034{
2035 u32 modes = 0;
2036
2037 if (eee_adv & SHMEM_EEE_100M_ADV)
2038 modes |= ADVERTISED_100baseT_Full;
2039 if (eee_adv & SHMEM_EEE_1G_ADV)
2040 modes |= ADVERTISED_1000baseT_Full;
2041 if (eee_adv & SHMEM_EEE_10G_ADV)
2042 modes |= ADVERTISED_10000baseT_Full;
2043
2044 return modes;
2045}
2046
2047static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
2048{
2049 u32 eee_adv = 0;
2050 if (modes & ADVERTISED_100baseT_Full)
2051 eee_adv |= SHMEM_EEE_100M_ADV;
2052 if (modes & ADVERTISED_1000baseT_Full)
2053 eee_adv |= SHMEM_EEE_1G_ADV;
2054 if (modes & ADVERTISED_10000baseT_Full)
2055 eee_adv |= SHMEM_EEE_10G_ADV;
2056
2057 return eee_adv << shift;
2058}
2059
2060static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
2061{
2062 struct bnx2x *bp = netdev_priv(dev);
2063 u32 eee_cfg;
2064
2065 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2066 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2067 return -EOPNOTSUPP;
2068 }
2069
Yuval Mintz08e9acc2012-09-10 05:51:04 +00002070 eee_cfg = bp->link_vars.eee_status;
Yuval Mintze9939c82012-06-06 17:13:08 +00002071
2072 edata->supported =
2073 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
2074 SHMEM_EEE_SUPPORTED_SHIFT);
2075
2076 edata->advertised =
2077 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
2078 SHMEM_EEE_ADV_STATUS_SHIFT);
2079 edata->lp_advertised =
2080 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
2081 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2082
2083 /* SHMEM value is in 16u units --> Convert to 1u units. */
2084 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
2085
2086 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0;
2087 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0;
2088 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
2089
2090 return 0;
2091}
2092
2093static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
2094{
2095 struct bnx2x *bp = netdev_priv(dev);
2096 u32 eee_cfg;
2097 u32 advertised;
2098
2099 if (IS_MF(bp))
2100 return 0;
2101
2102 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2103 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2104 return -EOPNOTSUPP;
2105 }
2106
Yuval Mintz08e9acc2012-09-10 05:51:04 +00002107 eee_cfg = bp->link_vars.eee_status;
Yuval Mintze9939c82012-06-06 17:13:08 +00002108
2109 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
2110 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
2111 return -EOPNOTSUPP;
2112 }
2113
2114 advertised = bnx2x_adv_to_eee(edata->advertised,
2115 SHMEM_EEE_ADV_STATUS_SHIFT);
2116 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
2117 DP(BNX2X_MSG_ETHTOOL,
Masanari Iidaefc7ce02012-11-02 04:36:17 +00002118 "Direct manipulation of EEE advertisement is not supported\n");
Yuval Mintze9939c82012-06-06 17:13:08 +00002119 return -EINVAL;
2120 }
2121
2122 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
2123 DP(BNX2X_MSG_ETHTOOL,
2124 "Maximal Tx Lpi timer supported is %x(u)\n",
2125 EEE_MODE_TIMER_MASK);
2126 return -EINVAL;
2127 }
2128 if (edata->tx_lpi_enabled &&
2129 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
2130 DP(BNX2X_MSG_ETHTOOL,
2131 "Minimal Tx Lpi timer supported is %d(u)\n",
2132 EEE_MODE_NVRAM_AGGRESSIVE_TIME);
2133 return -EINVAL;
2134 }
2135
2136 /* All is well; Apply changes*/
2137 if (edata->eee_enabled)
2138 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
2139 else
2140 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
2141
2142 if (edata->tx_lpi_enabled)
2143 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
2144 else
2145 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
2146
2147 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
2148 bp->link_params.eee_mode |= (edata->tx_lpi_timer &
2149 EEE_MODE_TIMER_MASK) |
2150 EEE_MODE_OVERRIDE_NVRAM |
2151 EEE_MODE_OUTPUT_TIME;
2152
Yuval Mintz16a5fd92013-06-02 00:06:18 +00002153 /* Restart link to propagate changes */
Yuval Mintze9939c82012-06-06 17:13:08 +00002154 if (netif_running(dev)) {
2155 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
Yuval Mintz5d07d862012-09-13 02:56:21 +00002156 bnx2x_force_link_reset(bp);
Yuval Mintze9939c82012-06-06 17:13:08 +00002157 bnx2x_link_set(bp);
2158 }
2159
2160 return 0;
2161}
2162
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002163enum {
2164 BNX2X_CHIP_E1_OFST = 0,
2165 BNX2X_CHIP_E1H_OFST,
2166 BNX2X_CHIP_E2_OFST,
2167 BNX2X_CHIP_E3_OFST,
2168 BNX2X_CHIP_E3B0_OFST,
2169 BNX2X_CHIP_MAX_OFST
2170};
2171
2172#define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
2173#define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
2174#define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
2175#define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
2176#define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
2177
2178#define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
2179#define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2180
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002181static int bnx2x_test_registers(struct bnx2x *bp)
2182{
2183 int idx, i, rc = -ENODEV;
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002184 u32 wr_val = 0, hw;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002185 int port = BP_PORT(bp);
2186 static const struct {
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002187 u32 hw;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002188 u32 offset0;
2189 u32 offset1;
2190 u32 mask;
2191 } reg_tbl[] = {
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002192/* 0 */ { BNX2X_CHIP_MASK_ALL,
2193 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2194 { BNX2X_CHIP_MASK_ALL,
2195 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
2196 { BNX2X_CHIP_MASK_E1X,
2197 HC_REG_AGG_INT_0, 4, 0x000003ff },
2198 { BNX2X_CHIP_MASK_ALL,
2199 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
2200 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2201 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
2202 { BNX2X_CHIP_MASK_E3B0,
2203 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
2204 { BNX2X_CHIP_MASK_ALL,
2205 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
2206 { BNX2X_CHIP_MASK_ALL,
2207 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
2208 { BNX2X_CHIP_MASK_ALL,
2209 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2210 { BNX2X_CHIP_MASK_ALL,
2211 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
2212/* 10 */ { BNX2X_CHIP_MASK_ALL,
2213 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2214 { BNX2X_CHIP_MASK_ALL,
2215 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
2216 { BNX2X_CHIP_MASK_ALL,
2217 QM_REG_CONNNUM_0, 4, 0x000fffff },
2218 { BNX2X_CHIP_MASK_ALL,
2219 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
2220 { BNX2X_CHIP_MASK_ALL,
2221 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
2222 { BNX2X_CHIP_MASK_ALL,
2223 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
2224 { BNX2X_CHIP_MASK_ALL,
2225 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2226 { BNX2X_CHIP_MASK_ALL,
2227 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
2228 { BNX2X_CHIP_MASK_ALL,
2229 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
2230 { BNX2X_CHIP_MASK_ALL,
2231 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
2232/* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2233 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
2234 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2235 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
2236 { BNX2X_CHIP_MASK_ALL,
2237 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
2238 { BNX2X_CHIP_MASK_ALL,
2239 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
2240 { BNX2X_CHIP_MASK_ALL,
2241 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
2242 { BNX2X_CHIP_MASK_ALL,
2243 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
2244 { BNX2X_CHIP_MASK_ALL,
2245 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
2246 { BNX2X_CHIP_MASK_ALL,
2247 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
2248 { BNX2X_CHIP_MASK_ALL,
2249 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
2250 { BNX2X_CHIP_MASK_ALL,
2251 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
2252/* 30 */ { BNX2X_CHIP_MASK_ALL,
2253 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
2254 { BNX2X_CHIP_MASK_ALL,
2255 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
2256 { BNX2X_CHIP_MASK_ALL,
2257 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2258 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2259 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
2260 { BNX2X_CHIP_MASK_ALL,
2261 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2262 { BNX2X_CHIP_MASK_ALL,
2263 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2264 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2265 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2266 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2267 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002268
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002269 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002270 };
2271
Yuval Mintz3fb43eb2013-05-27 04:08:31 +00002272 if (!bnx2x_is_nvm_accessible(bp)) {
Merav Sicron51c1a582012-03-18 10:33:38 +00002273 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2274 "cannot access eeprom when the interface is down\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002275 return rc;
Merav Sicron51c1a582012-03-18 10:33:38 +00002276 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002277
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002278 if (CHIP_IS_E1(bp))
2279 hw = BNX2X_CHIP_MASK_E1;
2280 else if (CHIP_IS_E1H(bp))
2281 hw = BNX2X_CHIP_MASK_E1H;
2282 else if (CHIP_IS_E2(bp))
2283 hw = BNX2X_CHIP_MASK_E2;
2284 else if (CHIP_IS_E3B0(bp))
2285 hw = BNX2X_CHIP_MASK_E3B0;
2286 else /* e3 A0 */
2287 hw = BNX2X_CHIP_MASK_E3;
2288
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002289 /* Repeat the test twice:
Miriam Shitrit07ba6af2013-01-14 05:11:46 +00002290 * First by writing 0x00000000, second by writing 0xffffffff
2291 */
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002292 for (idx = 0; idx < 2; idx++) {
2293
2294 switch (idx) {
2295 case 0:
2296 wr_val = 0;
2297 break;
2298 case 1:
2299 wr_val = 0xffffffff;
2300 break;
2301 }
2302
2303 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2304 u32 offset, mask, save_val, val;
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002305 if (!(hw & reg_tbl[i].hw))
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002306 continue;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002307
2308 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2309 mask = reg_tbl[i].mask;
2310
2311 save_val = REG_RD(bp, offset);
2312
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +00002313 REG_WR(bp, offset, wr_val & mask);
Dmitry Kravkovf85582f2010-10-06 03:34:21 +00002314
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002315 val = REG_RD(bp, offset);
2316
2317 /* Restore the original register's value */
2318 REG_WR(bp, offset, save_val);
2319
2320 /* verify value is as expected */
2321 if ((val & mask) != (wr_val & mask)) {
Merav Sicron51c1a582012-03-18 10:33:38 +00002322 DP(BNX2X_MSG_ETHTOOL,
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002323 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2324 offset, val, wr_val, mask);
2325 goto test_reg_exit;
2326 }
2327 }
2328 }
2329
2330 rc = 0;
2331
2332test_reg_exit:
2333 return rc;
2334}
2335
2336static int bnx2x_test_memory(struct bnx2x *bp)
2337{
2338 int i, j, rc = -ENODEV;
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002339 u32 val, index;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002340 static const struct {
2341 u32 offset;
2342 int size;
2343 } mem_tbl[] = {
2344 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
2345 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2346 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
2347 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
2348 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
2349 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
2350 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
2351
2352 { 0xffffffff, 0 }
2353 };
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002354
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002355 static const struct {
2356 char *name;
2357 u32 offset;
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002358 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002359 } prty_tbl[] = {
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002360 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
2361 {0x3ffc0, 0, 0, 0} },
2362 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
2363 {0x2, 0x2, 0, 0} },
2364 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2365 {0, 0, 0, 0} },
2366 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
2367 {0x3ffc0, 0, 0, 0} },
2368 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
2369 {0x3ffc0, 0, 0, 0} },
2370 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
2371 {0x3ffc1, 0, 0, 0} },
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002372
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002373 { NULL, 0xffffffff, {0, 0, 0, 0} }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002374 };
2375
Yuval Mintz3fb43eb2013-05-27 04:08:31 +00002376 if (!bnx2x_is_nvm_accessible(bp)) {
Merav Sicron51c1a582012-03-18 10:33:38 +00002377 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2378 "cannot access eeprom when the interface is down\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002379 return rc;
Merav Sicron51c1a582012-03-18 10:33:38 +00002380 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002381
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002382 if (CHIP_IS_E1(bp))
2383 index = BNX2X_CHIP_E1_OFST;
2384 else if (CHIP_IS_E1H(bp))
2385 index = BNX2X_CHIP_E1H_OFST;
2386 else if (CHIP_IS_E2(bp))
2387 index = BNX2X_CHIP_E2_OFST;
2388 else /* e3 */
2389 index = BNX2X_CHIP_E3_OFST;
2390
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002391 /* pre-Check the parity status */
2392 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2393 val = REG_RD(bp, prty_tbl[i].offset);
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002394 if (val & ~(prty_tbl[i].hw_mask[index])) {
Merav Sicron51c1a582012-03-18 10:33:38 +00002395 DP(BNX2X_MSG_ETHTOOL,
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002396 "%s is 0x%x\n", prty_tbl[i].name, val);
2397 goto test_mem_exit;
2398 }
2399 }
2400
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002401 /* Go through all the memories */
2402 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2403 for (j = 0; j < mem_tbl[i].size; j++)
2404 REG_RD(bp, mem_tbl[i].offset + j*4);
2405
2406 /* Check the parity status */
2407 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2408 val = REG_RD(bp, prty_tbl[i].offset);
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002409 if (val & ~(prty_tbl[i].hw_mask[index])) {
Merav Sicron51c1a582012-03-18 10:33:38 +00002410 DP(BNX2X_MSG_ETHTOOL,
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002411 "%s is 0x%x\n", prty_tbl[i].name, val);
2412 goto test_mem_exit;
2413 }
2414 }
2415
2416 rc = 0;
2417
2418test_mem_exit:
2419 return rc;
2420}
2421
Yaniv Rosnera22f0782010-09-07 11:41:20 +00002422static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002423{
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002424 int cnt = 1400;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002425
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002426 if (link_up) {
Yaniv Rosnera22f0782010-09-07 11:41:20 +00002427 while (bnx2x_link_test(bp, is_serdes) && cnt--)
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002428 msleep(20);
2429
2430 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
Merav Sicron51c1a582012-03-18 10:33:38 +00002431 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
Merav Sicron8970b2e2012-06-19 07:48:22 +00002432
2433 cnt = 1400;
2434 while (!bp->link_vars.link_up && cnt--)
2435 msleep(20);
2436
2437 if (cnt <= 0 && !bp->link_vars.link_up)
2438 DP(BNX2X_MSG_ETHTOOL,
2439 "Timeout waiting for link init\n");
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002440 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002441}
2442
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002443static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002444{
2445 unsigned int pkt_size, num_pkts, i;
2446 struct sk_buff *skb;
2447 unsigned char *packet;
2448 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2449 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
Merav Sicron65565882012-06-19 07:48:26 +00002450 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002451 u16 tx_start_idx, tx_idx;
2452 u16 rx_start_idx, rx_idx;
Dmitry Kravkovb0700b12012-01-23 07:31:53 +00002453 u16 pkt_prod, bd_prod;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002454 struct sw_tx_bd *tx_buf;
2455 struct eth_tx_start_bd *tx_start_bd;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002456 dma_addr_t mapping;
2457 union eth_rx_cqe *cqe;
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002458 u8 cqe_fp_flags, cqe_fp_type;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002459 struct sw_rx_bd *rx_buf;
2460 u16 len;
2461 int rc = -ENODEV;
Eric Dumazete52fcb22011-11-14 06:05:34 +00002462 u8 *data;
Merav Sicron8970b2e2012-06-19 07:48:22 +00002463 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2464 txdata->txq_index);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002465
2466 /* check the loopback mode */
2467 switch (loopback_mode) {
2468 case BNX2X_PHY_LOOPBACK:
Merav Sicron8970b2e2012-06-19 07:48:22 +00002469 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2470 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002471 return -EINVAL;
Merav Sicron8970b2e2012-06-19 07:48:22 +00002472 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002473 break;
2474 case BNX2X_MAC_LOOPBACK:
Yaniv Rosner32911332011-11-28 00:49:51 +00002475 if (CHIP_IS_E3(bp)) {
2476 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2477 if (bp->port.supported[cfg_idx] &
2478 (SUPPORTED_10000baseT_Full |
2479 SUPPORTED_20000baseMLD2_Full |
2480 SUPPORTED_20000baseKR2_Full))
2481 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2482 else
2483 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2484 } else
2485 bp->link_params.loopback_mode = LOOPBACK_BMAC;
2486
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002487 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2488 break;
Merav Sicron8970b2e2012-06-19 07:48:22 +00002489 case BNX2X_EXT_LOOPBACK:
2490 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2491 DP(BNX2X_MSG_ETHTOOL,
2492 "Can't configure external loopback\n");
2493 return -EINVAL;
2494 }
2495 break;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002496 default:
Merav Sicron51c1a582012-03-18 10:33:38 +00002497 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002498 return -EINVAL;
2499 }
2500
2501 /* prepare the loopback packet */
2502 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2503 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
Vladislav Zolotarova8c94b92011-02-06 11:21:02 -08002504 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002505 if (!skb) {
Merav Sicron51c1a582012-03-18 10:33:38 +00002506 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002507 rc = -ENOMEM;
2508 goto test_loopback_exit;
2509 }
2510 packet = skb_put(skb, pkt_size);
2511 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
Joe Perchesc7bf7162015-03-02 19:54:47 -08002512 eth_zero_addr(packet + ETH_ALEN);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002513 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2514 for (i = ETH_HLEN; i < pkt_size; i++)
2515 packet[i] = (unsigned char) (i & 0xff);
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002516 mapping = dma_map_single(&bp->pdev->dev, skb->data,
2517 skb_headlen(skb), DMA_TO_DEVICE);
2518 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2519 rc = -ENOMEM;
2520 dev_kfree_skb(skb);
Merav Sicron51c1a582012-03-18 10:33:38 +00002521 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002522 goto test_loopback_exit;
2523 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002524
2525 /* send the loopback packet */
2526 num_pkts = 0;
Ariel Elior6383c0b2011-07-14 08:31:57 +00002527 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002528 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2529
Dmitry Kravkov73dbb5e2011-12-06 02:05:12 +00002530 netdev_tx_sent_queue(txq, skb->len);
2531
Ariel Elior6383c0b2011-07-14 08:31:57 +00002532 pkt_prod = txdata->tx_pkt_prod++;
2533 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2534 tx_buf->first_bd = txdata->tx_bd_prod;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002535 tx_buf->skb = skb;
2536 tx_buf->flags = 0;
2537
Ariel Elior6383c0b2011-07-14 08:31:57 +00002538 bd_prod = TX_BD(txdata->tx_bd_prod);
2539 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002540 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2541 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2542 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2543 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
Dmitry Kravkov523224a2010-10-06 03:23:26 +00002544 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002545 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
Dmitry Kravkov523224a2010-10-06 03:23:26 +00002546 SET_FLAG(tx_start_bd->general_data,
Dmitry Kravkov523224a2010-10-06 03:23:26 +00002547 ETH_TX_START_BD_HDR_NBDS,
2548 1);
Yuval Mintz96bed4b2012-10-01 03:46:19 +00002549 SET_FLAG(tx_start_bd->general_data,
2550 ETH_TX_START_BD_PARSE_NBDS,
2551 0);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002552
2553 /* turn on parsing and get a BD */
2554 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
Dmitry Kravkovf85582f2010-10-06 03:34:21 +00002555
Yuval Mintz96bed4b2012-10-01 03:46:19 +00002556 if (CHIP_IS_E1x(bp)) {
2557 u16 global_data = 0;
2558 struct eth_tx_parse_bd_e1x *pbd_e1x =
2559 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2560 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2561 SET_FLAG(global_data,
2562 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2563 pbd_e1x->global_data = cpu_to_le16(global_data);
2564 } else {
2565 u32 parsing_data = 0;
2566 struct eth_tx_parse_bd_e2 *pbd_e2 =
2567 &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2568 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2569 SET_FLAG(parsing_data,
2570 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2571 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2572 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002573 wmb();
2574
Ariel Elior6383c0b2011-07-14 08:31:57 +00002575 txdata->tx_db.data.prod += 2;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002576 barrier();
Ariel Elior6383c0b2011-07-14 08:31:57 +00002577 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002578
2579 mmiowb();
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002580 barrier();
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002581
2582 num_pkts++;
Ariel Elior6383c0b2011-07-14 08:31:57 +00002583 txdata->tx_bd_prod += 2; /* start + pbd */
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002584
2585 udelay(100);
2586
Ariel Elior6383c0b2011-07-14 08:31:57 +00002587 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002588 if (tx_idx != tx_start_idx + num_pkts)
2589 goto test_loopback_exit;
2590
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002591 /* Unlike HC IGU won't generate an interrupt for status block
2592 * updates that have been performed while interrupts were
2593 * disabled.
2594 */
Eric Dumazete1210d12010-11-24 03:45:10 +00002595 if (bp->common.int_block == INT_BLOCK_IGU) {
2596 /* Disable local BHes to prevent a dead-lock situation between
2597 * sch_direct_xmit() and bnx2x_run_loopback() (calling
2598 * bnx2x_tx_int()), as both are taking netif_tx_lock().
2599 */
2600 local_bh_disable();
Ariel Elior6383c0b2011-07-14 08:31:57 +00002601 bnx2x_tx_int(bp, txdata);
Eric Dumazete1210d12010-11-24 03:45:10 +00002602 local_bh_enable();
2603 }
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002604
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002605 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2606 if (rx_idx != rx_start_idx + num_pkts)
2607 goto test_loopback_exit;
2608
Dmitry Kravkovb0700b12012-01-23 07:31:53 +00002609 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002610 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002611 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2612 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002613 goto test_loopback_rx_exit;
2614
Dmitry Kravkov621b4d62012-02-20 09:59:08 +00002615 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002616 if (len != pkt_size)
2617 goto test_loopback_rx_exit;
2618
2619 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
Vladislav Zolotarov9924caf2011-07-19 01:37:42 +00002620 dma_sync_single_for_cpu(&bp->pdev->dev,
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002621 dma_unmap_addr(rx_buf, mapping),
2622 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
Eric Dumazete52fcb22011-11-14 06:05:34 +00002623 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002624 for (i = ETH_HLEN; i < pkt_size; i++)
Eric Dumazete52fcb22011-11-14 06:05:34 +00002625 if (*(data + i) != (unsigned char) (i & 0xff))
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002626 goto test_loopback_rx_exit;
2627
2628 rc = 0;
2629
2630test_loopback_rx_exit:
2631
2632 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2633 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2634 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2635 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2636
2637 /* Update producers */
2638 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2639 fp_rx->rx_sge_prod);
2640
2641test_loopback_exit:
2642 bp->link_params.loopback_mode = LOOPBACK_NONE;
2643
2644 return rc;
2645}
2646
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002647static int bnx2x_test_loopback(struct bnx2x *bp)
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002648{
2649 int rc = 0, res;
2650
2651 if (BP_NOMCP(bp))
2652 return rc;
2653
2654 if (!netif_running(bp->dev))
2655 return BNX2X_LOOPBACK_FAILED;
2656
2657 bnx2x_netif_stop(bp, 1);
2658 bnx2x_acquire_phy_lock(bp);
2659
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002660 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002661 if (res) {
Merav Sicron51c1a582012-03-18 10:33:38 +00002662 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002663 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2664 }
2665
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002666 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002667 if (res) {
Merav Sicron51c1a582012-03-18 10:33:38 +00002668 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002669 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2670 }
2671
2672 bnx2x_release_phy_lock(bp);
2673 bnx2x_netif_start(bp);
2674
2675 return rc;
2676}
2677
Merav Sicron8970b2e2012-06-19 07:48:22 +00002678static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2679{
2680 int rc;
2681 u8 is_serdes =
2682 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2683
2684 if (BP_NOMCP(bp))
2685 return -ENODEV;
2686
2687 if (!netif_running(bp->dev))
2688 return BNX2X_EXT_LOOPBACK_FAILED;
2689
Yuval Mintz5d07d862012-09-13 02:56:21 +00002690 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
Merav Sicron8970b2e2012-06-19 07:48:22 +00002691 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2692 if (rc) {
2693 DP(BNX2X_MSG_ETHTOOL,
2694 "Can't perform self-test, nic_load (for external lb) failed\n");
2695 return -ENODEV;
2696 }
2697 bnx2x_wait_for_link(bp, 1, is_serdes);
2698
2699 bnx2x_netif_stop(bp, 1);
2700
2701 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2702 if (rc)
2703 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc);
2704
2705 bnx2x_netif_start(bp);
2706
2707 return rc;
2708}
2709
Dmitry Kravkovedb944d2013-04-22 03:48:09 +00002710struct code_entry {
2711 u32 sram_start_addr;
2712 u32 code_attribute;
2713#define CODE_IMAGE_TYPE_MASK 0xf0800003
2714#define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003
2715#define CODE_IMAGE_LENGTH_MASK 0x007ffffc
2716#define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000
2717 u32 nvm_start_addr;
2718};
2719
2720#define CODE_ENTRY_MAX 16
2721#define CODE_ENTRY_EXTENDED_DIR_IDX 15
2722#define MAX_IMAGES_IN_EXTENDED_DIR 64
2723#define NVRAM_DIR_OFFSET 0x14
2724
2725#define EXTENDED_DIR_EXISTS(code) \
2726 ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
2727 (code & CODE_IMAGE_LENGTH_MASK) != 0)
2728
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002729#define CRC32_RESIDUAL 0xdebb20e3
Dmitry Kravkovedb944d2013-04-22 03:48:09 +00002730#define CRC_BUFF_SIZE 256
2731
2732static int bnx2x_nvram_crc(struct bnx2x *bp,
2733 int offset,
2734 int size,
2735 u8 *buff)
2736{
2737 u32 crc = ~0;
2738 int rc = 0, done = 0;
2739
2740 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2741 "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size);
2742
2743 while (done < size) {
2744 int count = min_t(int, size - done, CRC_BUFF_SIZE);
2745
2746 rc = bnx2x_nvram_read(bp, offset + done, buff, count);
2747
2748 if (rc)
2749 return rc;
2750
2751 crc = crc32_le(crc, buff, count);
2752 done += count;
2753 }
2754
2755 if (crc != CRC32_RESIDUAL)
2756 rc = -EINVAL;
2757
2758 return rc;
2759}
2760
2761static int bnx2x_test_nvram_dir(struct bnx2x *bp,
2762 struct code_entry *entry,
2763 u8 *buff)
2764{
2765 size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
2766 u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
2767 int rc;
2768
2769 /* Zero-length images and AFEX profiles do not have CRC */
2770 if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA)
2771 return 0;
2772
2773 rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff);
2774 if (rc)
2775 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2776 "image %x has failed crc test (rc %d)\n", type, rc);
2777
2778 return rc;
2779}
2780
2781static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff)
2782{
2783 int rc;
2784 struct code_entry entry;
2785
2786 rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry));
2787 if (rc)
2788 return rc;
2789
2790 return bnx2x_test_nvram_dir(bp, &entry, buff);
2791}
2792
2793static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
2794{
2795 u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
2796 struct code_entry entry;
2797 int i;
2798
2799 rc = bnx2x_nvram_read32(bp,
2800 dir_offset +
2801 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
2802 (u32 *)&entry, sizeof(entry));
2803 if (rc)
2804 return rc;
2805
2806 if (!EXTENDED_DIR_EXISTS(entry.code_attribute))
2807 return 0;
2808
2809 rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
2810 &cnt, sizeof(u32));
2811 if (rc)
2812 return rc;
2813
2814 dir_offset = entry.nvm_start_addr + 8;
2815
2816 for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) {
2817 rc = bnx2x_test_dir_entry(bp, dir_offset +
2818 sizeof(struct code_entry) * i,
2819 buff);
2820 if (rc)
2821 return rc;
2822 }
2823
2824 return 0;
2825}
2826
2827static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff)
2828{
2829 u32 rc, dir_offset = NVRAM_DIR_OFFSET;
2830 int i;
2831
2832 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
2833
2834 for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) {
2835 rc = bnx2x_test_dir_entry(bp, dir_offset +
2836 sizeof(struct code_entry) * i,
2837 buff);
2838 if (rc)
2839 return rc;
2840 }
2841
2842 return bnx2x_test_nvram_ext_dirs(bp, buff);
2843}
2844
2845struct crc_pair {
2846 int offset;
2847 int size;
2848};
2849
2850static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
2851 const struct crc_pair *nvram_tbl, u8 *buf)
2852{
2853 int i;
2854
2855 for (i = 0; nvram_tbl[i].size; i++) {
2856 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset,
2857 nvram_tbl[i].size, buf);
2858 if (rc) {
2859 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2860 "nvram_tbl[%d] has failed crc test (rc %d)\n",
2861 i, rc);
2862 return rc;
2863 }
2864 }
2865
2866 return 0;
2867}
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002868
2869static int bnx2x_test_nvram(struct bnx2x *bp)
2870{
Dmitry Kravkovedb944d2013-04-22 03:48:09 +00002871 const struct crc_pair nvram_tbl[] = {
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002872 { 0, 0x14 }, /* bootstrap */
2873 { 0x14, 0xec }, /* dir */
2874 { 0x100, 0x350 }, /* manuf_info */
2875 { 0x450, 0xf0 }, /* feature_info */
2876 { 0x640, 0x64 }, /* upgrade_key_info */
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002877 { 0x708, 0x70 }, /* manuf_key_info */
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002878 { 0, 0 }
2879 };
Dmitry Kravkovedb944d2013-04-22 03:48:09 +00002880 const struct crc_pair nvram_tbl2[] = {
2881 { 0x7e8, 0x350 }, /* manuf_info2 */
2882 { 0xb38, 0xf0 }, /* feature_info */
2883 { 0, 0 }
2884 };
2885
Dmitry Kravkov85640952013-04-22 03:48:06 +00002886 u8 *buf;
Dmitry Kravkovedb944d2013-04-22 03:48:09 +00002887 int rc;
2888 u32 magic;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002889
2890 if (BP_NOMCP(bp))
2891 return 0;
2892
Dmitry Kravkovedb944d2013-04-22 03:48:09 +00002893 buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL);
Mintz Yuvalafa13b42012-02-15 02:10:27 +00002894 if (!buf) {
Merav Sicron51c1a582012-03-18 10:33:38 +00002895 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
Mintz Yuvalafa13b42012-02-15 02:10:27 +00002896 rc = -ENOMEM;
2897 goto test_nvram_exit;
2898 }
Mintz Yuvalafa13b42012-02-15 02:10:27 +00002899
Dmitry Kravkov85640952013-04-22 03:48:06 +00002900 rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic));
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002901 if (rc) {
Merav Sicron51c1a582012-03-18 10:33:38 +00002902 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2903 "magic value read (rc %d)\n", rc);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002904 goto test_nvram_exit;
2905 }
2906
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002907 if (magic != 0x669955aa) {
Merav Sicron51c1a582012-03-18 10:33:38 +00002908 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2909 "wrong magic value (0x%08x)\n", magic);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002910 rc = -ENODEV;
2911 goto test_nvram_exit;
2912 }
2913
Dmitry Kravkovedb944d2013-04-22 03:48:09 +00002914 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n");
2915 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf);
2916 if (rc)
2917 goto test_nvram_exit;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002918
Dmitry Kravkovedb944d2013-04-22 03:48:09 +00002919 if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
2920 u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
2921 SHARED_HW_CFG_HIDE_PORT1;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002922
Dmitry Kravkovedb944d2013-04-22 03:48:09 +00002923 if (!hide) {
Merav Sicron51c1a582012-03-18 10:33:38 +00002924 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
Dmitry Kravkovedb944d2013-04-22 03:48:09 +00002925 "Port 1 CRC test-set\n");
2926 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf);
2927 if (rc)
2928 goto test_nvram_exit;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002929 }
2930 }
2931
Dmitry Kravkovedb944d2013-04-22 03:48:09 +00002932 rc = bnx2x_test_nvram_dirs(bp, buf);
2933
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002934test_nvram_exit:
Mintz Yuvalafa13b42012-02-15 02:10:27 +00002935 kfree(buf);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002936 return rc;
2937}
2938
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002939/* Send an EMPTY ramrod on the first queue */
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002940static int bnx2x_test_intr(struct bnx2x *bp)
2941{
Yuval Mintz3b603062012-03-18 10:33:39 +00002942 struct bnx2x_queue_state_params params = {NULL};
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002943
Merav Sicron51c1a582012-03-18 10:33:38 +00002944 if (!netif_running(bp->dev)) {
2945 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2946 "cannot access eeprom when the interface is down\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002947 return -ENODEV;
Merav Sicron51c1a582012-03-18 10:33:38 +00002948 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002949
Barak Witkowski15192a82012-06-19 07:48:28 +00002950 params.q_obj = &bp->sp_objs->q_obj;
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002951 params.cmd = BNX2X_Q_CMD_EMPTY;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002952
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002953 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002954
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002955 return bnx2x_queue_state_change(bp, &params);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002956}
2957
2958static void bnx2x_self_test(struct net_device *dev,
2959 struct ethtool_test *etest, u64 *buf)
2960{
2961 struct bnx2x *bp = netdev_priv(dev);
Yaniv Rosnera336ca72013-01-14 05:11:44 +00002962 u8 is_serdes, link_up;
2963 int rc, cnt = 0;
Merav Sicroncf2c1df62012-06-19 07:48:23 +00002964
Yuval Mintz909d9fa2015-04-22 12:47:32 +03002965 if (pci_num_vf(bp->pdev)) {
2966 DP(BNX2X_MSG_IOV,
2967 "VFs are enabled, can not perform self test\n");
2968 return;
2969 }
2970
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002971 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
Merav Sicron51c1a582012-03-18 10:33:38 +00002972 netdev_err(bp->dev,
2973 "Handling parity error recovery. Try again later\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002974 etest->flags |= ETH_TEST_FL_FAILED;
2975 return;
2976 }
Yuval Mintz2de67432013-01-23 03:21:43 +00002977
Merav Sicron8970b2e2012-06-19 07:48:22 +00002978 DP(BNX2X_MSG_ETHTOOL,
2979 "Self-test command parameters: offline = %d, external_lb = %d\n",
2980 (etest->flags & ETH_TEST_FL_OFFLINE),
2981 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002982
Merav Sicroncf2c1df62012-06-19 07:48:23 +00002983 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002984
Yuval Mintzbd8e0122013-09-28 08:46:07 +03002985 if (bnx2x_test_nvram(bp) != 0) {
2986 if (!IS_MF(bp))
2987 buf[4] = 1;
2988 else
2989 buf[0] = 1;
2990 etest->flags |= ETH_TEST_FL_FAILED;
2991 }
2992
Merav Sicroncf2c1df62012-06-19 07:48:23 +00002993 if (!netif_running(dev)) {
Yuval Mintzbd8e0122013-09-28 08:46:07 +03002994 DP(BNX2X_MSG_ETHTOOL, "Interface is down\n");
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002995 return;
Merav Sicroncf2c1df62012-06-19 07:48:23 +00002996 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00002997
Yaniv Rosnera22f0782010-09-07 11:41:20 +00002998 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
Yaniv Rosnera336ca72013-01-14 05:11:44 +00002999 link_up = bp->link_vars.link_up;
Merav Sicroncf2c1df62012-06-19 07:48:23 +00003000 /* offline tests are not supported in MF mode */
3001 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003002 int port = BP_PORT(bp);
3003 u32 val;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003004
3005 /* save current value of input enable for TX port IF */
3006 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
3007 /* disable input for TX port IF */
3008 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
3009
Yuval Mintz5d07d862012-09-13 02:56:21 +00003010 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
Merav Sicroncf2c1df62012-06-19 07:48:23 +00003011 rc = bnx2x_nic_load(bp, LOAD_DIAG);
3012 if (rc) {
3013 etest->flags |= ETH_TEST_FL_FAILED;
3014 DP(BNX2X_MSG_ETHTOOL,
3015 "Can't perform self-test, nic_load (for offline) failed\n");
3016 return;
3017 }
3018
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003019 /* wait until link state is restored */
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03003020 bnx2x_wait_for_link(bp, 1, is_serdes);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003021
3022 if (bnx2x_test_registers(bp) != 0) {
3023 buf[0] = 1;
3024 etest->flags |= ETH_TEST_FL_FAILED;
3025 }
3026 if (bnx2x_test_memory(bp) != 0) {
3027 buf[1] = 1;
3028 etest->flags |= ETH_TEST_FL_FAILED;
3029 }
Dmitry Kravkovf85582f2010-10-06 03:34:21 +00003030
Merav Sicron8970b2e2012-06-19 07:48:22 +00003031 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003032 if (buf[2] != 0)
3033 etest->flags |= ETH_TEST_FL_FAILED;
3034
Merav Sicron8970b2e2012-06-19 07:48:22 +00003035 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
3036 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
3037 if (buf[3] != 0)
3038 etest->flags |= ETH_TEST_FL_FAILED;
3039 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
3040 }
3041
Yuval Mintz5d07d862012-09-13 02:56:21 +00003042 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003043
3044 /* restore input for TX port IF */
3045 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
Merav Sicroncf2c1df62012-06-19 07:48:23 +00003046 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
3047 if (rc) {
3048 etest->flags |= ETH_TEST_FL_FAILED;
3049 DP(BNX2X_MSG_ETHTOOL,
3050 "Can't perform self-test, nic_load (for online) failed\n");
3051 return;
3052 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003053 /* wait until link state is restored */
Yaniv Rosnera22f0782010-09-07 11:41:20 +00003054 bnx2x_wait_for_link(bp, link_up, is_serdes);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003055 }
Yuval Mintzbd8e0122013-09-28 08:46:07 +03003056
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003057 if (bnx2x_test_intr(bp) != 0) {
Merav Sicroncf2c1df62012-06-19 07:48:23 +00003058 if (!IS_MF(bp))
3059 buf[5] = 1;
3060 else
3061 buf[1] = 1;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003062 etest->flags |= ETH_TEST_FL_FAILED;
3063 }
Dmitry Kravkov633ac362011-02-28 03:37:12 +00003064
Yaniv Rosnera336ca72013-01-14 05:11:44 +00003065 if (link_up) {
3066 cnt = 100;
3067 while (bnx2x_link_test(bp, is_serdes) && --cnt)
3068 msleep(20);
3069 }
3070
3071 if (!cnt) {
Merav Sicroncf2c1df62012-06-19 07:48:23 +00003072 if (!IS_MF(bp))
3073 buf[6] = 1;
3074 else
3075 buf[2] = 1;
Dmitry Kravkov633ac362011-02-28 03:37:12 +00003076 etest->flags |= ETH_TEST_FL_FAILED;
3077 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003078}
3079
Michal Schmidt44c33c62015-12-04 17:22:36 +01003080#define IS_PORT_STAT(i) (bnx2x_stats_arr[i].is_port_stat)
Yuval Mintz3fb2d492015-11-19 17:04:36 +02003081#define HIDE_PORT_STAT(bp) IS_VF(bp)
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003082
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03003083/* ethtool statistics are displayed for all regular ethernet queues and the
3084 * fcoe L2 queue if not disabled
3085 */
Eric Dumazet1191cb82012-04-27 21:39:21 +00003086static int bnx2x_num_stat_queues(struct bnx2x *bp)
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03003087{
3088 return BNX2X_NUM_ETH_QUEUES(bp);
3089}
3090
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003091static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
3092{
3093 struct bnx2x *bp = netdev_priv(dev);
Yuval Mintz3521b4192013-05-22 21:21:49 +00003094 int i, num_strings = 0;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003095
3096 switch (stringset) {
3097 case ETH_SS_STATS:
3098 if (is_multi(bp)) {
Yuval Mintz3521b4192013-05-22 21:21:49 +00003099 num_strings = bnx2x_num_stat_queues(bp) *
3100 BNX2X_NUM_Q_STATS;
Yuval Mintzd5e83632012-01-23 07:31:52 +00003101 } else
Yuval Mintz3521b4192013-05-22 21:21:49 +00003102 num_strings = 0;
Yuval Mintzd8361052014-03-23 18:12:26 +02003103 if (HIDE_PORT_STAT(bp)) {
Yuval Mintzd5e83632012-01-23 07:31:52 +00003104 for (i = 0; i < BNX2X_NUM_STATS; i++)
Michal Schmidt44c33c62015-12-04 17:22:36 +01003105 if (!IS_PORT_STAT(i))
Yuval Mintz3521b4192013-05-22 21:21:49 +00003106 num_strings++;
Yuval Mintzd5e83632012-01-23 07:31:52 +00003107 } else
Yuval Mintz3521b4192013-05-22 21:21:49 +00003108 num_strings += BNX2X_NUM_STATS;
Yuval Mintzd5e83632012-01-23 07:31:52 +00003109
Yuval Mintz3521b4192013-05-22 21:21:49 +00003110 return num_strings;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003111
3112 case ETH_SS_TEST:
Merav Sicroncf2c1df62012-06-19 07:48:23 +00003113 return BNX2X_NUM_TESTS(bp);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003114
Yuval Mintz3521b4192013-05-22 21:21:49 +00003115 case ETH_SS_PRIV_FLAGS:
3116 return BNX2X_PRI_FLAG_LEN;
3117
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003118 default:
3119 return -EINVAL;
3120 }
3121}
3122
Yuval Mintz3521b4192013-05-22 21:21:49 +00003123static u32 bnx2x_get_private_flags(struct net_device *dev)
3124{
3125 struct bnx2x *bp = netdev_priv(dev);
3126 u32 flags = 0;
3127
3128 flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI;
3129 flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE;
3130 flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE;
3131
3132 return flags;
3133}
3134
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003135static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
3136{
3137 struct bnx2x *bp = netdev_priv(dev);
Merav Sicron58893352012-09-23 03:12:23 +00003138 int i, j, k, start;
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +00003139 char queue_name[MAX_QUEUE_NAME_LEN+1];
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003140
3141 switch (stringset) {
3142 case ETH_SS_STATS:
Yuval Mintzd5e83632012-01-23 07:31:52 +00003143 k = 0;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003144 if (is_multi(bp)) {
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03003145 for_each_eth_queue(bp, i) {
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +00003146 memset(queue_name, 0, sizeof(queue_name));
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03003147 sprintf(queue_name, "%d", i);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003148 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
Vladislav Zolotarovec6ba942010-12-13 05:44:01 +00003149 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
3150 ETH_GSTRING_LEN,
3151 bnx2x_q_stats_arr[j].string,
3152 queue_name);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003153 k += BNX2X_NUM_Q_STATS;
3154 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003155 }
Yuval Mintzd5e83632012-01-23 07:31:52 +00003156
Yuval Mintzd5e83632012-01-23 07:31:52 +00003157 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
Yuval Mintzd8361052014-03-23 18:12:26 +02003158 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
Yuval Mintzd5e83632012-01-23 07:31:52 +00003159 continue;
3160 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
3161 bnx2x_stats_arr[i].string);
3162 j++;
3163 }
3164
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003165 break;
3166
3167 case ETH_SS_TEST:
Merav Sicroncf2c1df62012-06-19 07:48:23 +00003168 /* First 4 tests cannot be done in MF mode */
3169 if (!IS_MF(bp))
3170 start = 0;
3171 else
3172 start = 4;
Merav Sicron58893352012-09-23 03:12:23 +00003173 memcpy(buf, bnx2x_tests_str_arr + start,
3174 ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
Yuval Mintz3521b4192013-05-22 21:21:49 +00003175 break;
3176
3177 case ETH_SS_PRIV_FLAGS:
3178 memcpy(buf, bnx2x_private_arr,
3179 ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN);
3180 break;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003181 }
3182}
3183
3184static void bnx2x_get_ethtool_stats(struct net_device *dev,
3185 struct ethtool_stats *stats, u64 *buf)
3186{
3187 struct bnx2x *bp = netdev_priv(dev);
3188 u32 *hw_stats, *offset;
Yuval Mintzd5e83632012-01-23 07:31:52 +00003189 int i, j, k = 0;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003190
3191 if (is_multi(bp)) {
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03003192 for_each_eth_queue(bp, i) {
Barak Witkowski15192a82012-06-19 07:48:28 +00003193 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003194 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
3195 if (bnx2x_q_stats_arr[j].size == 0) {
3196 /* skip this counter */
3197 buf[k + j] = 0;
3198 continue;
3199 }
3200 offset = (hw_stats +
3201 bnx2x_q_stats_arr[j].offset);
3202 if (bnx2x_q_stats_arr[j].size == 4) {
3203 /* 4-byte counter */
3204 buf[k + j] = (u64) *offset;
3205 continue;
3206 }
3207 /* 8-byte counter */
3208 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3209 }
3210 k += BNX2X_NUM_Q_STATS;
3211 }
Yuval Mintzd5e83632012-01-23 07:31:52 +00003212 }
3213
3214 hw_stats = (u32 *)&bp->eth_stats;
3215 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
Yuval Mintzd8361052014-03-23 18:12:26 +02003216 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
Yuval Mintzd5e83632012-01-23 07:31:52 +00003217 continue;
3218 if (bnx2x_stats_arr[i].size == 0) {
3219 /* skip this counter */
3220 buf[k + j] = 0;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003221 j++;
Yuval Mintzd5e83632012-01-23 07:31:52 +00003222 continue;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003223 }
Yuval Mintzd5e83632012-01-23 07:31:52 +00003224 offset = (hw_stats + bnx2x_stats_arr[i].offset);
3225 if (bnx2x_stats_arr[i].size == 4) {
3226 /* 4-byte counter */
3227 buf[k + j] = (u64) *offset;
3228 j++;
3229 continue;
3230 }
3231 /* 8-byte counter */
3232 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3233 j++;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003234 }
3235}
3236
stephen hemminger32d36132011-04-04 11:06:37 +00003237static int bnx2x_set_phys_id(struct net_device *dev,
3238 enum ethtool_phys_id_state state)
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003239{
3240 struct bnx2x *bp = netdev_priv(dev);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003241
Yuval Mintz3fb43eb2013-05-27 04:08:31 +00003242 if (!bnx2x_is_nvm_accessible(bp)) {
Merav Sicron51c1a582012-03-18 10:33:38 +00003243 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
3244 "cannot access eeprom when the interface is down\n");
stephen hemminger32d36132011-04-04 11:06:37 +00003245 return -EAGAIN;
Merav Sicron51c1a582012-03-18 10:33:38 +00003246 }
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003247
stephen hemminger32d36132011-04-04 11:06:37 +00003248 switch (state) {
3249 case ETHTOOL_ID_ACTIVE:
Allan, Bruce Wfce55922011-04-13 13:09:10 +00003250 return 1; /* cycle on/off once per second */
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003251
stephen hemminger32d36132011-04-04 11:06:37 +00003252 case ETHTOOL_ID_ON:
Yaniv Rosner8203c4b2012-11-27 03:46:33 +00003253 bnx2x_acquire_phy_lock(bp);
stephen hemminger32d36132011-04-04 11:06:37 +00003254 bnx2x_set_led(&bp->link_params, &bp->link_vars,
David S. Millere1943422011-04-19 00:21:33 -07003255 LED_MODE_ON, SPEED_1000);
Yaniv Rosner8203c4b2012-11-27 03:46:33 +00003256 bnx2x_release_phy_lock(bp);
stephen hemminger32d36132011-04-04 11:06:37 +00003257 break;
3258
3259 case ETHTOOL_ID_OFF:
Yaniv Rosner8203c4b2012-11-27 03:46:33 +00003260 bnx2x_acquire_phy_lock(bp);
stephen hemminger32d36132011-04-04 11:06:37 +00003261 bnx2x_set_led(&bp->link_params, &bp->link_vars,
David S. Millere1943422011-04-19 00:21:33 -07003262 LED_MODE_FRONT_PANEL_OFF, 0);
Yaniv Rosner8203c4b2012-11-27 03:46:33 +00003263 bnx2x_release_phy_lock(bp);
stephen hemminger32d36132011-04-04 11:06:37 +00003264 break;
3265
3266 case ETHTOOL_ID_INACTIVE:
Yaniv Rosner8203c4b2012-11-27 03:46:33 +00003267 bnx2x_acquire_phy_lock(bp);
David S. Millere1943422011-04-19 00:21:33 -07003268 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3269 LED_MODE_OPER,
3270 bp->link_vars.line_speed);
Yaniv Rosner8203c4b2012-11-27 03:46:33 +00003271 bnx2x_release_phy_lock(bp);
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003272 }
3273
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003274 return 0;
3275}
3276
Merav Sicron5d317c6a2012-06-19 07:48:24 +00003277static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3278{
Merav Sicron5d317c6a2012-06-19 07:48:24 +00003279 switch (info->flow_type) {
3280 case TCP_V4_FLOW:
3281 case TCP_V6_FLOW:
3282 info->data = RXH_IP_SRC | RXH_IP_DST |
3283 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3284 break;
3285 case UDP_V4_FLOW:
3286 if (bp->rss_conf_obj.udp_rss_v4)
3287 info->data = RXH_IP_SRC | RXH_IP_DST |
3288 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3289 else
3290 info->data = RXH_IP_SRC | RXH_IP_DST;
3291 break;
3292 case UDP_V6_FLOW:
3293 if (bp->rss_conf_obj.udp_rss_v6)
3294 info->data = RXH_IP_SRC | RXH_IP_DST |
3295 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3296 else
3297 info->data = RXH_IP_SRC | RXH_IP_DST;
3298 break;
3299 case IPV4_FLOW:
3300 case IPV6_FLOW:
3301 info->data = RXH_IP_SRC | RXH_IP_DST;
3302 break;
3303 default:
3304 info->data = 0;
3305 break;
3306 }
3307
3308 return 0;
3309}
3310
Tom Herbertab532cf2011-02-16 10:27:02 +00003311static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
Ben Hutchings815c7db2011-09-06 13:49:12 +00003312 u32 *rules __always_unused)
Tom Herbertab532cf2011-02-16 10:27:02 +00003313{
3314 struct bnx2x *bp = netdev_priv(dev);
3315
3316 switch (info->cmd) {
3317 case ETHTOOL_GRXRINGS:
3318 info->data = BNX2X_NUM_ETH_QUEUES(bp);
3319 return 0;
Merav Sicron5d317c6a2012-06-19 07:48:24 +00003320 case ETHTOOL_GRXFH:
3321 return bnx2x_get_rss_flags(bp, info);
3322 default:
3323 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3324 return -EOPNOTSUPP;
3325 }
3326}
Tom Herbertab532cf2011-02-16 10:27:02 +00003327
Merav Sicron5d317c6a2012-06-19 07:48:24 +00003328static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3329{
3330 int udp_rss_requested;
3331
3332 DP(BNX2X_MSG_ETHTOOL,
3333 "Set rss flags command parameters: flow type = %d, data = %llu\n",
3334 info->flow_type, info->data);
3335
3336 switch (info->flow_type) {
3337 case TCP_V4_FLOW:
3338 case TCP_V6_FLOW:
3339 /* For TCP only 4-tupple hash is supported */
3340 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
3341 RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
3342 DP(BNX2X_MSG_ETHTOOL,
3343 "Command parameters not supported\n");
3344 return -EINVAL;
Merav Sicron5d317c6a2012-06-19 07:48:24 +00003345 }
Yuval Mintz2de67432013-01-23 03:21:43 +00003346 return 0;
Merav Sicron5d317c6a2012-06-19 07:48:24 +00003347
3348 case UDP_V4_FLOW:
3349 case UDP_V6_FLOW:
3350 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
3351 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
Yuval Mintz2de67432013-01-23 03:21:43 +00003352 RXH_L4_B_0_1 | RXH_L4_B_2_3))
Merav Sicron5d317c6a2012-06-19 07:48:24 +00003353 udp_rss_requested = 1;
3354 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
3355 udp_rss_requested = 0;
3356 else
3357 return -EINVAL;
Yuval Mintzf9468e82015-10-08 16:19:01 +03003358
3359 if (CHIP_IS_E1x(bp) && udp_rss_requested) {
3360 DP(BNX2X_MSG_ETHTOOL,
3361 "57710, 57711 boards don't support RSS according to UDP 4-tuple\n");
3362 return -EINVAL;
3363 }
3364
Merav Sicron5d317c6a2012-06-19 07:48:24 +00003365 if ((info->flow_type == UDP_V4_FLOW) &&
3366 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3367 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3368 DP(BNX2X_MSG_ETHTOOL,
3369 "rss re-configured, UDP 4-tupple %s\n",
3370 udp_rss_requested ? "enabled" : "disabled");
Sudarsana Reddy Kalluru32680dc2018-07-24 02:43:52 -07003371 if (bp->state == BNX2X_STATE_OPEN)
3372 return bnx2x_rss(bp, &bp->rss_conf_obj, false,
3373 true);
Merav Sicron5d317c6a2012-06-19 07:48:24 +00003374 } else if ((info->flow_type == UDP_V6_FLOW) &&
3375 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3376 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
Merav Sicron5d317c6a2012-06-19 07:48:24 +00003377 DP(BNX2X_MSG_ETHTOOL,
3378 "rss re-configured, UDP 4-tupple %s\n",
3379 udp_rss_requested ? "enabled" : "disabled");
Sudarsana Reddy Kalluru32680dc2018-07-24 02:43:52 -07003380 if (bp->state == BNX2X_STATE_OPEN)
3381 return bnx2x_rss(bp, &bp->rss_conf_obj, false,
3382 true);
Merav Sicron5d317c6a2012-06-19 07:48:24 +00003383 }
Yuval Mintz924d75a2013-01-23 03:21:44 +00003384 return 0;
3385
Merav Sicron5d317c6a2012-06-19 07:48:24 +00003386 case IPV4_FLOW:
3387 case IPV6_FLOW:
3388 /* For IP only 2-tupple hash is supported */
3389 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3390 DP(BNX2X_MSG_ETHTOOL,
3391 "Command parameters not supported\n");
3392 return -EINVAL;
Merav Sicron5d317c6a2012-06-19 07:48:24 +00003393 }
Yuval Mintz924d75a2013-01-23 03:21:44 +00003394 return 0;
3395
Merav Sicron5d317c6a2012-06-19 07:48:24 +00003396 case SCTP_V4_FLOW:
3397 case AH_ESP_V4_FLOW:
3398 case AH_V4_FLOW:
3399 case ESP_V4_FLOW:
3400 case SCTP_V6_FLOW:
3401 case AH_ESP_V6_FLOW:
3402 case AH_V6_FLOW:
3403 case ESP_V6_FLOW:
3404 case IP_USER_FLOW:
3405 case ETHER_FLOW:
3406 /* RSS is not supported for these protocols */
3407 if (info->data) {
3408 DP(BNX2X_MSG_ETHTOOL,
3409 "Command parameters not supported\n");
3410 return -EINVAL;
Merav Sicron5d317c6a2012-06-19 07:48:24 +00003411 }
Yuval Mintz924d75a2013-01-23 03:21:44 +00003412 return 0;
3413
Merav Sicron5d317c6a2012-06-19 07:48:24 +00003414 default:
3415 return -EINVAL;
3416 }
3417}
3418
3419static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3420{
3421 struct bnx2x *bp = netdev_priv(dev);
3422
3423 switch (info->cmd) {
3424 case ETHTOOL_SRXFH:
3425 return bnx2x_set_rss_flags(bp, info);
Tom Herbertab532cf2011-02-16 10:27:02 +00003426 default:
Merav Sicron51c1a582012-03-18 10:33:38 +00003427 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
Tom Herbertab532cf2011-02-16 10:27:02 +00003428 return -EOPNOTSUPP;
3429 }
3430}
3431
Ben Hutchings7850f632011-12-15 13:55:01 +00003432static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
Tom Herbertab532cf2011-02-16 10:27:02 +00003433{
Dmitry Kravkov96305232012-04-03 18:41:30 +00003434 return T_ETH_INDIRECTION_TABLE_SIZE;
Ben Hutchings7850f632011-12-15 13:55:01 +00003435}
3436
Eyal Perry892311f2014-12-02 18:12:10 +02003437static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3438 u8 *hfunc)
Ben Hutchings7850f632011-12-15 13:55:01 +00003439{
3440 struct bnx2x *bp = netdev_priv(dev);
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03003441 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3442 size_t i;
Tom Herbertab532cf2011-02-16 10:27:02 +00003443
Eyal Perry892311f2014-12-02 18:12:10 +02003444 if (hfunc)
3445 *hfunc = ETH_RSS_HASH_TOP;
3446 if (!indir)
3447 return 0;
3448
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03003449 /* Get the current configuration of the RSS indirection table */
3450 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3451
3452 /*
3453 * We can't use a memcpy() as an internal storage of an
3454 * indirection table is a u8 array while indir->ring_index
3455 * points to an array of u32.
3456 *
3457 * Indirection table contains the FW Client IDs, so we need to
3458 * align the returned table to the Client ID of the leading RSS
3459 * queue.
3460 */
Ben Hutchings7850f632011-12-15 13:55:01 +00003461 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3462 indir[i] = ind_table[i] - bp->fp->cl_id;
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03003463
Tom Herbertab532cf2011-02-16 10:27:02 +00003464 return 0;
3465}
3466
Ben Hutchingsfe62d002014-05-15 01:25:27 +01003467static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir,
Eyal Perry892311f2014-12-02 18:12:10 +02003468 const u8 *key, const u8 hfunc)
Tom Herbertab532cf2011-02-16 10:27:02 +00003469{
3470 struct bnx2x *bp = netdev_priv(dev);
3471 size_t i;
Tom Herbertab532cf2011-02-16 10:27:02 +00003472
Eyal Perry892311f2014-12-02 18:12:10 +02003473 /* We require at least one supported parameter to be changed and no
3474 * change in any of the unsupported parameters
3475 */
3476 if (key ||
3477 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3478 return -EOPNOTSUPP;
3479
3480 if (!indir)
3481 return 0;
3482
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03003483 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03003484 /*
Ben Hutchingsfe62d002014-05-15 01:25:27 +01003485 * The same as in bnx2x_get_rxfh: we can't use a memcpy()
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03003486 * as an internal storage of an indirection table is a u8 array
3487 * while indir->ring_index points to an array of u32.
3488 *
3489 * Indirection table contains the FW Client IDs, so we need to
3490 * align the received table to the Client ID of the leading RSS
3491 * queue
3492 */
Merav Sicron5d317c6a2012-06-19 07:48:24 +00003493 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03003494 }
3495
Sudarsana Reddy Kalluru32680dc2018-07-24 02:43:52 -07003496 if (bp->state == BNX2X_STATE_OPEN)
3497 return bnx2x_config_rss_eth(bp, false);
3498
3499 return 0;
Tom Herbertab532cf2011-02-16 10:27:02 +00003500}
3501
Merav Sicron0e8d2ec2012-06-19 07:48:30 +00003502/**
3503 * bnx2x_get_channels - gets the number of RSS queues.
3504 *
3505 * @dev: net device
3506 * @channels: returns the number of max / current queues
3507 */
3508static void bnx2x_get_channels(struct net_device *dev,
3509 struct ethtool_channels *channels)
3510{
3511 struct bnx2x *bp = netdev_priv(dev);
3512
3513 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3514 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3515}
3516
3517/**
3518 * bnx2x_change_num_queues - change the number of RSS queues.
3519 *
3520 * @bp: bnx2x private structure
3521 *
3522 * Re-configure interrupt mode to get the new number of MSI-X
3523 * vectors and re-add NAPI objects.
3524 */
3525static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3526{
Merav Sicron0e8d2ec2012-06-19 07:48:30 +00003527 bnx2x_disable_msi(bp);
Merav Sicron55c11942012-11-07 00:45:48 +00003528 bp->num_ethernet_queues = num_rss;
3529 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3530 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
Merav Sicron0e8d2ec2012-06-19 07:48:30 +00003531 bnx2x_set_int_mode(bp);
Merav Sicron0e8d2ec2012-06-19 07:48:30 +00003532}
3533
3534/**
3535 * bnx2x_set_channels - sets the number of RSS queues.
3536 *
3537 * @dev: net device
3538 * @channels: includes the number of queues requested
3539 */
3540static int bnx2x_set_channels(struct net_device *dev,
3541 struct ethtool_channels *channels)
3542{
3543 struct bnx2x *bp = netdev_priv(dev);
3544
Merav Sicron0e8d2ec2012-06-19 07:48:30 +00003545 DP(BNX2X_MSG_ETHTOOL,
3546 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3547 channels->rx_count, channels->tx_count, channels->other_count,
3548 channels->combined_count);
3549
Yuval Mintz909d9fa2015-04-22 12:47:32 +03003550 if (pci_num_vf(bp->pdev)) {
3551 DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n");
3552 return -EPERM;
3553 }
3554
Merav Sicron0e8d2ec2012-06-19 07:48:30 +00003555 /* We don't support separate rx / tx channels.
3556 * We don't allow setting 'other' channels.
3557 */
3558 if (channels->rx_count || channels->tx_count || channels->other_count
3559 || (channels->combined_count == 0) ||
3560 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3561 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3562 return -EINVAL;
3563 }
3564
3565 /* Check if there was a change in the active parameters */
3566 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3567 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3568 return 0;
3569 }
3570
3571 /* Set the requested number of queues in bp context.
3572 * Note that the actual number of queues created during load may be
3573 * less than requested if memory is low.
3574 */
3575 if (unlikely(!netif_running(dev))) {
3576 bnx2x_change_num_queues(bp, channels->combined_count);
3577 return 0;
3578 }
Yuval Mintz5d07d862012-09-13 02:56:21 +00003579 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
Merav Sicron0e8d2ec2012-06-19 07:48:30 +00003580 bnx2x_change_num_queues(bp, channels->combined_count);
3581 return bnx2x_nic_load(bp, LOAD_NORMAL);
3582}
3583
Michal Kalderoneeed0182014-08-17 16:47:44 +03003584static int bnx2x_get_ts_info(struct net_device *dev,
3585 struct ethtool_ts_info *info)
3586{
3587 struct bnx2x *bp = netdev_priv(dev);
3588
3589 if (bp->flags & PTP_SUPPORTED) {
3590 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
3591 SOF_TIMESTAMPING_RX_SOFTWARE |
3592 SOF_TIMESTAMPING_SOFTWARE |
3593 SOF_TIMESTAMPING_TX_HARDWARE |
3594 SOF_TIMESTAMPING_RX_HARDWARE |
3595 SOF_TIMESTAMPING_RAW_HARDWARE;
3596
3597 if (bp->ptp_clock)
3598 info->phc_index = ptp_clock_index(bp->ptp_clock);
3599 else
3600 info->phc_index = -1;
3601
3602 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3603 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
Michal Kalderoneeed0182014-08-17 16:47:44 +03003604 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
Jacob Kellerdd3950c2015-04-22 14:40:32 -07003605 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
Michal Kalderoneeed0182014-08-17 16:47:44 +03003606
3607 info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON);
3608
3609 return 0;
3610 }
3611
3612 return ethtool_op_get_ts_info(dev, info);
3613}
3614
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003615static const struct ethtool_ops bnx2x_ethtool_ops = {
3616 .get_settings = bnx2x_get_settings,
3617 .set_settings = bnx2x_set_settings,
3618 .get_drvinfo = bnx2x_get_drvinfo,
3619 .get_regs_len = bnx2x_get_regs_len,
3620 .get_regs = bnx2x_get_regs,
Miriam Shitrit07ba6af2013-01-14 05:11:46 +00003621 .get_dump_flag = bnx2x_get_dump_flag,
3622 .get_dump_data = bnx2x_get_dump_data,
3623 .set_dump = bnx2x_set_dump,
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003624 .get_wol = bnx2x_get_wol,
3625 .set_wol = bnx2x_set_wol,
3626 .get_msglevel = bnx2x_get_msglevel,
3627 .set_msglevel = bnx2x_set_msglevel,
3628 .nway_reset = bnx2x_nway_reset,
3629 .get_link = bnx2x_get_link,
3630 .get_eeprom_len = bnx2x_get_eeprom_len,
3631 .get_eeprom = bnx2x_get_eeprom,
3632 .set_eeprom = bnx2x_set_eeprom,
3633 .get_coalesce = bnx2x_get_coalesce,
3634 .set_coalesce = bnx2x_set_coalesce,
3635 .get_ringparam = bnx2x_get_ringparam,
3636 .set_ringparam = bnx2x_set_ringparam,
3637 .get_pauseparam = bnx2x_get_pauseparam,
3638 .set_pauseparam = bnx2x_set_pauseparam,
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003639 .self_test = bnx2x_self_test,
3640 .get_sset_count = bnx2x_get_sset_count,
Yuval Mintz3521b4192013-05-22 21:21:49 +00003641 .get_priv_flags = bnx2x_get_private_flags,
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003642 .get_strings = bnx2x_get_strings,
stephen hemminger32d36132011-04-04 11:06:37 +00003643 .set_phys_id = bnx2x_set_phys_id,
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003644 .get_ethtool_stats = bnx2x_get_ethtool_stats,
Tom Herbertab532cf2011-02-16 10:27:02 +00003645 .get_rxnfc = bnx2x_get_rxnfc,
Merav Sicron5d317c6a2012-06-19 07:48:24 +00003646 .set_rxnfc = bnx2x_set_rxnfc,
Ben Hutchings7850f632011-12-15 13:55:01 +00003647 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
Ben Hutchingsfe62d002014-05-15 01:25:27 +01003648 .get_rxfh = bnx2x_get_rxfh,
3649 .set_rxfh = bnx2x_set_rxfh,
Merav Sicron0e8d2ec2012-06-19 07:48:30 +00003650 .get_channels = bnx2x_get_channels,
3651 .set_channels = bnx2x_set_channels,
Yuval Mintz24ea8182012-06-20 19:05:23 +00003652 .get_module_info = bnx2x_get_module_info,
3653 .get_module_eeprom = bnx2x_get_module_eeprom,
Yuval Mintze9939c82012-06-06 17:13:08 +00003654 .get_eee = bnx2x_get_eee,
3655 .set_eee = bnx2x_set_eee,
Michal Kalderoneeed0182014-08-17 16:47:44 +03003656 .get_ts_info = bnx2x_get_ts_info,
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003657};
3658
Ariel Elior005a07ba2013-03-11 05:17:42 +00003659static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
Dmitry Kravkov6495d152014-06-26 14:31:04 +03003660 .get_settings = bnx2x_get_vf_settings,
Ariel Elior005a07ba2013-03-11 05:17:42 +00003661 .get_drvinfo = bnx2x_get_drvinfo,
3662 .get_msglevel = bnx2x_get_msglevel,
3663 .set_msglevel = bnx2x_set_msglevel,
3664 .get_link = bnx2x_get_link,
3665 .get_coalesce = bnx2x_get_coalesce,
3666 .get_ringparam = bnx2x_get_ringparam,
3667 .set_ringparam = bnx2x_set_ringparam,
3668 .get_sset_count = bnx2x_get_sset_count,
3669 .get_strings = bnx2x_get_strings,
3670 .get_ethtool_stats = bnx2x_get_ethtool_stats,
3671 .get_rxnfc = bnx2x_get_rxnfc,
3672 .set_rxnfc = bnx2x_set_rxnfc,
3673 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
Ben Hutchingsfe62d002014-05-15 01:25:27 +01003674 .get_rxfh = bnx2x_get_rxfh,
3675 .set_rxfh = bnx2x_set_rxfh,
Ariel Elior005a07ba2013-03-11 05:17:42 +00003676 .get_channels = bnx2x_get_channels,
3677 .set_channels = bnx2x_set_channels,
3678};
3679
3680void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev)
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003681{
Wilfried Klaebe7ad24ea2014-05-11 00:12:32 +00003682 netdev->ethtool_ops = (IS_PF(bp)) ?
3683 &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops;
Dmitry Kravkovde0c62d2010-07-27 12:35:24 +00003684}