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Graf Yang0b39db22009-12-28 11:13:51 +00001/*
2 * Copyright 2007-2009 Analog Devices Inc.
3 * Graff Yang <graf.yang@analog.com>
4 *
5 * Licensed under the GPL-2 or later.
6 */
7
Graf Yang6f546bc2010-01-28 10:46:55 +00008#include <linux/smp.h>
Graf Yang0b39db22009-12-28 11:13:51 +00009#include <asm/blackfin.h>
Graf Yang1e924e22010-03-19 08:01:27 +000010#include <asm/cacheflush.h>
Graf Yang6f546bc2010-01-28 10:46:55 +000011#include <mach/pll.h>
Graf Yang0b39db22009-12-28 11:13:51 +000012
13int hotplug_coreb;
14
15void platform_cpu_die(void)
16{
Graf Yang6f546bc2010-01-28 10:46:55 +000017 unsigned long iwr;
Graf Yang1e924e22010-03-19 08:01:27 +000018
Graf Yang0b39db22009-12-28 11:13:51 +000019 hotplug_coreb = 1;
20
Graf Yang1e924e22010-03-19 08:01:27 +000021 /*
22 * When CoreB wakes up, the code in _coreb_trampoline_start cannot
23 * turn off the data cache. This causes the CoreB failed to boot.
24 * As a workaround, we invalidate all the data cache before sleep.
25 */
26 blackfin_invalidate_entire_dcache();
27
Graf Yang0b39db22009-12-28 11:13:51 +000028 /* disable core timer */
29 bfin_write_TCNTL(0);
30
Graf Yang6f546bc2010-01-28 10:46:55 +000031 /* clear ipi interrupt IRQ_SUPPLE_0 of CoreB */
Graf Yang0b39db22009-12-28 11:13:51 +000032 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + 1)));
33 SSYNC();
34
Graf Yang6f546bc2010-01-28 10:46:55 +000035 /* set CoreB wakeup by ipi0, iwr will be discarded */
36 bfin_iwr_set_sup0(&iwr, &iwr, &iwr);
37 SSYNC();
38
39 coreb_die();
Graf Yang0b39db22009-12-28 11:13:51 +000040}