viresh kumar | bc4e814 | 2010-04-01 12:30:58 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-spear3xx/spear310.c |
| 3 | * |
| 4 | * SPEAr310 machine source file |
| 5 | * |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame^] | 6 | * Copyright (C) 2009-2012 ST Microelectronics |
| 7 | * Viresh Kumar <viresh.kumar@st.com> |
viresh kumar | bc4e814 | 2010-04-01 12:30:58 +0100 | [diff] [blame] | 8 | * |
| 9 | * This file is licensed under the terms of the GNU General Public |
| 10 | * License version 2. This program is licensed "as is" without any |
| 11 | * warranty of any kind, whether express or implied. |
| 12 | */ |
| 13 | |
Viresh Kumar | 5fb00f9 | 2012-03-26 10:39:43 +0530 | [diff] [blame] | 14 | #define pr_fmt(fmt) "SPEAr310: " fmt |
| 15 | |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame^] | 16 | #include <linux/amba/pl08x.h> |
| 17 | #include <linux/amba/serial.h> |
| 18 | #include <linux/of_platform.h> |
| 19 | #include <asm/hardware/vic.h> |
| 20 | #include <asm/mach/arch.h> |
viresh kumar | 410782b | 2011-03-07 05:57:01 +0100 | [diff] [blame] | 21 | #include <plat/shirq.h> |
viresh kumar | bc4e814 | 2010-04-01 12:30:58 +0100 | [diff] [blame] | 22 | #include <mach/generic.h> |
viresh kumar | 02aa06b | 2011-03-07 05:57:02 +0100 | [diff] [blame] | 23 | #include <mach/hardware.h> |
viresh kumar | bc4e814 | 2010-04-01 12:30:58 +0100 | [diff] [blame] | 24 | |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 25 | /* pad multiplexing support */ |
| 26 | /* muxing registers */ |
| 27 | #define PAD_MUX_CONFIG_REG 0x08 |
| 28 | |
| 29 | /* devices */ |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 30 | static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 31 | { |
| 32 | .ids = 0x00, |
| 33 | .mask = PMX_TIMER_3_4_MASK, |
| 34 | }, |
| 35 | }; |
| 36 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 37 | struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 38 | .name = "emi_cs_0_1_4_5", |
| 39 | .modes = pmx_emi_cs_0_1_4_5_modes, |
| 40 | .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes), |
| 41 | .enb_on_reset = 1, |
| 42 | }; |
| 43 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 44 | static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 45 | { |
| 46 | .ids = 0x00, |
| 47 | .mask = PMX_TIMER_1_2_MASK, |
| 48 | }, |
| 49 | }; |
| 50 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 51 | struct pmx_dev spear310_pmx_emi_cs_2_3 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 52 | .name = "emi_cs_2_3", |
| 53 | .modes = pmx_emi_cs_2_3_modes, |
| 54 | .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes), |
| 55 | .enb_on_reset = 1, |
| 56 | }; |
| 57 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 58 | static struct pmx_dev_mode pmx_uart1_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 59 | { |
| 60 | .ids = 0x00, |
| 61 | .mask = PMX_FIRDA_MASK, |
| 62 | }, |
| 63 | }; |
| 64 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 65 | struct pmx_dev spear310_pmx_uart1 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 66 | .name = "uart1", |
| 67 | .modes = pmx_uart1_modes, |
| 68 | .mode_count = ARRAY_SIZE(pmx_uart1_modes), |
| 69 | .enb_on_reset = 1, |
| 70 | }; |
| 71 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 72 | static struct pmx_dev_mode pmx_uart2_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 73 | { |
| 74 | .ids = 0x00, |
| 75 | .mask = PMX_TIMER_1_2_MASK, |
| 76 | }, |
| 77 | }; |
| 78 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 79 | struct pmx_dev spear310_pmx_uart2 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 80 | .name = "uart2", |
| 81 | .modes = pmx_uart2_modes, |
| 82 | .mode_count = ARRAY_SIZE(pmx_uart2_modes), |
| 83 | .enb_on_reset = 1, |
| 84 | }; |
| 85 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 86 | static struct pmx_dev_mode pmx_uart3_4_5_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 87 | { |
| 88 | .ids = 0x00, |
| 89 | .mask = PMX_UART0_MODEM_MASK, |
| 90 | }, |
| 91 | }; |
| 92 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 93 | struct pmx_dev spear310_pmx_uart3_4_5 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 94 | .name = "uart3_4_5", |
| 95 | .modes = pmx_uart3_4_5_modes, |
| 96 | .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes), |
| 97 | .enb_on_reset = 1, |
| 98 | }; |
| 99 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 100 | static struct pmx_dev_mode pmx_fsmc_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 101 | { |
| 102 | .ids = 0x00, |
| 103 | .mask = PMX_SSP_CS_MASK, |
| 104 | }, |
| 105 | }; |
| 106 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 107 | struct pmx_dev spear310_pmx_fsmc = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 108 | .name = "fsmc", |
| 109 | .modes = pmx_fsmc_modes, |
| 110 | .mode_count = ARRAY_SIZE(pmx_fsmc_modes), |
| 111 | .enb_on_reset = 1, |
| 112 | }; |
| 113 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 114 | static struct pmx_dev_mode pmx_rs485_0_1_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 115 | { |
| 116 | .ids = 0x00, |
| 117 | .mask = PMX_MII_MASK, |
| 118 | }, |
| 119 | }; |
| 120 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 121 | struct pmx_dev spear310_pmx_rs485_0_1 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 122 | .name = "rs485_0_1", |
| 123 | .modes = pmx_rs485_0_1_modes, |
| 124 | .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes), |
| 125 | .enb_on_reset = 1, |
| 126 | }; |
| 127 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 128 | static struct pmx_dev_mode pmx_tdm0_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 129 | { |
| 130 | .ids = 0x00, |
| 131 | .mask = PMX_MII_MASK, |
| 132 | }, |
| 133 | }; |
| 134 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 135 | struct pmx_dev spear310_pmx_tdm0 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 136 | .name = "tdm0", |
| 137 | .modes = pmx_tdm0_modes, |
| 138 | .mode_count = ARRAY_SIZE(pmx_tdm0_modes), |
| 139 | .enb_on_reset = 1, |
| 140 | }; |
| 141 | |
| 142 | /* pmx driver structure */ |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 143 | static struct pmx_driver pmx_driver = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 144 | .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, |
| 145 | }; |
| 146 | |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 147 | /* spear3xx shared irq */ |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 148 | static struct shirq_dev_config shirq_ras1_config[] = { |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 149 | { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 150 | .virq = SPEAR310_VIRQ_SMII0, |
| 151 | .status_mask = SPEAR310_SMII0_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 152 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 153 | .virq = SPEAR310_VIRQ_SMII1, |
| 154 | .status_mask = SPEAR310_SMII1_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 155 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 156 | .virq = SPEAR310_VIRQ_SMII2, |
| 157 | .status_mask = SPEAR310_SMII2_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 158 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 159 | .virq = SPEAR310_VIRQ_SMII3, |
| 160 | .status_mask = SPEAR310_SMII3_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 161 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 162 | .virq = SPEAR310_VIRQ_WAKEUP_SMII0, |
| 163 | .status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 164 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 165 | .virq = SPEAR310_VIRQ_WAKEUP_SMII1, |
| 166 | .status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 167 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 168 | .virq = SPEAR310_VIRQ_WAKEUP_SMII2, |
| 169 | .status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 170 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 171 | .virq = SPEAR310_VIRQ_WAKEUP_SMII3, |
| 172 | .status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 173 | }, |
| 174 | }; |
| 175 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 176 | static struct spear_shirq shirq_ras1 = { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 177 | .irq = SPEAR3XX_IRQ_GEN_RAS_1, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 178 | .dev_config = shirq_ras1_config, |
| 179 | .dev_count = ARRAY_SIZE(shirq_ras1_config), |
| 180 | .regs = { |
| 181 | .enb_reg = -1, |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 182 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
| 183 | .status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 184 | .clear_reg = -1, |
| 185 | }, |
| 186 | }; |
| 187 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 188 | static struct shirq_dev_config shirq_ras2_config[] = { |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 189 | { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 190 | .virq = SPEAR310_VIRQ_UART1, |
| 191 | .status_mask = SPEAR310_UART1_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 192 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 193 | .virq = SPEAR310_VIRQ_UART2, |
| 194 | .status_mask = SPEAR310_UART2_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 195 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 196 | .virq = SPEAR310_VIRQ_UART3, |
| 197 | .status_mask = SPEAR310_UART3_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 198 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 199 | .virq = SPEAR310_VIRQ_UART4, |
| 200 | .status_mask = SPEAR310_UART4_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 201 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 202 | .virq = SPEAR310_VIRQ_UART5, |
| 203 | .status_mask = SPEAR310_UART5_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 204 | }, |
| 205 | }; |
| 206 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 207 | static struct spear_shirq shirq_ras2 = { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 208 | .irq = SPEAR3XX_IRQ_GEN_RAS_2, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 209 | .dev_config = shirq_ras2_config, |
| 210 | .dev_count = ARRAY_SIZE(shirq_ras2_config), |
| 211 | .regs = { |
| 212 | .enb_reg = -1, |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 213 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
| 214 | .status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 215 | .clear_reg = -1, |
| 216 | }, |
| 217 | }; |
| 218 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 219 | static struct shirq_dev_config shirq_ras3_config[] = { |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 220 | { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 221 | .virq = SPEAR310_VIRQ_EMI, |
| 222 | .status_mask = SPEAR310_EMI_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 223 | }, |
| 224 | }; |
| 225 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 226 | static struct spear_shirq shirq_ras3 = { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 227 | .irq = SPEAR3XX_IRQ_GEN_RAS_3, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 228 | .dev_config = shirq_ras3_config, |
| 229 | .dev_count = ARRAY_SIZE(shirq_ras3_config), |
| 230 | .regs = { |
| 231 | .enb_reg = -1, |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 232 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
| 233 | .status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 234 | .clear_reg = -1, |
| 235 | }, |
| 236 | }; |
| 237 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 238 | static struct shirq_dev_config shirq_intrcomm_ras_config[] = { |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 239 | { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 240 | .virq = SPEAR310_VIRQ_TDM_HDLC, |
| 241 | .status_mask = SPEAR310_TDM_HDLC_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 242 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 243 | .virq = SPEAR310_VIRQ_RS485_0, |
| 244 | .status_mask = SPEAR310_RS485_0_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 245 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 246 | .virq = SPEAR310_VIRQ_RS485_1, |
| 247 | .status_mask = SPEAR310_RS485_1_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 248 | }, |
| 249 | }; |
| 250 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 251 | static struct spear_shirq shirq_intrcomm_ras = { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 252 | .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 253 | .dev_config = shirq_intrcomm_ras_config, |
| 254 | .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config), |
| 255 | .regs = { |
| 256 | .enb_reg = -1, |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 257 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
| 258 | .status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 259 | .clear_reg = -1, |
| 260 | }, |
| 261 | }; |
| 262 | |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame^] | 263 | /* padmux devices to enable */ |
| 264 | static struct pmx_dev *spear310_evb_pmx_devs[] = { |
| 265 | /* spear3xx specific devices */ |
| 266 | &spear3xx_pmx_i2c, |
| 267 | &spear3xx_pmx_ssp, |
| 268 | &spear3xx_pmx_gpio_pin0, |
| 269 | &spear3xx_pmx_gpio_pin1, |
| 270 | &spear3xx_pmx_gpio_pin2, |
| 271 | &spear3xx_pmx_gpio_pin3, |
| 272 | &spear3xx_pmx_gpio_pin4, |
| 273 | &spear3xx_pmx_gpio_pin5, |
| 274 | &spear3xx_pmx_uart0, |
viresh kumar | c2c0783 | 2011-03-07 05:57:05 +0100 | [diff] [blame] | 275 | |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame^] | 276 | /* spear310 specific devices */ |
| 277 | &spear310_pmx_emi_cs_0_1_4_5, |
| 278 | &spear310_pmx_emi_cs_2_3, |
| 279 | &spear310_pmx_uart1, |
| 280 | &spear310_pmx_uart2, |
| 281 | &spear310_pmx_uart3_4_5, |
| 282 | &spear310_pmx_fsmc, |
| 283 | &spear310_pmx_rs485_0_1, |
| 284 | &spear310_pmx_tdm0, |
| 285 | }; |
| 286 | |
| 287 | /* uart devices plat data */ |
| 288 | static struct amba_pl011_data spear310_uart_data[] = { |
| 289 | { |
| 290 | .dma_filter = pl08x_filter_id, |
| 291 | .dma_tx_param = "uart1_tx", |
| 292 | .dma_rx_param = "uart1_rx", |
| 293 | }, { |
| 294 | .dma_filter = pl08x_filter_id, |
| 295 | .dma_tx_param = "uart2_tx", |
| 296 | .dma_rx_param = "uart2_rx", |
| 297 | }, { |
| 298 | .dma_filter = pl08x_filter_id, |
| 299 | .dma_tx_param = "uart3_tx", |
| 300 | .dma_rx_param = "uart3_rx", |
| 301 | }, { |
| 302 | .dma_filter = pl08x_filter_id, |
| 303 | .dma_tx_param = "uart4_tx", |
| 304 | .dma_rx_param = "uart4_rx", |
| 305 | }, { |
| 306 | .dma_filter = pl08x_filter_id, |
| 307 | .dma_tx_param = "uart5_tx", |
| 308 | .dma_rx_param = "uart5_rx", |
| 309 | }, |
| 310 | }; |
| 311 | |
| 312 | /* Add SPEAr310 auxdata to pass platform data */ |
| 313 | static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = { |
| 314 | OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, |
| 315 | &pl022_plat_data), |
| 316 | OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL, |
| 317 | &spear310_uart_data[0]), |
| 318 | OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL, |
| 319 | &spear310_uart_data[1]), |
| 320 | OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL, |
| 321 | &spear310_uart_data[2]), |
| 322 | OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL, |
| 323 | &spear310_uart_data[3]), |
| 324 | OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL, |
| 325 | &spear310_uart_data[4]), |
| 326 | {} |
| 327 | }; |
| 328 | |
| 329 | static void __init spear310_dt_init(void) |
viresh kumar | bc4e814 | 2010-04-01 12:30:58 +0100 | [diff] [blame] | 330 | { |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 331 | void __iomem *base; |
| 332 | int ret = 0; |
| 333 | |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame^] | 334 | of_platform_populate(NULL, of_default_bus_match_table, |
| 335 | spear310_auxdata_lookup, NULL); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 336 | |
Uwe Kleine-König | b595076 | 2010-11-01 15:38:34 -0400 | [diff] [blame] | 337 | /* shared irq registration */ |
viresh kumar | 5382116 | 2011-03-07 05:57:06 +0100 | [diff] [blame] | 338 | base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 339 | if (base) { |
| 340 | /* shirq 1 */ |
| 341 | shirq_ras1.regs.base = base; |
| 342 | ret = spear_shirq_register(&shirq_ras1); |
| 343 | if (ret) |
Viresh Kumar | 5fb00f9 | 2012-03-26 10:39:43 +0530 | [diff] [blame] | 344 | pr_err("Error registering Shared IRQ 1\n"); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 345 | |
| 346 | /* shirq 2 */ |
| 347 | shirq_ras2.regs.base = base; |
| 348 | ret = spear_shirq_register(&shirq_ras2); |
| 349 | if (ret) |
Viresh Kumar | 5fb00f9 | 2012-03-26 10:39:43 +0530 | [diff] [blame] | 350 | pr_err("Error registering Shared IRQ 2\n"); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 351 | |
| 352 | /* shirq 3 */ |
| 353 | shirq_ras3.regs.base = base; |
| 354 | ret = spear_shirq_register(&shirq_ras3); |
| 355 | if (ret) |
Viresh Kumar | 5fb00f9 | 2012-03-26 10:39:43 +0530 | [diff] [blame] | 356 | pr_err("Error registering Shared IRQ 3\n"); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 357 | |
| 358 | /* shirq 4 */ |
| 359 | shirq_intrcomm_ras.regs.base = base; |
| 360 | ret = spear_shirq_register(&shirq_intrcomm_ras); |
| 361 | if (ret) |
Viresh Kumar | 5fb00f9 | 2012-03-26 10:39:43 +0530 | [diff] [blame] | 362 | pr_err("Error registering Shared IRQ 4\n"); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 363 | } |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 364 | |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame^] | 365 | if (of_machine_is_compatible("st,spear310-evb")) { |
| 366 | /* pmx initialization */ |
| 367 | pmx_driver.base = base; |
| 368 | pmx_driver.mode = NULL; |
| 369 | pmx_driver.devs = spear310_evb_pmx_devs; |
| 370 | pmx_driver.devs_count = ARRAY_SIZE(spear310_evb_pmx_devs); |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 371 | |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame^] | 372 | ret = pmx_register(&pmx_driver); |
| 373 | if (ret) |
| 374 | pr_err("padmux: registration failed. err no: %d\n", |
| 375 | ret); |
| 376 | } |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 377 | } |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame^] | 378 | |
| 379 | static const char * const spear310_dt_board_compat[] = { |
| 380 | "st,spear310", |
| 381 | "st,spear310-evb", |
| 382 | NULL, |
| 383 | }; |
| 384 | |
| 385 | static void __init spear310_map_io(void) |
| 386 | { |
| 387 | spear3xx_map_io(); |
| 388 | spear310_clk_init(); |
| 389 | } |
| 390 | |
| 391 | DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree") |
| 392 | .map_io = spear310_map_io, |
| 393 | .init_irq = spear3xx_dt_init_irq, |
| 394 | .handle_irq = vic_handle_irq, |
| 395 | .timer = &spear3xx_timer, |
| 396 | .init_machine = spear310_dt_init, |
| 397 | .restart = spear_restart, |
| 398 | .dt_compat = spear310_dt_board_compat, |
| 399 | MACHINE_END |