arch/arm64/boot/dts/qcom/sdm845-gpu.dtsi

/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

&soc {

	msm_bus: qcom,kgsl-busmon{
		label = "kgsl-busmon";
		compatible = "qcom,kgsl-busmon";
	};

	gpubw: qcom,gpubw {
		compatible = "qcom,devbw";
		governor = "bw_vbif";
		qcom,src-dst-ports = <26 512>;
		/*
		 * active-only flag is used while registering the bus
		 * governor.It helps release the bus vote when the CPU
		 * subsystem is inactiv3
		 */
		qcom,active-only;
		qcom,bw-tbl =
			<     0 /*  off     */ >,
			<   762 /*  100 MHz */ >,
			<  1144 /*  150 MHz */ >,
			<  1525 /*  200 MHz */ >,
			<  2288 /*  300 MHz */ >,
			<  3143 /*  412 MHz */ >,
			<  4173 /*  547 MHz */ >,
			<  5195 /*  681 MHz */ >,
			<  5859 /*  768 MHz */ >,
			<  7759 /*  1017 MHz */ >,
			<  9887 /*  1296 MHz */ >,
			<  11863 /*  1555 MHz */ >,
			<  13763 /*  1804 MHz */ >;
	};

	msm_gpu: qcom,kgsl-3d0@5000000 {
		label = "kgsl-3d0";
		compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
		status = "ok";
		reg = <0x5000000 0x40000>;
		reg-names = "kgsl_3d0_reg_memory";
		interrupts = <0 300 0>;
		interrupt-names = "kgsl_3d0_irq";
		qcom,id = <0>;

		qcom,chipid = <0x06030000>;

		qcom,initial-pwrlevel = <2>;

		qcom,gpu-quirk-hfi-use-reg;
		qcom,gpu-quirk-two-pass-use-wfi;

		qcom,idle-timeout = <100000000>; //msecs
		qcom,no-nap;

		qcom,highest-bank-bit = <15>;

		qcom,min-access-length = <32>;

		qcom,ubwc-mode = <2>;

		qcom,snapshot-size = <1048576>; //bytes

		qcom,gpu-qdss-stm = <0x161c0000 0x40000>; // base addr, size

		qcom,tsens-name = "tsens_tz_sensor12";
		#cooling-cells = <2>;

		clocks = <&clock_gfx GPU_CC_GX_GFX3D_CLK>,
			<&clock_gcc GCC_GPU_CFG_AHB_CLK>,
			<&clock_gpucc GPU_CC_CXO_CLK>,
			<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
			<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>;

		clock-names = "core_clk", "iface_clk", "rbbmtimer_clk",
			"mem_clk", "mem_iface_clk";

		qcom,isense-clk-on-level = <1>;

		/* Bus Scale Settings */
		qcom,gpubw-dev = <&gpubw>;
		qcom,bus-control;
		qcom,msm-bus,name = "grp3d";
		qcom,msm-bus,num-cases = <13>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
				<26 512 0 0>,

				<26 512 0 800000>,      // 1 bus=100
				<26 512 0 1200000>,     // 2 bus=150
				<26 512 0 1600000>,     // 3 bus=200
				<26 512 0 2400000>,     // 4 bus=300
				<26 512 0 3296000>,     // 5 bus=412
				<26 512 0 4376000>,     // 6 bus=547
				<26 512 0 5448000>,     // 7 bus=681
				<26 512 0 6144000>,     // 8 bus=768
				<26 512 0 8136000>,     // 9 bus=1017
				<26 512 0 10368000>,    // 10 bus=1296
				<26 512 0 12440000>,    // 11 bus=1555
				<26 512 0 14432000>;    // 12 bus=1804

		/* GDSC regulator names */
		regulator-names = "vddcx", "vdd";
		/* GDSC oxili regulators */
		vddcx-supply = <&gpu_cx_gdsc>;
		vdd-supply = <&gpu_gx_gdsc>;

		/* GPU related llc slices */
		cache-slice-names = "gpu", "gpuhtw";
		cache-slices = <&llcc 12>, <&llcc 11>;

		/* GPU Mempools */
		qcom,gpu-mempools {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "qcom,gpu-mempools";

			/* 4K Page Pool configuration */
			qcom,gpu-mempool@0 {
				reg = <0>;
				qcom,mempool-page-size = <4096>;
				qcom,mempool-reserved = <2048>;
				qcom,mempool-allocate;
			};
			/* 8K Page Pool configuration */
			qcom,gpu-mempool@1 {
				reg = <1>;
				qcom,mempool-page-size = <8192>;
				qcom,mempool-reserved = <1024>;
				qcom,mempool-allocate;
			};
			/* 64K Page Pool configuration */
			qcom,gpu-mempool@2 {
				reg = <2>;
				qcom,mempool-page-size = <65536>;
				qcom,mempool-reserved = <256>;
			};
			/* 1M Page Pool configuration */
			qcom,gpu-mempool@3 {
				reg = <3>;
				qcom,mempool-page-size = <1048576>;
				qcom,mempool-reserved = <32>;
			};
		};

		/* Power levels */
		qcom,gpu-pwrlevels {
			#address-cells = <1>;
			#size-cells = <0>;

			compatible = "qcom,gpu-pwrlevels";

			qcom,gpu-pwrlevel@0 {
				reg = <0>;
				qcom,gpu-freq = <548000000>;
				qcom,bus-freq = <12>;
				qcom,bus-min = <11>;
				qcom,bus-max = <12>;
			};


			qcom,gpu-pwrlevel@1 {
				reg = <1>;
				qcom,gpu-freq = <425000000>;
				qcom,bus-freq = <7>;
				qcom,bus-min = <6>;
				qcom,bus-max = <8>;
			};

			qcom,gpu-pwrlevel@2 {
				reg = <2>;
				qcom,gpu-freq = <280000000>;
				qcom,bus-freq = <4>;
				qcom,bus-min = <3>;
				qcom,bus-max = <5>;
			};

			qcom,gpu-pwrlevel@3 {
				reg = <3>;
				qcom,gpu-freq = <27000000>;
				qcom,bus-freq = <0>;
				qcom,bus-min = <0>;
				qcom,bus-max = <0>;
			};
		};

	};

	kgsl_msm_iommu: qcom,kgsl-iommu {
		compatible = "qcom,kgsl-smmu-v2";

		reg = <0x05040000 0x10000>;
		qcom,protect = <0x40000 0x10000>;
		qcom,micro-mmu-control = <0x6000>;

		clocks =<&clock_gcc GCC_GPU_CFG_AHB_CLK>,
			<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
			<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>;

		clock-names = "iface_clk", "mem_clk", "mem_iface_clk";

		qcom,secure_align_mask = <0xfff>;
		qcom,global_pt;

		gfx3d_user: gfx3d_user {
			compatible = "qcom,smmu-kgsl-cb";
			label = "gfx3d_user";
			iommus = <&kgsl_smmu 0>;
			qcom,gpu-offset = <0x48000>;
		};

		gfx3d_secure: gfx3d_secure {
			compatible = "qcom,smmu-kgsl-cb";
			iommus = <&kgsl_smmu 2>;
		};
	};

	gmu: qcom,gmu {
		label = "kgsl-gmu";
		compatible = "qcom,gpu-gmu";

		reg = <0x506a000 0x26000>, <0xb200000 0x300000>;
		reg-names = "kgsl_gmu_reg", "kgsl_gmu_pdc_reg";

		interrupts = <0 304 0>, <0 305 0>;
		interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq";

		qcom,msm-bus,name = "cnoc";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			<26 10036 0 0>,		// CNOC off
			<26 10036 0 100>;	// CNOC on

		regulator-names = "vddcx", "vdd";
		vddcx-supply = <&gpu_cx_gdsc>;
		vdd-supply = <&gpu_gx_gdsc>;


		clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>,
				<&clock_gpucc GPU_CC_CXO_CLK>,
				<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
				<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
				<&clock_gpucc GPU_CC_AHB_CLK>;

		clock-names = "gmu_clk", "cxo_clk", "axi_clk",
				"memnoc_clk", "ahb_clk";

		qcom,gmu-pwrlevels {
			#address-cells = <1>;
			#size-cells = <0>;

			compatible = "qcom,gmu-pwrlevels";

			qcom,gmu-pwrlevel@0 {
				reg = <0>;
				qcom,gmu-freq = <400000000>;
			};

			qcom,gmu-pwrlevel@1 {
				reg = <1>;
				qcom,gmu-freq = <19200000>;
			};

			qcom,gmu-pwrlevel@2 {
				reg = <2>;
				qcom,gmu-freq = <0>;
			};
		};

		gmu_user: gmu_user {
			compatible = "qcom,smmu-gmu-user-cb";
			iommus = <&kgsl_smmu 4>;
		};

		gmu_kernel: gmu_kernel {
			compatible = "qcom,smmu-gmu-kernel-cb";
			iommus = <&kgsl_smmu 5>;
		};
	};
};