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Luciano Coelhof5fc0f82009-08-06 16:25:28 +03001/*
2 * This file is part of wl1271
3 *
4 * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
5 * Copyright (C) 2008-2009 Nokia Corporation
6 *
7 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25#ifndef __WL1271_H__
26#define __WL1271_H__
27
28#include <linux/mutex.h>
29#include <linux/completion.h>
30#include <linux/spinlock.h>
31#include <linux/list.h>
32#include <linux/bitops.h>
33#include <net/mac80211.h>
34
Juuso Oikarinen2b60100b2009-10-13 12:47:39 +030035#include "wl1271_conf.h"
36
Luciano Coelhof5fc0f82009-08-06 16:25:28 +030037#define DRIVER_NAME "wl1271"
38#define DRIVER_PREFIX DRIVER_NAME ": "
39
40enum {
41 DEBUG_NONE = 0,
42 DEBUG_IRQ = BIT(0),
43 DEBUG_SPI = BIT(1),
44 DEBUG_BOOT = BIT(2),
45 DEBUG_MAILBOX = BIT(3),
46 DEBUG_NETLINK = BIT(4),
47 DEBUG_EVENT = BIT(5),
48 DEBUG_TX = BIT(6),
49 DEBUG_RX = BIT(7),
50 DEBUG_SCAN = BIT(8),
51 DEBUG_CRYPT = BIT(9),
52 DEBUG_PSM = BIT(10),
53 DEBUG_MAC80211 = BIT(11),
54 DEBUG_CMD = BIT(12),
55 DEBUG_ACX = BIT(13),
56 DEBUG_ALL = ~0,
57};
58
59#define DEBUG_LEVEL (DEBUG_NONE)
60
61#define DEBUG_DUMP_LIMIT 1024
62
63#define wl1271_error(fmt, arg...) \
64 printk(KERN_ERR DRIVER_PREFIX "ERROR " fmt "\n", ##arg)
65
66#define wl1271_warning(fmt, arg...) \
67 printk(KERN_WARNING DRIVER_PREFIX "WARNING " fmt "\n", ##arg)
68
69#define wl1271_notice(fmt, arg...) \
70 printk(KERN_INFO DRIVER_PREFIX fmt "\n", ##arg)
71
72#define wl1271_info(fmt, arg...) \
73 printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg)
74
75#define wl1271_debug(level, fmt, arg...) \
76 do { \
77 if (level & DEBUG_LEVEL) \
78 printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg); \
79 } while (0)
80
81#define wl1271_dump(level, prefix, buf, len) \
82 do { \
83 if (level & DEBUG_LEVEL) \
84 print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \
85 DUMP_PREFIX_OFFSET, 16, 1, \
86 buf, \
87 min_t(size_t, len, DEBUG_DUMP_LIMIT), \
88 0); \
89 } while (0)
90
91#define wl1271_dump_ascii(level, prefix, buf, len) \
92 do { \
93 if (level & DEBUG_LEVEL) \
94 print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \
95 DUMP_PREFIX_OFFSET, 16, 1, \
96 buf, \
97 min_t(size_t, len, DEBUG_DUMP_LIMIT), \
98 true); \
99 } while (0)
100
101#define WL1271_DEFAULT_RX_CONFIG (CFG_UNI_FILTER_EN | \
Juuso Oikarinenc87dec92009-10-08 21:56:31 +0300102 CFG_BSSID_FILTER_EN | \
103 CFG_MC_FILTER_EN)
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300104
105#define WL1271_DEFAULT_RX_FILTER (CFG_RX_RCTS_ACK | CFG_RX_PRSP_EN | \
106 CFG_RX_MGMT_EN | CFG_RX_DATA_EN | \
107 CFG_RX_CTL_EN | CFG_RX_BCN_EN | \
108 CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN)
109
Juuso Oikarinen45b531a2009-10-13 12:47:41 +0300110#define WL1271_DEFAULT_BASIC_RATE_SET (CONF_TX_RATE_MASK_ALL)
Juuso Oikarinend94cd292009-10-08 21:56:25 +0300111
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300112#define WL1271_FW_NAME "wl1271-fw.bin"
113#define WL1271_NVS_NAME "wl1271-nvs.bin"
114
Juuso Oikarinen545f1da2009-10-08 21:56:23 +0300115/*
116 * FIXME: for the wl1271, a busy word count of 1 here will result in a more
117 * optimal SPI interface. There is some SPI bug however, causing RXS time outs
Juuso Oikarinenc6d5d062009-10-13 12:47:47 +0300118 * with this mode occasionally on boot, so lets have three for now. A value of
119 * three should make sure, that the chipset will always be ready, though this
120 * will impact throughput and latencies slightly.
Juuso Oikarinen545f1da2009-10-08 21:56:23 +0300121 */
Juuso Oikarinenc6d5d062009-10-13 12:47:47 +0300122#define WL1271_BUSY_WORD_CNT 3
Juuso Oikarinen545f1da2009-10-08 21:56:23 +0300123#define WL1271_BUSY_WORD_LEN (WL1271_BUSY_WORD_CNT * sizeof(u32))
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300124
125#define WL1271_ELP_HW_STATE_ASLEEP 0
126#define WL1271_ELP_HW_STATE_IRQ 1
127
Juuso Oikarinend94cd292009-10-08 21:56:25 +0300128#define WL1271_DEFAULT_BEACON_INT 100
129#define WL1271_DEFAULT_DTIM_PERIOD 1
130
Juuso Oikarinenc87dec92009-10-08 21:56:31 +0300131#define ACX_TX_DESCRIPTORS 32
Juuso Oikarinenbe7078c2009-10-08 21:56:26 +0300132
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300133enum wl1271_state {
134 WL1271_STATE_OFF,
135 WL1271_STATE_ON,
136 WL1271_STATE_PLT,
137};
138
139enum wl1271_partition_type {
140 PART_DOWN,
141 PART_WORK,
142 PART_DRPW,
143
144 PART_TABLE_LEN
145};
146
147struct wl1271_partition {
148 u32 size;
149 u32 start;
150};
151
152struct wl1271_partition_set {
153 struct wl1271_partition mem;
154 struct wl1271_partition reg;
Juuso Oikarinen451de972009-10-12 15:08:46 +0300155 struct wl1271_partition mem2;
156 struct wl1271_partition mem3;
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300157};
158
159struct wl1271;
160
161/* FIXME: I'm not sure about this structure name */
162struct wl1271_chip {
163 u32 id;
164 char fw_ver[21];
165};
166
167struct wl1271_stats {
168 struct acx_statistics *fw_stats;
169 unsigned long fw_stats_update;
170
171 unsigned int retry_count;
172 unsigned int excessive_retries;
173};
174
175struct wl1271_debugfs {
176 struct dentry *rootdir;
177 struct dentry *fw_statistics;
178
179 struct dentry *tx_internal_desc_overflow;
180
181 struct dentry *rx_out_of_mem;
182 struct dentry *rx_hdr_overflow;
183 struct dentry *rx_hw_stuck;
184 struct dentry *rx_dropped;
185 struct dentry *rx_fcs_err;
186 struct dentry *rx_xfr_hint_trig;
187 struct dentry *rx_path_reset;
188 struct dentry *rx_reset_counter;
189
190 struct dentry *dma_rx_requested;
191 struct dentry *dma_rx_errors;
192 struct dentry *dma_tx_requested;
193 struct dentry *dma_tx_errors;
194
195 struct dentry *isr_cmd_cmplt;
196 struct dentry *isr_fiqs;
197 struct dentry *isr_rx_headers;
198 struct dentry *isr_rx_mem_overflow;
199 struct dentry *isr_rx_rdys;
200 struct dentry *isr_irqs;
201 struct dentry *isr_tx_procs;
202 struct dentry *isr_decrypt_done;
203 struct dentry *isr_dma0_done;
204 struct dentry *isr_dma1_done;
205 struct dentry *isr_tx_exch_complete;
206 struct dentry *isr_commands;
207 struct dentry *isr_rx_procs;
208 struct dentry *isr_hw_pm_mode_changes;
209 struct dentry *isr_host_acknowledges;
210 struct dentry *isr_pci_pm;
211 struct dentry *isr_wakeups;
212 struct dentry *isr_low_rssi;
213
214 struct dentry *wep_addr_key_count;
215 struct dentry *wep_default_key_count;
216 /* skipping wep.reserved */
217 struct dentry *wep_key_not_found;
218 struct dentry *wep_decrypt_fail;
219 struct dentry *wep_packets;
220 struct dentry *wep_interrupt;
221
222 struct dentry *pwr_ps_enter;
223 struct dentry *pwr_elp_enter;
224 struct dentry *pwr_missing_bcns;
225 struct dentry *pwr_wake_on_host;
226 struct dentry *pwr_wake_on_timer_exp;
227 struct dentry *pwr_tx_with_ps;
228 struct dentry *pwr_tx_without_ps;
229 struct dentry *pwr_rcvd_beacons;
230 struct dentry *pwr_power_save_off;
231 struct dentry *pwr_enable_ps;
232 struct dentry *pwr_disable_ps;
233 struct dentry *pwr_fix_tsf_ps;
234 /* skipping cont_miss_bcns_spread for now */
235 struct dentry *pwr_rcvd_awake_beacons;
236
237 struct dentry *mic_rx_pkts;
238 struct dentry *mic_calc_failure;
239
240 struct dentry *aes_encrypt_fail;
241 struct dentry *aes_decrypt_fail;
242 struct dentry *aes_encrypt_packets;
243 struct dentry *aes_decrypt_packets;
244 struct dentry *aes_encrypt_interrupt;
245 struct dentry *aes_decrypt_interrupt;
246
247 struct dentry *event_heart_beat;
248 struct dentry *event_calibration;
249 struct dentry *event_rx_mismatch;
250 struct dentry *event_rx_mem_empty;
251 struct dentry *event_rx_pool;
252 struct dentry *event_oom_late;
253 struct dentry *event_phy_transmit_error;
254 struct dentry *event_tx_stuck;
255
256 struct dentry *ps_pspoll_timeouts;
257 struct dentry *ps_upsd_timeouts;
258 struct dentry *ps_upsd_max_sptime;
259 struct dentry *ps_upsd_max_apturn;
260 struct dentry *ps_pspoll_max_apturn;
261 struct dentry *ps_pspoll_utilization;
262 struct dentry *ps_upsd_utilization;
263
264 struct dentry *rxpipe_rx_prep_beacon_drop;
265 struct dentry *rxpipe_descr_host_int_trig_rx_data;
266 struct dentry *rxpipe_beacon_buffer_thres_host_int_trig_rx_data;
267 struct dentry *rxpipe_missed_beacon_host_int_trig_rx_data;
268 struct dentry *rxpipe_tx_xfr_host_int_trig_rx_data;
269
270 struct dentry *tx_queue_len;
271
272 struct dentry *retry_count;
273 struct dentry *excessive_retries;
274};
275
276#define NUM_TX_QUEUES 4
277#define NUM_RX_PKT_DESC 8
278
279/* FW status registers */
280struct wl1271_fw_status {
281 u32 intr;
282 u8 fw_rx_counter;
283 u8 drv_rx_counter;
284 u8 reserved;
285 u8 tx_results_counter;
286 u32 rx_pkt_descs[NUM_RX_PKT_DESC];
287 u32 tx_released_blks[NUM_TX_QUEUES];
288 u32 fw_localtime;
289 u32 padding[2];
290} __attribute__ ((packed));
291
292struct wl1271_rx_mem_pool_addr {
293 u32 addr;
294 u32 addr_extra;
295};
296
297struct wl1271 {
298 struct ieee80211_hw *hw;
299 bool mac80211_registered;
300
301 struct spi_device *spi;
302
303 void (*set_power)(bool enable);
304 int irq;
305
306 spinlock_t wl_lock;
307
308 enum wl1271_state state;
309 struct mutex mutex;
310
Juuso Oikarinen451de972009-10-12 15:08:46 +0300311 struct wl1271_partition_set part;
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300312
313 struct wl1271_chip chip;
314
315 int cmd_box_addr;
316 int event_box_addr;
317
318 u8 *fw;
319 size_t fw_len;
320 u8 *nvs;
321 size_t nvs_len;
322
323 u8 bssid[ETH_ALEN];
324 u8 mac_addr[ETH_ALEN];
325 u8 bss_type;
326 u8 ssid[IW_ESSID_MAX_SIZE + 1];
327 u8 ssid_len;
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300328 int channel;
329
330 struct wl1271_acx_mem_map *target_mem_map;
331
332 /* Accounting for allocated / available TX blocks on HW */
333 u32 tx_blocks_freed[NUM_TX_QUEUES];
334 u32 tx_blocks_available;
335 u8 tx_results_count;
336
337 /* Transmitted TX packets counter for chipset interface */
338 int tx_packets_count;
339
340 /* Time-offset between host and chipset clocks */
341 int time_offset;
342
343 /* Session counter for the chipset */
344 int session_counter;
345
346 /* Frames scheduled for transmission, not handled yet */
347 struct sk_buff_head tx_queue;
348 bool tx_queue_stopped;
349
350 struct work_struct tx_work;
Juuso Oikarinenc87dec92009-10-08 21:56:31 +0300351
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300352 struct work_struct filter_work;
Juuso Oikarinenc87dec92009-10-08 21:56:31 +0300353 struct wl1271_filter_params *filter_params;
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300354
355 /* Pending TX frames */
Juuso Oikarinenbe7078c2009-10-08 21:56:26 +0300356 struct sk_buff *tx_frames[ACX_TX_DESCRIPTORS];
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300357
Juuso Oikarinenac4e4ce2009-10-08 21:56:19 +0300358 /* Security sequence number counters */
359 u8 tx_security_last_seq;
360 u16 tx_security_seq_16;
361 u32 tx_security_seq_32;
362
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300363 /* FW Rx counter */
364 u32 rx_counter;
365
366 /* Rx memory pool address */
367 struct wl1271_rx_mem_pool_addr rx_mem_pool_addr;
368
369 /* The target interrupt mask */
370 struct work_struct irq_work;
371
372 /* The mbox event mask */
373 u32 event_mask;
374
375 /* Mailbox pointers */
376 u32 mbox_ptr[2];
377
378 /* Are we currently scanning */
379 bool scanning;
380
381 /* Our association ID */
382 u16 aid;
383
Juuso Oikarinend94cd292009-10-08 21:56:25 +0300384 /* currently configured rate set */
385 u32 basic_rate_set;
386
Juuso Oikarinen8a5a37a2009-10-08 21:56:24 +0300387 /* The current band */
388 enum ieee80211_band band;
389
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300390 /* Default key (for WEP) */
391 u32 default_key;
392
393 unsigned int rx_config;
394 unsigned int rx_filter;
395
396 /* is firmware in elp mode */
397 bool elp;
398
399 struct completion *elp_compl;
Juuso Oikarinen37b70a82009-10-08 21:56:21 +0300400 struct delayed_work elp_work;
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300401
402 /* we can be in psm, but not in elp, we have to differentiate */
403 bool psm;
404
405 /* PSM mode requested */
406 bool psm_requested;
407
408 /* in dBm */
409 int power_level;
410
411 struct wl1271_stats stats;
412 struct wl1271_debugfs debugfs;
413
414 u32 buffer_32;
415 u32 buffer_cmd;
Juuso Oikarinen545f1da2009-10-08 21:56:23 +0300416 u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300417 struct wl1271_rx_descriptor *rx_descriptor;
418
419 struct wl1271_fw_status *fw_status;
420 struct wl1271_tx_hw_res_if *tx_res_if;
Juuso Oikarinenb771eee2009-10-08 21:56:34 +0300421
422 struct ieee80211_vif *vif;
Luciano Coelhod6e19d12009-10-12 15:08:43 +0300423
424 /* Used for a workaround to send disconnect before rejoining */
425 bool joined;
Juuso Oikarinen2b60100b2009-10-13 12:47:39 +0300426
427 /* Current chipset configuration */
428 struct conf_drv_settings conf;
Luciano Coelhof5fc0f82009-08-06 16:25:28 +0300429};
430
431int wl1271_plt_start(struct wl1271 *wl);
432int wl1271_plt_stop(struct wl1271 *wl);
433
434#define JOIN_TIMEOUT 5000 /* 5000 milliseconds to join */
435
436#define SESSION_COUNTER_MAX 7 /* maximum value for the session counter */
437
438#define WL1271_DEFAULT_POWER_LEVEL 0
439
440#define WL1271_TX_QUEUE_MAX_LENGTH 20
441
442/* WL1271 needs a 200ms sleep after power on */
443#define WL1271_POWER_ON_SLEEP 200 /* in miliseconds */
444
445#endif