Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Synopsys Designware I2C adapter driver (master only). |
| 3 | * |
| 4 | * Based on the TI DAVINCI I2C adapter driver. |
| 5 | * |
| 6 | * Copyright (C) 2006 Texas Instruments. |
| 7 | * Copyright (C) 2007 MontaVista Software Inc. |
| 8 | * Copyright (C) 2009 Provigent Ltd. |
| 9 | * |
| 10 | * ---------------------------------------------------------------------------- |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License as published by |
| 14 | * the Free Software Foundation; either version 2 of the License, or |
| 15 | * (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 25 | * ---------------------------------------------------------------------------- |
| 26 | * |
| 27 | */ |
| 28 | #include <linux/kernel.h> |
| 29 | #include <linux/module.h> |
| 30 | #include <linux/delay.h> |
| 31 | #include <linux/i2c.h> |
| 32 | #include <linux/clk.h> |
| 33 | #include <linux/errno.h> |
| 34 | #include <linux/sched.h> |
| 35 | #include <linux/err.h> |
| 36 | #include <linux/interrupt.h> |
| 37 | #include <linux/platform_device.h> |
| 38 | #include <linux/io.h> |
| 39 | |
| 40 | /* |
| 41 | * Registers offset |
| 42 | */ |
| 43 | #define DW_IC_CON 0x0 |
| 44 | #define DW_IC_TAR 0x4 |
| 45 | #define DW_IC_DATA_CMD 0x10 |
| 46 | #define DW_IC_SS_SCL_HCNT 0x14 |
| 47 | #define DW_IC_SS_SCL_LCNT 0x18 |
| 48 | #define DW_IC_FS_SCL_HCNT 0x1c |
| 49 | #define DW_IC_FS_SCL_LCNT 0x20 |
| 50 | #define DW_IC_INTR_STAT 0x2c |
| 51 | #define DW_IC_INTR_MASK 0x30 |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 52 | #define DW_IC_RAW_INTR_STAT 0x34 |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 53 | #define DW_IC_CLR_INTR 0x40 |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 54 | #define DW_IC_CLR_RX_UNDER 0x44 |
| 55 | #define DW_IC_CLR_RX_OVER 0x48 |
| 56 | #define DW_IC_CLR_TX_OVER 0x4c |
| 57 | #define DW_IC_CLR_RD_REQ 0x50 |
| 58 | #define DW_IC_CLR_TX_ABRT 0x54 |
| 59 | #define DW_IC_CLR_RX_DONE 0x58 |
| 60 | #define DW_IC_CLR_ACTIVITY 0x5c |
| 61 | #define DW_IC_CLR_STOP_DET 0x60 |
| 62 | #define DW_IC_CLR_START_DET 0x64 |
| 63 | #define DW_IC_CLR_GEN_CALL 0x68 |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 64 | #define DW_IC_ENABLE 0x6c |
| 65 | #define DW_IC_STATUS 0x70 |
| 66 | #define DW_IC_TXFLR 0x74 |
| 67 | #define DW_IC_RXFLR 0x78 |
| 68 | #define DW_IC_COMP_PARAM_1 0xf4 |
| 69 | #define DW_IC_TX_ABRT_SOURCE 0x80 |
| 70 | |
| 71 | #define DW_IC_CON_MASTER 0x1 |
| 72 | #define DW_IC_CON_SPEED_STD 0x2 |
| 73 | #define DW_IC_CON_SPEED_FAST 0x4 |
| 74 | #define DW_IC_CON_10BITADDR_MASTER 0x10 |
| 75 | #define DW_IC_CON_RESTART_EN 0x20 |
| 76 | #define DW_IC_CON_SLAVE_DISABLE 0x40 |
| 77 | |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 78 | #define DW_IC_INTR_RX_UNDER 0x001 |
| 79 | #define DW_IC_INTR_RX_OVER 0x002 |
| 80 | #define DW_IC_INTR_RX_FULL 0x004 |
| 81 | #define DW_IC_INTR_TX_OVER 0x008 |
| 82 | #define DW_IC_INTR_TX_EMPTY 0x010 |
| 83 | #define DW_IC_INTR_RD_REQ 0x020 |
| 84 | #define DW_IC_INTR_TX_ABRT 0x040 |
| 85 | #define DW_IC_INTR_RX_DONE 0x080 |
| 86 | #define DW_IC_INTR_ACTIVITY 0x100 |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 87 | #define DW_IC_INTR_STOP_DET 0x200 |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 88 | #define DW_IC_INTR_START_DET 0x400 |
| 89 | #define DW_IC_INTR_GEN_CALL 0x800 |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 90 | |
| 91 | #define DW_IC_STATUS_ACTIVITY 0x1 |
| 92 | |
| 93 | #define DW_IC_ERR_TX_ABRT 0x1 |
| 94 | |
| 95 | /* |
| 96 | * status codes |
| 97 | */ |
| 98 | #define STATUS_IDLE 0x0 |
| 99 | #define STATUS_WRITE_IN_PROGRESS 0x1 |
| 100 | #define STATUS_READ_IN_PROGRESS 0x2 |
| 101 | |
| 102 | #define TIMEOUT 20 /* ms */ |
| 103 | |
| 104 | /* |
| 105 | * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register |
| 106 | * |
| 107 | * only expected abort codes are listed here |
| 108 | * refer to the datasheet for the full list |
| 109 | */ |
| 110 | #define ABRT_7B_ADDR_NOACK 0 |
| 111 | #define ABRT_10ADDR1_NOACK 1 |
| 112 | #define ABRT_10ADDR2_NOACK 2 |
| 113 | #define ABRT_TXDATA_NOACK 3 |
| 114 | #define ABRT_GCALL_NOACK 4 |
| 115 | #define ABRT_GCALL_READ 5 |
| 116 | #define ABRT_SBYTE_ACKDET 7 |
| 117 | #define ABRT_SBYTE_NORSTRT 9 |
| 118 | #define ABRT_10B_RD_NORSTRT 10 |
| 119 | #define ARB_MASTER_DIS 11 |
| 120 | #define ARB_LOST 12 |
| 121 | |
| 122 | static char *abort_sources[] = { |
| 123 | [ABRT_7B_ADDR_NOACK] = |
| 124 | "slave address not acknowledged (7bit mode)", |
| 125 | [ABRT_10ADDR1_NOACK] = |
| 126 | "first address byte not acknowledged (10bit mode)", |
| 127 | [ABRT_10ADDR2_NOACK] = |
| 128 | "second address byte not acknowledged (10bit mode)", |
| 129 | [ABRT_TXDATA_NOACK] = |
| 130 | "data not acknowledged", |
| 131 | [ABRT_GCALL_NOACK] = |
| 132 | "no acknowledgement for a general call", |
| 133 | [ABRT_GCALL_READ] = |
| 134 | "read after general call", |
| 135 | [ABRT_SBYTE_ACKDET] = |
| 136 | "start byte acknowledged", |
| 137 | [ABRT_SBYTE_NORSTRT] = |
| 138 | "trying to send start byte when restart is disabled", |
| 139 | [ABRT_10B_RD_NORSTRT] = |
| 140 | "trying to read when restart is disabled (10bit mode)", |
| 141 | [ARB_MASTER_DIS] = |
| 142 | "trying to use disabled adapter", |
| 143 | [ARB_LOST] = |
| 144 | "lost arbitration", |
| 145 | }; |
| 146 | |
| 147 | /** |
| 148 | * struct dw_i2c_dev - private i2c-designware data |
| 149 | * @dev: driver model device node |
| 150 | * @base: IO registers pointer |
| 151 | * @cmd_complete: tx completion indicator |
| 152 | * @pump_msg: continue in progress transfers |
| 153 | * @lock: protect this struct and IO registers |
| 154 | * @clk: input reference clock |
| 155 | * @cmd_err: run time hadware error code |
| 156 | * @msgs: points to an array of messages currently being transfered |
| 157 | * @msgs_num: the number of elements in msgs |
| 158 | * @msg_write_idx: the element index of the current tx message in the msgs |
| 159 | * array |
| 160 | * @tx_buf_len: the length of the current tx buffer |
| 161 | * @tx_buf: the current tx buffer |
| 162 | * @msg_read_idx: the element index of the current rx message in the msgs |
| 163 | * array |
| 164 | * @rx_buf_len: the length of the current rx buffer |
| 165 | * @rx_buf: the current rx buffer |
| 166 | * @msg_err: error status of the current transfer |
| 167 | * @status: i2c master status, one of STATUS_* |
| 168 | * @abort_source: copy of the TX_ABRT_SOURCE register |
| 169 | * @irq: interrupt number for the i2c master |
| 170 | * @adapter: i2c subsystem adapter node |
| 171 | * @tx_fifo_depth: depth of the hardware tx fifo |
| 172 | * @rx_fifo_depth: depth of the hardware rx fifo |
| 173 | */ |
| 174 | struct dw_i2c_dev { |
| 175 | struct device *dev; |
| 176 | void __iomem *base; |
| 177 | struct completion cmd_complete; |
| 178 | struct tasklet_struct pump_msg; |
| 179 | struct mutex lock; |
| 180 | struct clk *clk; |
| 181 | int cmd_err; |
| 182 | struct i2c_msg *msgs; |
| 183 | int msgs_num; |
| 184 | int msg_write_idx; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 185 | u32 tx_buf_len; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 186 | u8 *tx_buf; |
| 187 | int msg_read_idx; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 188 | u32 rx_buf_len; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 189 | u8 *rx_buf; |
| 190 | int msg_err; |
| 191 | unsigned int status; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 192 | u32 abort_source; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 193 | int irq; |
| 194 | struct i2c_adapter adapter; |
| 195 | unsigned int tx_fifo_depth; |
| 196 | unsigned int rx_fifo_depth; |
| 197 | }; |
| 198 | |
Shinya Kuribayashi | d60c7e8 | 2009-11-06 21:47:01 +0900 | [diff] [blame] | 199 | static u32 |
| 200 | i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) |
| 201 | { |
| 202 | /* |
| 203 | * DesignWare I2C core doesn't seem to have solid strategy to meet |
| 204 | * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec |
| 205 | * will result in violation of the tHD;STA spec. |
| 206 | */ |
| 207 | if (cond) |
| 208 | /* |
| 209 | * Conditional expression: |
| 210 | * |
| 211 | * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH |
| 212 | * |
| 213 | * This is based on the DW manuals, and represents an ideal |
| 214 | * configuration. The resulting I2C bus speed will be |
| 215 | * faster than any of the others. |
| 216 | * |
| 217 | * If your hardware is free from tHD;STA issue, try this one. |
| 218 | */ |
| 219 | return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset; |
| 220 | else |
| 221 | /* |
| 222 | * Conditional expression: |
| 223 | * |
| 224 | * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) |
| 225 | * |
| 226 | * This is just experimental rule; the tHD;STA period turned |
| 227 | * out to be proportinal to (_HCNT + 3). With this setting, |
| 228 | * we could meet both tHIGH and tHD;STA timing specs. |
| 229 | * |
| 230 | * If unsure, you'd better to take this alternative. |
| 231 | * |
| 232 | * The reason why we need to take into account "tf" here, |
| 233 | * is the same as described in i2c_dw_scl_lcnt(). |
| 234 | */ |
| 235 | return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset; |
| 236 | } |
| 237 | |
| 238 | static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) |
| 239 | { |
| 240 | /* |
| 241 | * Conditional expression: |
| 242 | * |
| 243 | * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) |
| 244 | * |
| 245 | * DW I2C core starts counting the SCL CNTs for the LOW period |
| 246 | * of the SCL clock (tLOW) as soon as it pulls the SCL line. |
| 247 | * In order to meet the tLOW timing spec, we need to take into |
| 248 | * account the fall time of SCL signal (tf). Default tf value |
| 249 | * should be 0.3 us, for safety. |
| 250 | */ |
| 251 | return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset; |
| 252 | } |
| 253 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 254 | /** |
| 255 | * i2c_dw_init() - initialize the designware i2c master hardware |
| 256 | * @dev: device private data |
| 257 | * |
| 258 | * This functions configures and enables the I2C master. |
| 259 | * This function is called during I2C init function, and in case of timeout at |
| 260 | * run time. |
| 261 | */ |
| 262 | static void i2c_dw_init(struct dw_i2c_dev *dev) |
| 263 | { |
| 264 | u32 input_clock_khz = clk_get_rate(dev->clk) / 1000; |
Shinya Kuribayashi | d60c7e8 | 2009-11-06 21:47:01 +0900 | [diff] [blame] | 265 | u32 ic_con, hcnt, lcnt; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 266 | |
| 267 | /* Disable the adapter */ |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 268 | writel(0, dev->base + DW_IC_ENABLE); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 269 | |
| 270 | /* set standard and fast speed deviders for high/low periods */ |
Shinya Kuribayashi | d60c7e8 | 2009-11-06 21:47:01 +0900 | [diff] [blame] | 271 | |
| 272 | /* Standard-mode */ |
| 273 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, |
| 274 | 40, /* tHD;STA = tHIGH = 4.0 us */ |
| 275 | 3, /* tf = 0.3 us */ |
| 276 | 0, /* 0: DW default, 1: Ideal */ |
| 277 | 0); /* No offset */ |
| 278 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, |
| 279 | 47, /* tLOW = 4.7 us */ |
| 280 | 3, /* tf = 0.3 us */ |
| 281 | 0); /* No offset */ |
| 282 | writel(hcnt, dev->base + DW_IC_SS_SCL_HCNT); |
| 283 | writel(lcnt, dev->base + DW_IC_SS_SCL_LCNT); |
| 284 | dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
| 285 | |
| 286 | /* Fast-mode */ |
| 287 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, |
| 288 | 6, /* tHD;STA = tHIGH = 0.6 us */ |
| 289 | 3, /* tf = 0.3 us */ |
| 290 | 0, /* 0: DW default, 1: Ideal */ |
| 291 | 0); /* No offset */ |
| 292 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, |
| 293 | 13, /* tLOW = 1.3 us */ |
| 294 | 3, /* tf = 0.3 us */ |
| 295 | 0); /* No offset */ |
| 296 | writel(hcnt, dev->base + DW_IC_FS_SCL_HCNT); |
| 297 | writel(lcnt, dev->base + DW_IC_FS_SCL_LCNT); |
| 298 | dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 299 | |
| 300 | /* configure the i2c master */ |
| 301 | ic_con = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | |
| 302 | DW_IC_CON_RESTART_EN | DW_IC_CON_SPEED_FAST; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 303 | writel(ic_con, dev->base + DW_IC_CON); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 304 | } |
| 305 | |
| 306 | /* |
| 307 | * Waiting for bus not busy |
| 308 | */ |
| 309 | static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) |
| 310 | { |
| 311 | int timeout = TIMEOUT; |
| 312 | |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 313 | while (readl(dev->base + DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 314 | if (timeout <= 0) { |
| 315 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); |
| 316 | return -ETIMEDOUT; |
| 317 | } |
| 318 | timeout--; |
| 319 | mdelay(1); |
| 320 | } |
| 321 | |
| 322 | return 0; |
| 323 | } |
| 324 | |
| 325 | /* |
| 326 | * Initiate low level master read/write transaction. |
| 327 | * This function is called from i2c_dw_xfer when starting a transfer. |
| 328 | * This function is also called from dw_i2c_pump_msg to continue a transfer |
| 329 | * that is longer than the size of the TX FIFO. |
| 330 | */ |
| 331 | static void |
Shinya Kuribayashi | e77cf23 | 2009-11-06 21:46:04 +0900 | [diff] [blame] | 332 | i2c_dw_xfer_msg(struct dw_i2c_dev *dev) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 333 | { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 334 | struct i2c_msg *msgs = dev->msgs; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 335 | u32 ic_con, intr_mask; |
| 336 | int tx_limit = dev->tx_fifo_depth - readl(dev->base + DW_IC_TXFLR); |
| 337 | int rx_limit = dev->rx_fifo_depth - readl(dev->base + DW_IC_RXFLR); |
| 338 | u32 addr = msgs[dev->msg_write_idx].addr; |
| 339 | u32 buf_len = dev->tx_buf_len; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 340 | |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame^] | 341 | intr_mask = DW_IC_INTR_STOP_DET | DW_IC_INTR_TX_ABRT; |
| 342 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 343 | if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { |
| 344 | /* Disable the adapter */ |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 345 | writel(0, dev->base + DW_IC_ENABLE); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 346 | |
| 347 | /* set the slave (target) address */ |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 348 | writel(msgs[dev->msg_write_idx].addr, dev->base + DW_IC_TAR); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 349 | |
| 350 | /* if the slave address is ten bit address, enable 10BITADDR */ |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 351 | ic_con = readl(dev->base + DW_IC_CON); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 352 | if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) |
| 353 | ic_con |= DW_IC_CON_10BITADDR_MASTER; |
| 354 | else |
| 355 | ic_con &= ~DW_IC_CON_10BITADDR_MASTER; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 356 | writel(ic_con, dev->base + DW_IC_CON); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 357 | |
| 358 | /* Enable the adapter */ |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 359 | writel(1, dev->base + DW_IC_ENABLE); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 360 | } |
| 361 | |
Shinya Kuribayashi | 6d2ea48 | 2009-11-06 21:46:29 +0900 | [diff] [blame] | 362 | for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 363 | /* if target address has changed, we need to |
| 364 | * reprogram the target address in the i2c |
| 365 | * adapter when we are done with this transfer |
| 366 | */ |
| 367 | if (msgs[dev->msg_write_idx].addr != addr) |
| 368 | return; |
| 369 | |
| 370 | if (msgs[dev->msg_write_idx].len == 0) { |
| 371 | dev_err(dev->dev, |
| 372 | "%s: invalid message length\n", __func__); |
| 373 | dev->msg_err = -EINVAL; |
| 374 | return; |
| 375 | } |
| 376 | |
| 377 | if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { |
| 378 | /* new i2c_msg */ |
| 379 | dev->tx_buf = msgs[dev->msg_write_idx].buf; |
| 380 | buf_len = msgs[dev->msg_write_idx].len; |
| 381 | } |
| 382 | |
| 383 | while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { |
| 384 | if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 385 | writel(0x100, dev->base + DW_IC_DATA_CMD); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 386 | rx_limit--; |
| 387 | } else |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 388 | writel(*(dev->tx_buf++), |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 389 | dev->base + DW_IC_DATA_CMD); |
| 390 | tx_limit--; buf_len--; |
| 391 | } |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame^] | 392 | |
| 393 | dev->tx_buf_len = buf_len; |
| 394 | |
| 395 | if (buf_len > 0) { |
| 396 | /* more bytes to be written */ |
| 397 | intr_mask |= DW_IC_INTR_TX_EMPTY; |
| 398 | dev->status |= STATUS_WRITE_IN_PROGRESS; |
| 399 | break; |
| 400 | } else |
| 401 | dev->status &= ~STATUS_WRITE_IN_PROGRESS; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 402 | } |
| 403 | |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 404 | writel(intr_mask, dev->base + DW_IC_INTR_MASK); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 405 | } |
| 406 | |
| 407 | static void |
Shinya Kuribayashi | 78839bd | 2009-11-06 21:45:39 +0900 | [diff] [blame] | 408 | i2c_dw_read(struct dw_i2c_dev *dev) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 409 | { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 410 | struct i2c_msg *msgs = dev->msgs; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 411 | u32 addr = msgs[dev->msg_read_idx].addr; |
| 412 | int rx_valid = readl(dev->base + DW_IC_RXFLR); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 413 | |
Shinya Kuribayashi | 6d2ea48 | 2009-11-06 21:46:29 +0900 | [diff] [blame] | 414 | for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 415 | u32 len; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 416 | u8 *buf; |
| 417 | |
| 418 | if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) |
| 419 | continue; |
| 420 | |
| 421 | /* different i2c client, reprogram the i2c adapter */ |
| 422 | if (msgs[dev->msg_read_idx].addr != addr) |
| 423 | return; |
| 424 | |
| 425 | if (!(dev->status & STATUS_READ_IN_PROGRESS)) { |
| 426 | len = msgs[dev->msg_read_idx].len; |
| 427 | buf = msgs[dev->msg_read_idx].buf; |
| 428 | } else { |
| 429 | len = dev->rx_buf_len; |
| 430 | buf = dev->rx_buf; |
| 431 | } |
| 432 | |
| 433 | for (; len > 0 && rx_valid > 0; len--, rx_valid--) |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 434 | *buf++ = readl(dev->base + DW_IC_DATA_CMD); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 435 | |
| 436 | if (len > 0) { |
| 437 | dev->status |= STATUS_READ_IN_PROGRESS; |
| 438 | dev->rx_buf_len = len; |
| 439 | dev->rx_buf = buf; |
| 440 | return; |
| 441 | } else |
| 442 | dev->status &= ~STATUS_READ_IN_PROGRESS; |
| 443 | } |
| 444 | } |
| 445 | |
| 446 | /* |
| 447 | * Prepare controller for a transaction and call i2c_dw_xfer_msg |
| 448 | */ |
| 449 | static int |
| 450 | i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) |
| 451 | { |
| 452 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); |
| 453 | int ret; |
| 454 | |
| 455 | dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); |
| 456 | |
| 457 | mutex_lock(&dev->lock); |
| 458 | |
| 459 | INIT_COMPLETION(dev->cmd_complete); |
| 460 | dev->msgs = msgs; |
| 461 | dev->msgs_num = num; |
| 462 | dev->cmd_err = 0; |
| 463 | dev->msg_write_idx = 0; |
| 464 | dev->msg_read_idx = 0; |
| 465 | dev->msg_err = 0; |
| 466 | dev->status = STATUS_IDLE; |
| 467 | |
| 468 | ret = i2c_dw_wait_bus_not_busy(dev); |
| 469 | if (ret < 0) |
| 470 | goto done; |
| 471 | |
| 472 | /* start the transfers */ |
Shinya Kuribayashi | e77cf23 | 2009-11-06 21:46:04 +0900 | [diff] [blame] | 473 | i2c_dw_xfer_msg(dev); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 474 | |
| 475 | /* wait for tx to complete */ |
| 476 | ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ); |
| 477 | if (ret == 0) { |
| 478 | dev_err(dev->dev, "controller timed out\n"); |
| 479 | i2c_dw_init(dev); |
| 480 | ret = -ETIMEDOUT; |
| 481 | goto done; |
| 482 | } else if (ret < 0) |
| 483 | goto done; |
| 484 | |
| 485 | if (dev->msg_err) { |
| 486 | ret = dev->msg_err; |
| 487 | goto done; |
| 488 | } |
| 489 | |
| 490 | /* no error */ |
| 491 | if (likely(!dev->cmd_err)) { |
| 492 | /* read rx fifo, and disable the adapter */ |
| 493 | do { |
Shinya Kuribayashi | 78839bd | 2009-11-06 21:45:39 +0900 | [diff] [blame] | 494 | i2c_dw_read(dev); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 495 | } while (dev->status & STATUS_READ_IN_PROGRESS); |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 496 | writel(0, dev->base + DW_IC_ENABLE); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 497 | ret = num; |
| 498 | goto done; |
| 499 | } |
| 500 | |
| 501 | /* We have an error */ |
| 502 | if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { |
| 503 | unsigned long abort_source = dev->abort_source; |
| 504 | int i; |
| 505 | |
| 506 | for_each_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) { |
| 507 | dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); |
| 508 | } |
| 509 | } |
| 510 | ret = -EIO; |
| 511 | |
| 512 | done: |
| 513 | mutex_unlock(&dev->lock); |
| 514 | |
| 515 | return ret; |
| 516 | } |
| 517 | |
| 518 | static u32 i2c_dw_func(struct i2c_adapter *adap) |
| 519 | { |
| 520 | return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR; |
| 521 | } |
| 522 | |
| 523 | static void dw_i2c_pump_msg(unsigned long data) |
| 524 | { |
| 525 | struct dw_i2c_dev *dev = (struct dw_i2c_dev *) data; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 526 | u32 intr_mask; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 527 | |
Shinya Kuribayashi | 78839bd | 2009-11-06 21:45:39 +0900 | [diff] [blame] | 528 | i2c_dw_read(dev); |
Shinya Kuribayashi | e77cf23 | 2009-11-06 21:46:04 +0900 | [diff] [blame] | 529 | i2c_dw_xfer_msg(dev); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 530 | |
| 531 | intr_mask = DW_IC_INTR_STOP_DET | DW_IC_INTR_TX_ABRT; |
| 532 | if (dev->status & STATUS_WRITE_IN_PROGRESS) |
| 533 | intr_mask |= DW_IC_INTR_TX_EMPTY; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 534 | writel(intr_mask, dev->base + DW_IC_INTR_MASK); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 535 | } |
| 536 | |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 537 | static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) |
| 538 | { |
| 539 | u32 stat; |
| 540 | |
| 541 | /* |
| 542 | * The IC_INTR_STAT register just indicates "enabled" interrupts. |
| 543 | * Ths unmasked raw version of interrupt status bits are available |
| 544 | * in the IC_RAW_INTR_STAT register. |
| 545 | * |
| 546 | * That is, |
| 547 | * stat = readl(IC_INTR_STAT); |
| 548 | * equals to, |
| 549 | * stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK); |
| 550 | * |
| 551 | * The raw version might be useful for debugging purposes. |
| 552 | */ |
| 553 | stat = readl(dev->base + DW_IC_INTR_STAT); |
| 554 | |
| 555 | /* |
| 556 | * Do not use the IC_CLR_INTR register to clear interrupts, or |
| 557 | * you'll miss some interrupts, triggered during the period from |
| 558 | * readl(IC_INTR_STAT) to readl(IC_CLR_INTR). |
| 559 | * |
| 560 | * Instead, use the separately-prepared IC_CLR_* registers. |
| 561 | */ |
| 562 | if (stat & DW_IC_INTR_RX_UNDER) |
| 563 | readl(dev->base + DW_IC_CLR_RX_UNDER); |
| 564 | if (stat & DW_IC_INTR_RX_OVER) |
| 565 | readl(dev->base + DW_IC_CLR_RX_OVER); |
| 566 | if (stat & DW_IC_INTR_TX_OVER) |
| 567 | readl(dev->base + DW_IC_CLR_TX_OVER); |
| 568 | if (stat & DW_IC_INTR_RD_REQ) |
| 569 | readl(dev->base + DW_IC_CLR_RD_REQ); |
| 570 | if (stat & DW_IC_INTR_TX_ABRT) { |
| 571 | /* |
| 572 | * The IC_TX_ABRT_SOURCE register is cleared whenever |
| 573 | * the IC_CLR_TX_ABRT is read. Preserve it beforehand. |
| 574 | */ |
| 575 | dev->abort_source = readl(dev->base + DW_IC_TX_ABRT_SOURCE); |
| 576 | readl(dev->base + DW_IC_CLR_TX_ABRT); |
| 577 | } |
| 578 | if (stat & DW_IC_INTR_RX_DONE) |
| 579 | readl(dev->base + DW_IC_CLR_RX_DONE); |
| 580 | if (stat & DW_IC_INTR_ACTIVITY) |
| 581 | readl(dev->base + DW_IC_CLR_ACTIVITY); |
| 582 | if (stat & DW_IC_INTR_STOP_DET) |
| 583 | readl(dev->base + DW_IC_CLR_STOP_DET); |
| 584 | if (stat & DW_IC_INTR_START_DET) |
| 585 | readl(dev->base + DW_IC_CLR_START_DET); |
| 586 | if (stat & DW_IC_INTR_GEN_CALL) |
| 587 | readl(dev->base + DW_IC_CLR_GEN_CALL); |
| 588 | |
| 589 | return stat; |
| 590 | } |
| 591 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 592 | /* |
| 593 | * Interrupt service routine. This gets called whenever an I2C interrupt |
| 594 | * occurs. |
| 595 | */ |
| 596 | static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) |
| 597 | { |
| 598 | struct dw_i2c_dev *dev = dev_id; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 599 | u32 stat; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 600 | |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 601 | stat = i2c_dw_read_clear_intrbits(dev); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 602 | dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 603 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 604 | if (stat & DW_IC_INTR_TX_ABRT) { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 605 | dev->cmd_err |= DW_IC_ERR_TX_ABRT; |
| 606 | dev->status = STATUS_IDLE; |
| 607 | } else if (stat & DW_IC_INTR_TX_EMPTY) |
| 608 | tasklet_schedule(&dev->pump_msg); |
| 609 | |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 610 | writel(0, dev->base + DW_IC_INTR_MASK); /* disable interrupts */ |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 611 | if (stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) |
| 612 | complete(&dev->cmd_complete); |
| 613 | |
| 614 | return IRQ_HANDLED; |
| 615 | } |
| 616 | |
| 617 | static struct i2c_algorithm i2c_dw_algo = { |
| 618 | .master_xfer = i2c_dw_xfer, |
| 619 | .functionality = i2c_dw_func, |
| 620 | }; |
| 621 | |
| 622 | static int __devinit dw_i2c_probe(struct platform_device *pdev) |
| 623 | { |
| 624 | struct dw_i2c_dev *dev; |
| 625 | struct i2c_adapter *adap; |
Shinya Kuribayashi | 91b52ca | 2009-11-06 21:45:07 +0900 | [diff] [blame] | 626 | struct resource *mem, *ioarea; |
| 627 | int irq, r; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 628 | |
| 629 | /* NOTE: driver uses the static register mapping */ |
| 630 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 631 | if (!mem) { |
| 632 | dev_err(&pdev->dev, "no mem resource?\n"); |
| 633 | return -EINVAL; |
| 634 | } |
| 635 | |
Shinya Kuribayashi | 91b52ca | 2009-11-06 21:45:07 +0900 | [diff] [blame] | 636 | irq = platform_get_irq(pdev, 0); |
| 637 | if (irq < 0) { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 638 | dev_err(&pdev->dev, "no irq resource?\n"); |
Shinya Kuribayashi | 91b52ca | 2009-11-06 21:45:07 +0900 | [diff] [blame] | 639 | return irq; /* -ENXIO */ |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 640 | } |
| 641 | |
| 642 | ioarea = request_mem_region(mem->start, resource_size(mem), |
| 643 | pdev->name); |
| 644 | if (!ioarea) { |
| 645 | dev_err(&pdev->dev, "I2C region already claimed\n"); |
| 646 | return -EBUSY; |
| 647 | } |
| 648 | |
| 649 | dev = kzalloc(sizeof(struct dw_i2c_dev), GFP_KERNEL); |
| 650 | if (!dev) { |
| 651 | r = -ENOMEM; |
| 652 | goto err_release_region; |
| 653 | } |
| 654 | |
| 655 | init_completion(&dev->cmd_complete); |
| 656 | tasklet_init(&dev->pump_msg, dw_i2c_pump_msg, (unsigned long) dev); |
| 657 | mutex_init(&dev->lock); |
| 658 | dev->dev = get_device(&pdev->dev); |
Shinya Kuribayashi | 91b52ca | 2009-11-06 21:45:07 +0900 | [diff] [blame] | 659 | dev->irq = irq; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 660 | platform_set_drvdata(pdev, dev); |
| 661 | |
| 662 | dev->clk = clk_get(&pdev->dev, NULL); |
| 663 | if (IS_ERR(dev->clk)) { |
| 664 | r = -ENODEV; |
| 665 | goto err_free_mem; |
| 666 | } |
| 667 | clk_enable(dev->clk); |
| 668 | |
| 669 | dev->base = ioremap(mem->start, resource_size(mem)); |
| 670 | if (dev->base == NULL) { |
| 671 | dev_err(&pdev->dev, "failure mapping io resources\n"); |
| 672 | r = -EBUSY; |
| 673 | goto err_unuse_clocks; |
| 674 | } |
| 675 | { |
| 676 | u32 param1 = readl(dev->base + DW_IC_COMP_PARAM_1); |
| 677 | |
| 678 | dev->tx_fifo_depth = ((param1 >> 16) & 0xff) + 1; |
| 679 | dev->rx_fifo_depth = ((param1 >> 8) & 0xff) + 1; |
| 680 | } |
| 681 | i2c_dw_init(dev); |
| 682 | |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 683 | writel(0, dev->base + DW_IC_INTR_MASK); /* disable IRQ */ |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 684 | r = request_irq(dev->irq, i2c_dw_isr, 0, pdev->name, dev); |
| 685 | if (r) { |
| 686 | dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq); |
| 687 | goto err_iounmap; |
| 688 | } |
| 689 | |
| 690 | adap = &dev->adapter; |
| 691 | i2c_set_adapdata(adap, dev); |
| 692 | adap->owner = THIS_MODULE; |
| 693 | adap->class = I2C_CLASS_HWMON; |
| 694 | strlcpy(adap->name, "Synopsys DesignWare I2C adapter", |
| 695 | sizeof(adap->name)); |
| 696 | adap->algo = &i2c_dw_algo; |
| 697 | adap->dev.parent = &pdev->dev; |
| 698 | |
| 699 | adap->nr = pdev->id; |
| 700 | r = i2c_add_numbered_adapter(adap); |
| 701 | if (r) { |
| 702 | dev_err(&pdev->dev, "failure adding adapter\n"); |
| 703 | goto err_free_irq; |
| 704 | } |
| 705 | |
| 706 | return 0; |
| 707 | |
| 708 | err_free_irq: |
| 709 | free_irq(dev->irq, dev); |
| 710 | err_iounmap: |
| 711 | iounmap(dev->base); |
| 712 | err_unuse_clocks: |
| 713 | clk_disable(dev->clk); |
| 714 | clk_put(dev->clk); |
| 715 | dev->clk = NULL; |
| 716 | err_free_mem: |
| 717 | platform_set_drvdata(pdev, NULL); |
| 718 | put_device(&pdev->dev); |
| 719 | kfree(dev); |
| 720 | err_release_region: |
| 721 | release_mem_region(mem->start, resource_size(mem)); |
| 722 | |
| 723 | return r; |
| 724 | } |
| 725 | |
| 726 | static int __devexit dw_i2c_remove(struct platform_device *pdev) |
| 727 | { |
| 728 | struct dw_i2c_dev *dev = platform_get_drvdata(pdev); |
| 729 | struct resource *mem; |
| 730 | |
| 731 | platform_set_drvdata(pdev, NULL); |
| 732 | i2c_del_adapter(&dev->adapter); |
| 733 | put_device(&pdev->dev); |
| 734 | |
| 735 | clk_disable(dev->clk); |
| 736 | clk_put(dev->clk); |
| 737 | dev->clk = NULL; |
| 738 | |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 739 | writel(0, dev->base + DW_IC_ENABLE); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 740 | free_irq(dev->irq, dev); |
| 741 | kfree(dev); |
| 742 | |
| 743 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 744 | release_mem_region(mem->start, resource_size(mem)); |
| 745 | return 0; |
| 746 | } |
| 747 | |
| 748 | /* work with hotplug and coldplug */ |
| 749 | MODULE_ALIAS("platform:i2c_designware"); |
| 750 | |
| 751 | static struct platform_driver dw_i2c_driver = { |
| 752 | .remove = __devexit_p(dw_i2c_remove), |
| 753 | .driver = { |
| 754 | .name = "i2c_designware", |
| 755 | .owner = THIS_MODULE, |
| 756 | }, |
| 757 | }; |
| 758 | |
| 759 | static int __init dw_i2c_init_driver(void) |
| 760 | { |
| 761 | return platform_driver_probe(&dw_i2c_driver, dw_i2c_probe); |
| 762 | } |
| 763 | module_init(dw_i2c_init_driver); |
| 764 | |
| 765 | static void __exit dw_i2c_exit_driver(void) |
| 766 | { |
| 767 | platform_driver_unregister(&dw_i2c_driver); |
| 768 | } |
| 769 | module_exit(dw_i2c_exit_driver); |
| 770 | |
| 771 | MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>"); |
| 772 | MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter"); |
| 773 | MODULE_LICENSE("GPL"); |