Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 1996, 97, 2000, 2001 by Ralf Baechle |
| 7 | * Copyright (C) 2001 MIPS Technologies, Inc. |
| 8 | */ |
| 9 | #include <linux/kernel.h> |
| 10 | #include <linux/sched.h> |
| 11 | #include <linux/signal.h> |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 12 | #include <linux/module.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | #include <asm/branch.h> |
| 14 | #include <asm/cpu.h> |
| 15 | #include <asm/cpu-features.h> |
Ralf Baechle | 1d74f6b | 2005-05-09 13:16:07 +0000 | [diff] [blame] | 16 | #include <asm/fpu.h> |
Leonid Yegoshin | fb6883e | 2013-03-25 13:08:40 -0500 | [diff] [blame] | 17 | #include <asm/fpu_emulator.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | #include <asm/inst.h> |
| 19 | #include <asm/ptrace.h> |
| 20 | #include <asm/uaccess.h> |
| 21 | |
Leonid Yegoshin | fb6883e | 2013-03-25 13:08:40 -0500 | [diff] [blame] | 22 | /* |
Steven J. Hill | 8508488 | 2013-03-25 13:45:19 -0500 | [diff] [blame] | 23 | * Calculate and return exception PC in case of branch delay slot |
| 24 | * for microMIPS and MIPS16e. It does not clear the ISA mode bit. |
Leonid Yegoshin | fb6883e | 2013-03-25 13:08:40 -0500 | [diff] [blame] | 25 | */ |
| 26 | int __isa_exception_epc(struct pt_regs *regs) |
| 27 | { |
Leonid Yegoshin | fb6883e | 2013-03-25 13:08:40 -0500 | [diff] [blame] | 28 | unsigned short inst; |
Steven J. Hill | 8508488 | 2013-03-25 13:45:19 -0500 | [diff] [blame] | 29 | long epc = regs->cp0_epc; |
Leonid Yegoshin | fb6883e | 2013-03-25 13:08:40 -0500 | [diff] [blame] | 30 | |
| 31 | /* Calculate exception PC in branch delay slot. */ |
| 32 | if (__get_user(inst, (u16 __user *) msk_isa16_mode(epc))) { |
| 33 | /* This should never happen because delay slot was checked. */ |
| 34 | force_sig(SIGSEGV, current); |
| 35 | return epc; |
| 36 | } |
Steven J. Hill | 8508488 | 2013-03-25 13:45:19 -0500 | [diff] [blame] | 37 | if (cpu_has_mips16) { |
| 38 | if (((union mips16e_instruction)inst).ri.opcode |
| 39 | == MIPS16e_jal_op) |
| 40 | epc += 4; |
| 41 | else |
| 42 | epc += 2; |
| 43 | } else if (mm_insn_16bit(inst)) |
Leonid Yegoshin | fb6883e | 2013-03-25 13:08:40 -0500 | [diff] [blame] | 44 | epc += 2; |
| 45 | else |
| 46 | epc += 4; |
| 47 | |
| 48 | return epc; |
| 49 | } |
| 50 | |
Ralf Baechle | 76fbfc3 | 2014-04-29 15:21:24 +0200 | [diff] [blame] | 51 | /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */ |
| 52 | static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7}; |
| 53 | |
| 54 | int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, |
| 55 | unsigned long *contpc) |
| 56 | { |
| 57 | union mips_instruction insn = (union mips_instruction)dec_insn.insn; |
| 58 | int bc_false = 0; |
| 59 | unsigned int fcr31; |
| 60 | unsigned int bit; |
| 61 | |
| 62 | if (!cpu_has_mmips) |
| 63 | return 0; |
| 64 | |
| 65 | switch (insn.mm_i_format.opcode) { |
| 66 | case mm_pool32a_op: |
| 67 | if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) == |
| 68 | mm_pool32axf_op) { |
| 69 | switch (insn.mm_i_format.simmediate >> |
| 70 | MM_POOL32A_MINOR_SHIFT) { |
| 71 | case mm_jalr_op: |
| 72 | case mm_jalrhb_op: |
| 73 | case mm_jalrs_op: |
| 74 | case mm_jalrshb_op: |
| 75 | if (insn.mm_i_format.rt != 0) /* Not mm_jr */ |
| 76 | regs->regs[insn.mm_i_format.rt] = |
| 77 | regs->cp0_epc + |
| 78 | dec_insn.pc_inc + |
| 79 | dec_insn.next_pc_inc; |
| 80 | *contpc = regs->regs[insn.mm_i_format.rs]; |
| 81 | return 1; |
| 82 | } |
| 83 | } |
| 84 | break; |
| 85 | case mm_pool32i_op: |
| 86 | switch (insn.mm_i_format.rt) { |
| 87 | case mm_bltzals_op: |
| 88 | case mm_bltzal_op: |
| 89 | regs->regs[31] = regs->cp0_epc + |
| 90 | dec_insn.pc_inc + |
| 91 | dec_insn.next_pc_inc; |
| 92 | /* Fall through */ |
| 93 | case mm_bltz_op: |
| 94 | if ((long)regs->regs[insn.mm_i_format.rs] < 0) |
| 95 | *contpc = regs->cp0_epc + |
| 96 | dec_insn.pc_inc + |
| 97 | (insn.mm_i_format.simmediate << 1); |
| 98 | else |
| 99 | *contpc = regs->cp0_epc + |
| 100 | dec_insn.pc_inc + |
| 101 | dec_insn.next_pc_inc; |
| 102 | return 1; |
| 103 | case mm_bgezals_op: |
| 104 | case mm_bgezal_op: |
| 105 | regs->regs[31] = regs->cp0_epc + |
| 106 | dec_insn.pc_inc + |
| 107 | dec_insn.next_pc_inc; |
| 108 | /* Fall through */ |
| 109 | case mm_bgez_op: |
| 110 | if ((long)regs->regs[insn.mm_i_format.rs] >= 0) |
| 111 | *contpc = regs->cp0_epc + |
| 112 | dec_insn.pc_inc + |
| 113 | (insn.mm_i_format.simmediate << 1); |
| 114 | else |
| 115 | *contpc = regs->cp0_epc + |
| 116 | dec_insn.pc_inc + |
| 117 | dec_insn.next_pc_inc; |
| 118 | return 1; |
| 119 | case mm_blez_op: |
| 120 | if ((long)regs->regs[insn.mm_i_format.rs] <= 0) |
| 121 | *contpc = regs->cp0_epc + |
| 122 | dec_insn.pc_inc + |
| 123 | (insn.mm_i_format.simmediate << 1); |
| 124 | else |
| 125 | *contpc = regs->cp0_epc + |
| 126 | dec_insn.pc_inc + |
| 127 | dec_insn.next_pc_inc; |
| 128 | return 1; |
| 129 | case mm_bgtz_op: |
| 130 | if ((long)regs->regs[insn.mm_i_format.rs] <= 0) |
| 131 | *contpc = regs->cp0_epc + |
| 132 | dec_insn.pc_inc + |
| 133 | (insn.mm_i_format.simmediate << 1); |
| 134 | else |
| 135 | *contpc = regs->cp0_epc + |
| 136 | dec_insn.pc_inc + |
| 137 | dec_insn.next_pc_inc; |
| 138 | return 1; |
| 139 | case mm_bc2f_op: |
| 140 | case mm_bc1f_op: |
| 141 | bc_false = 1; |
| 142 | /* Fall through */ |
| 143 | case mm_bc2t_op: |
| 144 | case mm_bc1t_op: |
| 145 | preempt_disable(); |
| 146 | if (is_fpu_owner()) |
Manuel Lauss | 842dfc1 | 2014-11-07 14:13:54 +0100 | [diff] [blame] | 147 | fcr31 = read_32bit_cp1_register(CP1_STATUS); |
Ralf Baechle | 76fbfc3 | 2014-04-29 15:21:24 +0200 | [diff] [blame] | 148 | else |
| 149 | fcr31 = current->thread.fpu.fcr31; |
| 150 | preempt_enable(); |
| 151 | |
| 152 | if (bc_false) |
| 153 | fcr31 = ~fcr31; |
| 154 | |
| 155 | bit = (insn.mm_i_format.rs >> 2); |
| 156 | bit += (bit != 0); |
| 157 | bit += 23; |
| 158 | if (fcr31 & (1 << bit)) |
| 159 | *contpc = regs->cp0_epc + |
| 160 | dec_insn.pc_inc + |
| 161 | (insn.mm_i_format.simmediate << 1); |
| 162 | else |
| 163 | *contpc = regs->cp0_epc + |
| 164 | dec_insn.pc_inc + dec_insn.next_pc_inc; |
| 165 | return 1; |
| 166 | } |
| 167 | break; |
| 168 | case mm_pool16c_op: |
| 169 | switch (insn.mm_i_format.rt) { |
| 170 | case mm_jalr16_op: |
| 171 | case mm_jalrs16_op: |
| 172 | regs->regs[31] = regs->cp0_epc + |
| 173 | dec_insn.pc_inc + dec_insn.next_pc_inc; |
| 174 | /* Fall through */ |
| 175 | case mm_jr16_op: |
| 176 | *contpc = regs->regs[insn.mm_i_format.rs]; |
| 177 | return 1; |
| 178 | } |
| 179 | break; |
| 180 | case mm_beqz16_op: |
| 181 | if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0) |
| 182 | *contpc = regs->cp0_epc + |
| 183 | dec_insn.pc_inc + |
| 184 | (insn.mm_b1_format.simmediate << 1); |
| 185 | else |
| 186 | *contpc = regs->cp0_epc + |
| 187 | dec_insn.pc_inc + dec_insn.next_pc_inc; |
| 188 | return 1; |
| 189 | case mm_bnez16_op: |
| 190 | if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0) |
| 191 | *contpc = regs->cp0_epc + |
| 192 | dec_insn.pc_inc + |
| 193 | (insn.mm_b1_format.simmediate << 1); |
| 194 | else |
| 195 | *contpc = regs->cp0_epc + |
| 196 | dec_insn.pc_inc + dec_insn.next_pc_inc; |
| 197 | return 1; |
| 198 | case mm_b16_op: |
| 199 | *contpc = regs->cp0_epc + dec_insn.pc_inc + |
| 200 | (insn.mm_b0_format.simmediate << 1); |
| 201 | return 1; |
| 202 | case mm_beq32_op: |
| 203 | if (regs->regs[insn.mm_i_format.rs] == |
| 204 | regs->regs[insn.mm_i_format.rt]) |
| 205 | *contpc = regs->cp0_epc + |
| 206 | dec_insn.pc_inc + |
| 207 | (insn.mm_i_format.simmediate << 1); |
| 208 | else |
| 209 | *contpc = regs->cp0_epc + |
| 210 | dec_insn.pc_inc + |
| 211 | dec_insn.next_pc_inc; |
| 212 | return 1; |
| 213 | case mm_bne32_op: |
| 214 | if (regs->regs[insn.mm_i_format.rs] != |
| 215 | regs->regs[insn.mm_i_format.rt]) |
| 216 | *contpc = regs->cp0_epc + |
| 217 | dec_insn.pc_inc + |
| 218 | (insn.mm_i_format.simmediate << 1); |
| 219 | else |
| 220 | *contpc = regs->cp0_epc + |
| 221 | dec_insn.pc_inc + dec_insn.next_pc_inc; |
| 222 | return 1; |
| 223 | case mm_jalx32_op: |
| 224 | regs->regs[31] = regs->cp0_epc + |
| 225 | dec_insn.pc_inc + dec_insn.next_pc_inc; |
| 226 | *contpc = regs->cp0_epc + dec_insn.pc_inc; |
| 227 | *contpc >>= 28; |
| 228 | *contpc <<= 28; |
| 229 | *contpc |= (insn.j_format.target << 2); |
| 230 | return 1; |
| 231 | case mm_jals32_op: |
| 232 | case mm_jal32_op: |
| 233 | regs->regs[31] = regs->cp0_epc + |
| 234 | dec_insn.pc_inc + dec_insn.next_pc_inc; |
| 235 | /* Fall through */ |
| 236 | case mm_j32_op: |
| 237 | *contpc = regs->cp0_epc + dec_insn.pc_inc; |
| 238 | *contpc >>= 27; |
| 239 | *contpc <<= 27; |
| 240 | *contpc |= (insn.j_format.target << 1); |
| 241 | set_isa16_mode(*contpc); |
| 242 | return 1; |
| 243 | } |
| 244 | return 0; |
| 245 | } |
| 246 | |
Leonid Yegoshin | fb6883e | 2013-03-25 13:08:40 -0500 | [diff] [blame] | 247 | /* |
| 248 | * Compute return address and emulate branch in microMIPS mode after an |
| 249 | * exception only. It does not handle compact branches/jumps and cannot |
| 250 | * be used in interrupt context. (Compact branches/jumps do not cause |
| 251 | * exceptions.) |
| 252 | */ |
| 253 | int __microMIPS_compute_return_epc(struct pt_regs *regs) |
| 254 | { |
| 255 | u16 __user *pc16; |
| 256 | u16 halfword; |
| 257 | unsigned int word; |
| 258 | unsigned long contpc; |
| 259 | struct mm_decoded_insn mminsn = { 0 }; |
| 260 | |
| 261 | mminsn.micro_mips_mode = 1; |
| 262 | |
| 263 | /* This load never faults. */ |
| 264 | pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc); |
| 265 | __get_user(halfword, pc16); |
| 266 | pc16++; |
| 267 | contpc = regs->cp0_epc + 2; |
| 268 | word = ((unsigned int)halfword << 16); |
| 269 | mminsn.pc_inc = 2; |
| 270 | |
| 271 | if (!mm_insn_16bit(halfword)) { |
| 272 | __get_user(halfword, pc16); |
| 273 | pc16++; |
| 274 | contpc = regs->cp0_epc + 4; |
| 275 | mminsn.pc_inc = 4; |
| 276 | word |= halfword; |
| 277 | } |
| 278 | mminsn.insn = word; |
| 279 | |
| 280 | if (get_user(halfword, pc16)) |
| 281 | goto sigsegv; |
| 282 | mminsn.next_pc_inc = 2; |
| 283 | word = ((unsigned int)halfword << 16); |
| 284 | |
| 285 | if (!mm_insn_16bit(halfword)) { |
| 286 | pc16++; |
| 287 | if (get_user(halfword, pc16)) |
| 288 | goto sigsegv; |
| 289 | mminsn.next_pc_inc = 4; |
| 290 | word |= halfword; |
| 291 | } |
| 292 | mminsn.next_insn = word; |
| 293 | |
| 294 | mm_isBranchInstr(regs, mminsn, &contpc); |
| 295 | |
| 296 | regs->cp0_epc = contpc; |
| 297 | |
| 298 | return 0; |
| 299 | |
| 300 | sigsegv: |
| 301 | force_sig(SIGSEGV, current); |
| 302 | return -EFAULT; |
| 303 | } |
| 304 | |
Steven J. Hill | 8508488 | 2013-03-25 13:45:19 -0500 | [diff] [blame] | 305 | /* |
| 306 | * Compute return address and emulate branch in MIPS16e mode after an |
| 307 | * exception only. It does not handle compact branches/jumps and cannot |
| 308 | * be used in interrupt context. (Compact branches/jumps do not cause |
| 309 | * exceptions.) |
| 310 | */ |
| 311 | int __MIPS16e_compute_return_epc(struct pt_regs *regs) |
| 312 | { |
| 313 | u16 __user *addr; |
| 314 | union mips16e_instruction inst; |
| 315 | u16 inst2; |
| 316 | u32 fullinst; |
| 317 | long epc; |
| 318 | |
| 319 | epc = regs->cp0_epc; |
| 320 | |
| 321 | /* Read the instruction. */ |
| 322 | addr = (u16 __user *)msk_isa16_mode(epc); |
| 323 | if (__get_user(inst.full, addr)) { |
| 324 | force_sig(SIGSEGV, current); |
| 325 | return -EFAULT; |
| 326 | } |
| 327 | |
| 328 | switch (inst.ri.opcode) { |
| 329 | case MIPS16e_extend_op: |
| 330 | regs->cp0_epc += 4; |
| 331 | return 0; |
| 332 | |
| 333 | /* |
| 334 | * JAL and JALX in MIPS16e mode |
| 335 | */ |
| 336 | case MIPS16e_jal_op: |
| 337 | addr += 1; |
| 338 | if (__get_user(inst2, addr)) { |
| 339 | force_sig(SIGSEGV, current); |
| 340 | return -EFAULT; |
| 341 | } |
| 342 | fullinst = ((unsigned)inst.full << 16) | inst2; |
| 343 | regs->regs[31] = epc + 6; |
| 344 | epc += 4; |
| 345 | epc >>= 28; |
| 346 | epc <<= 28; |
| 347 | /* |
| 348 | * JAL:5 X:1 TARGET[20-16]:5 TARGET[25:21]:5 TARGET[15:0]:16 |
| 349 | * |
| 350 | * ......TARGET[15:0].................TARGET[20:16]........... |
| 351 | * ......TARGET[25:21] |
| 352 | */ |
| 353 | epc |= |
| 354 | ((fullinst & 0xffff) << 2) | ((fullinst & 0x3e00000) >> 3) | |
| 355 | ((fullinst & 0x1f0000) << 7); |
| 356 | if (!inst.jal.x) |
| 357 | set_isa16_mode(epc); /* Set ISA mode bit. */ |
| 358 | regs->cp0_epc = epc; |
| 359 | return 0; |
| 360 | |
| 361 | /* |
| 362 | * J(AL)R(C) |
| 363 | */ |
| 364 | case MIPS16e_rr_op: |
| 365 | if (inst.rr.func == MIPS16e_jr_func) { |
| 366 | |
| 367 | if (inst.rr.ra) |
| 368 | regs->cp0_epc = regs->regs[31]; |
| 369 | else |
| 370 | regs->cp0_epc = |
| 371 | regs->regs[reg16to32[inst.rr.rx]]; |
| 372 | |
| 373 | if (inst.rr.l) { |
| 374 | if (inst.rr.nd) |
| 375 | regs->regs[31] = epc + 2; |
| 376 | else |
| 377 | regs->regs[31] = epc + 4; |
| 378 | } |
| 379 | return 0; |
| 380 | } |
| 381 | break; |
| 382 | } |
| 383 | |
| 384 | /* |
| 385 | * All other cases have no branch delay slot and are 16-bits. |
| 386 | * Branches do not cause an exception. |
| 387 | */ |
| 388 | regs->cp0_epc += 2; |
| 389 | |
| 390 | return 0; |
| 391 | } |
| 392 | |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 393 | /** |
| 394 | * __compute_return_epc_for_insn - Computes the return address and do emulate |
| 395 | * branch simulation, if required. |
| 396 | * |
| 397 | * @regs: Pointer to pt_regs |
| 398 | * @insn: branch instruction to decode |
| 399 | * @returns: -EFAULT on error and forces SIGBUS, and on success |
| 400 | * returns 0 or BRANCH_LIKELY_TAKEN as appropriate after |
| 401 | * evaluating the branch. |
Markos Chandras | a8ff66f | 2014-11-26 12:57:54 +0000 | [diff] [blame] | 402 | * |
| 403 | * MIPS R6 Compact branches and forbidden slots: |
| 404 | * Compact branches do not throw exceptions because they do |
| 405 | * not have delay slots. The forbidden slot instruction ($PC+4) |
| 406 | * is only executed if the branch was not taken. Otherwise the |
| 407 | * forbidden slot is skipped entirely. This means that the |
| 408 | * only possible reason to be here because of a MIPS R6 compact |
| 409 | * branch instruction is that the forbidden slot has thrown one. |
| 410 | * In that case the branch was not taken, so the EPC can be safely |
| 411 | * set to EPC + 8. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 412 | */ |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 413 | int __compute_return_epc_for_insn(struct pt_regs *regs, |
| 414 | union mips_instruction insn) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 415 | { |
Markos Chandras | c8a3458 | 2014-11-26 10:10:18 +0000 | [diff] [blame] | 416 | unsigned int bit, fcr31, dspcontrol, reg; |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 417 | long epc = regs->cp0_epc; |
| 418 | int ret = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 419 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 420 | switch (insn.i_format.opcode) { |
| 421 | /* |
| 422 | * jr and jalr are in r_format format. |
| 423 | */ |
| 424 | case spec_op: |
| 425 | switch (insn.r_format.func) { |
| 426 | case jalr_op: |
| 427 | regs->regs[insn.r_format.rd] = epc + 8; |
| 428 | /* Fall through */ |
| 429 | case jr_op: |
Markos Chandras | 5f9f41c | 2014-11-25 15:54:14 +0000 | [diff] [blame] | 430 | if (NO_R6EMU && insn.r_format.func == jr_op) |
| 431 | goto sigill_r6; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 432 | regs->cp0_epc = regs->regs[insn.r_format.rs]; |
| 433 | break; |
| 434 | } |
| 435 | break; |
| 436 | |
| 437 | /* |
| 438 | * This group contains: |
| 439 | * bltz_op, bgez_op, bltzl_op, bgezl_op, |
| 440 | * bltzal_op, bgezal_op, bltzall_op, bgezall_op. |
| 441 | */ |
| 442 | case bcond_op: |
| 443 | switch (insn.i_format.rt) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 444 | case bltzl_op: |
Markos Chandras | 319824e | 2014-11-25 16:02:23 +0000 | [diff] [blame] | 445 | if (NO_R6EMU) |
| 446 | goto sigill_r6; |
| 447 | case bltz_op: |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 448 | if ((long)regs->regs[insn.i_format.rs] < 0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 449 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 450 | if (insn.i_format.rt == bltzl_op) |
| 451 | ret = BRANCH_LIKELY_TAKEN; |
| 452 | } else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 453 | epc += 8; |
| 454 | regs->cp0_epc = epc; |
| 455 | break; |
| 456 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 457 | case bgezl_op: |
Markos Chandras | 319824e | 2014-11-25 16:02:23 +0000 | [diff] [blame] | 458 | if (NO_R6EMU) |
| 459 | goto sigill_r6; |
| 460 | case bgez_op: |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 461 | if ((long)regs->regs[insn.i_format.rs] >= 0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 462 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 463 | if (insn.i_format.rt == bgezl_op) |
| 464 | ret = BRANCH_LIKELY_TAKEN; |
| 465 | } else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 466 | epc += 8; |
| 467 | regs->cp0_epc = epc; |
| 468 | break; |
| 469 | |
| 470 | case bltzal_op: |
| 471 | case bltzall_op: |
Markos Chandras | 319824e | 2014-11-25 16:02:23 +0000 | [diff] [blame] | 472 | if (NO_R6EMU && (insn.i_format.rs || |
| 473 | insn.i_format.rt == bltzall_op)) { |
| 474 | ret = -SIGILL; |
| 475 | break; |
| 476 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 477 | regs->regs[31] = epc + 8; |
Markos Chandras | 319824e | 2014-11-25 16:02:23 +0000 | [diff] [blame] | 478 | /* |
| 479 | * OK we are here either because we hit a NAL |
| 480 | * instruction or because we are emulating an |
| 481 | * old bltzal{,l} one. Lets figure out what the |
| 482 | * case really is. |
| 483 | */ |
| 484 | if (!insn.i_format.rs) { |
| 485 | /* |
| 486 | * NAL or BLTZAL with rs == 0 |
| 487 | * Doesn't matter if we are R6 or not. The |
| 488 | * result is the same |
| 489 | */ |
| 490 | regs->cp0_epc += 4 + |
| 491 | (insn.i_format.simmediate << 2); |
| 492 | break; |
| 493 | } |
| 494 | /* Now do the real thing for non-R6 BLTZAL{,L} */ |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 495 | if ((long)regs->regs[insn.i_format.rs] < 0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 496 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 497 | if (insn.i_format.rt == bltzall_op) |
| 498 | ret = BRANCH_LIKELY_TAKEN; |
| 499 | } else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 500 | epc += 8; |
| 501 | regs->cp0_epc = epc; |
| 502 | break; |
| 503 | |
| 504 | case bgezal_op: |
| 505 | case bgezall_op: |
Markos Chandras | 319824e | 2014-11-25 16:02:23 +0000 | [diff] [blame] | 506 | if (NO_R6EMU && (insn.i_format.rs || |
| 507 | insn.i_format.rt == bgezall_op)) { |
| 508 | ret = -SIGILL; |
| 509 | break; |
| 510 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 511 | regs->regs[31] = epc + 8; |
Markos Chandras | 319824e | 2014-11-25 16:02:23 +0000 | [diff] [blame] | 512 | /* |
| 513 | * OK we are here either because we hit a BAL |
| 514 | * instruction or because we are emulating an |
| 515 | * old bgezal{,l} one. Lets figure out what the |
| 516 | * case really is. |
| 517 | */ |
| 518 | if (!insn.i_format.rs) { |
| 519 | /* |
| 520 | * BAL or BGEZAL with rs == 0 |
| 521 | * Doesn't matter if we are R6 or not. The |
| 522 | * result is the same |
| 523 | */ |
| 524 | regs->cp0_epc += 4 + |
| 525 | (insn.i_format.simmediate << 2); |
| 526 | break; |
| 527 | } |
| 528 | /* Now do the real thing for non-R6 BGEZAL{,L} */ |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 529 | if ((long)regs->regs[insn.i_format.rs] >= 0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 530 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 531 | if (insn.i_format.rt == bgezall_op) |
| 532 | ret = BRANCH_LIKELY_TAKEN; |
| 533 | } else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 534 | epc += 8; |
| 535 | regs->cp0_epc = epc; |
| 536 | break; |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 537 | |
Ralf Baechle | e50c0a8 | 2005-05-31 11:49:19 +0000 | [diff] [blame] | 538 | case bposge32_op: |
| 539 | if (!cpu_has_dsp) |
Markos Chandras | 5f9f41c | 2014-11-25 15:54:14 +0000 | [diff] [blame] | 540 | goto sigill_dsp; |
Ralf Baechle | e50c0a8 | 2005-05-31 11:49:19 +0000 | [diff] [blame] | 541 | |
| 542 | dspcontrol = rddsp(0x01); |
| 543 | |
| 544 | if (dspcontrol >= 32) { |
| 545 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
| 546 | } else |
| 547 | epc += 8; |
| 548 | regs->cp0_epc = epc; |
| 549 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 550 | } |
| 551 | break; |
| 552 | |
| 553 | /* |
| 554 | * These are unconditional and in j_format. |
| 555 | */ |
| 556 | case jal_op: |
| 557 | regs->regs[31] = regs->cp0_epc + 8; |
| 558 | case j_op: |
| 559 | epc += 4; |
| 560 | epc >>= 28; |
| 561 | epc <<= 28; |
| 562 | epc |= (insn.j_format.target << 2); |
| 563 | regs->cp0_epc = epc; |
Leonid Yegoshin | fb6883e | 2013-03-25 13:08:40 -0500 | [diff] [blame] | 564 | if (insn.i_format.opcode == jalx_op) |
| 565 | set_isa16_mode(regs->cp0_epc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 566 | break; |
| 567 | |
| 568 | /* |
| 569 | * These are conditional and in i_format. |
| 570 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 571 | case beql_op: |
Markos Chandras | 319824e | 2014-11-25 16:02:23 +0000 | [diff] [blame] | 572 | if (NO_R6EMU) |
| 573 | goto sigill_r6; |
| 574 | case beq_op: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 575 | if (regs->regs[insn.i_format.rs] == |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 576 | regs->regs[insn.i_format.rt]) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 577 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
Ralf Baechle | 41ca86e | 2014-05-22 23:19:00 +0200 | [diff] [blame] | 578 | if (insn.i_format.opcode == beql_op) |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 579 | ret = BRANCH_LIKELY_TAKEN; |
| 580 | } else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 581 | epc += 8; |
| 582 | regs->cp0_epc = epc; |
| 583 | break; |
| 584 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 585 | case bnel_op: |
Markos Chandras | 319824e | 2014-11-25 16:02:23 +0000 | [diff] [blame] | 586 | if (NO_R6EMU) |
| 587 | goto sigill_r6; |
| 588 | case bne_op: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 589 | if (regs->regs[insn.i_format.rs] != |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 590 | regs->regs[insn.i_format.rt]) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 591 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
Ralf Baechle | 41ca86e | 2014-05-22 23:19:00 +0200 | [diff] [blame] | 592 | if (insn.i_format.opcode == bnel_op) |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 593 | ret = BRANCH_LIKELY_TAKEN; |
| 594 | } else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 595 | epc += 8; |
| 596 | regs->cp0_epc = epc; |
| 597 | break; |
| 598 | |
Markos Chandras | 319824e | 2014-11-25 16:02:23 +0000 | [diff] [blame] | 599 | case blezl_op: /* not really i_format */ |
| 600 | if (NO_R6EMU) |
| 601 | goto sigill_r6; |
| 602 | case blez_op: |
Markos Chandras | a8ff66f | 2014-11-26 12:57:54 +0000 | [diff] [blame] | 603 | /* |
| 604 | * Compact branches for R6 for the |
| 605 | * blez and blezl opcodes. |
| 606 | * BLEZ | rs = 0 | rt != 0 == BLEZALC |
| 607 | * BLEZ | rs = rt != 0 == BGEZALC |
| 608 | * BLEZ | rs != 0 | rt != 0 == BGEUC |
| 609 | * BLEZL | rs = 0 | rt != 0 == BLEZC |
| 610 | * BLEZL | rs = rt != 0 == BGEZC |
| 611 | * BLEZL | rs != 0 | rt != 0 == BGEC |
| 612 | * |
| 613 | * For real BLEZ{,L}, rt is always 0. |
| 614 | */ |
| 615 | |
| 616 | if (cpu_has_mips_r6 && insn.i_format.rt) { |
| 617 | if ((insn.i_format.opcode == blez_op) && |
| 618 | ((!insn.i_format.rs && insn.i_format.rt) || |
| 619 | (insn.i_format.rs == insn.i_format.rt))) |
| 620 | regs->regs[31] = epc + 4; |
| 621 | regs->cp0_epc += 8; |
| 622 | break; |
| 623 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 624 | /* rt field assumed to be zero */ |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 625 | if ((long)regs->regs[insn.i_format.rs] <= 0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 626 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
Ralf Baechle | 41ca86e | 2014-05-22 23:19:00 +0200 | [diff] [blame] | 627 | if (insn.i_format.opcode == blezl_op) |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 628 | ret = BRANCH_LIKELY_TAKEN; |
| 629 | } else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 630 | epc += 8; |
| 631 | regs->cp0_epc = epc; |
| 632 | break; |
| 633 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 634 | case bgtzl_op: |
Markos Chandras | 319824e | 2014-11-25 16:02:23 +0000 | [diff] [blame] | 635 | if (NO_R6EMU) |
| 636 | goto sigill_r6; |
| 637 | case bgtz_op: |
Markos Chandras | f1b4406 | 2014-11-26 13:05:09 +0000 | [diff] [blame] | 638 | /* |
| 639 | * Compact branches for R6 for the |
| 640 | * bgtz and bgtzl opcodes. |
| 641 | * BGTZ | rs = 0 | rt != 0 == BGTZALC |
| 642 | * BGTZ | rs = rt != 0 == BLTZALC |
| 643 | * BGTZ | rs != 0 | rt != 0 == BLTUC |
| 644 | * BGTZL | rs = 0 | rt != 0 == BGTZC |
| 645 | * BGTZL | rs = rt != 0 == BLTZC |
| 646 | * BGTZL | rs != 0 | rt != 0 == BLTC |
| 647 | * |
| 648 | * *ZALC varint for BGTZ &&& rt != 0 |
| 649 | * For real GTZ{,L}, rt is always 0. |
| 650 | */ |
| 651 | if (cpu_has_mips_r6 && insn.i_format.rt) { |
| 652 | if ((insn.i_format.opcode == blez_op) && |
| 653 | ((!insn.i_format.rs && insn.i_format.rt) || |
| 654 | (insn.i_format.rs == insn.i_format.rt))) |
| 655 | regs->regs[31] = epc + 4; |
| 656 | regs->cp0_epc += 8; |
| 657 | break; |
| 658 | } |
| 659 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 660 | /* rt field assumed to be zero */ |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 661 | if ((long)regs->regs[insn.i_format.rs] > 0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 662 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
Ralf Baechle | 41ca86e | 2014-05-22 23:19:00 +0200 | [diff] [blame] | 663 | if (insn.i_format.opcode == bgtzl_op) |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 664 | ret = BRANCH_LIKELY_TAKEN; |
| 665 | } else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 666 | epc += 8; |
| 667 | regs->cp0_epc = epc; |
| 668 | break; |
| 669 | |
| 670 | /* |
| 671 | * And now the FPA/cp1 branch instructions. |
| 672 | */ |
| 673 | case cop1_op: |
Markos Chandras | c8a3458 | 2014-11-26 10:10:18 +0000 | [diff] [blame] | 674 | if (cpu_has_mips_r6 && |
| 675 | ((insn.i_format.rs == bc1eqz_op) || |
| 676 | (insn.i_format.rs == bc1nez_op))) { |
| 677 | if (!used_math()) { /* First time FPU user */ |
| 678 | ret = init_fpu(); |
| 679 | if (ret && NO_R6EMU) { |
| 680 | ret = -ret; |
| 681 | break; |
| 682 | } |
| 683 | ret = 0; |
| 684 | set_used_math(); |
| 685 | } |
| 686 | lose_fpu(1); /* Save FPU state for the emulator. */ |
| 687 | reg = insn.i_format.rt; |
| 688 | bit = 0; |
| 689 | switch (insn.i_format.rs) { |
| 690 | case bc1eqz_op: |
| 691 | /* Test bit 0 */ |
| 692 | if (get_fpr32(¤t->thread.fpu.fpr[reg], 0) |
| 693 | & 0x1) |
| 694 | bit = 1; |
| 695 | break; |
| 696 | case bc1nez_op: |
| 697 | /* Test bit 0 */ |
| 698 | if (!(get_fpr32(¤t->thread.fpu.fpr[reg], 0) |
| 699 | & 0x1)) |
| 700 | bit = 1; |
| 701 | break; |
| 702 | } |
| 703 | own_fpu(1); |
| 704 | if (bit) |
| 705 | epc = epc + 4 + |
| 706 | (insn.i_format.simmediate << 2); |
| 707 | else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 708 | epc += 8; |
| 709 | regs->cp0_epc = epc; |
Markos Chandras | c8a3458 | 2014-11-26 10:10:18 +0000 | [diff] [blame] | 710 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 711 | break; |
Markos Chandras | c8a3458 | 2014-11-26 10:10:18 +0000 | [diff] [blame] | 712 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 713 | |
Markos Chandras | c8a3458 | 2014-11-26 10:10:18 +0000 | [diff] [blame] | 714 | preempt_disable(); |
| 715 | if (is_fpu_owner()) |
| 716 | fcr31 = read_32bit_cp1_register(CP1_STATUS); |
| 717 | else |
| 718 | fcr31 = current->thread.fpu.fcr31; |
| 719 | preempt_enable(); |
| 720 | |
| 721 | bit = (insn.i_format.rt >> 2); |
| 722 | bit += (bit != 0); |
| 723 | bit += 23; |
| 724 | switch (insn.i_format.rt & 3) { |
| 725 | case 0: /* bc1f */ |
| 726 | case 2: /* bc1fl */ |
| 727 | if (~fcr31 & (1 << bit)) { |
| 728 | epc = epc + 4 + |
| 729 | (insn.i_format.simmediate << 2); |
| 730 | if (insn.i_format.rt == 2) |
| 731 | ret = BRANCH_LIKELY_TAKEN; |
| 732 | } else |
| 733 | epc += 8; |
| 734 | regs->cp0_epc = epc; |
| 735 | break; |
| 736 | |
| 737 | case 1: /* bc1t */ |
| 738 | case 3: /* bc1tl */ |
| 739 | if (fcr31 & (1 << bit)) { |
| 740 | epc = epc + 4 + |
| 741 | (insn.i_format.simmediate << 2); |
| 742 | if (insn.i_format.rt == 3) |
| 743 | ret = BRANCH_LIKELY_TAKEN; |
| 744 | } else |
| 745 | epc += 8; |
| 746 | regs->cp0_epc = epc; |
| 747 | break; |
| 748 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 749 | break; |
| 750 | } |
David Daney | 126336f | 2008-12-11 15:33:34 -0800 | [diff] [blame] | 751 | #ifdef CONFIG_CPU_CAVIUM_OCTEON |
| 752 | case lwc2_op: /* This is bbit0 on Octeon */ |
| 753 | if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) |
| 754 | == 0) |
| 755 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
| 756 | else |
| 757 | epc += 8; |
| 758 | regs->cp0_epc = epc; |
| 759 | break; |
| 760 | case ldc2_op: /* This is bbit032 on Octeon */ |
| 761 | if ((regs->regs[insn.i_format.rs] & |
| 762 | (1ull<<(insn.i_format.rt+32))) == 0) |
| 763 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
| 764 | else |
| 765 | epc += 8; |
| 766 | regs->cp0_epc = epc; |
| 767 | break; |
| 768 | case swc2_op: /* This is bbit1 on Octeon */ |
| 769 | if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) |
| 770 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
| 771 | else |
| 772 | epc += 8; |
| 773 | regs->cp0_epc = epc; |
| 774 | break; |
| 775 | case sdc2_op: /* This is bbit132 on Octeon */ |
| 776 | if (regs->regs[insn.i_format.rs] & |
| 777 | (1ull<<(insn.i_format.rt+32))) |
| 778 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
| 779 | else |
| 780 | epc += 8; |
| 781 | regs->cp0_epc = epc; |
| 782 | break; |
Markos Chandras | 8467ca0 | 2014-11-26 13:56:51 +0000 | [diff] [blame] | 783 | #else |
| 784 | case bc6_op: |
| 785 | /* Only valid for MIPS R6 */ |
| 786 | if (!cpu_has_mips_r6) { |
| 787 | ret = -SIGILL; |
| 788 | break; |
| 789 | } |
| 790 | regs->cp0_epc += 8; |
| 791 | break; |
David Daney | 126336f | 2008-12-11 15:33:34 -0800 | [diff] [blame] | 792 | #endif |
Markos Chandras | c893ce3 | 2014-11-26 14:08:52 +0000 | [diff] [blame^] | 793 | case cbcond0_op: |
| 794 | /* Only valid for MIPS R6 */ |
| 795 | if (!cpu_has_mips_r6) { |
| 796 | ret = -SIGILL; |
| 797 | break; |
| 798 | } |
| 799 | /* Compact branches: bovc, beqc, beqzalc */ |
| 800 | if (insn.i_format.rt && !insn.i_format.rs) |
| 801 | regs->regs[31] = epc + 4; |
| 802 | regs->cp0_epc += 8; |
| 803 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 804 | } |
| 805 | |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 806 | return ret; |
| 807 | |
Markos Chandras | 5f9f41c | 2014-11-25 15:54:14 +0000 | [diff] [blame] | 808 | sigill_dsp: |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 809 | printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm); |
| 810 | force_sig(SIGBUS, current); |
| 811 | return -EFAULT; |
Markos Chandras | 5f9f41c | 2014-11-25 15:54:14 +0000 | [diff] [blame] | 812 | sigill_r6: |
| 813 | pr_info("%s: R2 branch but r2-to-r6 emulator is not preset - sending SIGILL.\n", |
| 814 | current->comm); |
| 815 | force_sig(SIGILL, current); |
| 816 | return -EFAULT; |
Maneesh Soni | d8d4e3a | 2011-11-08 17:07:11 +0530 | [diff] [blame] | 817 | } |
| 818 | EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn); |
| 819 | |
| 820 | int __compute_return_epc(struct pt_regs *regs) |
| 821 | { |
| 822 | unsigned int __user *addr; |
| 823 | long epc; |
| 824 | union mips_instruction insn; |
| 825 | |
| 826 | epc = regs->cp0_epc; |
| 827 | if (epc & 3) |
| 828 | goto unaligned; |
| 829 | |
| 830 | /* |
| 831 | * Read the instruction |
| 832 | */ |
| 833 | addr = (unsigned int __user *) epc; |
| 834 | if (__get_user(insn.word, addr)) { |
| 835 | force_sig(SIGSEGV, current); |
| 836 | return -EFAULT; |
| 837 | } |
| 838 | |
| 839 | return __compute_return_epc_for_insn(regs, insn); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 840 | |
| 841 | unaligned: |
| 842 | printk("%s: unaligned epc - sending SIGBUS.\n", current->comm); |
| 843 | force_sig(SIGBUS, current); |
| 844 | return -EFAULT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 845 | } |