blob: e585163f1ad55202ecebd56d882992f8765e72fd [file] [log] [blame]
Grant Likelyc103de22011-06-04 18:38:28 -06001/*
2 * Moorestown platform Langwell chip GPIO driver
3 *
Andy Shevchenko611a4852013-05-22 13:20:14 +03004 * Copyright (c) 2008, 2009, 2013, Intel Corporation.
Alek Du8bf02612009-09-22 16:46:36 -07005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20/* Supports:
21 * Moorestown platform Langwell chip.
Alek Du8081c842010-05-26 14:42:25 -070022 * Medfield platform Penwell chip.
David Cohenf89a7682013-10-04 13:01:42 -070023 * Clovertrail platform Cloverview chip.
24 * Merrifield platform Tangier chip.
Alek Du8bf02612009-09-22 16:46:36 -070025 */
26
27#include <linux/module.h>
28#include <linux/pci.h>
Alan Cox72b43792010-10-27 15:33:23 -070029#include <linux/platform_device.h>
Alek Du8bf02612009-09-22 16:46:36 -070030#include <linux/kernel.h>
31#include <linux/delay.h>
32#include <linux/stddef.h>
33#include <linux/interrupt.h>
34#include <linux/init.h>
35#include <linux/irq.h>
36#include <linux/io.h>
37#include <linux/gpio.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090038#include <linux/slab.h>
Kristen Carlson Accardi78128032011-05-10 14:23:45 +010039#include <linux/pm_runtime.h>
Mika Westerberg465f2bd2012-05-02 11:15:50 +030040#include <linux/irqdomain.h>
Alek Du8bf02612009-09-22 16:46:36 -070041
David Cohenf89a7682013-10-04 13:01:42 -070042#define INTEL_MID_IRQ_TYPE_EDGE (1 << 0)
43#define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1)
David Cohend56d6b32013-10-04 13:01:40 -070044
Alek Du8081c842010-05-26 14:42:25 -070045/*
46 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
47 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
48 * registers to control them, so we only define the order here instead of a
49 * structure, to get a bit offset for a pin (use GPDR as an example):
50 *
51 * nreg = ngpio / 32;
52 * reg = offset / 32;
53 * bit = offset % 32;
54 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
55 *
56 * so the bit of reg_addr is to control pin offset's GPDR feature
57*/
58
59enum GPIO_REG {
60 GPLR = 0, /* pin level read-only */
61 GPDR, /* pin direction */
62 GPSR, /* pin set */
63 GPCR, /* pin clear */
64 GRER, /* rising edge detect */
65 GFER, /* falling edge detect */
66 GEDR, /* edge detect result */
Adrian Hunter8c0f7b12011-10-03 14:36:07 +030067 GAFR, /* alt function */
Alek Du8bf02612009-09-22 16:46:36 -070068};
69
David Cohenf89a7682013-10-04 13:01:42 -070070/* intel_mid gpio driver data */
71struct intel_mid_gpio_ddata {
David Cohend56d6b32013-10-04 13:01:40 -070072 u16 ngpio; /* number of gpio pins */
73 u32 gplr_offset; /* offset of first GPLR register from base */
74 u32 flis_base; /* base address of FLIS registers */
75 u32 flis_len; /* length of FLIS registers */
76 u32 (*get_flis_offset)(int gpio);
77 u32 chip_irq_type; /* chip interrupt type */
78};
79
David Cohenf89a7682013-10-04 13:01:42 -070080struct intel_mid_gpio {
Alek Du8bf02612009-09-22 16:46:36 -070081 struct gpio_chip chip;
Andy Shevchenko64c8cbc2013-05-22 13:20:11 +030082 void __iomem *reg_base;
Alek Du8bf02612009-09-22 16:46:36 -070083 spinlock_t lock;
Kristen Carlson Accardi78128032011-05-10 14:23:45 +010084 struct pci_dev *pdev;
Mika Westerberg465f2bd2012-05-02 11:15:50 +030085 struct irq_domain *domain;
Alek Du8bf02612009-09-22 16:46:36 -070086};
87
David Cohenf89a7682013-10-04 13:01:42 -070088#define to_intel_gpio_priv(chip) container_of(chip, struct intel_mid_gpio, chip)
David Cohen46ebfbc2012-12-20 14:45:51 -080089
Alek Du8081c842010-05-26 14:42:25 -070090static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
Andy Shevchenko611a4852013-05-22 13:20:14 +030091 enum GPIO_REG reg_type)
Alek Du8bf02612009-09-22 16:46:36 -070092{
David Cohenf89a7682013-10-04 13:01:42 -070093 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
Alek Du8081c842010-05-26 14:42:25 -070094 unsigned nreg = chip->ngpio / 32;
Alek Du8bf02612009-09-22 16:46:36 -070095 u8 reg = offset / 32;
Alek Du8bf02612009-09-22 16:46:36 -070096
David Cohenf89a7682013-10-04 13:01:42 -070097 return priv->reg_base + reg_type * nreg * 4 + reg * 4;
Alek Du8081c842010-05-26 14:42:25 -070098}
99
Adrian Hunter8c0f7b12011-10-03 14:36:07 +0300100static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
101 enum GPIO_REG reg_type)
102{
David Cohenf89a7682013-10-04 13:01:42 -0700103 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
Adrian Hunter8c0f7b12011-10-03 14:36:07 +0300104 unsigned nreg = chip->ngpio / 32;
105 u8 reg = offset / 16;
Adrian Hunter8c0f7b12011-10-03 14:36:07 +0300106
David Cohenf89a7682013-10-04 13:01:42 -0700107 return priv->reg_base + reg_type * nreg * 4 + reg * 4;
Adrian Hunter8c0f7b12011-10-03 14:36:07 +0300108}
109
David Cohenf89a7682013-10-04 13:01:42 -0700110static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
Adrian Hunter8c0f7b12011-10-03 14:36:07 +0300111{
112 void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
113 u32 value = readl(gafr);
114 int shift = (offset % 16) << 1, af = (value >> shift) & 3;
115
116 if (af) {
117 value &= ~(3 << shift);
118 writel(value, gafr);
119 }
120 return 0;
121}
122
David Cohenf89a7682013-10-04 13:01:42 -0700123static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
Alek Du8081c842010-05-26 14:42:25 -0700124{
125 void __iomem *gplr = gpio_reg(chip, offset, GPLR);
126
Alek Du8bf02612009-09-22 16:46:36 -0700127 return readl(gplr) & BIT(offset % 32);
128}
129
David Cohenf89a7682013-10-04 13:01:42 -0700130static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
Alek Du8bf02612009-09-22 16:46:36 -0700131{
Alek Du8bf02612009-09-22 16:46:36 -0700132 void __iomem *gpsr, *gpcr;
133
134 if (value) {
Alek Du8081c842010-05-26 14:42:25 -0700135 gpsr = gpio_reg(chip, offset, GPSR);
Alek Du8bf02612009-09-22 16:46:36 -0700136 writel(BIT(offset % 32), gpsr);
137 } else {
Alek Du8081c842010-05-26 14:42:25 -0700138 gpcr = gpio_reg(chip, offset, GPCR);
Alek Du8bf02612009-09-22 16:46:36 -0700139 writel(BIT(offset % 32), gpcr);
140 }
141}
142
David Cohenf89a7682013-10-04 13:01:42 -0700143static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
Alek Du8bf02612009-09-22 16:46:36 -0700144{
David Cohenf89a7682013-10-04 13:01:42 -0700145 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
Alek Du8081c842010-05-26 14:42:25 -0700146 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
Alek Du8bf02612009-09-22 16:46:36 -0700147 u32 value;
148 unsigned long flags;
Alek Du8bf02612009-09-22 16:46:36 -0700149
David Cohenf89a7682013-10-04 13:01:42 -0700150 if (priv->pdev)
151 pm_runtime_get(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100152
David Cohenf89a7682013-10-04 13:01:42 -0700153 spin_lock_irqsave(&priv->lock, flags);
Alek Du8bf02612009-09-22 16:46:36 -0700154 value = readl(gpdr);
155 value &= ~BIT(offset % 32);
156 writel(value, gpdr);
David Cohenf89a7682013-10-04 13:01:42 -0700157 spin_unlock_irqrestore(&priv->lock, flags);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100158
David Cohenf89a7682013-10-04 13:01:42 -0700159 if (priv->pdev)
160 pm_runtime_put(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100161
Alek Du8bf02612009-09-22 16:46:36 -0700162 return 0;
163}
164
David Cohenf89a7682013-10-04 13:01:42 -0700165static int intel_gpio_direction_output(struct gpio_chip *chip,
Alek Du8bf02612009-09-22 16:46:36 -0700166 unsigned offset, int value)
167{
David Cohenf89a7682013-10-04 13:01:42 -0700168 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
Alek Du8081c842010-05-26 14:42:25 -0700169 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
Alek Du8bf02612009-09-22 16:46:36 -0700170 unsigned long flags;
Alek Du8bf02612009-09-22 16:46:36 -0700171
David Cohenf89a7682013-10-04 13:01:42 -0700172 intel_gpio_set(chip, offset, value);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100173
David Cohenf89a7682013-10-04 13:01:42 -0700174 if (priv->pdev)
175 pm_runtime_get(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100176
David Cohenf89a7682013-10-04 13:01:42 -0700177 spin_lock_irqsave(&priv->lock, flags);
Alek Du8bf02612009-09-22 16:46:36 -0700178 value = readl(gpdr);
Justin P. Mattock6eab04a2011-04-08 19:49:08 -0700179 value |= BIT(offset % 32);
Alek Du8bf02612009-09-22 16:46:36 -0700180 writel(value, gpdr);
David Cohenf89a7682013-10-04 13:01:42 -0700181 spin_unlock_irqrestore(&priv->lock, flags);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100182
David Cohenf89a7682013-10-04 13:01:42 -0700183 if (priv->pdev)
184 pm_runtime_put(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100185
Alek Du8bf02612009-09-22 16:46:36 -0700186 return 0;
187}
188
David Cohenf89a7682013-10-04 13:01:42 -0700189static int intel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
Alek Du8bf02612009-09-22 16:46:36 -0700190{
David Cohenf89a7682013-10-04 13:01:42 -0700191 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
192 return irq_create_mapping(priv->domain, offset);
Alek Du8bf02612009-09-22 16:46:36 -0700193}
194
David Cohenf89a7682013-10-04 13:01:42 -0700195static int intel_mid_irq_type(struct irq_data *d, unsigned type)
Alek Du8bf02612009-09-22 16:46:36 -0700196{
David Cohenf89a7682013-10-04 13:01:42 -0700197 struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
Mika Westerberg465f2bd2012-05-02 11:15:50 +0300198 u32 gpio = irqd_to_hwirq(d);
Alek Du8bf02612009-09-22 16:46:36 -0700199 unsigned long flags;
200 u32 value;
David Cohenf89a7682013-10-04 13:01:42 -0700201 void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
202 void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
Alek Du8bf02612009-09-22 16:46:36 -0700203
David Cohenf89a7682013-10-04 13:01:42 -0700204 if (gpio >= priv->chip.ngpio)
Alek Du8bf02612009-09-22 16:46:36 -0700205 return -EINVAL;
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100206
David Cohenf89a7682013-10-04 13:01:42 -0700207 if (priv->pdev)
208 pm_runtime_get(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100209
David Cohenf89a7682013-10-04 13:01:42 -0700210 spin_lock_irqsave(&priv->lock, flags);
Alek Du8bf02612009-09-22 16:46:36 -0700211 if (type & IRQ_TYPE_EDGE_RISING)
212 value = readl(grer) | BIT(gpio % 32);
213 else
214 value = readl(grer) & (~BIT(gpio % 32));
215 writel(value, grer);
216
217 if (type & IRQ_TYPE_EDGE_FALLING)
218 value = readl(gfer) | BIT(gpio % 32);
219 else
220 value = readl(gfer) & (~BIT(gpio % 32));
221 writel(value, gfer);
David Cohenf89a7682013-10-04 13:01:42 -0700222 spin_unlock_irqrestore(&priv->lock, flags);
Alek Du8bf02612009-09-22 16:46:36 -0700223
David Cohenf89a7682013-10-04 13:01:42 -0700224 if (priv->pdev)
225 pm_runtime_put(&priv->pdev->dev);
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100226
Alek Du8bf02612009-09-22 16:46:36 -0700227 return 0;
Andrew Mortonfd0574c2010-10-27 15:33:22 -0700228}
Alek Du8bf02612009-09-22 16:46:36 -0700229
David Cohenf89a7682013-10-04 13:01:42 -0700230static void intel_mid_irq_unmask(struct irq_data *d)
Alek Du8bf02612009-09-22 16:46:36 -0700231{
Andrew Mortonfd0574c2010-10-27 15:33:22 -0700232}
Alek Du8bf02612009-09-22 16:46:36 -0700233
David Cohenf89a7682013-10-04 13:01:42 -0700234static void intel_mid_irq_mask(struct irq_data *d)
Alek Du8bf02612009-09-22 16:46:36 -0700235{
Andrew Mortonfd0574c2010-10-27 15:33:22 -0700236}
Alek Du8bf02612009-09-22 16:46:36 -0700237
Linus Walleijaa6baa72013-11-20 15:24:32 +0100238static unsigned int intel_mid_irq_startup(struct irq_data *d)
239{
240 struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
241
242 if (gpio_lock_as_irq(&priv->chip, irqd_to_hwirq(d)))
243 dev_err(priv->chip.dev,
244 "unable to lock HW IRQ %lu for IRQ\n",
245 irqd_to_hwirq(d));
246 intel_mid_irq_unmask(d);
247 return 0;
248}
249
250static void intel_mid_irq_shutdown(struct irq_data *d)
251{
252 struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
253
254 intel_mid_irq_mask(d);
255 gpio_unlock_as_irq(&priv->chip, irqd_to_hwirq(d));
256}
257
David Cohenf89a7682013-10-04 13:01:42 -0700258static struct irq_chip intel_mid_irqchip = {
259 .name = "INTEL_MID-GPIO",
260 .irq_mask = intel_mid_irq_mask,
261 .irq_unmask = intel_mid_irq_unmask,
262 .irq_set_type = intel_mid_irq_type,
Linus Walleijaa6baa72013-11-20 15:24:32 +0100263 .irq_startup = intel_mid_irq_startup,
264 .irq_shutdown = intel_mid_irq_shutdown,
Alek Du8bf02612009-09-22 16:46:36 -0700265};
266
David Cohenf89a7682013-10-04 13:01:42 -0700267static const struct intel_mid_gpio_ddata gpio_lincroft = {
David Cohend56d6b32013-10-04 13:01:40 -0700268 .ngpio = 64,
269};
270
David Cohenf89a7682013-10-04 13:01:42 -0700271static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
David Cohend56d6b32013-10-04 13:01:40 -0700272 .ngpio = 96,
David Cohenf89a7682013-10-04 13:01:42 -0700273 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
David Cohend56d6b32013-10-04 13:01:40 -0700274};
275
David Cohenf89a7682013-10-04 13:01:42 -0700276static const struct intel_mid_gpio_ddata gpio_penwell_core = {
David Cohend56d6b32013-10-04 13:01:40 -0700277 .ngpio = 96,
David Cohenf89a7682013-10-04 13:01:42 -0700278 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
David Cohend56d6b32013-10-04 13:01:40 -0700279};
280
David Cohenf89a7682013-10-04 13:01:42 -0700281static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
David Cohend56d6b32013-10-04 13:01:40 -0700282 .ngpio = 96,
David Cohenf89a7682013-10-04 13:01:42 -0700283 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL,
David Cohend56d6b32013-10-04 13:01:40 -0700284};
285
David Cohenf89a7682013-10-04 13:01:42 -0700286static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
David Cohend56d6b32013-10-04 13:01:40 -0700287 .ngpio = 96,
David Cohenf89a7682013-10-04 13:01:42 -0700288 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
David Cohend56d6b32013-10-04 13:01:40 -0700289};
290
David Cohenf89a7682013-10-04 13:01:42 -0700291static const struct intel_mid_gpio_ddata gpio_tangier = {
David Cohend56d6b32013-10-04 13:01:40 -0700292 .ngpio = 192,
293 .gplr_offset = 4,
294 .flis_base = 0xff0c0000,
295 .flis_len = 0x8000,
296 .get_flis_offset = NULL,
David Cohenf89a7682013-10-04 13:01:42 -0700297 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
David Cohend56d6b32013-10-04 13:01:40 -0700298};
299
Jingoo Han14f4a882013-12-03 08:08:45 +0900300static const struct pci_device_id intel_gpio_ids[] = {
David Cohend56d6b32013-10-04 13:01:40 -0700301 {
302 /* Lincroft */
303 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
304 .driver_data = (kernel_ulong_t)&gpio_lincroft,
305 },
306 {
307 /* Penwell AON */
308 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
309 .driver_data = (kernel_ulong_t)&gpio_penwell_aon,
310 },
311 {
312 /* Penwell Core */
313 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
314 .driver_data = (kernel_ulong_t)&gpio_penwell_core,
315 },
316 {
317 /* Cloverview Aon */
318 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
319 .driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
320 },
321 {
322 /* Cloverview Core */
323 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
324 .driver_data = (kernel_ulong_t)&gpio_cloverview_core,
325 },
326 {
327 /* Tangier */
328 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1199),
329 .driver_data = (kernel_ulong_t)&gpio_tangier,
330 },
331 { 0 }
Alek Du8bf02612009-09-22 16:46:36 -0700332};
David Cohenf89a7682013-10-04 13:01:42 -0700333MODULE_DEVICE_TABLE(pci, intel_gpio_ids);
Alek Du8bf02612009-09-22 16:46:36 -0700334
David Cohenf89a7682013-10-04 13:01:42 -0700335static void intel_mid_irq_handler(unsigned irq, struct irq_desc *desc)
Alek Du8bf02612009-09-22 16:46:36 -0700336{
Thomas Gleixner20e2aa92011-03-17 19:32:49 +0000337 struct irq_data *data = irq_desc_get_irq_data(desc);
David Cohenf89a7682013-10-04 13:01:42 -0700338 struct intel_mid_gpio *priv = irq_data_get_irq_handler_data(data);
Thomas Gleixner20e2aa92011-03-17 19:32:49 +0000339 struct irq_chip *chip = irq_data_get_irq_chip(data);
Thomas Gleixner84bead62011-03-17 19:32:58 +0000340 u32 base, gpio, mask;
Thomas Gleixner732063b2011-03-17 19:32:55 +0000341 unsigned long pending;
Alek Du8bf02612009-09-22 16:46:36 -0700342 void __iomem *gedr;
Alek Du8bf02612009-09-22 16:46:36 -0700343
344 /* check GPIO controller to check which pin triggered the interrupt */
David Cohenf89a7682013-10-04 13:01:42 -0700345 for (base = 0; base < priv->chip.ngpio; base += 32) {
346 gedr = gpio_reg(&priv->chip, base, GEDR);
Mika Westerbergc8f925b2012-05-10 13:01:22 +0300347 while ((pending = readl(gedr))) {
Mathias Nyman2345b202011-07-08 10:02:18 +0100348 gpio = __ffs(pending);
Thomas Gleixner84bead62011-03-17 19:32:58 +0000349 mask = BIT(gpio);
Thomas Gleixner84bead62011-03-17 19:32:58 +0000350 /* Clear before handling so we can't lose an edge */
351 writel(mask, gedr);
David Cohenf89a7682013-10-04 13:01:42 -0700352 generic_handle_irq(irq_find_mapping(priv->domain,
Mika Westerberg465f2bd2012-05-02 11:15:50 +0300353 base + gpio));
Thomas Gleixner732063b2011-03-17 19:32:55 +0000354 }
Alek Du8bf02612009-09-22 16:46:36 -0700355 }
Feng Tang0766d202011-01-25 15:07:15 -0800356
Thomas Gleixner20e2aa92011-03-17 19:32:49 +0000357 chip->irq_eoi(data);
Alek Du8bf02612009-09-22 16:46:36 -0700358}
359
David Cohenf89a7682013-10-04 13:01:42 -0700360static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
Mika Westerbergf5f93112012-04-05 12:15:17 +0300361{
362 void __iomem *reg;
363 unsigned base;
364
David Cohenf89a7682013-10-04 13:01:42 -0700365 for (base = 0; base < priv->chip.ngpio; base += 32) {
Mika Westerbergf5f93112012-04-05 12:15:17 +0300366 /* Clear the rising-edge detect register */
David Cohenf89a7682013-10-04 13:01:42 -0700367 reg = gpio_reg(&priv->chip, base, GRER);
Mika Westerbergf5f93112012-04-05 12:15:17 +0300368 writel(0, reg);
369 /* Clear the falling-edge detect register */
David Cohenf89a7682013-10-04 13:01:42 -0700370 reg = gpio_reg(&priv->chip, base, GFER);
Mika Westerbergf5f93112012-04-05 12:15:17 +0300371 writel(0, reg);
372 /* Clear the edge detect status register */
David Cohenf89a7682013-10-04 13:01:42 -0700373 reg = gpio_reg(&priv->chip, base, GEDR);
Mika Westerbergf5f93112012-04-05 12:15:17 +0300374 writel(~0, reg);
375 }
376}
377
Linus Walleijba519dd2013-10-11 19:27:02 +0200378static int intel_gpio_irq_map(struct irq_domain *d, unsigned int irq,
379 irq_hw_number_t hwirq)
Mika Westerberg465f2bd2012-05-02 11:15:50 +0300380{
David Cohenf89a7682013-10-04 13:01:42 -0700381 struct intel_mid_gpio *priv = d->host_data;
Mika Westerberg465f2bd2012-05-02 11:15:50 +0300382
Linus Walleije5428a62013-11-26 14:28:32 +0100383 irq_set_chip_and_handler(irq, &intel_mid_irqchip, handle_simple_irq);
Linus Walleijba519dd2013-10-11 19:27:02 +0200384 irq_set_chip_data(irq, priv);
385 irq_set_irq_type(irq, IRQ_TYPE_NONE);
Mika Westerberg465f2bd2012-05-02 11:15:50 +0300386
387 return 0;
388}
389
David Cohenf89a7682013-10-04 13:01:42 -0700390static const struct irq_domain_ops intel_gpio_irq_ops = {
391 .map = intel_gpio_irq_map,
Mika Westerberg465f2bd2012-05-02 11:15:50 +0300392 .xlate = irq_domain_xlate_twocell,
393};
394
David Cohenf89a7682013-10-04 13:01:42 -0700395static int intel_gpio_runtime_idle(struct device *dev)
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100396{
xinhui.pan84a34572014-01-31 13:08:01 -0800397 int err = pm_schedule_suspend(dev, 500);
398 return err ?: -EBUSY;
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100399}
400
David Cohenf89a7682013-10-04 13:01:42 -0700401static const struct dev_pm_ops intel_gpio_pm_ops = {
402 SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100403};
404
David Cohenf89a7682013-10-04 13:01:42 -0700405static int intel_gpio_probe(struct pci_dev *pdev,
Andy Shevchenko64c8cbc2013-05-22 13:20:11 +0300406 const struct pci_device_id *id)
Alek Du8bf02612009-09-22 16:46:36 -0700407{
Andy Shevchenko64c8cbc2013-05-22 13:20:11 +0300408 void __iomem *base;
David Cohenf89a7682013-10-04 13:01:42 -0700409 struct intel_mid_gpio *priv;
Alek Du8bf02612009-09-22 16:46:36 -0700410 u32 gpio_base;
David Cohen2519f9a2013-05-06 16:11:03 -0700411 u32 irq_base;
Julia Lawalld6a2b7b2012-08-05 11:52:34 +0200412 int retval;
David Cohenf89a7682013-10-04 13:01:42 -0700413 struct intel_mid_gpio_ddata *ddata =
414 (struct intel_mid_gpio_ddata *)id->driver_data;
Alek Du8bf02612009-09-22 16:46:36 -0700415
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300416 retval = pcim_enable_device(pdev);
Alek Du8bf02612009-09-22 16:46:36 -0700417 if (retval)
Mika Westerberg8302c742012-04-05 12:15:15 +0300418 return retval;
Alek Du8bf02612009-09-22 16:46:36 -0700419
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300420 retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
Alek Du8bf02612009-09-22 16:46:36 -0700421 if (retval) {
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300422 dev_err(&pdev->dev, "I/O memory mapping error\n");
423 return retval;
Alek Du8bf02612009-09-22 16:46:36 -0700424 }
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300425
426 base = pcim_iomap_table(pdev)[1];
Andy Shevchenko64c8cbc2013-05-22 13:20:11 +0300427
428 irq_base = readl(base);
429 gpio_base = readl(sizeof(u32) + base);
430
Alek Du8bf02612009-09-22 16:46:36 -0700431 /* release the IO mapping, since we already get the info from bar1 */
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300432 pcim_iounmap_regions(pdev, 1 << 1);
Alek Du8bf02612009-09-22 16:46:36 -0700433
David Cohenf89a7682013-10-04 13:01:42 -0700434 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
435 if (!priv) {
Andy Shevchenko8aca1192013-05-22 13:20:13 +0300436 dev_err(&pdev->dev, "can't allocate chip data\n");
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300437 return -ENOMEM;
Alek Du8bf02612009-09-22 16:46:36 -0700438 }
Mika Westerbergb3e35af2012-04-05 12:15:16 +0300439
David Cohenf89a7682013-10-04 13:01:42 -0700440 priv->reg_base = pcim_iomap_table(pdev)[0];
441 priv->chip.label = dev_name(&pdev->dev);
Linus Walleijaa6baa72013-11-20 15:24:32 +0100442 priv->chip.dev = &pdev->dev;
David Cohenf89a7682013-10-04 13:01:42 -0700443 priv->chip.request = intel_gpio_request;
444 priv->chip.direction_input = intel_gpio_direction_input;
445 priv->chip.direction_output = intel_gpio_direction_output;
446 priv->chip.get = intel_gpio_get;
447 priv->chip.set = intel_gpio_set;
448 priv->chip.to_irq = intel_gpio_to_irq;
449 priv->chip.base = gpio_base;
450 priv->chip.ngpio = ddata->ngpio;
Linus Walleij9fb1f392013-12-04 14:42:46 +0100451 priv->chip.can_sleep = false;
David Cohenf89a7682013-10-04 13:01:42 -0700452 priv->pdev = pdev;
David Cohen2519f9a2013-05-06 16:11:03 -0700453
David Cohenf89a7682013-10-04 13:01:42 -0700454 spin_lock_init(&priv->lock);
Andy Shevchenkoaeb168f2013-05-22 13:20:10 +0300455
David Cohenf89a7682013-10-04 13:01:42 -0700456 priv->domain = irq_domain_add_simple(pdev->dev.of_node, ddata->ngpio,
457 irq_base, &intel_gpio_irq_ops, priv);
458 if (!priv->domain)
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300459 return -ENOMEM;
David Cohen2519f9a2013-05-06 16:11:03 -0700460
David Cohenf89a7682013-10-04 13:01:42 -0700461 pci_set_drvdata(pdev, priv);
462 retval = gpiochip_add(&priv->chip);
Alek Du8bf02612009-09-22 16:46:36 -0700463 if (retval) {
Andy Shevchenko8aca1192013-05-22 13:20:13 +0300464 dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
Andy Shevchenko786e07e2013-05-22 13:20:12 +0300465 return retval;
Alek Du8bf02612009-09-22 16:46:36 -0700466 }
Mika Westerbergf5f93112012-04-05 12:15:17 +0300467
David Cohenf89a7682013-10-04 13:01:42 -0700468 intel_mid_irq_init_hw(priv);
Mika Westerbergf5f93112012-04-05 12:15:17 +0300469
David Cohenf89a7682013-10-04 13:01:42 -0700470 irq_set_handler_data(pdev->irq, priv);
471 irq_set_chained_handler(pdev->irq, intel_mid_irq_handler);
Alek Du8bf02612009-09-22 16:46:36 -0700472
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100473 pm_runtime_put_noidle(&pdev->dev);
474 pm_runtime_allow(&pdev->dev);
475
Mika Westerberg8302c742012-04-05 12:15:15 +0300476 return 0;
Alek Du8bf02612009-09-22 16:46:36 -0700477}
478
David Cohenf89a7682013-10-04 13:01:42 -0700479static struct pci_driver intel_gpio_driver = {
480 .name = "intel_mid_gpio",
481 .id_table = intel_gpio_ids,
482 .probe = intel_gpio_probe,
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100483 .driver = {
David Cohenf89a7682013-10-04 13:01:42 -0700484 .pm = &intel_gpio_pm_ops,
Kristen Carlson Accardi78128032011-05-10 14:23:45 +0100485 },
Alek Du8bf02612009-09-22 16:46:36 -0700486};
487
David Cohenf89a7682013-10-04 13:01:42 -0700488static int __init intel_gpio_init(void)
Alek Du8bf02612009-09-22 16:46:36 -0700489{
David Cohenf89a7682013-10-04 13:01:42 -0700490 return pci_register_driver(&intel_gpio_driver);
Alek Du8bf02612009-09-22 16:46:36 -0700491}
492
David Cohenf89a7682013-10-04 13:01:42 -0700493device_initcall(intel_gpio_init);