blob: 044bc98fb459e46fac62b929696ad047f835360d [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/console.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090029#include <linux/slab.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020030#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
Dave Airlie28d52042009-09-21 14:33:58 +100033#include <linux/vgaarb.h>
Dave Airlie6a9ee8a2010-02-01 15:38:10 +100034#include <linux/vga_switcheroo.h>
Matthew Garrettbcc65fd2011-08-08 16:21:16 +000035#include <linux/efi.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020036#include "radeon_reg.h"
37#include "radeon.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020038#include "atom.h"
39
Jerome Glisse1b5331d2010-04-12 20:21:53 +000040static const char radeon_family_name[][16] = {
41 "R100",
42 "RV100",
43 "RS100",
44 "RV200",
45 "RS200",
46 "R200",
47 "RV250",
48 "RS300",
49 "RV280",
50 "R300",
51 "R350",
52 "RV350",
53 "RV380",
54 "R420",
55 "R423",
56 "RV410",
57 "RS400",
58 "RS480",
59 "RS600",
60 "RS690",
61 "RS740",
62 "RV515",
63 "R520",
64 "RV530",
65 "RV560",
66 "RV570",
67 "R580",
68 "R600",
69 "RV610",
70 "RV630",
71 "RV670",
72 "RV620",
73 "RV635",
74 "RS780",
75 "RS880",
76 "RV770",
77 "RV730",
78 "RV710",
79 "RV740",
80 "CEDAR",
81 "REDWOOD",
82 "JUNIPER",
83 "CYPRESS",
84 "HEMLOCK",
Alex Deucherb08ebe72010-12-03 15:34:16 -050085 "PALM",
Alex Deucher4df64e62011-05-31 15:42:46 -040086 "SUMO",
87 "SUMO2",
Alex Deucher1fe18302011-01-06 21:19:12 -050088 "BARTS",
89 "TURKS",
90 "CAICOS",
Alex Deucherb7cfc9f2011-03-02 20:07:27 -050091 "CAYMAN",
Alex Deucher8848f752012-03-20 17:18:28 -040092 "ARUBA",
Alex Deuchercb28bb32012-03-20 17:17:59 -040093 "TAHITI",
94 "PITCAIRN",
95 "VERDE",
Alex Deucher624d3522012-12-18 17:01:35 -050096 "OLAND",
Alex Deucherb5d9d722012-07-26 18:53:55 -040097 "HAINAN",
Alex Deucher6eac752e2013-06-07 11:36:11 -040098 "BONAIRE",
99 "KAVERI",
100 "KABINI",
Alex Deucher3bf599e2013-08-06 15:13:36 -0400101 "HAWAII",
Jerome Glisse1b5331d2010-04-12 20:21:53 +0000102 "LAST",
103};
104
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000105#if defined(CONFIG_VGA_SWITCHEROO)
106bool radeon_is_px(void);
107#else
108static inline bool radeon_is_px(void) { return false; }
109#endif
110
Alex Deucher0c195112012-07-17 14:02:33 -0400111/**
Alex Deucher2e1b65f2013-02-26 11:26:51 -0500112 * radeon_program_register_sequence - program an array of registers.
113 *
114 * @rdev: radeon_device pointer
115 * @registers: pointer to the register array
116 * @array_size: size of the register array
117 *
118 * Programs an array or registers with and and or masks.
119 * This is a helper for setting golden registers.
120 */
121void radeon_program_register_sequence(struct radeon_device *rdev,
122 const u32 *registers,
123 const u32 array_size)
124{
125 u32 tmp, reg, and_mask, or_mask;
126 int i;
127
128 if (array_size % 3)
129 return;
130
131 for (i = 0; i < array_size; i +=3) {
132 reg = registers[i + 0];
133 and_mask = registers[i + 1];
134 or_mask = registers[i + 2];
135
136 if (and_mask == 0xffffffff) {
137 tmp = or_mask;
138 } else {
139 tmp = RREG32(reg);
140 tmp &= ~and_mask;
141 tmp |= or_mask;
142 }
143 WREG32(reg, tmp);
144 }
145}
146
Alex Deucher1a0041b2013-10-02 13:01:36 -0400147void radeon_pci_config_reset(struct radeon_device *rdev)
148{
149 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
150}
151
Alex Deucher2e1b65f2013-02-26 11:26:51 -0500152/**
Alex Deucher0c195112012-07-17 14:02:33 -0400153 * radeon_surface_init - Clear GPU surface registers.
154 *
155 * @rdev: radeon_device pointer
156 *
157 * Clear GPU surface registers (r1xx-r5xx).
Michel Dänzerb1e3a6d2009-06-23 16:12:54 +0200158 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000159void radeon_surface_init(struct radeon_device *rdev)
Michel Dänzerb1e3a6d2009-06-23 16:12:54 +0200160{
161 /* FIXME: check this out */
162 if (rdev->family < CHIP_R600) {
163 int i;
164
Dave Airlie550e2d92009-12-09 14:15:38 +1000165 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
166 if (rdev->surface_regs[i].bo)
167 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
168 else
169 radeon_clear_surface_reg(rdev, i);
Michel Dänzerb1e3a6d2009-06-23 16:12:54 +0200170 }
Dave Airliee024e112009-06-24 09:48:08 +1000171 /* enable surfaces */
172 WREG32(RADEON_SURFACE_CNTL, 0);
Michel Dänzerb1e3a6d2009-06-23 16:12:54 +0200173 }
174}
175
176/*
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200177 * GPU scratch registers helpers function.
178 */
Alex Deucher0c195112012-07-17 14:02:33 -0400179/**
180 * radeon_scratch_init - Init scratch register driver information.
181 *
182 * @rdev: radeon_device pointer
183 *
184 * Init CP scratch register driver information (r1xx-r5xx)
185 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000186void radeon_scratch_init(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200187{
188 int i;
189
190 /* FIXME: check this out */
191 if (rdev->family < CHIP_R300) {
192 rdev->scratch.num_reg = 5;
193 } else {
194 rdev->scratch.num_reg = 7;
195 }
Alex Deucher724c80e2010-08-27 18:25:25 -0400196 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200197 for (i = 0; i < rdev->scratch.num_reg; i++) {
198 rdev->scratch.free[i] = true;
Alex Deucher724c80e2010-08-27 18:25:25 -0400199 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200200 }
201}
202
Alex Deucher0c195112012-07-17 14:02:33 -0400203/**
204 * radeon_scratch_get - Allocate a scratch register
205 *
206 * @rdev: radeon_device pointer
207 * @reg: scratch register mmio offset
208 *
209 * Allocate a CP scratch register for use by the driver (all asics).
210 * Returns 0 on success or -EINVAL on failure.
211 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200212int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
213{
214 int i;
215
216 for (i = 0; i < rdev->scratch.num_reg; i++) {
217 if (rdev->scratch.free[i]) {
218 rdev->scratch.free[i] = false;
219 *reg = rdev->scratch.reg[i];
220 return 0;
221 }
222 }
223 return -EINVAL;
224}
225
Alex Deucher0c195112012-07-17 14:02:33 -0400226/**
227 * radeon_scratch_free - Free a scratch register
228 *
229 * @rdev: radeon_device pointer
230 * @reg: scratch register mmio offset
231 *
232 * Free a CP scratch register allocated for use by the driver (all asics)
233 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200234void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
235{
236 int i;
237
238 for (i = 0; i < rdev->scratch.num_reg; i++) {
239 if (rdev->scratch.reg[i] == reg) {
240 rdev->scratch.free[i] = true;
241 return;
242 }
243 }
244}
245
Alex Deucher0c195112012-07-17 14:02:33 -0400246/*
Alex Deucher75efdee2013-03-04 12:47:46 -0500247 * GPU doorbell aperture helpers function.
248 */
249/**
250 * radeon_doorbell_init - Init doorbell driver information.
251 *
252 * @rdev: radeon_device pointer
253 *
254 * Init doorbell driver information (CIK)
255 * Returns 0 on success, error on failure.
256 */
Rashika Kheria28f5a6c2014-01-06 20:51:40 +0530257static int radeon_doorbell_init(struct radeon_device *rdev)
Alex Deucher75efdee2013-03-04 12:47:46 -0500258{
Alex Deucher75efdee2013-03-04 12:47:46 -0500259 /* doorbell bar mapping */
260 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
261 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
262
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -0500263 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);
264 if (rdev->doorbell.num_doorbells == 0)
265 return -EINVAL;
Alex Deucher75efdee2013-03-04 12:47:46 -0500266
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -0500267 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));
Alex Deucher75efdee2013-03-04 12:47:46 -0500268 if (rdev->doorbell.ptr == NULL) {
269 return -ENOMEM;
270 }
271 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
272 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
273
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -0500274 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));
Alex Deucher75efdee2013-03-04 12:47:46 -0500275
Alex Deucher75efdee2013-03-04 12:47:46 -0500276 return 0;
277}
278
279/**
280 * radeon_doorbell_fini - Tear down doorbell driver information.
281 *
282 * @rdev: radeon_device pointer
283 *
284 * Tear down doorbell driver information (CIK)
285 */
Rashika Kheria28f5a6c2014-01-06 20:51:40 +0530286static void radeon_doorbell_fini(struct radeon_device *rdev)
Alex Deucher75efdee2013-03-04 12:47:46 -0500287{
288 iounmap(rdev->doorbell.ptr);
289 rdev->doorbell.ptr = NULL;
290}
291
292/**
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -0500293 * radeon_doorbell_get - Allocate a doorbell entry
Alex Deucher75efdee2013-03-04 12:47:46 -0500294 *
295 * @rdev: radeon_device pointer
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -0500296 * @doorbell: doorbell index
Alex Deucher75efdee2013-03-04 12:47:46 -0500297 *
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -0500298 * Allocate a doorbell for use by the driver (all asics).
Alex Deucher75efdee2013-03-04 12:47:46 -0500299 * Returns 0 on success or -EINVAL on failure.
300 */
301int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)
302{
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -0500303 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);
304 if (offset < rdev->doorbell.num_doorbells) {
305 __set_bit(offset, rdev->doorbell.used);
306 *doorbell = offset;
307 return 0;
308 } else {
309 return -EINVAL;
Alex Deucher75efdee2013-03-04 12:47:46 -0500310 }
Alex Deucher75efdee2013-03-04 12:47:46 -0500311}
312
313/**
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -0500314 * radeon_doorbell_free - Free a doorbell entry
Alex Deucher75efdee2013-03-04 12:47:46 -0500315 *
316 * @rdev: radeon_device pointer
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -0500317 * @doorbell: doorbell index
Alex Deucher75efdee2013-03-04 12:47:46 -0500318 *
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -0500319 * Free a doorbell allocated for use by the driver (all asics)
Alex Deucher75efdee2013-03-04 12:47:46 -0500320 */
321void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
322{
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -0500323 if (doorbell < rdev->doorbell.num_doorbells)
324 __clear_bit(doorbell, rdev->doorbell.used);
Alex Deucher75efdee2013-03-04 12:47:46 -0500325}
326
327/*
Alex Deucher0c195112012-07-17 14:02:33 -0400328 * radeon_wb_*()
329 * Writeback is the the method by which the the GPU updates special pages
330 * in memory with the status of certain GPU events (fences, ring pointers,
331 * etc.).
332 */
333
334/**
335 * radeon_wb_disable - Disable Writeback
336 *
337 * @rdev: radeon_device pointer
338 *
339 * Disables Writeback (all asics). Used for suspend.
340 */
Alex Deucher724c80e2010-08-27 18:25:25 -0400341void radeon_wb_disable(struct radeon_device *rdev)
342{
Alex Deucher724c80e2010-08-27 18:25:25 -0400343 rdev->wb.enabled = false;
344}
345
Alex Deucher0c195112012-07-17 14:02:33 -0400346/**
347 * radeon_wb_fini - Disable Writeback and free memory
348 *
349 * @rdev: radeon_device pointer
350 *
351 * Disables Writeback and frees the Writeback memory (all asics).
352 * Used at driver shutdown.
353 */
Alex Deucher724c80e2010-08-27 18:25:25 -0400354void radeon_wb_fini(struct radeon_device *rdev)
355{
356 radeon_wb_disable(rdev);
357 if (rdev->wb.wb_obj) {
Jerome Glisse089920f2013-06-06 17:51:21 -0400358 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
359 radeon_bo_kunmap(rdev->wb.wb_obj);
360 radeon_bo_unpin(rdev->wb.wb_obj);
361 radeon_bo_unreserve(rdev->wb.wb_obj);
362 }
Alex Deucher724c80e2010-08-27 18:25:25 -0400363 radeon_bo_unref(&rdev->wb.wb_obj);
364 rdev->wb.wb = NULL;
365 rdev->wb.wb_obj = NULL;
366 }
367}
368
Alex Deucher0c195112012-07-17 14:02:33 -0400369/**
370 * radeon_wb_init- Init Writeback driver info and allocate memory
371 *
372 * @rdev: radeon_device pointer
373 *
374 * Disables Writeback and frees the Writeback memory (all asics).
375 * Used at driver startup.
376 * Returns 0 on success or an -error on failure.
377 */
Alex Deucher724c80e2010-08-27 18:25:25 -0400378int radeon_wb_init(struct radeon_device *rdev)
379{
380 int r;
381
382 if (rdev->wb.wb_obj == NULL) {
Daniel Vetter441921d2011-02-18 17:59:16 +0100383 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
Alex Deucher40f5cf92012-05-10 18:33:13 -0400384 RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj);
Alex Deucher724c80e2010-08-27 18:25:25 -0400385 if (r) {
386 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
387 return r;
388 }
Jerome Glisse089920f2013-06-06 17:51:21 -0400389 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
390 if (unlikely(r != 0)) {
391 radeon_wb_fini(rdev);
392 return r;
393 }
394 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
395 &rdev->wb.gpu_addr);
396 if (r) {
397 radeon_bo_unreserve(rdev->wb.wb_obj);
398 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
399 radeon_wb_fini(rdev);
400 return r;
401 }
402 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
Alex Deucher724c80e2010-08-27 18:25:25 -0400403 radeon_bo_unreserve(rdev->wb.wb_obj);
Jerome Glisse089920f2013-06-06 17:51:21 -0400404 if (r) {
405 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
406 radeon_wb_fini(rdev);
407 return r;
408 }
Alex Deucher724c80e2010-08-27 18:25:25 -0400409 }
410
Alex Deuchere6ba7592011-06-13 22:02:51 +0000411 /* clear wb memory */
412 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
Alex Deucherd0f8a852010-09-04 05:04:34 -0400413 /* disable event_write fences */
414 rdev->wb.use_event = false;
Alex Deucher724c80e2010-08-27 18:25:25 -0400415 /* disabled via module param */
Jerome Glisse3b7a2b22012-05-09 15:34:47 +0200416 if (radeon_no_wb == 1) {
Alex Deucher724c80e2010-08-27 18:25:25 -0400417 rdev->wb.enabled = false;
Jerome Glisse3b7a2b22012-05-09 15:34:47 +0200418 } else {
Alex Deucher724c80e2010-08-27 18:25:25 -0400419 if (rdev->flags & RADEON_IS_AGP) {
Alex Deucher28eebb72012-01-03 09:48:38 -0500420 /* often unreliable on AGP */
421 rdev->wb.enabled = false;
422 } else if (rdev->family < CHIP_R300) {
423 /* often unreliable on pre-r300 */
Alex Deucher724c80e2010-08-27 18:25:25 -0400424 rdev->wb.enabled = false;
Alex Deucherd0f8a852010-09-04 05:04:34 -0400425 } else {
Alex Deucher724c80e2010-08-27 18:25:25 -0400426 rdev->wb.enabled = true;
Alex Deucherd0f8a852010-09-04 05:04:34 -0400427 /* event_write fences are only available on r600+ */
Jerome Glisse3b7a2b22012-05-09 15:34:47 +0200428 if (rdev->family >= CHIP_R600) {
Alex Deucherd0f8a852010-09-04 05:04:34 -0400429 rdev->wb.use_event = true;
Jerome Glisse3b7a2b22012-05-09 15:34:47 +0200430 }
Alex Deucherd0f8a852010-09-04 05:04:34 -0400431 }
Alex Deucher724c80e2010-08-27 18:25:25 -0400432 }
Alex Deucherc994ead2012-05-03 17:06:28 -0400433 /* always use writeback/events on NI, APUs */
434 if (rdev->family >= CHIP_PALM) {
Alex Deucher7d527852011-01-06 21:19:27 -0500435 rdev->wb.enabled = true;
436 rdev->wb.use_event = true;
437 }
Alex Deucher724c80e2010-08-27 18:25:25 -0400438
439 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
440
441 return 0;
442}
443
Jerome Glissed594e462010-02-17 21:54:29 +0000444/**
445 * radeon_vram_location - try to find VRAM location
446 * @rdev: radeon device structure holding all necessary informations
447 * @mc: memory controller structure holding memory informations
448 * @base: base address at which to put VRAM
449 *
450 * Function will place try to place VRAM at base address provided
451 * as parameter (which is so far either PCI aperture address or
452 * for IGP TOM base address).
453 *
454 * If there is not enough space to fit the unvisible VRAM in the 32bits
455 * address space then we limit the VRAM size to the aperture.
456 *
457 * If we are using AGP and if the AGP aperture doesn't allow us to have
458 * room for all the VRAM than we restrict the VRAM to the PCI aperture
459 * size and print a warning.
460 *
461 * This function will never fails, worst case are limiting VRAM.
462 *
463 * Note: GTT start, end, size should be initialized before calling this
464 * function on AGP platform.
465 *
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300466 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
Jerome Glissed594e462010-02-17 21:54:29 +0000467 * this shouldn't be a problem as we are using the PCI aperture as a reference.
468 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
469 * not IGP.
470 *
471 * Note: we use mc_vram_size as on some board we need to program the mc to
472 * cover the whole aperture even if VRAM size is inferior to aperture size
473 * Novell bug 204882 + along with lots of ubuntu ones
474 *
475 * Note: when limiting vram it's safe to overwritte real_vram_size because
476 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
477 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
478 * ones)
479 *
480 * Note: IGP TOM addr should be the same as the aperture addr, we don't
481 * explicitly check for that thought.
482 *
483 * FIXME: when reducing VRAM size align new size on power of 2.
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200484 */
Jerome Glissed594e462010-02-17 21:54:29 +0000485void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200486{
Christian König1bcb04f2012-10-23 15:53:16 +0200487 uint64_t limit = (uint64_t)radeon_vram_limit << 20;
488
Jerome Glissed594e462010-02-17 21:54:29 +0000489 mc->vram_start = base;
Alex Deucher9ed8b1f2013-04-08 11:13:01 -0400490 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
Jerome Glissed594e462010-02-17 21:54:29 +0000491 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
492 mc->real_vram_size = mc->aper_size;
493 mc->mc_vram_size = mc->aper_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200494 }
Jerome Glissed594e462010-02-17 21:54:29 +0000495 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
Jerome Glisse2cbeb4e2010-08-16 11:54:36 -0400496 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
Jerome Glissed594e462010-02-17 21:54:29 +0000497 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
498 mc->real_vram_size = mc->aper_size;
499 mc->mc_vram_size = mc->aper_size;
500 }
501 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
Christian König1bcb04f2012-10-23 15:53:16 +0200502 if (limit && limit < mc->real_vram_size)
503 mc->real_vram_size = limit;
Alex Deucherdd7cc552010-12-03 14:37:21 -0500504 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
Jerome Glissed594e462010-02-17 21:54:29 +0000505 mc->mc_vram_size >> 20, mc->vram_start,
506 mc->vram_end, mc->real_vram_size >> 20);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200507}
508
Jerome Glissed594e462010-02-17 21:54:29 +0000509/**
510 * radeon_gtt_location - try to find GTT location
511 * @rdev: radeon device structure holding all necessary informations
512 * @mc: memory controller structure holding memory informations
513 *
514 * Function will place try to place GTT before or after VRAM.
515 *
516 * If GTT size is bigger than space left then we ajust GTT size.
517 * Thus function will never fails.
518 *
519 * FIXME: when reducing GTT size align new size on power of 2.
520 */
521void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
522{
523 u64 size_af, size_bf;
524
Alex Deucher9ed8b1f2013-04-08 11:13:01 -0400525 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
Alex Deucher8d369bb2010-07-15 10:51:10 -0400526 size_bf = mc->vram_start & ~mc->gtt_base_align;
Jerome Glissed594e462010-02-17 21:54:29 +0000527 if (size_bf > size_af) {
528 if (mc->gtt_size > size_bf) {
529 dev_warn(rdev->dev, "limiting GTT\n");
530 mc->gtt_size = size_bf;
531 }
Alex Deucher8d369bb2010-07-15 10:51:10 -0400532 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
Jerome Glissed594e462010-02-17 21:54:29 +0000533 } else {
534 if (mc->gtt_size > size_af) {
535 dev_warn(rdev->dev, "limiting GTT\n");
536 mc->gtt_size = size_af;
537 }
Alex Deucher8d369bb2010-07-15 10:51:10 -0400538 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
Jerome Glissed594e462010-02-17 21:54:29 +0000539 }
540 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
Alex Deucherdd7cc552010-12-03 14:37:21 -0500541 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
Jerome Glissed594e462010-02-17 21:54:29 +0000542 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
543}
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200544
545/*
546 * GPU helpers function.
547 */
Alex Deucher0c195112012-07-17 14:02:33 -0400548/**
549 * radeon_card_posted - check if the hw has already been initialized
550 *
551 * @rdev: radeon_device pointer
552 *
553 * Check if the asic has been initialized (all asics).
554 * Used at driver startup.
555 * Returns true if initialized or false if not.
556 */
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200557bool radeon_card_posted(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200558{
559 uint32_t reg;
560
Alex Deucher50a583f2013-05-22 13:29:33 -0400561 /* required for EFI mode on macbook2,1 which uses an r5xx asic */
Matt Fleming83e68182012-11-14 09:42:35 +0000562 if (efi_enabled(EFI_BOOT) &&
Alex Deucher50a583f2013-05-22 13:29:33 -0400563 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
564 (rdev->family < CHIP_R600))
Matthew Garrettbcc65fd2011-08-08 16:21:16 +0000565 return false;
566
Alex Deucher2cf3a4f2013-05-22 11:30:34 -0400567 if (ASIC_IS_NODCE(rdev))
568 goto check_memsize;
569
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200570 /* first check CRTCs */
Alex Deucher09fb8bd2013-05-22 11:22:51 -0400571 if (ASIC_IS_DCE4(rdev)) {
Alex Deucher18007402010-11-22 17:56:28 -0500572 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
573 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
Alex Deucher09fb8bd2013-05-22 11:22:51 -0400574 if (rdev->num_crtc >= 4) {
575 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
576 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
577 }
578 if (rdev->num_crtc >= 6) {
579 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
580 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
581 }
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500582 if (reg & EVERGREEN_CRTC_MASTER_EN)
583 return true;
584 } else if (ASIC_IS_AVIVO(rdev)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200585 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
586 RREG32(AVIVO_D2CRTC_CONTROL);
587 if (reg & AVIVO_CRTC_EN) {
588 return true;
589 }
590 } else {
591 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
592 RREG32(RADEON_CRTC2_GEN_CNTL);
593 if (reg & RADEON_CRTC_EN) {
594 return true;
595 }
596 }
597
Alex Deucher2cf3a4f2013-05-22 11:30:34 -0400598check_memsize:
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200599 /* then check MEM_SIZE, in case the crtcs are off */
600 if (rdev->family >= CHIP_R600)
601 reg = RREG32(R600_CONFIG_MEMSIZE);
602 else
603 reg = RREG32(RADEON_CONFIG_MEMSIZE);
604
605 if (reg)
606 return true;
607
608 return false;
609
610}
611
Alex Deucher0c195112012-07-17 14:02:33 -0400612/**
613 * radeon_update_bandwidth_info - update display bandwidth params
614 *
615 * @rdev: radeon_device pointer
616 *
617 * Used when sclk/mclk are switched or display modes are set.
618 * params are used to calculate display watermarks (all asics)
619 */
Alex Deucherf47299c2010-03-16 20:54:38 -0400620void radeon_update_bandwidth_info(struct radeon_device *rdev)
621{
622 fixed20_12 a;
Alex Deucher88072862010-08-10 12:33:20 -0400623 u32 sclk = rdev->pm.current_sclk;
624 u32 mclk = rdev->pm.current_mclk;
625
626 /* sclk/mclk in Mhz */
627 a.full = dfixed_const(100);
628 rdev->pm.sclk.full = dfixed_const(sclk);
629 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
630 rdev->pm.mclk.full = dfixed_const(mclk);
631 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
Alex Deucherf47299c2010-03-16 20:54:38 -0400632
633 if (rdev->flags & RADEON_IS_IGP) {
Ben Skeggs68adac52010-04-28 11:46:42 +1000634 a.full = dfixed_const(16);
Alex Deucherf47299c2010-03-16 20:54:38 -0400635 /* core_bandwidth = sclk(Mhz) * 16 */
Ben Skeggs68adac52010-04-28 11:46:42 +1000636 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
Alex Deucherf47299c2010-03-16 20:54:38 -0400637 }
638}
639
Alex Deucher0c195112012-07-17 14:02:33 -0400640/**
641 * radeon_boot_test_post_card - check and possibly initialize the hw
642 *
643 * @rdev: radeon_device pointer
644 *
645 * Check if the asic is initialized and if not, attempt to initialize
646 * it (all asics).
647 * Returns true if initialized or false if not.
648 */
Dave Airlie72542d72009-12-01 14:06:31 +1000649bool radeon_boot_test_post_card(struct radeon_device *rdev)
650{
651 if (radeon_card_posted(rdev))
652 return true;
653
654 if (rdev->bios) {
655 DRM_INFO("GPU not posted. posting now...\n");
656 if (rdev->is_atom_bios)
657 atom_asic_init(rdev->mode_info.atom_context);
658 else
659 radeon_combios_asic_init(rdev->ddev);
660 return true;
661 } else {
662 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
663 return false;
664 }
665}
666
Alex Deucher0c195112012-07-17 14:02:33 -0400667/**
668 * radeon_dummy_page_init - init dummy page used by the driver
669 *
670 * @rdev: radeon_device pointer
671 *
672 * Allocate the dummy page used by the driver (all asics).
673 * This dummy page is used by the driver as a filler for gart entries
674 * when pages are taken out of the GART
675 * Returns 0 on sucess, -ENOMEM on failure.
676 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000677int radeon_dummy_page_init(struct radeon_device *rdev)
678{
Dave Airlie82568562010-02-05 16:00:07 +1000679 if (rdev->dummy_page.page)
680 return 0;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000681 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
682 if (rdev->dummy_page.page == NULL)
683 return -ENOMEM;
684 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
685 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
Benjamin Herrenschmidta30f6fb72010-08-10 14:48:58 +1000686 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
687 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000688 __free_page(rdev->dummy_page.page);
689 rdev->dummy_page.page = NULL;
690 return -ENOMEM;
691 }
692 return 0;
693}
694
Alex Deucher0c195112012-07-17 14:02:33 -0400695/**
696 * radeon_dummy_page_fini - free dummy page used by the driver
697 *
698 * @rdev: radeon_device pointer
699 *
700 * Frees the dummy page used by the driver (all asics).
701 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000702void radeon_dummy_page_fini(struct radeon_device *rdev)
703{
704 if (rdev->dummy_page.page == NULL)
705 return;
706 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
707 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
708 __free_page(rdev->dummy_page.page);
709 rdev->dummy_page.page = NULL;
710}
711
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200712
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200713/* ATOM accessor methods */
Alex Deucher0c195112012-07-17 14:02:33 -0400714/*
715 * ATOM is an interpreted byte code stored in tables in the vbios. The
716 * driver registers callbacks to access registers and the interpreter
717 * in the driver parses the tables and executes then to program specific
718 * actions (set display modes, asic init, etc.). See radeon_atombios.c,
719 * atombios.h, and atom.c
720 */
721
722/**
723 * cail_pll_read - read PLL register
724 *
725 * @info: atom card_info pointer
726 * @reg: PLL register offset
727 *
728 * Provides a PLL register accessor for the atom interpreter (r4xx+).
729 * Returns the value of the PLL register.
730 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200731static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
732{
733 struct radeon_device *rdev = info->dev->dev_private;
734 uint32_t r;
735
736 r = rdev->pll_rreg(rdev, reg);
737 return r;
738}
739
Alex Deucher0c195112012-07-17 14:02:33 -0400740/**
741 * cail_pll_write - write PLL register
742 *
743 * @info: atom card_info pointer
744 * @reg: PLL register offset
745 * @val: value to write to the pll register
746 *
747 * Provides a PLL register accessor for the atom interpreter (r4xx+).
748 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200749static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
750{
751 struct radeon_device *rdev = info->dev->dev_private;
752
753 rdev->pll_wreg(rdev, reg, val);
754}
755
Alex Deucher0c195112012-07-17 14:02:33 -0400756/**
757 * cail_mc_read - read MC (Memory Controller) register
758 *
759 * @info: atom card_info pointer
760 * @reg: MC register offset
761 *
762 * Provides an MC register accessor for the atom interpreter (r4xx+).
763 * Returns the value of the MC register.
764 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200765static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
766{
767 struct radeon_device *rdev = info->dev->dev_private;
768 uint32_t r;
769
770 r = rdev->mc_rreg(rdev, reg);
771 return r;
772}
773
Alex Deucher0c195112012-07-17 14:02:33 -0400774/**
775 * cail_mc_write - write MC (Memory Controller) register
776 *
777 * @info: atom card_info pointer
778 * @reg: MC register offset
779 * @val: value to write to the pll register
780 *
781 * Provides a MC register accessor for the atom interpreter (r4xx+).
782 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200783static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
784{
785 struct radeon_device *rdev = info->dev->dev_private;
786
787 rdev->mc_wreg(rdev, reg, val);
788}
789
Alex Deucher0c195112012-07-17 14:02:33 -0400790/**
791 * cail_reg_write - write MMIO register
792 *
793 * @info: atom card_info pointer
794 * @reg: MMIO register offset
795 * @val: value to write to the pll register
796 *
797 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
798 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200799static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
800{
801 struct radeon_device *rdev = info->dev->dev_private;
802
803 WREG32(reg*4, val);
804}
805
Alex Deucher0c195112012-07-17 14:02:33 -0400806/**
807 * cail_reg_read - read MMIO register
808 *
809 * @info: atom card_info pointer
810 * @reg: MMIO register offset
811 *
812 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
813 * Returns the value of the MMIO register.
814 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200815static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
816{
817 struct radeon_device *rdev = info->dev->dev_private;
818 uint32_t r;
819
820 r = RREG32(reg*4);
821 return r;
822}
823
Alex Deucher0c195112012-07-17 14:02:33 -0400824/**
825 * cail_ioreg_write - write IO register
826 *
827 * @info: atom card_info pointer
828 * @reg: IO register offset
829 * @val: value to write to the pll register
830 *
831 * Provides a IO register accessor for the atom interpreter (r4xx+).
832 */
Alex Deucher351a52a2010-06-30 11:52:50 -0400833static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
834{
835 struct radeon_device *rdev = info->dev->dev_private;
836
837 WREG32_IO(reg*4, val);
838}
839
Alex Deucher0c195112012-07-17 14:02:33 -0400840/**
841 * cail_ioreg_read - read IO register
842 *
843 * @info: atom card_info pointer
844 * @reg: IO register offset
845 *
846 * Provides an IO register accessor for the atom interpreter (r4xx+).
847 * Returns the value of the IO register.
848 */
Alex Deucher351a52a2010-06-30 11:52:50 -0400849static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
850{
851 struct radeon_device *rdev = info->dev->dev_private;
852 uint32_t r;
853
854 r = RREG32_IO(reg*4);
855 return r;
856}
857
Alex Deucher0c195112012-07-17 14:02:33 -0400858/**
859 * radeon_atombios_init - init the driver info and callbacks for atombios
860 *
861 * @rdev: radeon_device pointer
862 *
863 * Initializes the driver info and register access callbacks for the
864 * ATOM interpreter (r4xx+).
865 * Returns 0 on sucess, -ENOMEM on failure.
866 * Called at driver startup.
867 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200868int radeon_atombios_init(struct radeon_device *rdev)
869{
Mathias Fröhlich61c4b242009-10-27 15:08:01 -0400870 struct card_info *atom_card_info =
871 kzalloc(sizeof(struct card_info), GFP_KERNEL);
872
873 if (!atom_card_info)
874 return -ENOMEM;
875
876 rdev->mode_info.atom_card_info = atom_card_info;
877 atom_card_info->dev = rdev->ddev;
878 atom_card_info->reg_read = cail_reg_read;
879 atom_card_info->reg_write = cail_reg_write;
Alex Deucher351a52a2010-06-30 11:52:50 -0400880 /* needed for iio ops */
881 if (rdev->rio_mem) {
882 atom_card_info->ioreg_read = cail_ioreg_read;
883 atom_card_info->ioreg_write = cail_ioreg_write;
884 } else {
885 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
886 atom_card_info->ioreg_read = cail_reg_read;
887 atom_card_info->ioreg_write = cail_reg_write;
888 }
Mathias Fröhlich61c4b242009-10-27 15:08:01 -0400889 atom_card_info->mc_read = cail_mc_read;
890 atom_card_info->mc_write = cail_mc_write;
891 atom_card_info->pll_read = cail_pll_read;
892 atom_card_info->pll_write = cail_pll_write;
893
894 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
Tim Gardner0e34d092013-02-11 14:34:32 -0700895 if (!rdev->mode_info.atom_context) {
896 radeon_atombios_fini(rdev);
897 return -ENOMEM;
898 }
899
Rafał Miłeckic31ad972009-12-17 00:00:46 +0100900 mutex_init(&rdev->mode_info.atom_context->mutex);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200901 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
Dave Airlied904ef92009-11-17 06:29:46 +1000902 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200903 return 0;
904}
905
Alex Deucher0c195112012-07-17 14:02:33 -0400906/**
907 * radeon_atombios_fini - free the driver info and callbacks for atombios
908 *
909 * @rdev: radeon_device pointer
910 *
911 * Frees the driver info and register access callbacks for the ATOM
912 * interpreter (r4xx+).
913 * Called at driver shutdown.
914 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200915void radeon_atombios_fini(struct radeon_device *rdev)
916{
Jerome Glisse4a04a842009-12-09 17:39:16 +0100917 if (rdev->mode_info.atom_context) {
918 kfree(rdev->mode_info.atom_context->scratch);
Jerome Glisse4a04a842009-12-09 17:39:16 +0100919 }
Tim Gardner0e34d092013-02-11 14:34:32 -0700920 kfree(rdev->mode_info.atom_context);
921 rdev->mode_info.atom_context = NULL;
Mathias Fröhlich61c4b242009-10-27 15:08:01 -0400922 kfree(rdev->mode_info.atom_card_info);
Tim Gardner0e34d092013-02-11 14:34:32 -0700923 rdev->mode_info.atom_card_info = NULL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200924}
925
Alex Deucher0c195112012-07-17 14:02:33 -0400926/* COMBIOS */
927/*
928 * COMBIOS is the bios format prior to ATOM. It provides
929 * command tables similar to ATOM, but doesn't have a unified
930 * parser. See radeon_combios.c
931 */
932
933/**
934 * radeon_combios_init - init the driver info for combios
935 *
936 * @rdev: radeon_device pointer
937 *
938 * Initializes the driver info for combios (r1xx-r3xx).
939 * Returns 0 on sucess.
940 * Called at driver startup.
941 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200942int radeon_combios_init(struct radeon_device *rdev)
943{
944 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
945 return 0;
946}
947
Alex Deucher0c195112012-07-17 14:02:33 -0400948/**
949 * radeon_combios_fini - free the driver info for combios
950 *
951 * @rdev: radeon_device pointer
952 *
953 * Frees the driver info for combios (r1xx-r3xx).
954 * Called at driver shutdown.
955 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200956void radeon_combios_fini(struct radeon_device *rdev)
957{
958}
959
Alex Deucher0c195112012-07-17 14:02:33 -0400960/* if we get transitioned to only one device, take VGA back */
961/**
962 * radeon_vga_set_decode - enable/disable vga decode
963 *
964 * @cookie: radeon_device pointer
965 * @state: enable/disable vga decode
966 *
967 * Enable/disable vga decode (all asics).
968 * Returns VGA resource flags.
969 */
Dave Airlie28d52042009-09-21 14:33:58 +1000970static unsigned int radeon_vga_set_decode(void *cookie, bool state)
971{
972 struct radeon_device *rdev = cookie;
Dave Airlie28d52042009-09-21 14:33:58 +1000973 radeon_vga_set_state(rdev, state);
974 if (state)
975 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
976 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
977 else
978 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
979}
Dave Airliec1176d62009-10-08 14:03:05 +1000980
Alex Deucher0c195112012-07-17 14:02:33 -0400981/**
Christian König1bcb04f2012-10-23 15:53:16 +0200982 * radeon_check_pot_argument - check that argument is a power of two
983 *
984 * @arg: value to check
985 *
986 * Validates that a certain argument is a power of two (all asics).
987 * Returns true if argument is valid.
988 */
989static bool radeon_check_pot_argument(int arg)
990{
991 return (arg & (arg - 1)) == 0;
992}
993
994/**
Alex Deucher0c195112012-07-17 14:02:33 -0400995 * radeon_check_arguments - validate module params
996 *
997 * @rdev: radeon_device pointer
998 *
999 * Validates certain module parameters and updates
1000 * the associated values used by the driver (all asics).
1001 */
Lauri Kasanen1109ca02012-08-31 13:43:50 -04001002static void radeon_check_arguments(struct radeon_device *rdev)
Jerome Glisse36421332009-12-11 21:18:34 +01001003{
1004 /* vramlimit must be a power of two */
Christian König1bcb04f2012-10-23 15:53:16 +02001005 if (!radeon_check_pot_argument(radeon_vram_limit)) {
Jerome Glisse36421332009-12-11 21:18:34 +01001006 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
1007 radeon_vram_limit);
1008 radeon_vram_limit = 0;
Jerome Glisse36421332009-12-11 21:18:34 +01001009 }
Christian König1bcb04f2012-10-23 15:53:16 +02001010
Alex Deucheredcd26e2013-07-05 17:16:51 -04001011 if (radeon_gart_size == -1) {
1012 /* default to a larger gart size on newer asics */
1013 if (rdev->family >= CHIP_RV770)
1014 radeon_gart_size = 1024;
1015 else
1016 radeon_gart_size = 512;
1017 }
Jerome Glisse36421332009-12-11 21:18:34 +01001018 /* gtt size must be power of two and greater or equal to 32M */
Christian König1bcb04f2012-10-23 15:53:16 +02001019 if (radeon_gart_size < 32) {
Alex Deucheredcd26e2013-07-05 17:16:51 -04001020 dev_warn(rdev->dev, "gart size (%d) too small\n",
Jerome Glisse36421332009-12-11 21:18:34 +01001021 radeon_gart_size);
Alex Deucheredcd26e2013-07-05 17:16:51 -04001022 if (rdev->family >= CHIP_RV770)
1023 radeon_gart_size = 1024;
1024 else
1025 radeon_gart_size = 512;
Christian König1bcb04f2012-10-23 15:53:16 +02001026 } else if (!radeon_check_pot_argument(radeon_gart_size)) {
Jerome Glisse36421332009-12-11 21:18:34 +01001027 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
1028 radeon_gart_size);
Alex Deucheredcd26e2013-07-05 17:16:51 -04001029 if (rdev->family >= CHIP_RV770)
1030 radeon_gart_size = 1024;
1031 else
1032 radeon_gart_size = 512;
Jerome Glisse36421332009-12-11 21:18:34 +01001033 }
Christian König1bcb04f2012-10-23 15:53:16 +02001034 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
1035
Jerome Glisse36421332009-12-11 21:18:34 +01001036 /* AGP mode can only be -1, 1, 2, 4, 8 */
1037 switch (radeon_agpmode) {
1038 case -1:
1039 case 0:
1040 case 1:
1041 case 2:
1042 case 4:
1043 case 8:
1044 break;
1045 default:
1046 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
1047 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
1048 radeon_agpmode = 0;
1049 break;
1050 }
1051}
1052
Alex Deucher0c195112012-07-17 14:02:33 -04001053/**
Maarten Lankhorstd1f98092013-01-07 15:18:47 +01001054 * radeon_switcheroo_quirk_long_wakeup - return true if longer d3 delay is
1055 * needed for waking up.
1056 *
1057 * @pdev: pci dev pointer
1058 */
1059static bool radeon_switcheroo_quirk_long_wakeup(struct pci_dev *pdev)
1060{
1061
1062 /* 6600m in a macbook pro */
1063 if (pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1064 pdev->subsystem_device == 0x00e2) {
1065 printk(KERN_INFO "radeon: quirking longer d3 wakeup delay\n");
1066 return true;
1067 }
1068
1069 return false;
1070}
1071
1072/**
Alex Deucher0c195112012-07-17 14:02:33 -04001073 * radeon_switcheroo_set_state - set switcheroo state
1074 *
1075 * @pdev: pci dev pointer
1076 * @state: vga switcheroo state
1077 *
1078 * Callback for the switcheroo driver. Suspends or resumes the
1079 * the asics before or after it is powered up using ACPI methods.
1080 */
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10001081static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1082{
1083 struct drm_device *dev = pci_get_drvdata(pdev);
Dave Airlie10ebc0b2012-09-17 14:40:31 +10001084
1085 if (radeon_is_px() && state == VGA_SWITCHEROO_OFF)
1086 return;
1087
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10001088 if (state == VGA_SWITCHEROO_ON) {
Maarten Lankhorstd1f98092013-01-07 15:18:47 +01001089 unsigned d3_delay = dev->pdev->d3_delay;
1090
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10001091 printk(KERN_INFO "radeon: switched on\n");
1092 /* don't suspend or resume card normally */
Dave Airlie5bcf7192010-12-07 09:20:40 +10001093 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
Maarten Lankhorstd1f98092013-01-07 15:18:47 +01001094
1095 if (d3_delay < 20 && radeon_switcheroo_quirk_long_wakeup(pdev))
1096 dev->pdev->d3_delay = 20;
1097
Dave Airlie10ebc0b2012-09-17 14:40:31 +10001098 radeon_resume_kms(dev, true, true);
Maarten Lankhorstd1f98092013-01-07 15:18:47 +01001099
1100 dev->pdev->d3_delay = d3_delay;
1101
Dave Airlie5bcf7192010-12-07 09:20:40 +10001102 dev->switch_power_state = DRM_SWITCH_POWER_ON;
Dave Airliefbf81762010-06-01 09:09:06 +10001103 drm_kms_helper_poll_enable(dev);
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10001104 } else {
1105 printk(KERN_INFO "radeon: switched off\n");
Dave Airliefbf81762010-06-01 09:09:06 +10001106 drm_kms_helper_poll_disable(dev);
Dave Airlie5bcf7192010-12-07 09:20:40 +10001107 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
Dave Airlie10ebc0b2012-09-17 14:40:31 +10001108 radeon_suspend_kms(dev, true, true);
Dave Airlie5bcf7192010-12-07 09:20:40 +10001109 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10001110 }
1111}
1112
Alex Deucher0c195112012-07-17 14:02:33 -04001113/**
1114 * radeon_switcheroo_can_switch - see if switcheroo state can change
1115 *
1116 * @pdev: pci dev pointer
1117 *
1118 * Callback for the switcheroo driver. Check of the switcheroo
1119 * state can be changed.
1120 * Returns true if the state can be changed, false if not.
1121 */
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10001122static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
1123{
1124 struct drm_device *dev = pci_get_drvdata(pdev);
1125 bool can_switch;
1126
1127 spin_lock(&dev->count_lock);
1128 can_switch = (dev->open_count == 0);
1129 spin_unlock(&dev->count_lock);
1130 return can_switch;
1131}
1132
Takashi Iwai26ec6852012-05-11 07:51:17 +02001133static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
1134 .set_gpu_state = radeon_switcheroo_set_state,
1135 .reprobe = NULL,
1136 .can_switch = radeon_switcheroo_can_switch,
1137};
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10001138
Alex Deucher0c195112012-07-17 14:02:33 -04001139/**
1140 * radeon_device_init - initialize the driver
1141 *
1142 * @rdev: radeon_device pointer
1143 * @pdev: drm dev pointer
1144 * @pdev: pci dev pointer
1145 * @flags: driver flags
1146 *
1147 * Initializes the driver info and hw (all asics).
1148 * Returns 0 for success or an error on failure.
1149 * Called at driver startup.
1150 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001151int radeon_device_init(struct radeon_device *rdev,
1152 struct drm_device *ddev,
1153 struct pci_dev *pdev,
1154 uint32_t flags)
1155{
Alex Deucher351a52a2010-06-30 11:52:50 -04001156 int r, i;
Dave Airliead49f502009-07-10 22:36:26 +10001157 int dma_bits;
Dave Airlie10ebc0b2012-09-17 14:40:31 +10001158 bool runtime = false;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001159
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001160 rdev->shutdown = false;
Jerome Glisse9f022dd2009-09-11 15:35:22 +02001161 rdev->dev = &pdev->dev;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001162 rdev->ddev = ddev;
1163 rdev->pdev = pdev;
1164 rdev->flags = flags;
1165 rdev->family = flags & RADEON_FAMILY_MASK;
1166 rdev->is_atom_bios = false;
1167 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
Alex Deucheredcd26e2013-07-05 17:16:51 -04001168 rdev->mc.gtt_size = 512 * 1024 * 1024;
Jerome Glisse733289c2009-09-16 15:24:21 +02001169 rdev->accel_working = false;
Alex Deucher8b25ed32012-07-17 14:02:30 -04001170 /* set up ring ids */
1171 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1172 rdev->ring[i].idx = i;
1173 }
Jerome Glisse1b5331d2010-04-12 20:21:53 +00001174
Thomas Reimd522d9c2011-07-29 14:28:59 +00001175 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
1176 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
1177 pdev->subsystem_vendor, pdev->subsystem_device);
Jerome Glisse1b5331d2010-04-12 20:21:53 +00001178
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001179 /* mutex initialization are all done here so we
1180 * can recall function without having locking issues */
Christian Königd6999bc2012-05-09 15:34:45 +02001181 mutex_init(&rdev->ring_lock);
Alex Deucher40bacf12009-12-23 03:23:21 -05001182 mutex_init(&rdev->dc_hw_i2c_mutex);
Christian Koenigc20dc362012-05-16 21:45:24 +02001183 atomic_set(&rdev->ih.lock, 0);
Jerome Glisse4c788672009-11-20 14:29:23 +01001184 mutex_init(&rdev->gem.mutex);
Rafał Miłeckic913e232009-12-22 23:02:16 +01001185 mutex_init(&rdev->pm.mutex);
Marek Olšák6759a0a2012-08-09 16:34:17 +02001186 mutex_init(&rdev->gpu_clock_mutex);
Alex Deucherf61d5b462013-08-06 12:40:16 -04001187 mutex_init(&rdev->srbm_mutex);
Christian Königdb7fce32012-05-11 14:57:18 +02001188 init_rwsem(&rdev->pm.mclk_lock);
Jerome Glissedee53e72012-07-02 12:45:19 -04001189 init_rwsem(&rdev->exclusive_lock);
Rafał Miłecki73a6d3f2010-01-08 00:22:47 +01001190 init_waitqueue_head(&rdev->irq.vblank_queue);
Alex Deucher1b9c3dd2012-05-10 13:00:06 -04001191 r = radeon_gem_init(rdev);
1192 if (r)
1193 return r;
Jerome Glisse721604a2012-01-05 22:11:05 -05001194 /* initialize vm here */
Christian König36ff39c2012-05-09 10:07:08 +02001195 mutex_init(&rdev->vm_manager.lock);
Alex Deucher23d4f1f2012-10-08 09:45:46 -04001196 /* Adjust VM size here.
1197 * Currently set to 4GB ((1 << 20) 4k pages).
1198 * Max GPUVM size for cayman and SI is 40 bits.
1199 */
Jerome Glisse721604a2012-01-05 22:11:05 -05001200 rdev->vm_manager.max_pfn = 1 << 20;
1201 INIT_LIST_HEAD(&rdev->vm_manager.lru_vm);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001202
Jerome Glisse4aac0472009-09-14 18:29:49 +02001203 /* Set asic functions */
1204 r = radeon_asic_init(rdev);
Jerome Glisse36421332009-12-11 21:18:34 +01001205 if (r)
Jerome Glisse4aac0472009-09-14 18:29:49 +02001206 return r;
Jerome Glisse36421332009-12-11 21:18:34 +01001207 radeon_check_arguments(rdev);
Jerome Glisse4aac0472009-09-14 18:29:49 +02001208
Alex Deucherf95df9c2010-03-21 14:02:25 -04001209 /* all of the newer IGP chips have an internal gart
1210 * However some rs4xx report as AGP, so remove that here.
1211 */
1212 if ((rdev->family >= CHIP_RS400) &&
1213 (rdev->flags & RADEON_IS_IGP)) {
1214 rdev->flags &= ~RADEON_IS_AGP;
1215 }
1216
Jerome Glisse30256a32009-11-30 17:47:59 +01001217 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
Jerome Glisseb574f252009-10-06 19:04:29 +02001218 radeon_agp_disable(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001219 }
1220
Alex Deucher9ed8b1f2013-04-08 11:13:01 -04001221 /* Set the internal MC address mask
1222 * This is the max address of the GPU's
1223 * internal address space.
1224 */
1225 if (rdev->family >= CHIP_CAYMAN)
1226 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1227 else if (rdev->family >= CHIP_CEDAR)
1228 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
1229 else
1230 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
1231
Dave Airliead49f502009-07-10 22:36:26 +10001232 /* set DMA mask + need_dma32 flags.
1233 * PCIE - can handle 40-bits.
Alex Deucher005a83f2011-10-05 10:02:57 -04001234 * IGP - can handle 40-bits
Dave Airliead49f502009-07-10 22:36:26 +10001235 * AGP - generally dma32 is safest
Alex Deucher005a83f2011-10-05 10:02:57 -04001236 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
Dave Airliead49f502009-07-10 22:36:26 +10001237 */
1238 rdev->need_dma32 = false;
1239 if (rdev->flags & RADEON_IS_AGP)
1240 rdev->need_dma32 = true;
Alex Deucher005a83f2011-10-05 10:02:57 -04001241 if ((rdev->flags & RADEON_IS_PCI) &&
Jerome Glisse4a2b6662012-08-28 16:50:22 -04001242 (rdev->family <= CHIP_RS740))
Dave Airliead49f502009-07-10 22:36:26 +10001243 rdev->need_dma32 = true;
1244
1245 dma_bits = rdev->need_dma32 ? 32 : 40;
1246 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001247 if (r) {
Daniel Haid62fff812011-06-08 20:04:45 +10001248 rdev->need_dma32 = true;
Konrad Rzeszutek Wilkc52494f2011-10-17 17:15:08 -04001249 dma_bits = 32;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001250 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
1251 }
Konrad Rzeszutek Wilkc52494f2011-10-17 17:15:08 -04001252 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1253 if (r) {
1254 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
1255 printk(KERN_WARNING "radeon: No coherent DMA available.\n");
1256 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001257
1258 /* Registers mapping */
1259 /* TODO: block userspace mapping of io register */
Daniel Vetter2c385152012-12-02 14:06:15 +01001260 spin_lock_init(&rdev->mmio_idx_lock);
Alex Deucherfe781182013-09-03 18:19:42 -04001261 spin_lock_init(&rdev->smc_idx_lock);
Alex Deucher0a5b7b02013-09-03 19:00:09 -04001262 spin_lock_init(&rdev->pll_idx_lock);
1263 spin_lock_init(&rdev->mc_idx_lock);
1264 spin_lock_init(&rdev->pcie_idx_lock);
1265 spin_lock_init(&rdev->pciep_idx_lock);
1266 spin_lock_init(&rdev->pif_idx_lock);
1267 spin_lock_init(&rdev->cg_idx_lock);
1268 spin_lock_init(&rdev->uvd_idx_lock);
1269 spin_lock_init(&rdev->rcu_idx_lock);
1270 spin_lock_init(&rdev->didt_idx_lock);
1271 spin_lock_init(&rdev->end_idx_lock);
Alex Deucherefad86db2012-12-18 21:24:37 -05001272 if (rdev->family >= CHIP_BONAIRE) {
1273 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
1274 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
1275 } else {
1276 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
1277 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
1278 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001279 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
1280 if (rdev->rmmio == NULL) {
1281 return -ENOMEM;
1282 }
1283 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
1284 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
1285
Alex Deucher75efdee2013-03-04 12:47:46 -05001286 /* doorbell bar mapping */
1287 if (rdev->family >= CHIP_BONAIRE)
1288 radeon_doorbell_init(rdev);
1289
Alex Deucher351a52a2010-06-30 11:52:50 -04001290 /* io port mapping */
1291 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1292 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
1293 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
1294 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
1295 break;
1296 }
1297 }
1298 if (rdev->rio_mem == NULL)
1299 DRM_ERROR("Unable to find PCI I/O BAR\n");
1300
Dave Airlie28d52042009-09-21 14:33:58 +10001301 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
Dave Airlie93239ea2009-10-28 11:09:58 +10001302 /* this will fail for cards that aren't VGA class devices, just
1303 * ignore it */
1304 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
Dave Airlie10ebc0b2012-09-17 14:40:31 +10001305
1306 if (radeon_runtime_pm == 1)
1307 runtime = true;
1308 if ((radeon_runtime_pm == -1) && radeon_is_px())
1309 runtime = true;
1310 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime);
1311 if (runtime)
1312 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain);
Dave Airlie28d52042009-09-21 14:33:58 +10001313
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001314 r = radeon_init(rdev);
Jerome Glisseb574f252009-10-06 19:04:29 +02001315 if (r)
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001316 return r;
Michel Dänzerb1e3a6d2009-06-23 16:12:54 +02001317
Christian König04eb2202012-07-07 12:47:58 +02001318 r = radeon_ib_ring_tests(rdev);
1319 if (r)
1320 DRM_ERROR("ib ring test failed (%d).\n", r);
1321
Jerome Glisse409851f2013-04-25 22:29:27 -04001322 r = radeon_gem_debugfs_init(rdev);
1323 if (r) {
1324 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1325 }
1326
Jerome Glisseb574f252009-10-06 19:04:29 +02001327 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1328 /* Acceleration not working on AGP card try again
1329 * with fallback to PCI or PCIE GART
1330 */
Jerome Glissea2d07b72010-03-09 14:45:11 +00001331 radeon_asic_reset(rdev);
Jerome Glisseb574f252009-10-06 19:04:29 +02001332 radeon_fini(rdev);
1333 radeon_agp_disable(rdev);
1334 r = radeon_init(rdev);
Jerome Glisse4aac0472009-09-14 18:29:49 +02001335 if (r)
1336 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001337 }
Alex Deucher6c7bcce2013-12-18 14:07:14 -05001338
Christian König60a7e392011-09-27 12:31:00 +02001339 if ((radeon_testing & 1)) {
Alex Deucher4a1132a2013-09-23 10:38:26 -04001340 if (rdev->accel_working)
1341 radeon_test_moves(rdev);
1342 else
1343 DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
Michel Dänzerecc0b322009-07-21 11:23:57 +02001344 }
Christian König60a7e392011-09-27 12:31:00 +02001345 if ((radeon_testing & 2)) {
Alex Deucher4a1132a2013-09-23 10:38:26 -04001346 if (rdev->accel_working)
1347 radeon_test_syncing(rdev);
1348 else
1349 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
Christian König60a7e392011-09-27 12:31:00 +02001350 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001351 if (radeon_benchmarking) {
Alex Deucher4a1132a2013-09-23 10:38:26 -04001352 if (rdev->accel_working)
1353 radeon_benchmark(rdev, radeon_benchmarking);
1354 else
1355 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001356 }
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +02001357 return 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001358}
1359
Christian König4d8bf9a2011-10-24 14:54:54 +02001360static void radeon_debugfs_remove_files(struct radeon_device *rdev);
1361
Alex Deucher0c195112012-07-17 14:02:33 -04001362/**
1363 * radeon_device_fini - tear down the driver
1364 *
1365 * @rdev: radeon_device pointer
1366 *
1367 * Tear down the driver info (all asics).
1368 * Called at driver shutdown.
1369 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001370void radeon_device_fini(struct radeon_device *rdev)
1371{
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001372 DRM_INFO("radeon: finishing device.\n");
1373 rdev->shutdown = true;
Jerome Glisse90aca4d2010-03-09 14:45:12 +00001374 /* evict vram memory */
1375 radeon_bo_evict_vram(rdev);
Jerome Glisse62a8ea32009-10-01 18:02:11 +02001376 radeon_fini(rdev);
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10001377 vga_switcheroo_unregister_client(rdev->pdev);
Dave Airliec1176d62009-10-08 14:03:05 +10001378 vga_client_register(rdev->pdev, NULL, NULL, NULL);
Alex Deuchere0a2ca72010-07-08 12:24:52 -04001379 if (rdev->rio_mem)
1380 pci_iounmap(rdev->pdev, rdev->rio_mem);
Alex Deucher351a52a2010-06-30 11:52:50 -04001381 rdev->rio_mem = NULL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001382 iounmap(rdev->rmmio);
1383 rdev->rmmio = NULL;
Alex Deucher75efdee2013-03-04 12:47:46 -05001384 if (rdev->family >= CHIP_BONAIRE)
1385 radeon_doorbell_fini(rdev);
Christian König4d8bf9a2011-10-24 14:54:54 +02001386 radeon_debugfs_remove_files(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001387}
1388
1389
1390/*
1391 * Suspend & resume.
1392 */
Alex Deucher0c195112012-07-17 14:02:33 -04001393/**
1394 * radeon_suspend_kms - initiate device suspend
1395 *
1396 * @pdev: drm dev pointer
1397 * @state: suspend state
1398 *
1399 * Puts the hw in the suspend state (all asics).
1400 * Returns 0 for success or an error on failure.
1401 * Called at driver suspend.
1402 */
Dave Airlie10ebc0b2012-09-17 14:40:31 +10001403int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001404{
Darren Jenkins875c1862009-12-30 12:18:30 +11001405 struct radeon_device *rdev;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001406 struct drm_crtc *crtc;
Alex Deucherd8dcaa12010-06-02 12:08:41 -04001407 struct drm_connector *connector;
Alex Deucher74652802011-08-25 13:39:48 -04001408 int i, r;
Jerome Glisse5f8f6352012-12-17 11:04:32 -05001409 bool force_completion = false;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001410
Darren Jenkins875c1862009-12-30 12:18:30 +11001411 if (dev == NULL || dev->dev_private == NULL) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001412 return -ENODEV;
1413 }
Dave Airlie7473e832012-09-13 12:02:30 +10001414
Darren Jenkins875c1862009-12-30 12:18:30 +11001415 rdev = dev->dev_private;
1416
Dave Airlie5bcf7192010-12-07 09:20:40 +10001417 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10001418 return 0;
Alex Deucherd8dcaa12010-06-02 12:08:41 -04001419
Seth Forshee86698c22012-01-31 19:06:25 -06001420 drm_kms_helper_poll_disable(dev);
1421
Alex Deucherd8dcaa12010-06-02 12:08:41 -04001422 /* turn off display hw */
1423 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1424 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1425 }
1426
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001427 /* unpin the front buffers */
1428 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1429 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
Jerome Glisse4c788672009-11-20 14:29:23 +01001430 struct radeon_bo *robj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001431
1432 if (rfb == NULL || rfb->obj == NULL) {
1433 continue;
1434 }
Daniel Vetter7e4d15d2011-02-18 17:59:17 +01001435 robj = gem_to_radeon_bo(rfb->obj);
Dave Airlie38651672010-03-30 05:34:13 +00001436 /* don't unpin kernel fb objects */
1437 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
Jerome Glisse4c788672009-11-20 14:29:23 +01001438 r = radeon_bo_reserve(robj, false);
Dave Airlie38651672010-03-30 05:34:13 +00001439 if (r == 0) {
Jerome Glisse4c788672009-11-20 14:29:23 +01001440 radeon_bo_unpin(robj);
1441 radeon_bo_unreserve(robj);
1442 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001443 }
1444 }
1445 /* evict vram memory */
Jerome Glisse4c788672009-11-20 14:29:23 +01001446 radeon_bo_evict_vram(rdev);
Christian König8a47cc92012-05-09 15:34:48 +02001447
1448 mutex_lock(&rdev->ring_lock);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001449 /* wait for gpu to finish processing current batch */
Jerome Glisse5f8f6352012-12-17 11:04:32 -05001450 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1451 r = radeon_fence_wait_empty_locked(rdev, i);
1452 if (r) {
1453 /* delay GPU reset to resume */
1454 force_completion = true;
1455 }
1456 }
1457 if (force_completion) {
1458 radeon_fence_driver_force_completion(rdev);
1459 }
Christian König8a47cc92012-05-09 15:34:48 +02001460 mutex_unlock(&rdev->ring_lock);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001461
Yang Zhaof657c2a2009-09-15 12:21:01 +10001462 radeon_save_bios_scratch_regs(rdev);
1463
Jerome Glisse62a8ea32009-10-01 18:02:11 +02001464 radeon_suspend(rdev);
Alex Deucherd4877cf2009-12-04 16:56:37 -05001465 radeon_hpd_fini(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001466 /* evict remaining vram memory */
Jerome Glisse4c788672009-11-20 14:29:23 +01001467 radeon_bo_evict_vram(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001468
Jerome Glisse10b06122010-05-21 18:48:54 +02001469 radeon_agp_suspend(rdev);
1470
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001471 pci_save_state(dev->pdev);
Dave Airlie7473e832012-09-13 12:02:30 +10001472 if (suspend) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001473 /* Shut down the device */
1474 pci_disable_device(dev->pdev);
1475 pci_set_power_state(dev->pdev, PCI_D3hot);
1476 }
Dave Airlie10ebc0b2012-09-17 14:40:31 +10001477
1478 if (fbcon) {
1479 console_lock();
1480 radeon_fbdev_set_suspend(rdev, 1);
1481 console_unlock();
1482 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001483 return 0;
1484}
1485
Alex Deucher0c195112012-07-17 14:02:33 -04001486/**
1487 * radeon_resume_kms - initiate device resume
1488 *
1489 * @pdev: drm dev pointer
1490 *
1491 * Bring the hw back to operating state (all asics).
1492 * Returns 0 for success or an error on failure.
1493 * Called at driver resume.
1494 */
Dave Airlie10ebc0b2012-09-17 14:40:31 +10001495int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001496{
Cedric Godin09bdf592010-06-11 14:40:56 -04001497 struct drm_connector *connector;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001498 struct radeon_device *rdev = dev->dev_private;
Christian König04eb2202012-07-07 12:47:58 +02001499 int r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001500
Dave Airlie5bcf7192010-12-07 09:20:40 +10001501 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10001502 return 0;
1503
Dave Airlie10ebc0b2012-09-17 14:40:31 +10001504 if (fbcon) {
1505 console_lock();
1506 }
Dave Airlie7473e832012-09-13 12:02:30 +10001507 if (resume) {
1508 pci_set_power_state(dev->pdev, PCI_D0);
1509 pci_restore_state(dev->pdev);
1510 if (pci_enable_device(dev->pdev)) {
Dave Airlie10ebc0b2012-09-17 14:40:31 +10001511 if (fbcon)
1512 console_unlock();
Dave Airlie7473e832012-09-13 12:02:30 +10001513 return -1;
1514 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001515 }
Dave Airlie0ebf1712009-11-05 15:39:10 +10001516 /* resume AGP if in use */
1517 radeon_agp_resume(rdev);
Jerome Glisse62a8ea32009-10-01 18:02:11 +02001518 radeon_resume(rdev);
Christian König04eb2202012-07-07 12:47:58 +02001519
1520 r = radeon_ib_ring_tests(rdev);
1521 if (r)
1522 DRM_ERROR("ib ring test failed (%d).\n", r);
1523
Alex Deucherbc6a6292014-02-25 12:01:28 -05001524 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
Alex Deucher6c7bcce2013-12-18 14:07:14 -05001525 /* do dpm late init */
1526 r = radeon_pm_late_init(rdev);
1527 if (r) {
1528 rdev->pm.dpm_enabled = false;
1529 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1530 }
Alex Deucherbc6a6292014-02-25 12:01:28 -05001531 } else {
1532 /* resume old pm late */
1533 radeon_pm_resume(rdev);
Alex Deucher6c7bcce2013-12-18 14:07:14 -05001534 }
1535
Yang Zhaof657c2a2009-09-15 12:21:01 +10001536 radeon_restore_bios_scratch_regs(rdev);
Cedric Godin09bdf592010-06-11 14:40:56 -04001537
Dave Airlie10ebc0b2012-09-17 14:40:31 +10001538 if (fbcon) {
1539 radeon_fbdev_set_suspend(rdev, 0);
1540 console_unlock();
1541 }
Alex Deucher6c7bcce2013-12-18 14:07:14 -05001542
Alex Deucher3fa47d92012-01-20 14:56:39 -05001543 /* init dig PHYs, disp eng pll */
1544 if (rdev->is_atom_bios) {
Alex Deucherac89af12011-05-22 13:20:36 -04001545 radeon_atom_encoder_init(rdev);
Alex Deucherf3f1f032012-03-20 17:18:04 -04001546 radeon_atom_disp_eng_pll_init(rdev);
Alex Deucherbced76f2012-09-14 09:45:50 -04001547 /* turn on the BL */
1548 if (rdev->mode_info.bl_encoder) {
1549 u8 bl_level = radeon_get_backlight_level(rdev,
1550 rdev->mode_info.bl_encoder);
1551 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1552 bl_level);
1553 }
Alex Deucher3fa47d92012-01-20 14:56:39 -05001554 }
Alex Deucherd4877cf2009-12-04 16:56:37 -05001555 /* reset hpd state */
1556 radeon_hpd_init(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001557 /* blat the mode back in */
1558 drm_helper_resume_force_mode(dev);
Alex Deuchera93f3442010-12-20 11:22:29 -05001559 /* turn on display hw */
1560 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1561 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1562 }
Seth Forshee86698c22012-01-31 19:06:25 -06001563
1564 drm_kms_helper_poll_enable(dev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001565 return 0;
1566}
1567
Alex Deucher0c195112012-07-17 14:02:33 -04001568/**
1569 * radeon_gpu_reset - reset the asic
1570 *
1571 * @rdev: radeon device pointer
1572 *
1573 * Attempt the reset the GPU if it has hung (all asics).
1574 * Returns 0 for success or an error on failure.
1575 */
Jerome Glisse90aca4d2010-03-09 14:45:12 +00001576int radeon_gpu_reset(struct radeon_device *rdev)
1577{
Christian König55d7c222012-07-09 11:52:44 +02001578 unsigned ring_sizes[RADEON_NUM_RINGS];
1579 uint32_t *ring_data[RADEON_NUM_RINGS];
1580
1581 bool saved = false;
1582
1583 int i, r;
Dave Airlie8fd1b842011-02-10 14:46:06 +10001584 int resched;
Jerome Glisse90aca4d2010-03-09 14:45:12 +00001585
Jerome Glissedee53e72012-07-02 12:45:19 -04001586 down_write(&rdev->exclusive_lock);
Christian Königf9eaf9a2013-10-29 20:14:47 +01001587
1588 if (!rdev->needs_reset) {
1589 up_write(&rdev->exclusive_lock);
1590 return 0;
1591 }
1592
1593 rdev->needs_reset = false;
1594
Jerome Glisse90aca4d2010-03-09 14:45:12 +00001595 radeon_save_bios_scratch_regs(rdev);
Dave Airlie8fd1b842011-02-10 14:46:06 +10001596 /* block TTM */
1597 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
Alex Deucher95f59502013-07-31 09:16:42 -04001598 radeon_pm_suspend(rdev);
Jerome Glisse90aca4d2010-03-09 14:45:12 +00001599 radeon_suspend(rdev);
1600
Christian König55d7c222012-07-09 11:52:44 +02001601 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1602 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1603 &ring_data[i]);
1604 if (ring_sizes[i]) {
1605 saved = true;
1606 dev_info(rdev->dev, "Saved %d dwords of commands "
1607 "on ring %d.\n", ring_sizes[i], i);
1608 }
Jerome Glisse90aca4d2010-03-09 14:45:12 +00001609 }
Michel Dänzer7a1619b2011-11-10 18:57:26 +01001610
Christian König55d7c222012-07-09 11:52:44 +02001611retry:
1612 r = radeon_asic_reset(rdev);
1613 if (!r) {
1614 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1615 radeon_resume(rdev);
1616 }
1617
1618 radeon_restore_bios_scratch_regs(rdev);
Christian König55d7c222012-07-09 11:52:44 +02001619
1620 if (!r) {
1621 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1622 radeon_ring_restore(rdev, &rdev->ring[i],
1623 ring_sizes[i], ring_data[i]);
Christian Königf54b3502012-08-29 13:24:15 +02001624 ring_sizes[i] = 0;
1625 ring_data[i] = NULL;
Christian König55d7c222012-07-09 11:52:44 +02001626 }
1627
1628 r = radeon_ib_ring_tests(rdev);
1629 if (r) {
1630 dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
1631 if (saved) {
Christian Königf54b3502012-08-29 13:24:15 +02001632 saved = false;
Christian König55d7c222012-07-09 11:52:44 +02001633 radeon_suspend(rdev);
1634 goto retry;
1635 }
1636 }
1637 } else {
Jerome Glisse76903b92012-12-17 10:29:06 -05001638 radeon_fence_driver_force_completion(rdev);
Christian König55d7c222012-07-09 11:52:44 +02001639 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1640 kfree(ring_data[i]);
1641 }
1642 }
1643
Alex Deucher95f59502013-07-31 09:16:42 -04001644 radeon_pm_resume(rdev);
Jerome Glissed3493572012-12-14 16:20:46 -05001645 drm_helper_resume_force_mode(rdev->ddev);
1646
Christian König55d7c222012-07-09 11:52:44 +02001647 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
Michel Dänzer7a1619b2011-11-10 18:57:26 +01001648 if (r) {
1649 /* bad news, how to tell it to userspace ? */
1650 dev_info(rdev->dev, "GPU reset failed\n");
1651 }
1652
Jerome Glissedee53e72012-07-02 12:45:19 -04001653 up_write(&rdev->exclusive_lock);
Jerome Glisse90aca4d2010-03-09 14:45:12 +00001654 return r;
1655}
1656
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001657
1658/*
1659 * Debugfs
1660 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001661int radeon_debugfs_add_files(struct radeon_device *rdev,
1662 struct drm_info_list *files,
1663 unsigned nfiles)
1664{
1665 unsigned i;
1666
Christian König4d8bf9a2011-10-24 14:54:54 +02001667 for (i = 0; i < rdev->debugfs_count; i++) {
1668 if (rdev->debugfs[i].files == files) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001669 /* Already registered */
1670 return 0;
1671 }
1672 }
Michael Wittenc245cb92011-09-16 20:45:30 +00001673
Christian König4d8bf9a2011-10-24 14:54:54 +02001674 i = rdev->debugfs_count + 1;
Michael Wittenc245cb92011-09-16 20:45:30 +00001675 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1676 DRM_ERROR("Reached maximum number of debugfs components.\n");
1677 DRM_ERROR("Report so we increase "
1678 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001679 return -EINVAL;
1680 }
Christian König4d8bf9a2011-10-24 14:54:54 +02001681 rdev->debugfs[rdev->debugfs_count].files = files;
1682 rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1683 rdev->debugfs_count = i;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001684#if defined(CONFIG_DEBUG_FS)
1685 drm_debugfs_create_files(files, nfiles,
1686 rdev->ddev->control->debugfs_root,
1687 rdev->ddev->control);
1688 drm_debugfs_create_files(files, nfiles,
1689 rdev->ddev->primary->debugfs_root,
1690 rdev->ddev->primary);
1691#endif
1692 return 0;
1693}
1694
Christian König4d8bf9a2011-10-24 14:54:54 +02001695static void radeon_debugfs_remove_files(struct radeon_device *rdev)
1696{
1697#if defined(CONFIG_DEBUG_FS)
1698 unsigned i;
1699
1700 for (i = 0; i < rdev->debugfs_count; i++) {
1701 drm_debugfs_remove_files(rdev->debugfs[i].files,
1702 rdev->debugfs[i].num_files,
1703 rdev->ddev->control);
1704 drm_debugfs_remove_files(rdev->debugfs[i].files,
1705 rdev->debugfs[i].num_files,
1706 rdev->ddev->primary);
1707 }
1708#endif
1709}
1710
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001711#if defined(CONFIG_DEBUG_FS)
1712int radeon_debugfs_init(struct drm_minor *minor)
1713{
1714 return 0;
1715}
1716
1717void radeon_debugfs_cleanup(struct drm_minor *minor)
1718{
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001719}
1720#endif