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Alexander Shiyan161b96c2012-11-07 21:30:29 +04001/*
2 * CLPS711X SPI bus driver
3 *
Alexander Shiyan98984792014-01-10 17:02:05 +04004 * Copyright (C) 2012-2014 Alexander Shiyan <shc_work@mail.ru>
Alexander Shiyan161b96c2012-11-07 21:30:29 +04005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/io.h>
13#include <linux/clk.h>
Alexander Shiyan161b96c2012-11-07 21:30:29 +040014#include <linux/gpio.h>
15#include <linux/delay.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
Alexander Shiyan3dc92592014-03-22 10:57:35 +040019#include <linux/regmap.h>
20#include <linux/mfd/syscon.h>
21#include <linux/mfd/syscon/clps711x.h>
Alexander Shiyan161b96c2012-11-07 21:30:29 +040022#include <linux/spi/spi.h>
23#include <linux/platform_data/spi-clps711x.h>
24
Alexander Shiyan161b96c2012-11-07 21:30:29 +040025#define DRIVER_NAME "spi-clps711x"
26
Alexander Shiyan3dc92592014-03-22 10:57:35 +040027#define SYNCIO_FRMLEN(x) ((x) << 8)
28#define SYNCIO_TXFRMEN (1 << 14)
29
Alexander Shiyan161b96c2012-11-07 21:30:29 +040030struct spi_clps711x_data {
Alexander Shiyan3dc92592014-03-22 10:57:35 +040031 void __iomem *syncio;
32 struct regmap *syscon;
33 struct regmap *syscon1;
Alexander Shiyan161b96c2012-11-07 21:30:29 +040034 struct clk *spi_clk;
Alexander Shiyan161b96c2012-11-07 21:30:29 +040035
36 u8 *tx_buf;
37 u8 *rx_buf;
Alexander Shiyan8dda9d92014-02-02 10:59:49 +040038 unsigned int bpw;
Alexander Shiyan161b96c2012-11-07 21:30:29 +040039 int len;
Alexander Shiyan161b96c2012-11-07 21:30:29 +040040};
41
42static int spi_clps711x_setup(struct spi_device *spi)
43{
Alexander Shiyan161b96c2012-11-07 21:30:29 +040044 /* We are expect that SPI-device is not selected */
Alexander Shiyan3e9ea4b2014-02-02 10:59:50 +040045 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
Alexander Shiyan161b96c2012-11-07 21:30:29 +040046
47 return 0;
48}
49
Alexander Shiyan8dda9d92014-02-02 10:59:49 +040050static void spi_clps711x_setup_xfer(struct spi_device *spi,
51 struct spi_transfer *xfer)
Alexander Shiyan161b96c2012-11-07 21:30:29 +040052{
Axel Lin6f50c6bc2014-03-26 23:44:18 +080053 struct spi_master *master = spi->master;
54 struct spi_clps711x_data *hw = spi_master_get_devdata(master);
Alexander Shiyan161b96c2012-11-07 21:30:29 +040055
Alexander Shiyan161b96c2012-11-07 21:30:29 +040056 /* Setup SPI frequency divider */
Axel Lin6f50c6bc2014-03-26 23:44:18 +080057 if (xfer->speed_hz >= master->max_speed_hz)
Alexander Shiyan3dc92592014-03-22 10:57:35 +040058 regmap_update_bits(hw->syscon1, SYSCON_OFFSET,
59 SYSCON1_ADCKSEL_MASK, SYSCON1_ADCKSEL(3));
Axel Lin6f50c6bc2014-03-26 23:44:18 +080060 else if (xfer->speed_hz >= (master->max_speed_hz / 2))
Alexander Shiyan3dc92592014-03-22 10:57:35 +040061 regmap_update_bits(hw->syscon1, SYSCON_OFFSET,
62 SYSCON1_ADCKSEL_MASK, SYSCON1_ADCKSEL(2));
Axel Lin6f50c6bc2014-03-26 23:44:18 +080063 else if (xfer->speed_hz >= (master->max_speed_hz / 8))
Alexander Shiyan3dc92592014-03-22 10:57:35 +040064 regmap_update_bits(hw->syscon1, SYSCON_OFFSET,
65 SYSCON1_ADCKSEL_MASK, SYSCON1_ADCKSEL(1));
Alexander Shiyan161b96c2012-11-07 21:30:29 +040066 else
Alexander Shiyan3dc92592014-03-22 10:57:35 +040067 regmap_update_bits(hw->syscon1, SYSCON_OFFSET,
68 SYSCON1_ADCKSEL_MASK, SYSCON1_ADCKSEL(0));
Alexander Shiyan161b96c2012-11-07 21:30:29 +040069}
70
Axel Linbf5c2e22014-02-18 17:15:54 +080071static int spi_clps711x_prepare_message(struct spi_master *master,
72 struct spi_message *msg)
Alexander Shiyan161b96c2012-11-07 21:30:29 +040073{
Alexander Shiyan3dc92592014-03-22 10:57:35 +040074 struct spi_clps711x_data *hw = spi_master_get_devdata(master);
Alexander Shiyan8dda9d92014-02-02 10:59:49 +040075 struct spi_device *spi = msg->spi;
Alexander Shiyan161b96c2012-11-07 21:30:29 +040076
Alexander Shiyan3dc92592014-03-22 10:57:35 +040077 /* Setup mode for transfer */
78 return regmap_update_bits(hw->syscon, SYSCON_OFFSET, SYSCON3_ADCCKNSEN,
79 (spi->mode & SPI_CPHA) ?
80 SYSCON3_ADCCKNSEN : 0);
Alexander Shiyan161b96c2012-11-07 21:30:29 +040081}
82
Axel Linbf5c2e22014-02-18 17:15:54 +080083static int spi_clps711x_transfer_one(struct spi_master *master,
84 struct spi_device *spi,
85 struct spi_transfer *xfer)
86{
87 struct spi_clps711x_data *hw = spi_master_get_devdata(master);
88 u8 data;
89
90 spi_clps711x_setup_xfer(spi, xfer);
91
92 hw->len = xfer->len;
Axel Linbed890b2014-03-02 23:24:18 +080093 hw->bpw = xfer->bits_per_word;
Axel Linbf5c2e22014-02-18 17:15:54 +080094 hw->tx_buf = (u8 *)xfer->tx_buf;
95 hw->rx_buf = (u8 *)xfer->rx_buf;
96
97 /* Initiate transfer */
98 data = hw->tx_buf ? *hw->tx_buf++ : 0;
Alexander Shiyan3dc92592014-03-22 10:57:35 +040099 writel(data | SYNCIO_FRMLEN(hw->bpw) | SYNCIO_TXFRMEN, hw->syncio);
100
Axel Linbf5c2e22014-02-18 17:15:54 +0800101 return 1;
102}
103
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400104static irqreturn_t spi_clps711x_isr(int irq, void *dev_id)
105{
Axel Linbf5c2e22014-02-18 17:15:54 +0800106 struct spi_master *master = dev_id;
107 struct spi_clps711x_data *hw = spi_master_get_devdata(master);
Alexander Shiyanc7a26f12014-02-02 10:59:48 +0400108 u8 data;
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400109
110 /* Handle RX */
Alexander Shiyan3dc92592014-03-22 10:57:35 +0400111 data = readb(hw->syncio);
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400112 if (hw->rx_buf)
Alexander Shiyanc7a26f12014-02-02 10:59:48 +0400113 *hw->rx_buf++ = data;
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400114
115 /* Handle TX */
Alexander Shiyanc7a26f12014-02-02 10:59:48 +0400116 if (--hw->len > 0) {
117 data = hw->tx_buf ? *hw->tx_buf++ : 0;
Alexander Shiyan3dc92592014-03-22 10:57:35 +0400118 writel(data | SYNCIO_FRMLEN(hw->bpw) | SYNCIO_TXFRMEN,
119 hw->syncio);
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400120 } else
Axel Linbf5c2e22014-02-18 17:15:54 +0800121 spi_finalize_current_transfer(master);
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400122
123 return IRQ_HANDLED;
124}
125
Grant Likelyfd4a3192012-12-07 16:57:14 +0000126static int spi_clps711x_probe(struct platform_device *pdev)
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400127{
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400128 struct spi_clps711x_data *hw;
129 struct spi_clps711x_pdata *pdata = dev_get_platdata(&pdev->dev);
Alexander Shiyan3dc92592014-03-22 10:57:35 +0400130 struct spi_master *master;
131 struct resource *res;
132 int i, irq, ret;
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400133
134 if (!pdata) {
135 dev_err(&pdev->dev, "No platform data supplied\n");
136 return -EINVAL;
137 }
138
139 if (pdata->num_chipselect < 1) {
140 dev_err(&pdev->dev, "At least one CS must be defined\n");
141 return -EINVAL;
142 }
143
Alexander Shiyan3dc92592014-03-22 10:57:35 +0400144 irq = platform_get_irq(pdev, 0);
145 if (irq < 0)
146 return irq;
147
Alexander Shiyan3e9ea4b2014-02-02 10:59:50 +0400148 master = spi_alloc_master(&pdev->dev, sizeof(*hw));
149 if (!master)
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400150 return -ENOMEM;
Alexander Shiyan3e9ea4b2014-02-02 10:59:50 +0400151
152 master->cs_gpios = devm_kzalloc(&pdev->dev, sizeof(int) *
153 pdata->num_chipselect, GFP_KERNEL);
154 if (!master->cs_gpios) {
155 ret = -ENOMEM;
156 goto err_out;
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400157 }
158
159 master->bus_num = pdev->id;
160 master->mode_bits = SPI_CPHA | SPI_CS_HIGH;
Alexander Shiyan8dda9d92014-02-02 10:59:49 +0400161 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 8);
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400162 master->num_chipselect = pdata->num_chipselect;
163 master->setup = spi_clps711x_setup;
Axel Linbf5c2e22014-02-18 17:15:54 +0800164 master->prepare_message = spi_clps711x_prepare_message;
165 master->transfer_one = spi_clps711x_transfer_one;
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400166
167 hw = spi_master_get_devdata(master);
168
169 for (i = 0; i < master->num_chipselect; i++) {
Alexander Shiyan3e9ea4b2014-02-02 10:59:50 +0400170 master->cs_gpios[i] = pdata->chipselect[i];
Axel Linfcba2122014-03-04 12:59:53 +0800171 ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i],
172 DRIVER_NAME);
173 if (ret) {
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400174 dev_err(&pdev->dev, "Can't get CS GPIO %i\n", i);
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400175 goto err_out;
176 }
177 }
178
179 hw->spi_clk = devm_clk_get(&pdev->dev, "spi");
180 if (IS_ERR(hw->spi_clk)) {
181 dev_err(&pdev->dev, "Can't get clocks\n");
182 ret = PTR_ERR(hw->spi_clk);
183 goto err_out;
184 }
Axel Lin6f50c6bc2014-03-26 23:44:18 +0800185 master->max_speed_hz = clk_get_rate(hw->spi_clk);
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400186
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400187 platform_set_drvdata(pdev, master);
188
Alexander Shiyan3dc92592014-03-22 10:57:35 +0400189 hw->syscon = syscon_regmap_lookup_by_pdevname("syscon.3");
190 if (IS_ERR(hw->syscon)) {
191 ret = PTR_ERR(hw->syscon);
Sachin Kamatc7083792013-09-27 15:32:53 +0530192 goto err_out;
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400193 }
194
Alexander Shiyan3dc92592014-03-22 10:57:35 +0400195 hw->syscon1 = syscon_regmap_lookup_by_pdevname("syscon.1");
196 if (IS_ERR(hw->syscon1)) {
197 ret = PTR_ERR(hw->syscon1);
198 goto err_out;
199 }
200
201 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
202 hw->syncio = devm_ioremap_resource(&pdev->dev, res);
203 if (IS_ERR(hw->syncio)) {
204 ret = PTR_ERR(hw->syncio);
205 goto err_out;
206 }
207
208 /* Disable extended mode due hardware problems */
209 regmap_update_bits(hw->syscon, SYSCON_OFFSET, SYSCON3_ADCCON, 0);
210
211 /* Clear possible pending interrupt */
212 readl(hw->syncio);
213
214 ret = devm_request_irq(&pdev->dev, irq, spi_clps711x_isr, 0,
215 dev_name(&pdev->dev), master);
216 if (ret)
217 goto err_out;
218
Jingoo Hanc493fc42013-09-24 13:27:48 +0900219 ret = devm_spi_register_master(&pdev->dev, master);
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400220 if (!ret) {
221 dev_info(&pdev->dev,
222 "SPI bus driver initialized. Master clock %u Hz\n",
Axel Lin6f50c6bc2014-03-26 23:44:18 +0800223 master->max_speed_hz);
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400224 return 0;
225 }
226
227 dev_err(&pdev->dev, "Failed to register master\n");
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400228
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400229err_out:
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400230 spi_master_put(master);
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400231
232 return ret;
233}
234
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400235static struct platform_driver clps711x_spi_driver = {
236 .driver = {
237 .name = DRIVER_NAME,
238 .owner = THIS_MODULE,
239 },
240 .probe = spi_clps711x_probe,
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400241};
242module_platform_driver(clps711x_spi_driver);
243
244MODULE_LICENSE("GPL");
245MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
246MODULE_DESCRIPTION("CLPS711X SPI bus driver");
Axel Lin350a9b32014-01-14 17:01:54 +0800247MODULE_ALIAS("platform:" DRIVER_NAME);