blob: 6b157eeabcc5c9b07009c4d91a291122b3732887 [file] [log] [blame]
Bryan Wud7df69f2013-01-02 15:53:51 -08001/dts-v1/;
2
Stephen Warren1bd0bd42012-10-17 16:38:21 -06003#include "tegra30.dtsi"
Bryan Wud7df69f2013-01-02 15:53:51 -08004
5/ {
6 model = "NVIDIA Tegra30 Beaver evaluation board";
7 compatible = "nvidia,beaver", "nvidia,tegra30";
8
Stephen Warren553c0a22013-12-09 14:43:59 -07009 aliases {
10 rtc0 = "/i2c@7000d000/tps65911@2d";
11 rtc1 = "/rtc@7000e000";
Olof Johanssonc4574aa2014-11-11 12:49:30 -080012 serial0 = &uarta;
Stephen Warren553c0a22013-12-09 14:43:59 -070013 };
14
Bryan Wud7df69f2013-01-02 15:53:51 -080015 memory {
Stephen Warren30022bb2013-05-13 09:47:31 +000016 reg = <0x80000000 0x7ff00000>;
Bryan Wud7df69f2013-01-02 15:53:51 -080017 };
18
Stephen Warren58ecb232013-11-25 17:53:16 -070019 pcie-controller@00003000 {
Thierry Redingbb034cb2013-08-09 16:49:28 +020020 status = "okay";
Thierry Redingcca86142014-05-28 16:49:12 +020021
22 avdd-pexa-supply = <&ldo1_reg>;
23 vdd-pexa-supply = <&ldo1_reg>;
24 avdd-pexb-supply = <&ldo1_reg>;
25 vdd-pexb-supply = <&ldo1_reg>;
26 avdd-pex-pll-supply = <&ldo1_reg>;
27 avdd-plle-supply = <&ldo1_reg>;
28 vddio-pex-ctl-supply = <&sys_3v3_reg>;
29 hvdd-pex-supply = <&sys_3v3_pexs_reg>;
30
Thierry Redingbb034cb2013-08-09 16:49:28 +020031 pci@1,0 {
32 status = "okay";
Stephen Warren44fefab2013-08-09 16:49:29 +020033 nvidia,num-lanes = <2>;
Thierry Redingbb034cb2013-08-09 16:49:28 +020034 };
35
36 pci@2,0 {
Stephen Warren44fefab2013-08-09 16:49:29 +020037 nvidia,num-lanes = <2>;
Thierry Redingbb034cb2013-08-09 16:49:28 +020038 };
39
40 pci@3,0 {
Stephen Warren44fefab2013-08-09 16:49:29 +020041 status = "okay";
42 nvidia,num-lanes = <2>;
Thierry Redingbb034cb2013-08-09 16:49:28 +020043 };
44 };
45
Stephen Warren58ecb232013-11-25 17:53:16 -070046 host1x@50000000 {
47 hdmi@54280000 {
Thierry Reding9bd80b42013-08-12 17:49:03 +020048 status = "okay";
49
Thierry Reding597eb8e2014-04-25 17:44:49 +020050 hdmi-supply = <&vdd_5v0_hdmi>;
Thierry Reding9bd80b42013-08-12 17:49:03 +020051 vdd-supply = <&sys_3v3_reg>;
52 pll-supply = <&vio_reg>;
53
54 nvidia,hpd-gpio =
55 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
56 nvidia,ddc-i2c-bus = <&hdmiddc>;
57 };
58 };
59
Stephen Warren58ecb232013-11-25 17:53:16 -070060 pinmux@70000868 {
Bryan Wud7df69f2013-01-02 15:53:51 -080061 pinctrl-names = "default";
62 pinctrl-0 = <&state_default>;
63
64 state_default: pinmux {
65 sdmmc1_clk_pz0 {
66 nvidia,pins = "sdmmc1_clk_pz0";
67 nvidia,function = "sdmmc1";
Laxman Dewangana47c6622013-12-05 16:14:09 +053068 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
69 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -080070 };
71 sdmmc1_cmd_pz1 {
72 nvidia,pins = "sdmmc1_cmd_pz1",
73 "sdmmc1_dat0_py7",
74 "sdmmc1_dat1_py6",
75 "sdmmc1_dat2_py5",
76 "sdmmc1_dat3_py4";
77 nvidia,function = "sdmmc1";
Laxman Dewangana47c6622013-12-05 16:14:09 +053078 nvidia,pull = <TEGRA_PIN_PULL_UP>;
79 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -080080 };
81 sdmmc3_clk_pa6 {
82 nvidia,pins = "sdmmc3_clk_pa6";
83 nvidia,function = "sdmmc3";
Laxman Dewangana47c6622013-12-05 16:14:09 +053084 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
85 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -080086 };
87 sdmmc3_cmd_pa7 {
88 nvidia,pins = "sdmmc3_cmd_pa7",
89 "sdmmc3_dat0_pb7",
90 "sdmmc3_dat1_pb6",
91 "sdmmc3_dat2_pb5",
92 "sdmmc3_dat3_pb4";
93 nvidia,function = "sdmmc3";
Laxman Dewangana47c6622013-12-05 16:14:09 +053094 nvidia,pull = <TEGRA_PIN_PULL_UP>;
95 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -080096 };
97 sdmmc4_clk_pcc4 {
98 nvidia,pins = "sdmmc4_clk_pcc4",
99 "sdmmc4_rst_n_pcc3";
100 nvidia,function = "sdmmc4";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530101 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
102 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800103 };
104 sdmmc4_dat0_paa0 {
105 nvidia,pins = "sdmmc4_dat0_paa0",
106 "sdmmc4_dat1_paa1",
107 "sdmmc4_dat2_paa2",
108 "sdmmc4_dat3_paa3",
109 "sdmmc4_dat4_paa4",
110 "sdmmc4_dat5_paa5",
111 "sdmmc4_dat6_paa6",
112 "sdmmc4_dat7_paa7";
113 nvidia,function = "sdmmc4";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530114 nvidia,pull = <TEGRA_PIN_PULL_UP>;
115 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800116 };
117 dap2_fs_pa2 {
118 nvidia,pins = "dap2_fs_pa2",
119 "dap2_sclk_pa3",
120 "dap2_din_pa4",
121 "dap2_dout_pa5";
122 nvidia,function = "i2s1";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530123 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
124 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800125 };
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300126 pex_l1_prsnt_n_pdd4 {
127 nvidia,pins = "pex_l1_prsnt_n_pdd4",
128 "pex_l1_clkreq_n_pdd6";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530129 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300130 };
Bryan Wud7df69f2013-01-02 15:53:51 -0800131 sdio3 {
132 nvidia,pins = "drive_sdio3";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530133 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
134 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800135 nvidia,pull-down-strength = <46>;
136 nvidia,pull-up-strength = <42>;
137 nvidia,slew-rate-rising = <1>;
138 nvidia,slew-rate-falling = <1>;
139 };
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300140 gpv {
141 nvidia,pins = "drive_gpv";
142 nvidia,pull-up-strength = <16>;
143 };
Bryan Wud7df69f2013-01-02 15:53:51 -0800144 };
145 };
146
147 serial@70006000 {
148 status = "okay";
Bryan Wud7df69f2013-01-02 15:53:51 -0800149 };
150
151 i2c@7000c000 {
152 status = "okay";
153 clock-frequency = <100000>;
154 };
155
156 i2c@7000c400 {
157 status = "okay";
158 clock-frequency = <100000>;
159 };
160
161 i2c@7000c500 {
162 status = "okay";
163 clock-frequency = <100000>;
164 };
165
Thierry Reding9bd80b42013-08-12 17:49:03 +0200166 hdmiddc: i2c@7000c700 {
Bryan Wud7df69f2013-01-02 15:53:51 -0800167 status = "okay";
168 clock-frequency = <100000>;
169 };
170
171 i2c@7000d000 {
172 status = "okay";
173 clock-frequency = <100000>;
174
Stephen Warren58ecb232013-11-25 17:53:16 -0700175 rt5640: rt5640@1c {
Stephen Warren23037bb2013-03-27 16:53:20 -0600176 compatible = "realtek,rt5640";
177 reg = <0x1c>;
178 interrupt-parent = <&gpio>;
179 interrupts = <TEGRA_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
180 realtek,ldo1-en-gpios =
181 <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>;
182 };
183
Bryan Wud7df69f2013-01-02 15:53:51 -0800184 pmic: tps65911@2d {
185 compatible = "ti,tps65911";
186 reg = <0x2d>;
187
Stephen Warren6cecf912013-02-13 12:51:51 -0700188 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800189 #interrupt-cells = <2>;
190 interrupt-controller;
191
192 ti,system-power-controller;
193
194 #gpio-cells = <2>;
195 gpio-controller;
196
197 vcc1-supply = <&vdd_5v_in_reg>;
198 vcc2-supply = <&vdd_5v_in_reg>;
199 vcc3-supply = <&vio_reg>;
200 vcc4-supply = <&vdd_5v_in_reg>;
201 vcc5-supply = <&vdd_5v_in_reg>;
202 vcc6-supply = <&vdd2_reg>;
203 vcc7-supply = <&vdd_5v_in_reg>;
204 vccio-supply = <&vdd_5v_in_reg>;
205
206 regulators {
207 #address-cells = <1>;
208 #size-cells = <0>;
209
210 vdd1_reg: vdd1 {
211 regulator-name = "vddio_ddr_1v2";
212 regulator-min-microvolt = <1200000>;
213 regulator-max-microvolt = <1200000>;
214 regulator-always-on;
215 };
216
217 vdd2_reg: vdd2 {
218 regulator-name = "vdd_1v5_gen";
219 regulator-min-microvolt = <1500000>;
220 regulator-max-microvolt = <1500000>;
221 regulator-always-on;
222 };
223
224 vddctrl_reg: vddctrl {
225 regulator-name = "vdd_cpu,vdd_sys";
226 regulator-min-microvolt = <1000000>;
227 regulator-max-microvolt = <1000000>;
228 regulator-always-on;
229 };
230
231 vio_reg: vio {
232 regulator-name = "vdd_1v8_gen";
233 regulator-min-microvolt = <1800000>;
234 regulator-max-microvolt = <1800000>;
235 regulator-always-on;
236 };
237
238 ldo1_reg: ldo1 {
239 regulator-name = "vdd_pexa,vdd_pexb";
240 regulator-min-microvolt = <1050000>;
241 regulator-max-microvolt = <1050000>;
242 };
243
244 ldo2_reg: ldo2 {
245 regulator-name = "vdd_sata,avdd_plle";
246 regulator-min-microvolt = <1050000>;
247 regulator-max-microvolt = <1050000>;
248 };
249
250 /* LDO3 is not connected to anything */
251
252 ldo4_reg: ldo4 {
253 regulator-name = "vdd_rtc";
254 regulator-min-microvolt = <1200000>;
255 regulator-max-microvolt = <1200000>;
256 regulator-always-on;
257 };
258
259 ldo5_reg: ldo5 {
260 regulator-name = "vddio_sdmmc,avdd_vdac";
261 regulator-min-microvolt = <3300000>;
262 regulator-max-microvolt = <3300000>;
263 regulator-always-on;
264 };
265
266 ldo6_reg: ldo6 {
267 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
268 regulator-min-microvolt = <1200000>;
269 regulator-max-microvolt = <1200000>;
270 };
271
272 ldo7_reg: ldo7 {
273 regulator-name = "vdd_pllm,x,u,a_p_c_s";
274 regulator-min-microvolt = <1200000>;
275 regulator-max-microvolt = <1200000>;
276 regulator-always-on;
277 };
278
279 ldo8_reg: ldo8 {
280 regulator-name = "vdd_ddr_hs";
281 regulator-min-microvolt = <1000000>;
282 regulator-max-microvolt = <1000000>;
283 regulator-always-on;
284 };
285 };
286 };
Stephen Warren57899052013-11-26 14:43:45 -0700287
288 tps62361@60 {
289 compatible = "ti,tps62361";
290 reg = <0x60>;
291
292 regulator-name = "tps62361-vout";
293 regulator-min-microvolt = <500000>;
294 regulator-max-microvolt = <1500000>;
295 regulator-boot-on;
296 regulator-always-on;
297 ti,vsel0-state-high;
298 ti,vsel1-state-high;
299 };
Bryan Wud7df69f2013-01-02 15:53:51 -0800300 };
301
302 spi@7000da00 {
303 status = "okay";
304 spi-max-frequency = <25000000>;
305 spi-flash@1 {
306 compatible = "winbond,w25q32";
307 reg = <1>;
308 spi-max-frequency = <20000000>;
309 };
310 };
311
Stephen Warren58ecb232013-11-25 17:53:16 -0700312 pmc@7000e400 {
Bryan Wud7df69f2013-01-02 15:53:51 -0800313 status = "okay";
314 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800315 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800316 nvidia,cpu-pwr-good-time = <2000>;
317 nvidia,cpu-pwr-off-time = <200>;
318 nvidia,core-pwr-good-time = <3845 3845>;
319 nvidia,core-pwr-off-time = <0>;
320 nvidia,core-power-req-active-high;
321 nvidia,sys-clock-req-active-high;
Bryan Wud7df69f2013-01-02 15:53:51 -0800322 };
323
Stephen Warren57899052013-11-26 14:43:45 -0700324 ahub@70080000 {
325 i2s@70080400 {
326 status = "okay";
327 };
328 };
329
Bryan Wud7df69f2013-01-02 15:53:51 -0800330 sdhci@78000000 {
331 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700332 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
333 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
334 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800335 bus-width = <4>;
336 };
337
338 sdhci@78000600 {
339 status = "okay";
340 bus-width = <8>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600341 non-removable;
Bryan Wud7df69f2013-01-02 15:53:51 -0800342 };
343
Eric Brower4c696502013-12-19 18:08:53 -0800344 usb@7d004000 {
345 status = "okay";
346 };
347
348 phy2: usb-phy@7d004000 {
349 vbus-supply = <&sys_3v3_reg>;
350 status = "okay";
351 };
352
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300353 usb@7d008000 {
354 status = "okay";
355 };
356
357 usb-phy@7d008000 {
358 vbus-supply = <&usb3_vbus_reg>;
359 status = "okay";
360 };
361
Joseph Lo7021d122013-04-03 19:31:27 +0800362 clocks {
363 compatible = "simple-bus";
364 #address-cells = <1>;
365 #size-cells = <0>;
366
Stephen Warren58ecb232013-11-25 17:53:16 -0700367 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800368 compatible = "fixed-clock";
369 reg=<0>;
370 #clock-cells = <0>;
371 clock-frequency = <32768>;
372 };
373 };
374
Stephen Warren57899052013-11-26 14:43:45 -0700375 gpio-leds {
376 compatible = "gpio-leds";
377
378 gpled1 {
379 label = "LED1"; /* CR5A1 (blue) */
380 gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
381 };
382 gpled2 {
383 label = "LED2"; /* CR4A2 (green) */
384 gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
385 };
386 };
387
Bryan Wud7df69f2013-01-02 15:53:51 -0800388 regulators {
389 compatible = "simple-bus";
390 #address-cells = <1>;
391 #size-cells = <0>;
392
393 vdd_5v_in_reg: regulator@0 {
394 compatible = "regulator-fixed";
395 reg = <0>;
396 regulator-name = "vdd_5v_in";
397 regulator-min-microvolt = <5000000>;
398 regulator-max-microvolt = <5000000>;
399 regulator-always-on;
400 };
401
402 chargepump_5v_reg: regulator@1 {
403 compatible = "regulator-fixed";
404 reg = <1>;
405 regulator-name = "chargepump_5v";
406 regulator-min-microvolt = <5000000>;
407 regulator-max-microvolt = <5000000>;
408 regulator-boot-on;
409 regulator-always-on;
410 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700411 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800412 };
413
414 ddr_reg: regulator@2 {
415 compatible = "regulator-fixed";
416 reg = <2>;
417 regulator-name = "vdd_ddr";
418 regulator-min-microvolt = <1500000>;
419 regulator-max-microvolt = <1500000>;
420 regulator-always-on;
421 regulator-boot-on;
422 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700423 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800424 vin-supply = <&vdd_5v_in_reg>;
425 };
426
427 vdd_5v_sata_reg: regulator@3 {
428 compatible = "regulator-fixed";
429 reg = <3>;
430 regulator-name = "vdd_5v_sata";
431 regulator-min-microvolt = <5000000>;
432 regulator-max-microvolt = <5000000>;
433 regulator-always-on;
434 regulator-boot-on;
435 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700436 gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800437 vin-supply = <&vdd_5v_in_reg>;
438 };
439
440 usb1_vbus_reg: regulator@4 {
441 compatible = "regulator-fixed";
442 reg = <4>;
443 regulator-name = "usb1_vbus";
444 regulator-min-microvolt = <5000000>;
445 regulator-max-microvolt = <5000000>;
446 enable-active-high;
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300447 gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800448 gpio-open-drain;
449 vin-supply = <&vdd_5v_in_reg>;
450 };
451
452 usb3_vbus_reg: regulator@5 {
453 compatible = "regulator-fixed";
454 reg = <5>;
455 regulator-name = "usb3_vbus";
456 regulator-min-microvolt = <5000000>;
457 regulator-max-microvolt = <5000000>;
458 enable-active-high;
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300459 gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800460 gpio-open-drain;
461 vin-supply = <&vdd_5v_in_reg>;
462 };
463
464 sys_3v3_reg: regulator@6 {
465 compatible = "regulator-fixed";
466 reg = <6>;
467 regulator-name = "sys_3v3,vdd_3v3_alw";
468 regulator-min-microvolt = <3300000>;
469 regulator-max-microvolt = <3300000>;
470 regulator-always-on;
471 regulator-boot-on;
472 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700473 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800474 vin-supply = <&vdd_5v_in_reg>;
475 };
476
477 sys_3v3_pexs_reg: regulator@7 {
478 compatible = "regulator-fixed";
479 reg = <7>;
480 regulator-name = "sys_3v3_pexs";
481 regulator-min-microvolt = <3300000>;
482 regulator-max-microvolt = <3300000>;
483 regulator-always-on;
484 regulator-boot-on;
485 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700486 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800487 vin-supply = <&sys_3v3_reg>;
488 };
Thierry Reding597eb8e2014-04-25 17:44:49 +0200489
490 vdd_5v0_hdmi: regulator@8 {
491 compatible = "regulator-fixed";
492 reg = <8>;
493 regulator-name = "+VDD_5V_HDMI";
494 regulator-min-microvolt = <5000000>;
495 regulator-max-microvolt = <5000000>;
496 regulator-always-on;
497 regulator-boot-on;
498 vin-supply = <&sys_3v3_reg>;
499 };
Bryan Wud7df69f2013-01-02 15:53:51 -0800500 };
Eric Browerb4dd3e02013-05-10 14:40:29 +0000501
Stephen Warren23037bb2013-03-27 16:53:20 -0600502 sound {
503 compatible = "nvidia,tegra-audio-rt5640-beaver",
504 "nvidia,tegra-audio-rt5640";
505 nvidia,model = "NVIDIA Tegra Beaver";
506
507 nvidia,audio-routing =
508 "Headphones", "HPOR",
Stephen Warrenac472282013-08-14 13:54:24 -0600509 "Headphones", "HPOL",
510 "Mic Jack", "MICBIAS1",
511 "IN2P", "Mic Jack";
Stephen Warren23037bb2013-03-27 16:53:20 -0600512
513 nvidia,i2s-controller = <&tegra_i2s1>;
514 nvidia,audio-codec = <&rt5640>;
515
516 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
517
518 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
519 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
520 <&tegra_car TEGRA30_CLK_EXTERN1>;
521 clock-names = "pll_a", "pll_a_out0", "mclk";
522 };
Bryan Wud7df69f2013-01-02 15:53:51 -0800523};