blob: 9fe0a2c5a9bedf3898d4ab6e6a201615e3078246 [file] [log] [blame]
Vishal Verma5d0f6132013-03-04 18:40:58 -07001/*
2 * NVM Express device driver
Matthew Wilcox8757ad62014-04-11 10:37:39 -04003 * Copyright (c) 2011-2014, Intel Corporation.
Vishal Verma5d0f6132013-03-04 18:40:58 -07004 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
Vishal Verma5d0f6132013-03-04 18:40:58 -070013 */
14
15/*
16 * Refer to the SCSI-NVMe Translation spec for details on how
17 * each command is translated.
18 */
19
20#include <linux/nvme.h>
21#include <linux/bio.h>
22#include <linux/bitops.h>
23#include <linux/blkdev.h>
Keith Busch320a3822013-10-23 13:07:34 -060024#include <linux/compat.h>
Vishal Verma5d0f6132013-03-04 18:40:58 -070025#include <linux/delay.h>
26#include <linux/errno.h>
27#include <linux/fs.h>
28#include <linux/genhd.h>
29#include <linux/idr.h>
30#include <linux/init.h>
31#include <linux/interrupt.h>
32#include <linux/io.h>
33#include <linux/kdev_t.h>
34#include <linux/kthread.h>
35#include <linux/kernel.h>
36#include <linux/mm.h>
37#include <linux/module.h>
38#include <linux/moduleparam.h>
39#include <linux/pci.h>
40#include <linux/poison.h>
41#include <linux/sched.h>
42#include <linux/slab.h>
43#include <linux/types.h>
Christoph Hellwig37268972015-05-22 11:12:42 +020044#include <asm/unaligned.h>
Vishal Verma5d0f6132013-03-04 18:40:58 -070045#include <scsi/sg.h>
46#include <scsi/scsi.h>
47
48
49static int sg_version_num = 30534; /* 2 digits for each component */
50
Vishal Verma5d0f6132013-03-04 18:40:58 -070051/* VPD Page Codes */
52#define VPD_SUPPORTED_PAGES 0x00
53#define VPD_SERIAL_NUMBER 0x80
54#define VPD_DEVICE_IDENTIFIERS 0x83
55#define VPD_EXTENDED_INQUIRY 0x86
Keith Busch7f749d92015-04-07 15:34:18 -060056#define VPD_BLOCK_LIMITS 0xB0
Vishal Verma5d0f6132013-03-04 18:40:58 -070057#define VPD_BLOCK_DEV_CHARACTERISTICS 0xB1
58
Christoph Hellwig37268972015-05-22 11:12:42 +020059/* format unit paramter list offsets */
Vishal Verma5d0f6132013-03-04 18:40:58 -070060#define FORMAT_UNIT_SHORT_PARM_LIST_LEN 4
61#define FORMAT_UNIT_LONG_PARM_LIST_LEN 8
62#define FORMAT_UNIT_PROT_INT_OFFSET 3
63#define FORMAT_UNIT_PROT_FIELD_USAGE_OFFSET 0
64#define FORMAT_UNIT_PROT_FIELD_USAGE_MASK 0x07
65
66/* Misc. defines */
Vishal Verma5d0f6132013-03-04 18:40:58 -070067#define FIXED_SENSE_DATA 0x70
68#define DESC_FORMAT_SENSE_DATA 0x72
69#define FIXED_SENSE_DATA_ADD_LENGTH 10
70#define LUN_ENTRY_SIZE 8
71#define LUN_DATA_HEADER_SIZE 8
72#define ALL_LUNS_RETURNED 0x02
73#define ALL_WELL_KNOWN_LUNS_RETURNED 0x01
74#define RESTRICTED_LUNS_RETURNED 0x00
75#define NVME_POWER_STATE_START_VALID 0x00
76#define NVME_POWER_STATE_ACTIVE 0x01
77#define NVME_POWER_STATE_IDLE 0x02
78#define NVME_POWER_STATE_STANDBY 0x03
79#define NVME_POWER_STATE_LU_CONTROL 0x07
80#define POWER_STATE_0 0
81#define POWER_STATE_1 1
82#define POWER_STATE_2 2
83#define POWER_STATE_3 3
84#define DOWNLOAD_SAVE_ACTIVATE 0x05
85#define DOWNLOAD_SAVE_DEFER_ACTIVATE 0x0E
86#define ACTIVATE_DEFERRED_MICROCODE 0x0F
87#define FORMAT_UNIT_IMMED_MASK 0x2
88#define FORMAT_UNIT_IMMED_OFFSET 1
89#define KELVIN_TEMP_FACTOR 273
90#define FIXED_FMT_SENSE_DATA_SIZE 18
91#define DESC_FMT_SENSE_DATA_SIZE 8
92
93/* SCSI/NVMe defines and bit masks */
94#define INQ_STANDARD_INQUIRY_PAGE 0x00
95#define INQ_SUPPORTED_VPD_PAGES_PAGE 0x00
96#define INQ_UNIT_SERIAL_NUMBER_PAGE 0x80
97#define INQ_DEVICE_IDENTIFICATION_PAGE 0x83
98#define INQ_EXTENDED_INQUIRY_DATA_PAGE 0x86
Keith Busch7f749d92015-04-07 15:34:18 -060099#define INQ_BDEV_LIMITS_PAGE 0xB0
Vishal Verma5d0f6132013-03-04 18:40:58 -0700100#define INQ_BDEV_CHARACTERISTICS_PAGE 0xB1
101#define INQ_SERIAL_NUMBER_LENGTH 0x14
Keith Busch7f749d92015-04-07 15:34:18 -0600102#define INQ_NUM_SUPPORTED_VPD_PAGES 6
Vishal Verma5d0f6132013-03-04 18:40:58 -0700103#define VERSION_SPC_4 0x06
104#define ACA_UNSUPPORTED 0
105#define STANDARD_INQUIRY_LENGTH 36
106#define ADDITIONAL_STD_INQ_LENGTH 31
107#define EXTENDED_INQUIRY_DATA_PAGE_LENGTH 0x3C
108#define RESERVED_FIELD 0
109
110/* SCSI READ/WRITE Defines */
111#define IO_CDB_WP_MASK 0xE0
112#define IO_CDB_WP_SHIFT 5
113#define IO_CDB_FUA_MASK 0x8
Vishal Verma5d0f6132013-03-04 18:40:58 -0700114#define IO_6_CDB_LBA_MASK 0x001FFFFF
Vishal Verma5d0f6132013-03-04 18:40:58 -0700115
116/* Mode Sense/Select defines */
117#define MODE_PAGE_INFO_EXCEP 0x1C
118#define MODE_PAGE_CACHING 0x08
119#define MODE_PAGE_CONTROL 0x0A
120#define MODE_PAGE_POWER_CONDITION 0x1A
121#define MODE_PAGE_RETURN_ALL 0x3F
122#define MODE_PAGE_BLK_DES_LEN 0x08
123#define MODE_PAGE_LLBAA_BLK_DES_LEN 0x10
124#define MODE_PAGE_CACHING_LEN 0x14
125#define MODE_PAGE_CONTROL_LEN 0x0C
126#define MODE_PAGE_POW_CND_LEN 0x28
127#define MODE_PAGE_INF_EXC_LEN 0x0C
128#define MODE_PAGE_ALL_LEN 0x54
129#define MODE_SENSE6_MPH_SIZE 4
Vishal Verma5d0f6132013-03-04 18:40:58 -0700130#define MODE_SENSE_PAGE_CONTROL_MASK 0xC0
131#define MODE_SENSE_PAGE_CODE_OFFSET 2
132#define MODE_SENSE_PAGE_CODE_MASK 0x3F
Vishal Verma5d0f6132013-03-04 18:40:58 -0700133#define MODE_SENSE_LLBAA_MASK 0x10
134#define MODE_SENSE_LLBAA_SHIFT 4
Vishal Verma5d0f6132013-03-04 18:40:58 -0700135#define MODE_SENSE_DBD_MASK 8
136#define MODE_SENSE_DBD_SHIFT 3
137#define MODE_SENSE10_MPH_SIZE 8
Vishal Verma5d0f6132013-03-04 18:40:58 -0700138#define MODE_SELECT_CDB_PAGE_FORMAT_MASK 0x10
139#define MODE_SELECT_CDB_SAVE_PAGES_MASK 0x1
140#define MODE_SELECT_6_BD_OFFSET 3
141#define MODE_SELECT_10_BD_OFFSET 6
142#define MODE_SELECT_10_LLBAA_OFFSET 4
143#define MODE_SELECT_10_LLBAA_MASK 1
144#define MODE_SELECT_6_MPH_SIZE 4
145#define MODE_SELECT_10_MPH_SIZE 8
146#define CACHING_MODE_PAGE_WCE_MASK 0x04
147#define MODE_SENSE_BLK_DESC_ENABLED 0
148#define MODE_SENSE_BLK_DESC_COUNT 1
149#define MODE_SELECT_PAGE_CODE_MASK 0x3F
150#define SHORT_DESC_BLOCK 8
151#define LONG_DESC_BLOCK 16
152#define MODE_PAGE_POW_CND_LEN_FIELD 0x26
153#define MODE_PAGE_INF_EXC_LEN_FIELD 0x0A
154#define MODE_PAGE_CACHING_LEN_FIELD 0x12
155#define MODE_PAGE_CONTROL_LEN_FIELD 0x0A
156#define MODE_SENSE_PC_CURRENT_VALUES 0
157
158/* Log Sense defines */
159#define LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE 0x00
160#define LOG_PAGE_SUPPORTED_LOG_PAGES_LENGTH 0x07
161#define LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE 0x2F
162#define LOG_PAGE_TEMPERATURE_PAGE 0x0D
Vishal Verma5d0f6132013-03-04 18:40:58 -0700163#define LOG_SENSE_CDB_SP_NOT_ENABLED 0
Vishal Verma5d0f6132013-03-04 18:40:58 -0700164#define LOG_SENSE_CDB_PC_MASK 0xC0
165#define LOG_SENSE_CDB_PC_SHIFT 6
166#define LOG_SENSE_CDB_PC_CUMULATIVE_VALUES 1
167#define LOG_SENSE_CDB_PAGE_CODE_MASK 0x3F
Vishal Verma5d0f6132013-03-04 18:40:58 -0700168#define REMAINING_INFO_EXCP_PAGE_LENGTH 0x8
169#define LOG_INFO_EXCP_PAGE_LENGTH 0xC
170#define REMAINING_TEMP_PAGE_LENGTH 0xC
171#define LOG_TEMP_PAGE_LENGTH 0x10
172#define LOG_TEMP_UNKNOWN 0xFF
173#define SUPPORTED_LOG_PAGES_PAGE_LENGTH 0x3
174
175/* Read Capacity defines */
176#define READ_CAP_10_RESP_SIZE 8
177#define READ_CAP_16_RESP_SIZE 32
178
179/* NVMe Namespace and Command Defines */
Vishal Verma5d0f6132013-03-04 18:40:58 -0700180#define BYTES_TO_DWORDS 4
181#define NVME_MAX_FIRMWARE_SLOT 7
182
183/* Report LUNs defines */
184#define REPORT_LUNS_FIRST_LUN_OFFSET 8
185
186/* SCSI ADDITIONAL SENSE Codes */
187
188#define SCSI_ASC_NO_SENSE 0x00
189#define SCSI_ASC_PERIPHERAL_DEV_WRITE_FAULT 0x03
190#define SCSI_ASC_LUN_NOT_READY 0x04
191#define SCSI_ASC_WARNING 0x0B
192#define SCSI_ASC_LOG_BLOCK_GUARD_CHECK_FAILED 0x10
193#define SCSI_ASC_LOG_BLOCK_APPTAG_CHECK_FAILED 0x10
194#define SCSI_ASC_LOG_BLOCK_REFTAG_CHECK_FAILED 0x10
195#define SCSI_ASC_UNRECOVERED_READ_ERROR 0x11
196#define SCSI_ASC_MISCOMPARE_DURING_VERIFY 0x1D
197#define SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID 0x20
198#define SCSI_ASC_ILLEGAL_COMMAND 0x20
199#define SCSI_ASC_ILLEGAL_BLOCK 0x21
200#define SCSI_ASC_INVALID_CDB 0x24
201#define SCSI_ASC_INVALID_LUN 0x25
202#define SCSI_ASC_INVALID_PARAMETER 0x26
203#define SCSI_ASC_FORMAT_COMMAND_FAILED 0x31
204#define SCSI_ASC_INTERNAL_TARGET_FAILURE 0x44
205
206/* SCSI ADDITIONAL SENSE Code Qualifiers */
207
208#define SCSI_ASCQ_CAUSE_NOT_REPORTABLE 0x00
209#define SCSI_ASCQ_FORMAT_COMMAND_FAILED 0x01
210#define SCSI_ASCQ_LOG_BLOCK_GUARD_CHECK_FAILED 0x01
211#define SCSI_ASCQ_LOG_BLOCK_APPTAG_CHECK_FAILED 0x02
212#define SCSI_ASCQ_LOG_BLOCK_REFTAG_CHECK_FAILED 0x03
213#define SCSI_ASCQ_FORMAT_IN_PROGRESS 0x04
214#define SCSI_ASCQ_POWER_LOSS_EXPECTED 0x08
215#define SCSI_ASCQ_INVALID_LUN_ID 0x09
216
Christoph Hellwig37268972015-05-22 11:12:42 +0200217/* copied from drivers/usb/gadget/function/storage_common.h */
218static inline u32 get_unaligned_be24(u8 *buf)
219{
220 return 0xffffff & (u32) get_unaligned_be32(buf - 1);
221}
Vishal Verma5d0f6132013-03-04 18:40:58 -0700222
223/* Struct to gather data that needs to be extracted from a SCSI CDB.
224 Not conforming to any particular CDB variant, but compatible with all. */
225
226struct nvme_trans_io_cdb {
227 u8 fua;
228 u8 prot_info;
229 u64 lba;
230 u32 xfer_len;
231};
232
233
234/* Internal Helper Functions */
235
236
237/* Copy data to userspace memory */
238
239static int nvme_trans_copy_to_user(struct sg_io_hdr *hdr, void *from,
240 unsigned long n)
241{
Vishal Verma5d0f6132013-03-04 18:40:58 -0700242 int i;
243 void *index = from;
244 size_t remaining = n;
245 size_t xfer_len;
246
247 if (hdr->iovec_count > 0) {
Vishal Verma8741ee42013-04-04 17:52:27 -0600248 struct sg_iovec sgl;
Vishal Verma5d0f6132013-03-04 18:40:58 -0700249
250 for (i = 0; i < hdr->iovec_count; i++) {
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200251 if (copy_from_user(&sgl, hdr->dxferp +
Vishal Verma8741ee42013-04-04 17:52:27 -0600252 i * sizeof(struct sg_iovec),
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200253 sizeof(struct sg_iovec)))
Vishal Verma8741ee42013-04-04 17:52:27 -0600254 return -EFAULT;
255 xfer_len = min(remaining, sgl.iov_len);
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200256 if (copy_to_user(sgl.iov_base, index, xfer_len))
257 return -EFAULT;
258
Vishal Verma5d0f6132013-03-04 18:40:58 -0700259 index += xfer_len;
260 remaining -= xfer_len;
261 if (remaining == 0)
262 break;
263 }
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200264 return 0;
Vishal Verma5d0f6132013-03-04 18:40:58 -0700265 }
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200266
267 if (copy_to_user(hdr->dxferp, from, n))
268 return -EFAULT;
269 return 0;
Vishal Verma5d0f6132013-03-04 18:40:58 -0700270}
271
272/* Copy data from userspace memory */
273
274static int nvme_trans_copy_from_user(struct sg_io_hdr *hdr, void *to,
275 unsigned long n)
276{
Vishal Verma5d0f6132013-03-04 18:40:58 -0700277 int i;
278 void *index = to;
279 size_t remaining = n;
280 size_t xfer_len;
281
282 if (hdr->iovec_count > 0) {
Vishal Verma8741ee42013-04-04 17:52:27 -0600283 struct sg_iovec sgl;
Vishal Verma5d0f6132013-03-04 18:40:58 -0700284
285 for (i = 0; i < hdr->iovec_count; i++) {
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200286 if (copy_from_user(&sgl, hdr->dxferp +
Vishal Verma8741ee42013-04-04 17:52:27 -0600287 i * sizeof(struct sg_iovec),
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200288 sizeof(struct sg_iovec)))
Vishal Verma8741ee42013-04-04 17:52:27 -0600289 return -EFAULT;
290 xfer_len = min(remaining, sgl.iov_len);
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200291 if (copy_from_user(index, sgl.iov_base, xfer_len))
292 return -EFAULT;
Vishal Verma5d0f6132013-03-04 18:40:58 -0700293 index += xfer_len;
294 remaining -= xfer_len;
295 if (remaining == 0)
296 break;
297 }
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200298 return 0;
Vishal Verma5d0f6132013-03-04 18:40:58 -0700299 }
300
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200301 if (copy_from_user(to, hdr->dxferp, n))
302 return -EFAULT;
303 return 0;
Vishal Verma5d0f6132013-03-04 18:40:58 -0700304}
305
306/* Status/Sense Buffer Writeback */
307
308static int nvme_trans_completion(struct sg_io_hdr *hdr, u8 status, u8 sense_key,
309 u8 asc, u8 ascq)
310{
Vishal Verma5d0f6132013-03-04 18:40:58 -0700311 u8 xfer_len;
312 u8 resp[DESC_FMT_SENSE_DATA_SIZE];
313
314 if (scsi_status_is_good(status)) {
315 hdr->status = SAM_STAT_GOOD;
316 hdr->masked_status = GOOD;
317 hdr->host_status = DID_OK;
318 hdr->driver_status = DRIVER_OK;
319 hdr->sb_len_wr = 0;
320 } else {
321 hdr->status = status;
322 hdr->masked_status = status >> 1;
323 hdr->host_status = DID_OK;
324 hdr->driver_status = DRIVER_OK;
325
326 memset(resp, 0, DESC_FMT_SENSE_DATA_SIZE);
327 resp[0] = DESC_FORMAT_SENSE_DATA;
328 resp[1] = sense_key;
329 resp[2] = asc;
330 resp[3] = ascq;
331
332 xfer_len = min_t(u8, hdr->mx_sb_len, DESC_FMT_SENSE_DATA_SIZE);
333 hdr->sb_len_wr = xfer_len;
Vishal Verma8741ee42013-04-04 17:52:27 -0600334 if (copy_to_user(hdr->sbp, resp, xfer_len) > 0)
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200335 return -EFAULT;
Vishal Verma5d0f6132013-03-04 18:40:58 -0700336 }
337
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200338 return 0;
Vishal Verma5d0f6132013-03-04 18:40:58 -0700339}
340
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200341/*
342 * Take a status code from a lowlevel routine, and if it was a positive NVMe
343 * error code update the sense data based on it. In either case the passed
344 * in value is returned again, unless an -EFAULT from copy_to_user overrides
345 * it.
346 */
Vishal Verma5d0f6132013-03-04 18:40:58 -0700347static int nvme_trans_status_code(struct sg_io_hdr *hdr, int nvme_sc)
348{
349 u8 status, sense_key, asc, ascq;
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200350 int res;
Vishal Verma5d0f6132013-03-04 18:40:58 -0700351
352 /* For non-nvme (Linux) errors, simply return the error code */
353 if (nvme_sc < 0)
354 return nvme_sc;
355
356 /* Mask DNR, More, and reserved fields */
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200357 switch (nvme_sc & 0x7FF) {
Vishal Verma5d0f6132013-03-04 18:40:58 -0700358 /* Generic Command Status */
359 case NVME_SC_SUCCESS:
360 status = SAM_STAT_GOOD;
361 sense_key = NO_SENSE;
362 asc = SCSI_ASC_NO_SENSE;
363 ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
364 break;
365 case NVME_SC_INVALID_OPCODE:
366 status = SAM_STAT_CHECK_CONDITION;
367 sense_key = ILLEGAL_REQUEST;
368 asc = SCSI_ASC_ILLEGAL_COMMAND;
369 ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
370 break;
371 case NVME_SC_INVALID_FIELD:
372 status = SAM_STAT_CHECK_CONDITION;
373 sense_key = ILLEGAL_REQUEST;
374 asc = SCSI_ASC_INVALID_CDB;
375 ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
376 break;
377 case NVME_SC_DATA_XFER_ERROR:
378 status = SAM_STAT_CHECK_CONDITION;
379 sense_key = MEDIUM_ERROR;
380 asc = SCSI_ASC_NO_SENSE;
381 ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
382 break;
383 case NVME_SC_POWER_LOSS:
384 status = SAM_STAT_TASK_ABORTED;
385 sense_key = ABORTED_COMMAND;
386 asc = SCSI_ASC_WARNING;
387 ascq = SCSI_ASCQ_POWER_LOSS_EXPECTED;
388 break;
389 case NVME_SC_INTERNAL:
390 status = SAM_STAT_CHECK_CONDITION;
391 sense_key = HARDWARE_ERROR;
392 asc = SCSI_ASC_INTERNAL_TARGET_FAILURE;
393 ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
394 break;
395 case NVME_SC_ABORT_REQ:
396 status = SAM_STAT_TASK_ABORTED;
397 sense_key = ABORTED_COMMAND;
398 asc = SCSI_ASC_NO_SENSE;
399 ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
400 break;
401 case NVME_SC_ABORT_QUEUE:
402 status = SAM_STAT_TASK_ABORTED;
403 sense_key = ABORTED_COMMAND;
404 asc = SCSI_ASC_NO_SENSE;
405 ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
406 break;
407 case NVME_SC_FUSED_FAIL:
408 status = SAM_STAT_TASK_ABORTED;
409 sense_key = ABORTED_COMMAND;
410 asc = SCSI_ASC_NO_SENSE;
411 ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
412 break;
413 case NVME_SC_FUSED_MISSING:
414 status = SAM_STAT_TASK_ABORTED;
415 sense_key = ABORTED_COMMAND;
416 asc = SCSI_ASC_NO_SENSE;
417 ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
418 break;
419 case NVME_SC_INVALID_NS:
420 status = SAM_STAT_CHECK_CONDITION;
421 sense_key = ILLEGAL_REQUEST;
422 asc = SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID;
423 ascq = SCSI_ASCQ_INVALID_LUN_ID;
424 break;
425 case NVME_SC_LBA_RANGE:
426 status = SAM_STAT_CHECK_CONDITION;
427 sense_key = ILLEGAL_REQUEST;
428 asc = SCSI_ASC_ILLEGAL_BLOCK;
429 ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
430 break;
431 case NVME_SC_CAP_EXCEEDED:
432 status = SAM_STAT_CHECK_CONDITION;
433 sense_key = MEDIUM_ERROR;
434 asc = SCSI_ASC_NO_SENSE;
435 ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
436 break;
437 case NVME_SC_NS_NOT_READY:
438 status = SAM_STAT_CHECK_CONDITION;
439 sense_key = NOT_READY;
440 asc = SCSI_ASC_LUN_NOT_READY;
441 ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
442 break;
443
444 /* Command Specific Status */
445 case NVME_SC_INVALID_FORMAT:
446 status = SAM_STAT_CHECK_CONDITION;
447 sense_key = ILLEGAL_REQUEST;
448 asc = SCSI_ASC_FORMAT_COMMAND_FAILED;
449 ascq = SCSI_ASCQ_FORMAT_COMMAND_FAILED;
450 break;
451 case NVME_SC_BAD_ATTRIBUTES:
452 status = SAM_STAT_CHECK_CONDITION;
453 sense_key = ILLEGAL_REQUEST;
454 asc = SCSI_ASC_INVALID_CDB;
455 ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
456 break;
457
458 /* Media Errors */
459 case NVME_SC_WRITE_FAULT:
460 status = SAM_STAT_CHECK_CONDITION;
461 sense_key = MEDIUM_ERROR;
462 asc = SCSI_ASC_PERIPHERAL_DEV_WRITE_FAULT;
463 ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
464 break;
465 case NVME_SC_READ_ERROR:
466 status = SAM_STAT_CHECK_CONDITION;
467 sense_key = MEDIUM_ERROR;
468 asc = SCSI_ASC_UNRECOVERED_READ_ERROR;
469 ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
470 break;
471 case NVME_SC_GUARD_CHECK:
472 status = SAM_STAT_CHECK_CONDITION;
473 sense_key = MEDIUM_ERROR;
474 asc = SCSI_ASC_LOG_BLOCK_GUARD_CHECK_FAILED;
475 ascq = SCSI_ASCQ_LOG_BLOCK_GUARD_CHECK_FAILED;
476 break;
477 case NVME_SC_APPTAG_CHECK:
478 status = SAM_STAT_CHECK_CONDITION;
479 sense_key = MEDIUM_ERROR;
480 asc = SCSI_ASC_LOG_BLOCK_APPTAG_CHECK_FAILED;
481 ascq = SCSI_ASCQ_LOG_BLOCK_APPTAG_CHECK_FAILED;
482 break;
483 case NVME_SC_REFTAG_CHECK:
484 status = SAM_STAT_CHECK_CONDITION;
485 sense_key = MEDIUM_ERROR;
486 asc = SCSI_ASC_LOG_BLOCK_REFTAG_CHECK_FAILED;
487 ascq = SCSI_ASCQ_LOG_BLOCK_REFTAG_CHECK_FAILED;
488 break;
489 case NVME_SC_COMPARE_FAILED:
490 status = SAM_STAT_CHECK_CONDITION;
491 sense_key = MISCOMPARE;
492 asc = SCSI_ASC_MISCOMPARE_DURING_VERIFY;
493 ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
494 break;
495 case NVME_SC_ACCESS_DENIED:
496 status = SAM_STAT_CHECK_CONDITION;
497 sense_key = ILLEGAL_REQUEST;
498 asc = SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID;
499 ascq = SCSI_ASCQ_INVALID_LUN_ID;
500 break;
501
502 /* Unspecified/Default */
503 case NVME_SC_CMDID_CONFLICT:
504 case NVME_SC_CMD_SEQ_ERROR:
505 case NVME_SC_CQ_INVALID:
506 case NVME_SC_QID_INVALID:
507 case NVME_SC_QUEUE_SIZE:
508 case NVME_SC_ABORT_LIMIT:
509 case NVME_SC_ABORT_MISSING:
510 case NVME_SC_ASYNC_LIMIT:
511 case NVME_SC_FIRMWARE_SLOT:
512 case NVME_SC_FIRMWARE_IMAGE:
513 case NVME_SC_INVALID_VECTOR:
514 case NVME_SC_INVALID_LOG_PAGE:
515 default:
516 status = SAM_STAT_CHECK_CONDITION;
517 sense_key = ILLEGAL_REQUEST;
518 asc = SCSI_ASC_NO_SENSE;
519 ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
520 break;
521 }
522
523 res = nvme_trans_completion(hdr, status, sense_key, asc, ascq);
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200524 return res ? res : nvme_sc;
Vishal Verma5d0f6132013-03-04 18:40:58 -0700525}
526
527/* INQUIRY Helper Functions */
528
529static int nvme_trans_standard_inquiry_page(struct nvme_ns *ns,
530 struct sg_io_hdr *hdr, u8 *inq_response,
531 int alloc_len)
532{
533 struct nvme_dev *dev = ns->dev;
534 dma_addr_t dma_addr;
535 void *mem;
536 struct nvme_id_ns *id_ns;
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200537 int res;
Vishal Verma5d0f6132013-03-04 18:40:58 -0700538 int nvme_sc;
539 int xfer_len;
540 u8 resp_data_format = 0x02;
541 u8 protect;
542 u8 cmdque = 0x01 << 1;
Keith Buschdedf4b12014-04-29 15:52:27 -0600543 u8 fw_offset = sizeof(dev->firmware_rev);
Vishal Verma5d0f6132013-03-04 18:40:58 -0700544
Christoph Hellwige75ec752015-05-22 11:12:39 +0200545 mem = dma_alloc_coherent(dev->dev, sizeof(struct nvme_id_ns),
Vishal Verma5d0f6132013-03-04 18:40:58 -0700546 &dma_addr, GFP_KERNEL);
547 if (mem == NULL) {
548 res = -ENOMEM;
549 goto out_dma;
550 }
551
552 /* nvme ns identify - use DPS value for PROTECT field */
553 nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
554 res = nvme_trans_status_code(hdr, nvme_sc);
Vishal Verma5d0f6132013-03-04 18:40:58 -0700555 if (res)
556 goto out_free;
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200557
Vishal Verma5d0f6132013-03-04 18:40:58 -0700558 id_ns = mem;
559 (id_ns->dps) ? (protect = 0x01) : (protect = 0);
560
561 memset(inq_response, 0, STANDARD_INQUIRY_LENGTH);
562 inq_response[2] = VERSION_SPC_4;
563 inq_response[3] = resp_data_format; /*normaca=0 | hisup=0 */
564 inq_response[4] = ADDITIONAL_STD_INQ_LENGTH;
565 inq_response[5] = protect; /* sccs=0 | acc=0 | tpgs=0 | pc3=0 */
566 inq_response[7] = cmdque; /* wbus16=0 | sync=0 | vs=0 */
567 strncpy(&inq_response[8], "NVMe ", 8);
568 strncpy(&inq_response[16], dev->model, 16);
Keith Buschdedf4b12014-04-29 15:52:27 -0600569
570 while (dev->firmware_rev[fw_offset - 1] == ' ' && fw_offset > 4)
571 fw_offset--;
572 fw_offset -= 4;
573 strncpy(&inq_response[32], dev->firmware_rev + fw_offset, 4);
Vishal Verma5d0f6132013-03-04 18:40:58 -0700574
575 xfer_len = min(alloc_len, STANDARD_INQUIRY_LENGTH);
576 res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
577
578 out_free:
Christoph Hellwige75ec752015-05-22 11:12:39 +0200579 dma_free_coherent(dev->dev, sizeof(struct nvme_id_ns), mem, dma_addr);
Vishal Verma5d0f6132013-03-04 18:40:58 -0700580 out_dma:
581 return res;
582}
583
584static int nvme_trans_supported_vpd_pages(struct nvme_ns *ns,
585 struct sg_io_hdr *hdr, u8 *inq_response,
586 int alloc_len)
587{
Vishal Verma5d0f6132013-03-04 18:40:58 -0700588 int xfer_len;
589
590 memset(inq_response, 0, STANDARD_INQUIRY_LENGTH);
591 inq_response[1] = INQ_SUPPORTED_VPD_PAGES_PAGE; /* Page Code */
592 inq_response[3] = INQ_NUM_SUPPORTED_VPD_PAGES; /* Page Length */
593 inq_response[4] = INQ_SUPPORTED_VPD_PAGES_PAGE;
594 inq_response[5] = INQ_UNIT_SERIAL_NUMBER_PAGE;
595 inq_response[6] = INQ_DEVICE_IDENTIFICATION_PAGE;
596 inq_response[7] = INQ_EXTENDED_INQUIRY_DATA_PAGE;
597 inq_response[8] = INQ_BDEV_CHARACTERISTICS_PAGE;
Keith Busch7f749d92015-04-07 15:34:18 -0600598 inq_response[9] = INQ_BDEV_LIMITS_PAGE;
Vishal Verma5d0f6132013-03-04 18:40:58 -0700599
600 xfer_len = min(alloc_len, STANDARD_INQUIRY_LENGTH);
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200601 return nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
Vishal Verma5d0f6132013-03-04 18:40:58 -0700602}
603
604static int nvme_trans_unit_serial_page(struct nvme_ns *ns,
605 struct sg_io_hdr *hdr, u8 *inq_response,
606 int alloc_len)
607{
608 struct nvme_dev *dev = ns->dev;
Vishal Verma5d0f6132013-03-04 18:40:58 -0700609 int xfer_len;
610
611 memset(inq_response, 0, STANDARD_INQUIRY_LENGTH);
612 inq_response[1] = INQ_UNIT_SERIAL_NUMBER_PAGE; /* Page Code */
613 inq_response[3] = INQ_SERIAL_NUMBER_LENGTH; /* Page Length */
614 strncpy(&inq_response[4], dev->serial, INQ_SERIAL_NUMBER_LENGTH);
615
616 xfer_len = min(alloc_len, STANDARD_INQUIRY_LENGTH);
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200617 return nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
Vishal Verma5d0f6132013-03-04 18:40:58 -0700618}
619
620static int nvme_trans_device_id_page(struct nvme_ns *ns, struct sg_io_hdr *hdr,
621 u8 *inq_response, int alloc_len)
622{
623 struct nvme_dev *dev = ns->dev;
624 dma_addr_t dma_addr;
625 void *mem;
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200626 int res;
Vishal Verma5d0f6132013-03-04 18:40:58 -0700627 int nvme_sc;
Vishal Verma5d0f6132013-03-04 18:40:58 -0700628 int xfer_len;
Vishal Verma8741ee42013-04-04 17:52:27 -0600629 __be32 tmp_id = cpu_to_be32(ns->ns_id);
Vishal Verma5d0f6132013-03-04 18:40:58 -0700630
Christoph Hellwige75ec752015-05-22 11:12:39 +0200631 mem = dma_alloc_coherent(dev->dev, sizeof(struct nvme_id_ns),
Vishal Verma5d0f6132013-03-04 18:40:58 -0700632 &dma_addr, GFP_KERNEL);
633 if (mem == NULL) {
634 res = -ENOMEM;
635 goto out_dma;
636 }
637
Keith Busch4f1982b2015-02-19 13:42:14 -0700638 memset(inq_response, 0, alloc_len);
Vishal Verma5d0f6132013-03-04 18:40:58 -0700639 inq_response[1] = INQ_DEVICE_IDENTIFICATION_PAGE; /* Page Code */
Keith Busch4f1982b2015-02-19 13:42:14 -0700640 if (readl(&dev->bar->vs) >= NVME_VS(1, 1)) {
641 struct nvme_id_ns *id_ns = mem;
642 void *eui = id_ns->eui64;
643 int len = sizeof(id_ns->eui64);
Vishal Verma5d0f6132013-03-04 18:40:58 -0700644
Keith Busch4f1982b2015-02-19 13:42:14 -0700645 nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
646 res = nvme_trans_status_code(hdr, nvme_sc);
647 if (res)
648 goto out_free;
Keith Busch4f1982b2015-02-19 13:42:14 -0700649
650 if (readl(&dev->bar->vs) >= NVME_VS(1, 2)) {
651 if (bitmap_empty(eui, len * 8)) {
652 eui = id_ns->nguid;
653 len = sizeof(id_ns->nguid);
654 }
655 }
656 if (bitmap_empty(eui, len * 8))
657 goto scsi_string;
658
659 inq_response[3] = 4 + len; /* Page Length */
660 /* Designation Descriptor start */
661 inq_response[4] = 0x01; /* Proto ID=0h | Code set=1h */
662 inq_response[5] = 0x02; /* PIV=0b | Asso=00b | Designator Type=2h */
663 inq_response[6] = 0x00; /* Rsvd */
664 inq_response[7] = len; /* Designator Length */
665 memcpy(&inq_response[8], eui, len);
666 } else {
667 scsi_string:
668 if (alloc_len < 72) {
669 res = nvme_trans_completion(hdr,
670 SAM_STAT_CHECK_CONDITION,
671 ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
672 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
673 goto out_free;
674 }
675 inq_response[3] = 0x48; /* Page Length */
676 /* Designation Descriptor start */
677 inq_response[4] = 0x03; /* Proto ID=0h | Code set=3h */
678 inq_response[5] = 0x08; /* PIV=0b | Asso=00b | Designator Type=8h */
679 inq_response[6] = 0x00; /* Rsvd */
680 inq_response[7] = 0x44; /* Designator Length */
681
Christoph Hellwige75ec752015-05-22 11:12:39 +0200682 sprintf(&inq_response[8], "%04x", to_pci_dev(dev->dev)->vendor);
Keith Busch4f1982b2015-02-19 13:42:14 -0700683 memcpy(&inq_response[12], dev->model, sizeof(dev->model));
684 sprintf(&inq_response[52], "%04x", tmp_id);
685 memcpy(&inq_response[56], dev->serial, sizeof(dev->serial));
686 }
687 xfer_len = alloc_len;
Vishal Verma5d0f6132013-03-04 18:40:58 -0700688 res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
689
690 out_free:
Christoph Hellwige75ec752015-05-22 11:12:39 +0200691 dma_free_coherent(dev->dev, sizeof(struct nvme_id_ns), mem, dma_addr);
Vishal Verma5d0f6132013-03-04 18:40:58 -0700692 out_dma:
693 return res;
694}
695
696static int nvme_trans_ext_inq_page(struct nvme_ns *ns, struct sg_io_hdr *hdr,
697 int alloc_len)
698{
699 u8 *inq_response;
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200700 int res;
Vishal Verma5d0f6132013-03-04 18:40:58 -0700701 int nvme_sc;
702 struct nvme_dev *dev = ns->dev;
703 dma_addr_t dma_addr;
704 void *mem;
705 struct nvme_id_ctrl *id_ctrl;
706 struct nvme_id_ns *id_ns;
707 int xfer_len;
708 u8 microcode = 0x80;
709 u8 spt;
710 u8 spt_lut[8] = {0, 0, 2, 1, 4, 6, 5, 7};
711 u8 grd_chk, app_chk, ref_chk, protect;
712 u8 uask_sup = 0x20;
713 u8 v_sup;
714 u8 luiclr = 0x01;
715
716 inq_response = kmalloc(EXTENDED_INQUIRY_DATA_PAGE_LENGTH, GFP_KERNEL);
717 if (inq_response == NULL) {
718 res = -ENOMEM;
719 goto out_mem;
720 }
721
Christoph Hellwige75ec752015-05-22 11:12:39 +0200722 mem = dma_alloc_coherent(dev->dev, sizeof(struct nvme_id_ns),
Vishal Verma5d0f6132013-03-04 18:40:58 -0700723 &dma_addr, GFP_KERNEL);
724 if (mem == NULL) {
725 res = -ENOMEM;
726 goto out_dma;
727 }
728
729 /* nvme ns identify */
730 nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
731 res = nvme_trans_status_code(hdr, nvme_sc);
732 if (res)
733 goto out_free;
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200734
Vishal Verma5d0f6132013-03-04 18:40:58 -0700735 id_ns = mem;
736 spt = spt_lut[(id_ns->dpc) & 0x07] << 3;
737 (id_ns->dps) ? (protect = 0x01) : (protect = 0);
738 grd_chk = protect << 2;
739 app_chk = protect << 1;
740 ref_chk = protect;
741
742 /* nvme controller identify */
743 nvme_sc = nvme_identify(dev, 0, 1, dma_addr);
744 res = nvme_trans_status_code(hdr, nvme_sc);
745 if (res)
746 goto out_free;
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200747
Vishal Verma5d0f6132013-03-04 18:40:58 -0700748 id_ctrl = mem;
749 v_sup = id_ctrl->vwc;
750
751 memset(inq_response, 0, EXTENDED_INQUIRY_DATA_PAGE_LENGTH);
752 inq_response[1] = INQ_EXTENDED_INQUIRY_DATA_PAGE; /* Page Code */
753 inq_response[2] = 0x00; /* Page Length MSB */
754 inq_response[3] = 0x3C; /* Page Length LSB */
755 inq_response[4] = microcode | spt | grd_chk | app_chk | ref_chk;
756 inq_response[5] = uask_sup;
757 inq_response[6] = v_sup;
758 inq_response[7] = luiclr;
759 inq_response[8] = 0;
760 inq_response[9] = 0;
761
762 xfer_len = min(alloc_len, EXTENDED_INQUIRY_DATA_PAGE_LENGTH);
763 res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
764
765 out_free:
Christoph Hellwige75ec752015-05-22 11:12:39 +0200766 dma_free_coherent(dev->dev, sizeof(struct nvme_id_ns), mem, dma_addr);
Vishal Verma5d0f6132013-03-04 18:40:58 -0700767 out_dma:
768 kfree(inq_response);
769 out_mem:
770 return res;
771}
772
Keith Busch7f749d92015-04-07 15:34:18 -0600773static int nvme_trans_bdev_limits_page(struct nvme_ns *ns, struct sg_io_hdr *hdr,
774 u8 *inq_response, int alloc_len)
775{
776 __be32 max_sectors = cpu_to_be32(queue_max_hw_sectors(ns->queue));
777 __be32 max_discard = cpu_to_be32(ns->queue->limits.max_discard_sectors);
778 __be32 discard_desc_count = cpu_to_be32(0x100);
779
780 memset(inq_response, 0, STANDARD_INQUIRY_LENGTH);
781 inq_response[1] = VPD_BLOCK_LIMITS;
782 inq_response[3] = 0x3c; /* Page Length */
783 memcpy(&inq_response[8], &max_sectors, sizeof(u32));
784 memcpy(&inq_response[20], &max_discard, sizeof(u32));
785
786 if (max_discard)
787 memcpy(&inq_response[24], &discard_desc_count, sizeof(u32));
788
789 return nvme_trans_copy_to_user(hdr, inq_response, 0x3c);
790}
791
Vishal Verma5d0f6132013-03-04 18:40:58 -0700792static int nvme_trans_bdev_char_page(struct nvme_ns *ns, struct sg_io_hdr *hdr,
793 int alloc_len)
794{
795 u8 *inq_response;
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200796 int res;
Vishal Verma5d0f6132013-03-04 18:40:58 -0700797 int xfer_len;
798
Tushar Behera03ea83e2013-06-10 10:20:55 +0530799 inq_response = kzalloc(EXTENDED_INQUIRY_DATA_PAGE_LENGTH, GFP_KERNEL);
Vishal Verma5d0f6132013-03-04 18:40:58 -0700800 if (inq_response == NULL) {
801 res = -ENOMEM;
802 goto out_mem;
803 }
804
Vishal Verma5d0f6132013-03-04 18:40:58 -0700805 inq_response[1] = INQ_BDEV_CHARACTERISTICS_PAGE; /* Page Code */
806 inq_response[2] = 0x00; /* Page Length MSB */
807 inq_response[3] = 0x3C; /* Page Length LSB */
808 inq_response[4] = 0x00; /* Medium Rotation Rate MSB */
809 inq_response[5] = 0x01; /* Medium Rotation Rate LSB */
810 inq_response[6] = 0x00; /* Form Factor */
811
812 xfer_len = min(alloc_len, EXTENDED_INQUIRY_DATA_PAGE_LENGTH);
813 res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
814
815 kfree(inq_response);
816 out_mem:
817 return res;
818}
819
820/* LOG SENSE Helper Functions */
821
822static int nvme_trans_log_supp_pages(struct nvme_ns *ns, struct sg_io_hdr *hdr,
823 int alloc_len)
824{
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200825 int res;
Vishal Verma5d0f6132013-03-04 18:40:58 -0700826 int xfer_len;
827 u8 *log_response;
828
Tushar Behera03ea83e2013-06-10 10:20:55 +0530829 log_response = kzalloc(LOG_PAGE_SUPPORTED_LOG_PAGES_LENGTH, GFP_KERNEL);
Vishal Verma5d0f6132013-03-04 18:40:58 -0700830 if (log_response == NULL) {
831 res = -ENOMEM;
832 goto out_mem;
833 }
Vishal Verma5d0f6132013-03-04 18:40:58 -0700834
835 log_response[0] = LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE;
836 /* Subpage=0x00, Page Length MSB=0 */
837 log_response[3] = SUPPORTED_LOG_PAGES_PAGE_LENGTH;
838 log_response[4] = LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE;
839 log_response[5] = LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE;
840 log_response[6] = LOG_PAGE_TEMPERATURE_PAGE;
841
842 xfer_len = min(alloc_len, LOG_PAGE_SUPPORTED_LOG_PAGES_LENGTH);
843 res = nvme_trans_copy_to_user(hdr, log_response, xfer_len);
844
845 kfree(log_response);
846 out_mem:
847 return res;
848}
849
850static int nvme_trans_log_info_exceptions(struct nvme_ns *ns,
851 struct sg_io_hdr *hdr, int alloc_len)
852{
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200853 int res;
Vishal Verma5d0f6132013-03-04 18:40:58 -0700854 int xfer_len;
855 u8 *log_response;
856 struct nvme_command c;
857 struct nvme_dev *dev = ns->dev;
858 struct nvme_smart_log *smart_log;
859 dma_addr_t dma_addr;
860 void *mem;
861 u8 temp_c;
862 u16 temp_k;
863
Tushar Behera03ea83e2013-06-10 10:20:55 +0530864 log_response = kzalloc(LOG_INFO_EXCP_PAGE_LENGTH, GFP_KERNEL);
Vishal Verma5d0f6132013-03-04 18:40:58 -0700865 if (log_response == NULL) {
866 res = -ENOMEM;
867 goto out_mem;
868 }
Vishal Verma5d0f6132013-03-04 18:40:58 -0700869
Christoph Hellwige75ec752015-05-22 11:12:39 +0200870 mem = dma_alloc_coherent(dev->dev, sizeof(struct nvme_smart_log),
Vishal Verma5d0f6132013-03-04 18:40:58 -0700871 &dma_addr, GFP_KERNEL);
872 if (mem == NULL) {
873 res = -ENOMEM;
874 goto out_dma;
875 }
876
877 /* Get SMART Log Page */
878 memset(&c, 0, sizeof(c));
879 c.common.opcode = nvme_admin_get_log_page;
880 c.common.nsid = cpu_to_le32(0xFFFFFFFF);
881 c.common.prp1 = cpu_to_le64(dma_addr);
Indraneel Mukherjee4131f2f2014-05-29 12:02:03 +0530882 c.common.cdw10[0] = cpu_to_le32((((sizeof(struct nvme_smart_log) /
Matthew Wilcoxef351b92014-06-13 10:54:21 -0400883 BYTES_TO_DWORDS) - 1) << 16) | NVME_LOG_SMART);
Christoph Hellwigf705f832015-05-22 11:12:38 +0200884 res = nvme_submit_sync_cmd(dev->admin_q, &c);
Vishal Verma5d0f6132013-03-04 18:40:58 -0700885 if (res != NVME_SC_SUCCESS) {
886 temp_c = LOG_TEMP_UNKNOWN;
887 } else {
888 smart_log = mem;
889 temp_k = (smart_log->temperature[1] << 8) +
890 (smart_log->temperature[0]);
891 temp_c = temp_k - KELVIN_TEMP_FACTOR;
892 }
893
894 log_response[0] = LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE;
895 /* Subpage=0x00, Page Length MSB=0 */
896 log_response[3] = REMAINING_INFO_EXCP_PAGE_LENGTH;
897 /* Informational Exceptions Log Parameter 1 Start */
898 /* Parameter Code=0x0000 bytes 4,5 */
899 log_response[6] = 0x23; /* DU=0, TSD=1, ETC=0, TMC=0, FMT_AND_LNK=11b */
900 log_response[7] = 0x04; /* PARAMETER LENGTH */
901 /* Add sense Code and qualifier = 0x00 each */
902 /* Use Temperature from NVMe Get Log Page, convert to C from K */
903 log_response[10] = temp_c;
904
905 xfer_len = min(alloc_len, LOG_INFO_EXCP_PAGE_LENGTH);
906 res = nvme_trans_copy_to_user(hdr, log_response, xfer_len);
907
Christoph Hellwige75ec752015-05-22 11:12:39 +0200908 dma_free_coherent(dev->dev, sizeof(struct nvme_smart_log),
Vishal Verma5d0f6132013-03-04 18:40:58 -0700909 mem, dma_addr);
910 out_dma:
911 kfree(log_response);
912 out_mem:
913 return res;
914}
915
916static int nvme_trans_log_temperature(struct nvme_ns *ns, struct sg_io_hdr *hdr,
917 int alloc_len)
918{
Christoph Hellwige61b0a82015-05-22 11:12:41 +0200919 int res;
Vishal Verma5d0f6132013-03-04 18:40:58 -0700920 int xfer_len;
921 u8 *log_response;
922 struct nvme_command c;
923 struct nvme_dev *dev = ns->dev;
924 struct nvme_smart_log *smart_log;
925 dma_addr_t dma_addr;
926 void *mem;
927 u32 feature_resp;
928 u8 temp_c_cur, temp_c_thresh;
929 u16 temp_k;
930
Tushar Behera03ea83e2013-06-10 10:20:55 +0530931 log_response = kzalloc(LOG_TEMP_PAGE_LENGTH, GFP_KERNEL);
Vishal Verma5d0f6132013-03-04 18:40:58 -0700932 if (log_response == NULL) {
933 res = -ENOMEM;
934 goto out_mem;
935 }
Vishal Verma5d0f6132013-03-04 18:40:58 -0700936
Christoph Hellwige75ec752015-05-22 11:12:39 +0200937 mem = dma_alloc_coherent(dev->dev, sizeof(struct nvme_smart_log),
Vishal Verma5d0f6132013-03-04 18:40:58 -0700938 &dma_addr, GFP_KERNEL);
939 if (mem == NULL) {
940 res = -ENOMEM;
941 goto out_dma;
942 }
943
944 /* Get SMART Log Page */
945 memset(&c, 0, sizeof(c));
946 c.common.opcode = nvme_admin_get_log_page;
947 c.common.nsid = cpu_to_le32(0xFFFFFFFF);
948 c.common.prp1 = cpu_to_le64(dma_addr);
Indraneel Mukherjee4131f2f2014-05-29 12:02:03 +0530949 c.common.cdw10[0] = cpu_to_le32((((sizeof(struct nvme_smart_log) /
Matthew Wilcoxef351b92014-06-13 10:54:21 -0400950 BYTES_TO_DWORDS) - 1) << 16) | NVME_LOG_SMART);
Christoph Hellwigf705f832015-05-22 11:12:38 +0200951 res = nvme_submit_sync_cmd(dev->admin_q, &c);
Vishal Verma5d0f6132013-03-04 18:40:58 -0700952 if (res != NVME_SC_SUCCESS) {
953 temp_c_cur = LOG_TEMP_UNKNOWN;
954 } else {
955 smart_log = mem;
956 temp_k = (smart_log->temperature[1] << 8) +
957 (smart_log->temperature[0]);
958 temp_c_cur = temp_k - KELVIN_TEMP_FACTOR;
959 }
960
961 /* Get Features for Temp Threshold */
962 res = nvme_get_features(dev, NVME_FEAT_TEMP_THRESH, 0, 0,
963 &feature_resp);
964 if (res != NVME_SC_SUCCESS)
965 temp_c_thresh = LOG_TEMP_UNKNOWN;
966 else
967 temp_c_thresh = (feature_resp & 0xFFFF) - KELVIN_TEMP_FACTOR;
968
969 log_response[0] = LOG_PAGE_TEMPERATURE_PAGE;
970 /* Subpage=0x00, Page Length MSB=0 */
971 log_response[3] = REMAINING_TEMP_PAGE_LENGTH;
972 /* Temperature Log Parameter 1 (Temperature) Start */
973 /* Parameter Code = 0x0000 */
974 log_response[6] = 0x01; /* Format and Linking = 01b */
975 log_response[7] = 0x02; /* Parameter Length */
976 /* Use Temperature from NVMe Get Log Page, convert to C from K */
977 log_response[9] = temp_c_cur;
978 /* Temperature Log Parameter 2 (Reference Temperature) Start */
979 log_response[11] = 0x01; /* Parameter Code = 0x0001 */
980 log_response[12] = 0x01; /* Format and Linking = 01b */
981 log_response[13] = 0x02; /* Parameter Length */
982 /* Use Temperature Thresh from NVMe Get Log Page, convert to C from K */
983 log_response[15] = temp_c_thresh;
984
985 xfer_len = min(alloc_len, LOG_TEMP_PAGE_LENGTH);
986 res = nvme_trans_copy_to_user(hdr, log_response, xfer_len);
987
Christoph Hellwige75ec752015-05-22 11:12:39 +0200988 dma_free_coherent(dev->dev, sizeof(struct nvme_smart_log),
Vishal Verma5d0f6132013-03-04 18:40:58 -0700989 mem, dma_addr);
990 out_dma:
991 kfree(log_response);
992 out_mem:
993 return res;
994}
995
996/* MODE SENSE Helper Functions */
997
998static int nvme_trans_fill_mode_parm_hdr(u8 *resp, int len, u8 cdb10, u8 llbaa,
999 u16 mode_data_length, u16 blk_desc_len)
1000{
1001 /* Quick check to make sure I don't stomp on my own memory... */
1002 if ((cdb10 && len < 8) || (!cdb10 && len < 4))
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001003 return -EINVAL;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001004
1005 if (cdb10) {
1006 resp[0] = (mode_data_length & 0xFF00) >> 8;
1007 resp[1] = (mode_data_length & 0x00FF);
1008 /* resp[2] and [3] are zero */
1009 resp[4] = llbaa;
1010 resp[5] = RESERVED_FIELD;
1011 resp[6] = (blk_desc_len & 0xFF00) >> 8;
1012 resp[7] = (blk_desc_len & 0x00FF);
1013 } else {
1014 resp[0] = (mode_data_length & 0x00FF);
1015 /* resp[1] and [2] are zero */
1016 resp[3] = (blk_desc_len & 0x00FF);
1017 }
1018
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001019 return 0;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001020}
1021
1022static int nvme_trans_fill_blk_desc(struct nvme_ns *ns, struct sg_io_hdr *hdr,
1023 u8 *resp, int len, u8 llbaa)
1024{
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001025 int res;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001026 int nvme_sc;
1027 struct nvme_dev *dev = ns->dev;
1028 dma_addr_t dma_addr;
1029 void *mem;
1030 struct nvme_id_ns *id_ns;
1031 u8 flbas;
1032 u32 lba_length;
1033
1034 if (llbaa == 0 && len < MODE_PAGE_BLK_DES_LEN)
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001035 return -EINVAL;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001036 else if (llbaa > 0 && len < MODE_PAGE_LLBAA_BLK_DES_LEN)
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001037 return -EINVAL;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001038
Christoph Hellwige75ec752015-05-22 11:12:39 +02001039 mem = dma_alloc_coherent(dev->dev, sizeof(struct nvme_id_ns),
Vishal Verma5d0f6132013-03-04 18:40:58 -07001040 &dma_addr, GFP_KERNEL);
1041 if (mem == NULL) {
1042 res = -ENOMEM;
1043 goto out;
1044 }
1045
1046 /* nvme ns identify */
1047 nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
1048 res = nvme_trans_status_code(hdr, nvme_sc);
1049 if (res)
1050 goto out_dma;
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001051
Vishal Verma5d0f6132013-03-04 18:40:58 -07001052 id_ns = mem;
1053 flbas = (id_ns->flbas) & 0x0F;
1054 lba_length = (1 << (id_ns->lbaf[flbas].ds));
1055
1056 if (llbaa == 0) {
Vishal Verma8741ee42013-04-04 17:52:27 -06001057 __be32 tmp_cap = cpu_to_be32(le64_to_cpu(id_ns->ncap));
Vishal Verma5d0f6132013-03-04 18:40:58 -07001058 /* Byte 4 is reserved */
Vishal Verma8741ee42013-04-04 17:52:27 -06001059 __be32 tmp_len = cpu_to_be32(lba_length & 0x00FFFFFF);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001060
1061 memcpy(resp, &tmp_cap, sizeof(u32));
1062 memcpy(&resp[4], &tmp_len, sizeof(u32));
1063 } else {
Vishal Verma8741ee42013-04-04 17:52:27 -06001064 __be64 tmp_cap = cpu_to_be64(le64_to_cpu(id_ns->ncap));
1065 __be32 tmp_len = cpu_to_be32(lba_length);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001066
1067 memcpy(resp, &tmp_cap, sizeof(u64));
1068 /* Bytes 8, 9, 10, 11 are reserved */
1069 memcpy(&resp[12], &tmp_len, sizeof(u32));
1070 }
1071
1072 out_dma:
Christoph Hellwige75ec752015-05-22 11:12:39 +02001073 dma_free_coherent(dev->dev, sizeof(struct nvme_id_ns), mem, dma_addr);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001074 out:
1075 return res;
1076}
1077
1078static int nvme_trans_fill_control_page(struct nvme_ns *ns,
1079 struct sg_io_hdr *hdr, u8 *resp,
1080 int len)
1081{
1082 if (len < MODE_PAGE_CONTROL_LEN)
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001083 return -EINVAL;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001084
1085 resp[0] = MODE_PAGE_CONTROL;
1086 resp[1] = MODE_PAGE_CONTROL_LEN_FIELD;
1087 resp[2] = 0x0E; /* TST=000b, TMF_ONLY=0, DPICZ=1,
1088 * D_SENSE=1, GLTSD=1, RLEC=0 */
1089 resp[3] = 0x12; /* Q_ALGO_MODIFIER=1h, NUAR=0, QERR=01b */
1090 /* Byte 4: VS=0, RAC=0, UA_INT=0, SWP=0 */
1091 resp[5] = 0x40; /* ATO=0, TAS=1, ATMPE=0, RWWP=0, AUTOLOAD=0 */
1092 /* resp[6] and [7] are obsolete, thus zero */
1093 resp[8] = 0xFF; /* Busy timeout period = 0xffff */
1094 resp[9] = 0xFF;
1095 /* Bytes 10,11: Extended selftest completion time = 0x0000 */
1096
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001097 return 0;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001098}
1099
1100static int nvme_trans_fill_caching_page(struct nvme_ns *ns,
1101 struct sg_io_hdr *hdr,
1102 u8 *resp, int len)
1103{
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001104 int res = 0;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001105 int nvme_sc;
1106 struct nvme_dev *dev = ns->dev;
1107 u32 feature_resp;
1108 u8 vwc;
1109
1110 if (len < MODE_PAGE_CACHING_LEN)
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001111 return -EINVAL;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001112
1113 nvme_sc = nvme_get_features(dev, NVME_FEAT_VOLATILE_WC, 0, 0,
1114 &feature_resp);
1115 res = nvme_trans_status_code(hdr, nvme_sc);
1116 if (res)
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001117 return res;
1118
Vishal Verma5d0f6132013-03-04 18:40:58 -07001119 vwc = feature_resp & 0x00000001;
1120
1121 resp[0] = MODE_PAGE_CACHING;
1122 resp[1] = MODE_PAGE_CACHING_LEN_FIELD;
1123 resp[2] = vwc << 2;
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001124 return 0;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001125}
1126
1127static int nvme_trans_fill_pow_cnd_page(struct nvme_ns *ns,
1128 struct sg_io_hdr *hdr, u8 *resp,
1129 int len)
1130{
Vishal Verma5d0f6132013-03-04 18:40:58 -07001131 if (len < MODE_PAGE_POW_CND_LEN)
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001132 return -EINVAL;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001133
1134 resp[0] = MODE_PAGE_POWER_CONDITION;
1135 resp[1] = MODE_PAGE_POW_CND_LEN_FIELD;
1136 /* All other bytes are zero */
1137
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001138 return 0;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001139}
1140
1141static int nvme_trans_fill_inf_exc_page(struct nvme_ns *ns,
1142 struct sg_io_hdr *hdr, u8 *resp,
1143 int len)
1144{
Vishal Verma5d0f6132013-03-04 18:40:58 -07001145 if (len < MODE_PAGE_INF_EXC_LEN)
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001146 return -EINVAL;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001147
1148 resp[0] = MODE_PAGE_INFO_EXCEP;
1149 resp[1] = MODE_PAGE_INF_EXC_LEN_FIELD;
1150 resp[2] = 0x88;
1151 /* All other bytes are zero */
1152
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001153 return 0;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001154}
1155
1156static int nvme_trans_fill_all_pages(struct nvme_ns *ns, struct sg_io_hdr *hdr,
1157 u8 *resp, int len)
1158{
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001159 int res;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001160 u16 mode_pages_offset_1 = 0;
1161 u16 mode_pages_offset_2, mode_pages_offset_3, mode_pages_offset_4;
1162
1163 mode_pages_offset_2 = mode_pages_offset_1 + MODE_PAGE_CACHING_LEN;
1164 mode_pages_offset_3 = mode_pages_offset_2 + MODE_PAGE_CONTROL_LEN;
1165 mode_pages_offset_4 = mode_pages_offset_3 + MODE_PAGE_POW_CND_LEN;
1166
1167 res = nvme_trans_fill_caching_page(ns, hdr, &resp[mode_pages_offset_1],
1168 MODE_PAGE_CACHING_LEN);
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001169 if (res)
1170 return res;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001171 res = nvme_trans_fill_control_page(ns, hdr, &resp[mode_pages_offset_2],
1172 MODE_PAGE_CONTROL_LEN);
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001173 if (res)
1174 return res;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001175 res = nvme_trans_fill_pow_cnd_page(ns, hdr, &resp[mode_pages_offset_3],
1176 MODE_PAGE_POW_CND_LEN);
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001177 if (res)
1178 return res;
1179 return nvme_trans_fill_inf_exc_page(ns, hdr, &resp[mode_pages_offset_4],
Vishal Verma5d0f6132013-03-04 18:40:58 -07001180 MODE_PAGE_INF_EXC_LEN);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001181}
1182
1183static inline int nvme_trans_get_blk_desc_len(u8 dbd, u8 llbaa)
1184{
1185 if (dbd == MODE_SENSE_BLK_DESC_ENABLED) {
1186 /* SPC-4: len = 8 x Num_of_descriptors if llbaa = 0, 16x if 1 */
1187 return 8 * (llbaa + 1) * MODE_SENSE_BLK_DESC_COUNT;
1188 } else {
1189 return 0;
1190 }
1191}
1192
1193static int nvme_trans_mode_page_create(struct nvme_ns *ns,
1194 struct sg_io_hdr *hdr, u8 *cmd,
1195 u16 alloc_len, u8 cdb10,
1196 int (*mode_page_fill_func)
1197 (struct nvme_ns *,
1198 struct sg_io_hdr *hdr, u8 *, int),
1199 u16 mode_pages_tot_len)
1200{
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001201 int res;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001202 int xfer_len;
1203 u8 *response;
1204 u8 dbd, llbaa;
1205 u16 resp_size;
1206 int mph_size;
1207 u16 mode_pages_offset_1;
1208 u16 blk_desc_len, blk_desc_offset, mode_data_length;
1209
Christoph Hellwig37268972015-05-22 11:12:42 +02001210 dbd = (cmd[1] & MODE_SENSE_DBD_MASK) >> MODE_SENSE_DBD_SHIFT;
1211 llbaa = (cmd[1] & MODE_SENSE_LLBAA_MASK) >> MODE_SENSE_LLBAA_SHIFT;
1212 mph_size = cdb10 ? MODE_SENSE10_MPH_SIZE : MODE_SENSE6_MPH_SIZE;
1213
Vishal Verma5d0f6132013-03-04 18:40:58 -07001214 blk_desc_len = nvme_trans_get_blk_desc_len(dbd, llbaa);
1215
1216 resp_size = mph_size + blk_desc_len + mode_pages_tot_len;
1217 /* Refer spc4r34 Table 440 for calculation of Mode data Length field */
1218 mode_data_length = 3 + (3 * cdb10) + blk_desc_len + mode_pages_tot_len;
1219
1220 blk_desc_offset = mph_size;
1221 mode_pages_offset_1 = blk_desc_offset + blk_desc_len;
1222
Tushar Behera03ea83e2013-06-10 10:20:55 +05301223 response = kzalloc(resp_size, GFP_KERNEL);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001224 if (response == NULL) {
1225 res = -ENOMEM;
1226 goto out_mem;
1227 }
Vishal Verma5d0f6132013-03-04 18:40:58 -07001228
1229 res = nvme_trans_fill_mode_parm_hdr(&response[0], mph_size, cdb10,
1230 llbaa, mode_data_length, blk_desc_len);
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001231 if (res)
Vishal Verma5d0f6132013-03-04 18:40:58 -07001232 goto out_free;
1233 if (blk_desc_len > 0) {
1234 res = nvme_trans_fill_blk_desc(ns, hdr,
1235 &response[blk_desc_offset],
1236 blk_desc_len, llbaa);
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001237 if (res)
Vishal Verma5d0f6132013-03-04 18:40:58 -07001238 goto out_free;
1239 }
1240 res = mode_page_fill_func(ns, hdr, &response[mode_pages_offset_1],
1241 mode_pages_tot_len);
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001242 if (res)
Vishal Verma5d0f6132013-03-04 18:40:58 -07001243 goto out_free;
1244
1245 xfer_len = min(alloc_len, resp_size);
1246 res = nvme_trans_copy_to_user(hdr, response, xfer_len);
1247
1248 out_free:
1249 kfree(response);
1250 out_mem:
1251 return res;
1252}
1253
1254/* Read Capacity Helper Functions */
1255
1256static void nvme_trans_fill_read_cap(u8 *response, struct nvme_id_ns *id_ns,
1257 u8 cdb16)
1258{
1259 u8 flbas;
1260 u32 lba_length;
1261 u64 rlba;
1262 u8 prot_en;
1263 u8 p_type_lut[4] = {0, 0, 1, 2};
Vishal Verma8741ee42013-04-04 17:52:27 -06001264 __be64 tmp_rlba;
1265 __be32 tmp_rlba_32;
1266 __be32 tmp_len;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001267
1268 flbas = (id_ns->flbas) & 0x0F;
1269 lba_length = (1 << (id_ns->lbaf[flbas].ds));
1270 rlba = le64_to_cpup(&id_ns->nsze) - 1;
1271 (id_ns->dps) ? (prot_en = 0x01) : (prot_en = 0);
1272
1273 if (!cdb16) {
1274 if (rlba > 0xFFFFFFFF)
1275 rlba = 0xFFFFFFFF;
1276 tmp_rlba_32 = cpu_to_be32(rlba);
1277 tmp_len = cpu_to_be32(lba_length);
1278 memcpy(response, &tmp_rlba_32, sizeof(u32));
1279 memcpy(&response[4], &tmp_len, sizeof(u32));
1280 } else {
1281 tmp_rlba = cpu_to_be64(rlba);
1282 tmp_len = cpu_to_be32(lba_length);
1283 memcpy(response, &tmp_rlba, sizeof(u64));
1284 memcpy(&response[8], &tmp_len, sizeof(u32));
1285 response[12] = (p_type_lut[id_ns->dps & 0x3] << 1) | prot_en;
1286 /* P_I_Exponent = 0x0 | LBPPBE = 0x0 */
1287 /* LBPME = 0 | LBPRZ = 0 | LALBA = 0x00 */
1288 /* Bytes 16-31 - Reserved */
1289 }
1290}
1291
1292/* Start Stop Unit Helper Functions */
1293
1294static int nvme_trans_power_state(struct nvme_ns *ns, struct sg_io_hdr *hdr,
1295 u8 pc, u8 pcmod, u8 start)
1296{
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001297 int res;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001298 int nvme_sc;
1299 struct nvme_dev *dev = ns->dev;
1300 dma_addr_t dma_addr;
1301 void *mem;
1302 struct nvme_id_ctrl *id_ctrl;
1303 int lowest_pow_st; /* max npss = lowest power consumption */
1304 unsigned ps_desired = 0;
1305
1306 /* NVMe Controller Identify */
Christoph Hellwige75ec752015-05-22 11:12:39 +02001307 mem = dma_alloc_coherent(dev->dev, sizeof(struct nvme_id_ctrl),
Vishal Verma5d0f6132013-03-04 18:40:58 -07001308 &dma_addr, GFP_KERNEL);
1309 if (mem == NULL) {
1310 res = -ENOMEM;
1311 goto out;
1312 }
1313 nvme_sc = nvme_identify(dev, 0, 1, dma_addr);
1314 res = nvme_trans_status_code(hdr, nvme_sc);
1315 if (res)
1316 goto out_dma;
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001317
Vishal Verma5d0f6132013-03-04 18:40:58 -07001318 id_ctrl = mem;
Dan McLeranb8e08082014-06-06 08:27:27 -06001319 lowest_pow_st = max(POWER_STATE_0, (int)(id_ctrl->npss - 1));
Vishal Verma5d0f6132013-03-04 18:40:58 -07001320
1321 switch (pc) {
1322 case NVME_POWER_STATE_START_VALID:
1323 /* Action unspecified if POWER CONDITION MODIFIER != 0 */
1324 if (pcmod == 0 && start == 0x1)
1325 ps_desired = POWER_STATE_0;
1326 if (pcmod == 0 && start == 0x0)
1327 ps_desired = lowest_pow_st;
1328 break;
1329 case NVME_POWER_STATE_ACTIVE:
1330 /* Action unspecified if POWER CONDITION MODIFIER != 0 */
1331 if (pcmod == 0)
1332 ps_desired = POWER_STATE_0;
1333 break;
1334 case NVME_POWER_STATE_IDLE:
1335 /* Action unspecified if POWER CONDITION MODIFIER != [0,1,2] */
Vishal Verma5d0f6132013-03-04 18:40:58 -07001336 if (pcmod == 0x0)
Dan McLeranb8e08082014-06-06 08:27:27 -06001337 ps_desired = POWER_STATE_1;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001338 else if (pcmod == 0x1)
Dan McLeranb8e08082014-06-06 08:27:27 -06001339 ps_desired = POWER_STATE_2;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001340 else if (pcmod == 0x2)
Dan McLeranb8e08082014-06-06 08:27:27 -06001341 ps_desired = POWER_STATE_3;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001342 break;
1343 case NVME_POWER_STATE_STANDBY:
1344 /* Action unspecified if POWER CONDITION MODIFIER != [0,1] */
1345 if (pcmod == 0x0)
Dan McLeranb8e08082014-06-06 08:27:27 -06001346 ps_desired = max(POWER_STATE_0, (lowest_pow_st - 2));
Vishal Verma5d0f6132013-03-04 18:40:58 -07001347 else if (pcmod == 0x1)
Dan McLeranb8e08082014-06-06 08:27:27 -06001348 ps_desired = max(POWER_STATE_0, (lowest_pow_st - 1));
Vishal Verma5d0f6132013-03-04 18:40:58 -07001349 break;
1350 case NVME_POWER_STATE_LU_CONTROL:
1351 default:
1352 res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
1353 ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
1354 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
1355 break;
1356 }
1357 nvme_sc = nvme_set_features(dev, NVME_FEAT_POWER_MGMT, ps_desired, 0,
1358 NULL);
1359 res = nvme_trans_status_code(hdr, nvme_sc);
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001360
Vishal Verma5d0f6132013-03-04 18:40:58 -07001361 out_dma:
Christoph Hellwige75ec752015-05-22 11:12:39 +02001362 dma_free_coherent(dev->dev, sizeof(struct nvme_id_ctrl), mem, dma_addr);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001363 out:
1364 return res;
1365}
1366
Christoph Hellwigb90c48d2015-05-22 11:12:40 +02001367static int nvme_trans_send_activate_fw_cmd(struct nvme_ns *ns, struct sg_io_hdr *hdr,
1368 u8 buffer_id)
1369{
1370 struct nvme_command c;
1371 int nvme_sc;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001372
Christoph Hellwigb90c48d2015-05-22 11:12:40 +02001373 memset(&c, 0, sizeof(c));
1374 c.common.opcode = nvme_admin_activate_fw;
1375 c.common.cdw10[0] = cpu_to_le32(buffer_id | NVME_FWACT_REPL_ACTV);
1376
1377 nvme_sc = nvme_submit_sync_cmd(ns->queue, &c);
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001378 return nvme_trans_status_code(hdr, nvme_sc);
Christoph Hellwigb90c48d2015-05-22 11:12:40 +02001379}
1380
1381static int nvme_trans_send_download_fw_cmd(struct nvme_ns *ns, struct sg_io_hdr *hdr,
Vishal Verma5d0f6132013-03-04 18:40:58 -07001382 u8 opcode, u32 tot_len, u32 offset,
1383 u8 buffer_id)
1384{
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001385 int res;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001386 int nvme_sc;
1387 struct nvme_dev *dev = ns->dev;
1388 struct nvme_command c;
1389 struct nvme_iod *iod = NULL;
1390 unsigned length;
1391
1392 memset(&c, 0, sizeof(c));
Christoph Hellwigb90c48d2015-05-22 11:12:40 +02001393 c.common.opcode = nvme_admin_download_fw;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001394
Christoph Hellwigb90c48d2015-05-22 11:12:40 +02001395 if (hdr->iovec_count > 0) {
1396 /* Assuming SGL is not allowed for this command */
1397 return nvme_trans_completion(hdr,
1398 SAM_STAT_CHECK_CONDITION,
1399 ILLEGAL_REQUEST,
1400 SCSI_ASC_INVALID_CDB,
1401 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001402 }
Christoph Hellwigb90c48d2015-05-22 11:12:40 +02001403 iod = nvme_map_user_pages(dev, DMA_TO_DEVICE,
1404 (unsigned long)hdr->dxferp, tot_len);
1405 if (IS_ERR(iod))
1406 return PTR_ERR(iod);
1407 length = nvme_setup_prps(dev, iod, tot_len, GFP_KERNEL);
1408 if (length != tot_len) {
1409 res = -ENOMEM;
1410 goto out_unmap;
1411 }
1412
1413 c.dlfw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1414 c.dlfw.prp2 = cpu_to_le64(iod->first_dma);
1415 c.dlfw.numd = cpu_to_le32((tot_len/BYTES_TO_DWORDS) - 1);
1416 c.dlfw.offset = cpu_to_le32(offset/BYTES_TO_DWORDS);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001417
Christoph Hellwigf705f832015-05-22 11:12:38 +02001418 nvme_sc = nvme_submit_sync_cmd(dev->admin_q, &c);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001419 res = nvme_trans_status_code(hdr, nvme_sc);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001420
1421 out_unmap:
Christoph Hellwigb90c48d2015-05-22 11:12:40 +02001422 nvme_unmap_user_pages(dev, DMA_TO_DEVICE, iod);
1423 nvme_free_iod(dev, iod);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001424 return res;
1425}
1426
1427/* Mode Select Helper Functions */
1428
1429static inline void nvme_trans_modesel_get_bd_len(u8 *parm_list, u8 cdb10,
1430 u16 *bd_len, u8 *llbaa)
1431{
1432 if (cdb10) {
1433 /* 10 Byte CDB */
1434 *bd_len = (parm_list[MODE_SELECT_10_BD_OFFSET] << 8) +
1435 parm_list[MODE_SELECT_10_BD_OFFSET + 1];
Keith Busch9ac16932015-01-09 16:52:08 -07001436 *llbaa = parm_list[MODE_SELECT_10_LLBAA_OFFSET] &
Vishal Verma5d0f6132013-03-04 18:40:58 -07001437 MODE_SELECT_10_LLBAA_MASK;
1438 } else {
1439 /* 6 Byte CDB */
1440 *bd_len = parm_list[MODE_SELECT_6_BD_OFFSET];
1441 }
1442}
1443
1444static void nvme_trans_modesel_save_bd(struct nvme_ns *ns, u8 *parm_list,
1445 u16 idx, u16 bd_len, u8 llbaa)
1446{
1447 u16 bd_num;
1448
1449 bd_num = bd_len / ((llbaa == 0) ?
1450 SHORT_DESC_BLOCK : LONG_DESC_BLOCK);
1451 /* Store block descriptor info if a FORMAT UNIT comes later */
1452 /* TODO Saving 1st BD info; what to do if multiple BD received? */
1453 if (llbaa == 0) {
1454 /* Standard Block Descriptor - spc4r34 7.5.5.1 */
1455 ns->mode_select_num_blocks =
1456 (parm_list[idx + 1] << 16) +
1457 (parm_list[idx + 2] << 8) +
1458 (parm_list[idx + 3]);
1459
1460 ns->mode_select_block_len =
1461 (parm_list[idx + 5] << 16) +
1462 (parm_list[idx + 6] << 8) +
1463 (parm_list[idx + 7]);
1464 } else {
1465 /* Long LBA Block Descriptor - sbc3r27 6.4.2.3 */
1466 ns->mode_select_num_blocks =
1467 (((u64)parm_list[idx + 0]) << 56) +
1468 (((u64)parm_list[idx + 1]) << 48) +
1469 (((u64)parm_list[idx + 2]) << 40) +
1470 (((u64)parm_list[idx + 3]) << 32) +
1471 (((u64)parm_list[idx + 4]) << 24) +
1472 (((u64)parm_list[idx + 5]) << 16) +
1473 (((u64)parm_list[idx + 6]) << 8) +
1474 ((u64)parm_list[idx + 7]);
1475
1476 ns->mode_select_block_len =
1477 (parm_list[idx + 12] << 24) +
1478 (parm_list[idx + 13] << 16) +
1479 (parm_list[idx + 14] << 8) +
1480 (parm_list[idx + 15]);
1481 }
1482}
1483
Vishal Verma710a1432013-05-13 14:55:18 -06001484static int nvme_trans_modesel_get_mp(struct nvme_ns *ns, struct sg_io_hdr *hdr,
Vishal Verma5d0f6132013-03-04 18:40:58 -07001485 u8 *mode_page, u8 page_code)
1486{
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001487 int res = 0;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001488 int nvme_sc;
1489 struct nvme_dev *dev = ns->dev;
1490 unsigned dword11;
1491
1492 switch (page_code) {
1493 case MODE_PAGE_CACHING:
1494 dword11 = ((mode_page[2] & CACHING_MODE_PAGE_WCE_MASK) ? 1 : 0);
1495 nvme_sc = nvme_set_features(dev, NVME_FEAT_VOLATILE_WC, dword11,
1496 0, NULL);
1497 res = nvme_trans_status_code(hdr, nvme_sc);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001498 break;
1499 case MODE_PAGE_CONTROL:
1500 break;
1501 case MODE_PAGE_POWER_CONDITION:
1502 /* Verify the OS is not trying to set timers */
1503 if ((mode_page[2] & 0x01) != 0 || (mode_page[3] & 0x0F) != 0) {
1504 res = nvme_trans_completion(hdr,
1505 SAM_STAT_CHECK_CONDITION,
1506 ILLEGAL_REQUEST,
1507 SCSI_ASC_INVALID_PARAMETER,
1508 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001509 break;
1510 }
1511 break;
1512 default:
1513 res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
1514 ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
1515 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001516 break;
1517 }
1518
1519 return res;
1520}
1521
1522static int nvme_trans_modesel_data(struct nvme_ns *ns, struct sg_io_hdr *hdr,
1523 u8 *cmd, u16 parm_list_len, u8 pf,
1524 u8 sp, u8 cdb10)
1525{
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001526 int res;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001527 u8 *parm_list;
1528 u16 bd_len;
1529 u8 llbaa = 0;
1530 u16 index, saved_index;
1531 u8 page_code;
1532 u16 mp_size;
1533
1534 /* Get parm list from data-in/out buffer */
1535 parm_list = kmalloc(parm_list_len, GFP_KERNEL);
1536 if (parm_list == NULL) {
1537 res = -ENOMEM;
1538 goto out;
1539 }
1540
1541 res = nvme_trans_copy_from_user(hdr, parm_list, parm_list_len);
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001542 if (res)
Vishal Verma5d0f6132013-03-04 18:40:58 -07001543 goto out_mem;
1544
1545 nvme_trans_modesel_get_bd_len(parm_list, cdb10, &bd_len, &llbaa);
1546 index = (cdb10) ? (MODE_SELECT_10_MPH_SIZE) : (MODE_SELECT_6_MPH_SIZE);
1547
1548 if (bd_len != 0) {
1549 /* Block Descriptors present, parse */
1550 nvme_trans_modesel_save_bd(ns, parm_list, index, bd_len, llbaa);
1551 index += bd_len;
1552 }
1553 saved_index = index;
1554
1555 /* Multiple mode pages may be present; iterate through all */
1556 /* In 1st Iteration, don't do NVME Command, only check for CDB errors */
1557 do {
1558 page_code = parm_list[index] & MODE_SELECT_PAGE_CODE_MASK;
1559 mp_size = parm_list[index + 1] + 2;
1560 if ((page_code != MODE_PAGE_CACHING) &&
1561 (page_code != MODE_PAGE_CONTROL) &&
1562 (page_code != MODE_PAGE_POWER_CONDITION)) {
1563 res = nvme_trans_completion(hdr,
1564 SAM_STAT_CHECK_CONDITION,
1565 ILLEGAL_REQUEST,
1566 SCSI_ASC_INVALID_CDB,
1567 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
1568 goto out_mem;
1569 }
1570 index += mp_size;
1571 } while (index < parm_list_len);
1572
1573 /* In 2nd Iteration, do the NVME Commands */
1574 index = saved_index;
1575 do {
1576 page_code = parm_list[index] & MODE_SELECT_PAGE_CODE_MASK;
1577 mp_size = parm_list[index + 1] + 2;
1578 res = nvme_trans_modesel_get_mp(ns, hdr, &parm_list[index],
1579 page_code);
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001580 if (res)
Vishal Verma5d0f6132013-03-04 18:40:58 -07001581 break;
1582 index += mp_size;
1583 } while (index < parm_list_len);
1584
1585 out_mem:
1586 kfree(parm_list);
1587 out:
1588 return res;
1589}
1590
1591/* Format Unit Helper Functions */
1592
1593static int nvme_trans_fmt_set_blk_size_count(struct nvme_ns *ns,
1594 struct sg_io_hdr *hdr)
1595{
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001596 int res = 0;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001597 int nvme_sc;
1598 struct nvme_dev *dev = ns->dev;
1599 dma_addr_t dma_addr;
1600 void *mem;
1601 struct nvme_id_ns *id_ns;
1602 u8 flbas;
1603
1604 /*
1605 * SCSI Expects a MODE SELECT would have been issued prior to
1606 * a FORMAT UNIT, and the block size and number would be used
1607 * from the block descriptor in it. If a MODE SELECT had not
1608 * been issued, FORMAT shall use the current values for both.
1609 */
1610
1611 if (ns->mode_select_num_blocks == 0 || ns->mode_select_block_len == 0) {
Christoph Hellwige75ec752015-05-22 11:12:39 +02001612 mem = dma_alloc_coherent(dev->dev,
Vishal Verma5d0f6132013-03-04 18:40:58 -07001613 sizeof(struct nvme_id_ns), &dma_addr, GFP_KERNEL);
1614 if (mem == NULL) {
1615 res = -ENOMEM;
1616 goto out;
1617 }
1618 /* nvme ns identify */
1619 nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
1620 res = nvme_trans_status_code(hdr, nvme_sc);
1621 if (res)
1622 goto out_dma;
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001623
Vishal Verma5d0f6132013-03-04 18:40:58 -07001624 id_ns = mem;
1625
1626 if (ns->mode_select_num_blocks == 0)
Vishal Verma8741ee42013-04-04 17:52:27 -06001627 ns->mode_select_num_blocks = le64_to_cpu(id_ns->ncap);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001628 if (ns->mode_select_block_len == 0) {
1629 flbas = (id_ns->flbas) & 0x0F;
1630 ns->mode_select_block_len =
1631 (1 << (id_ns->lbaf[flbas].ds));
1632 }
1633 out_dma:
Christoph Hellwige75ec752015-05-22 11:12:39 +02001634 dma_free_coherent(dev->dev, sizeof(struct nvme_id_ns),
Vishal Verma5d0f6132013-03-04 18:40:58 -07001635 mem, dma_addr);
1636 }
1637 out:
1638 return res;
1639}
1640
1641static int nvme_trans_fmt_get_parm_header(struct sg_io_hdr *hdr, u8 len,
1642 u8 format_prot_info, u8 *nvme_pf_code)
1643{
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001644 int res;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001645 u8 *parm_list;
1646 u8 pf_usage, pf_code;
1647
1648 parm_list = kmalloc(len, GFP_KERNEL);
1649 if (parm_list == NULL) {
1650 res = -ENOMEM;
1651 goto out;
1652 }
1653 res = nvme_trans_copy_from_user(hdr, parm_list, len);
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001654 if (res)
Vishal Verma5d0f6132013-03-04 18:40:58 -07001655 goto out_mem;
1656
1657 if ((parm_list[FORMAT_UNIT_IMMED_OFFSET] &
1658 FORMAT_UNIT_IMMED_MASK) != 0) {
1659 res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
1660 ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
1661 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
1662 goto out_mem;
1663 }
1664
1665 if (len == FORMAT_UNIT_LONG_PARM_LIST_LEN &&
1666 (parm_list[FORMAT_UNIT_PROT_INT_OFFSET] & 0x0F) != 0) {
1667 res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
1668 ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
1669 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
1670 goto out_mem;
1671 }
1672 pf_usage = parm_list[FORMAT_UNIT_PROT_FIELD_USAGE_OFFSET] &
1673 FORMAT_UNIT_PROT_FIELD_USAGE_MASK;
1674 pf_code = (pf_usage << 2) | format_prot_info;
1675 switch (pf_code) {
1676 case 0:
1677 *nvme_pf_code = 0;
1678 break;
1679 case 2:
1680 *nvme_pf_code = 1;
1681 break;
1682 case 3:
1683 *nvme_pf_code = 2;
1684 break;
1685 case 7:
1686 *nvme_pf_code = 3;
1687 break;
1688 default:
1689 res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
1690 ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
1691 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
1692 break;
1693 }
1694
1695 out_mem:
1696 kfree(parm_list);
1697 out:
1698 return res;
1699}
1700
1701static int nvme_trans_fmt_send_cmd(struct nvme_ns *ns, struct sg_io_hdr *hdr,
1702 u8 prot_info)
1703{
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001704 int res;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001705 int nvme_sc;
1706 struct nvme_dev *dev = ns->dev;
1707 dma_addr_t dma_addr;
1708 void *mem;
1709 struct nvme_id_ns *id_ns;
1710 u8 i;
1711 u8 flbas, nlbaf;
1712 u8 selected_lbaf = 0xFF;
1713 u32 cdw10 = 0;
1714 struct nvme_command c;
1715
1716 /* Loop thru LBAF's in id_ns to match reqd lbaf, put in cdw10 */
Christoph Hellwige75ec752015-05-22 11:12:39 +02001717 mem = dma_alloc_coherent(dev->dev, sizeof(struct nvme_id_ns),
Vishal Verma5d0f6132013-03-04 18:40:58 -07001718 &dma_addr, GFP_KERNEL);
1719 if (mem == NULL) {
1720 res = -ENOMEM;
1721 goto out;
1722 }
1723 /* nvme ns identify */
1724 nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
1725 res = nvme_trans_status_code(hdr, nvme_sc);
1726 if (res)
1727 goto out_dma;
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001728
Vishal Verma5d0f6132013-03-04 18:40:58 -07001729 id_ns = mem;
1730 flbas = (id_ns->flbas) & 0x0F;
1731 nlbaf = id_ns->nlbaf;
1732
1733 for (i = 0; i < nlbaf; i++) {
1734 if (ns->mode_select_block_len == (1 << (id_ns->lbaf[i].ds))) {
1735 selected_lbaf = i;
1736 break;
1737 }
1738 }
1739 if (selected_lbaf > 0x0F) {
1740 res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
1741 ILLEGAL_REQUEST, SCSI_ASC_INVALID_PARAMETER,
1742 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
1743 }
Vishal Verma8741ee42013-04-04 17:52:27 -06001744 if (ns->mode_select_num_blocks != le64_to_cpu(id_ns->ncap)) {
Vishal Verma5d0f6132013-03-04 18:40:58 -07001745 res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
1746 ILLEGAL_REQUEST, SCSI_ASC_INVALID_PARAMETER,
1747 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
1748 }
1749
1750 cdw10 |= prot_info << 5;
1751 cdw10 |= selected_lbaf & 0x0F;
1752 memset(&c, 0, sizeof(c));
1753 c.format.opcode = nvme_admin_format_nvm;
Vishal Verma8741ee42013-04-04 17:52:27 -06001754 c.format.nsid = cpu_to_le32(ns->ns_id);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001755 c.format.cdw10 = cpu_to_le32(cdw10);
1756
Christoph Hellwigf705f832015-05-22 11:12:38 +02001757 nvme_sc = nvme_submit_sync_cmd(dev->admin_q, &c);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001758 res = nvme_trans_status_code(hdr, nvme_sc);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001759
1760 out_dma:
Christoph Hellwige75ec752015-05-22 11:12:39 +02001761 dma_free_coherent(dev->dev, sizeof(struct nvme_id_ns), mem, dma_addr);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001762 out:
1763 return res;
1764}
1765
1766/* Read/Write Helper Functions */
1767
1768static inline void nvme_trans_get_io_cdb6(u8 *cmd,
1769 struct nvme_trans_io_cdb *cdb_info)
1770{
1771 cdb_info->fua = 0;
1772 cdb_info->prot_info = 0;
Christoph Hellwig37268972015-05-22 11:12:42 +02001773 cdb_info->lba = get_unaligned_be32(&cmd[0]) & IO_6_CDB_LBA_MASK;
1774 cdb_info->xfer_len = cmd[4];
Vishal Verma5d0f6132013-03-04 18:40:58 -07001775
1776 /* sbc3r27 sec 5.32 - TRANSFER LEN of 0 implies a 256 Block transfer */
1777 if (cdb_info->xfer_len == 0)
Christoph Hellwig37268972015-05-22 11:12:42 +02001778 cdb_info->xfer_len = 256;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001779}
1780
1781static inline void nvme_trans_get_io_cdb10(u8 *cmd,
1782 struct nvme_trans_io_cdb *cdb_info)
1783{
Christoph Hellwig37268972015-05-22 11:12:42 +02001784 cdb_info->fua = cmd[1] & IO_CDB_FUA_MASK;
1785 cdb_info->prot_info = cmd[1] & IO_CDB_WP_MASK >> IO_CDB_WP_SHIFT;
1786 cdb_info->lba = get_unaligned_be32(&cmd[2]);
1787 cdb_info->xfer_len = get_unaligned_be16(&cmd[7]);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001788}
1789
1790static inline void nvme_trans_get_io_cdb12(u8 *cmd,
1791 struct nvme_trans_io_cdb *cdb_info)
1792{
Christoph Hellwig37268972015-05-22 11:12:42 +02001793 cdb_info->fua = cmd[1] & IO_CDB_FUA_MASK;
1794 cdb_info->prot_info = cmd[1] & IO_CDB_WP_MASK >> IO_CDB_WP_SHIFT;
1795 cdb_info->lba = get_unaligned_be32(&cmd[2]);
1796 cdb_info->xfer_len = get_unaligned_be32(&cmd[6]);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001797}
1798
1799static inline void nvme_trans_get_io_cdb16(u8 *cmd,
1800 struct nvme_trans_io_cdb *cdb_info)
1801{
Christoph Hellwig37268972015-05-22 11:12:42 +02001802 cdb_info->fua = cmd[1] & IO_CDB_FUA_MASK;
1803 cdb_info->prot_info = cmd[1] & IO_CDB_WP_MASK >> IO_CDB_WP_SHIFT;
1804 cdb_info->lba = get_unaligned_be64(&cmd[2]);
1805 cdb_info->xfer_len = get_unaligned_be32(&cmd[10]);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001806}
1807
1808static inline u32 nvme_trans_io_get_num_cmds(struct sg_io_hdr *hdr,
1809 struct nvme_trans_io_cdb *cdb_info,
1810 u32 max_blocks)
1811{
1812 /* If using iovecs, send one nvme command per vector */
1813 if (hdr->iovec_count > 0)
1814 return hdr->iovec_count;
1815 else if (cdb_info->xfer_len > max_blocks)
1816 return ((cdb_info->xfer_len - 1) / max_blocks) + 1;
1817 else
1818 return 1;
1819}
1820
1821static u16 nvme_trans_io_get_control(struct nvme_ns *ns,
1822 struct nvme_trans_io_cdb *cdb_info)
1823{
1824 u16 control = 0;
1825
1826 /* When Protection information support is added, implement here */
1827
1828 if (cdb_info->fua > 0)
1829 control |= NVME_RW_FUA;
1830
1831 return control;
1832}
1833
1834static int nvme_trans_do_nvme_io(struct nvme_ns *ns, struct sg_io_hdr *hdr,
1835 struct nvme_trans_io_cdb *cdb_info, u8 is_write)
1836{
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001837 int nvme_sc = NVME_SC_SUCCESS;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001838 struct nvme_dev *dev = ns->dev;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001839 u32 num_cmds;
1840 struct nvme_iod *iod;
1841 u64 unit_len;
1842 u64 unit_num_blocks; /* Number of blocks to xfer in each nvme cmd */
1843 u32 retcode;
1844 u32 i = 0;
1845 u64 nvme_offset = 0;
Vishal Verma8741ee42013-04-04 17:52:27 -06001846 void __user *next_mapping_addr;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001847 struct nvme_command c;
1848 u8 opcode = (is_write ? nvme_cmd_write : nvme_cmd_read);
1849 u16 control;
Keith Buschddcb7762014-03-24 10:03:56 -04001850 u32 max_blocks = queue_max_hw_sectors(ns->queue);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001851
1852 num_cmds = nvme_trans_io_get_num_cmds(hdr, cdb_info, max_blocks);
1853
1854 /*
1855 * This loop handles two cases.
1856 * First, when an SGL is used in the form of an iovec list:
1857 * - Use iov_base as the next mapping address for the nvme command_id
1858 * - Use iov_len as the data transfer length for the command.
1859 * Second, when we have a single buffer
1860 * - If larger than max_blocks, split into chunks, offset
1861 * each nvme command accordingly.
1862 */
1863 for (i = 0; i < num_cmds; i++) {
1864 memset(&c, 0, sizeof(c));
1865 if (hdr->iovec_count > 0) {
Vishal Verma8741ee42013-04-04 17:52:27 -06001866 struct sg_iovec sgl;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001867
Vishal Verma8741ee42013-04-04 17:52:27 -06001868 retcode = copy_from_user(&sgl, hdr->dxferp +
1869 i * sizeof(struct sg_iovec),
1870 sizeof(struct sg_iovec));
1871 if (retcode)
1872 return -EFAULT;
1873 unit_len = sgl.iov_len;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001874 unit_num_blocks = unit_len >> ns->lba_shift;
Vishal Verma8741ee42013-04-04 17:52:27 -06001875 next_mapping_addr = sgl.iov_base;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001876 } else {
1877 unit_num_blocks = min((u64)max_blocks,
1878 (cdb_info->xfer_len - nvme_offset));
1879 unit_len = unit_num_blocks << ns->lba_shift;
1880 next_mapping_addr = hdr->dxferp +
1881 ((1 << ns->lba_shift) * nvme_offset);
1882 }
1883
1884 c.rw.opcode = opcode;
1885 c.rw.nsid = cpu_to_le32(ns->ns_id);
1886 c.rw.slba = cpu_to_le64(cdb_info->lba + nvme_offset);
1887 c.rw.length = cpu_to_le16(unit_num_blocks - 1);
1888 control = nvme_trans_io_get_control(ns, cdb_info);
1889 c.rw.control = cpu_to_le16(control);
1890
1891 iod = nvme_map_user_pages(dev,
1892 (is_write) ? DMA_TO_DEVICE : DMA_FROM_DEVICE,
1893 (unsigned long)next_mapping_addr, unit_len);
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001894 if (IS_ERR(iod))
1895 return PTR_ERR(iod);
1896
Keith Buschedd10d32014-04-03 16:45:23 -06001897 retcode = nvme_setup_prps(dev, iod, unit_len, GFP_KERNEL);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001898 if (retcode != unit_len) {
1899 nvme_unmap_user_pages(dev,
1900 (is_write) ? DMA_TO_DEVICE : DMA_FROM_DEVICE,
1901 iod);
1902 nvme_free_iod(dev, iod);
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001903 return -ENOMEM;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001904 }
Keith Buschedd10d32014-04-03 16:45:23 -06001905 c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1906 c.rw.prp2 = cpu_to_le64(iod->first_dma);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001907
1908 nvme_offset += unit_num_blocks;
1909
Christoph Hellwigf705f832015-05-22 11:12:38 +02001910 nvme_sc = nvme_submit_sync_cmd(ns->queue, &c);
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001911
Vishal Verma5d0f6132013-03-04 18:40:58 -07001912 nvme_unmap_user_pages(dev,
1913 (is_write) ? DMA_TO_DEVICE : DMA_FROM_DEVICE,
1914 iod);
1915 nvme_free_iod(dev, iod);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001916
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001917
1918 if (nvme_sc != NVME_SC_SUCCESS)
1919 break;
1920 }
1921
1922 return nvme_trans_status_code(hdr, nvme_sc);
Vishal Verma5d0f6132013-03-04 18:40:58 -07001923}
1924
1925
1926/* SCSI Command Translation Functions */
1927
1928static int nvme_trans_io(struct nvme_ns *ns, struct sg_io_hdr *hdr, u8 is_write,
1929 u8 *cmd)
1930{
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001931 int res = 0;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001932 struct nvme_trans_io_cdb cdb_info;
1933 u8 opcode = cmd[0];
1934 u64 xfer_bytes;
1935 u64 sum_iov_len = 0;
Vishal Verma8741ee42013-04-04 17:52:27 -06001936 struct sg_iovec sgl;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001937 int i;
Vishal Verma8741ee42013-04-04 17:52:27 -06001938 size_t not_copied;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001939
1940 /* Extract Fields from CDB */
1941 switch (opcode) {
1942 case WRITE_6:
1943 case READ_6:
1944 nvme_trans_get_io_cdb6(cmd, &cdb_info);
1945 break;
1946 case WRITE_10:
1947 case READ_10:
1948 nvme_trans_get_io_cdb10(cmd, &cdb_info);
1949 break;
1950 case WRITE_12:
1951 case READ_12:
1952 nvme_trans_get_io_cdb12(cmd, &cdb_info);
1953 break;
1954 case WRITE_16:
1955 case READ_16:
1956 nvme_trans_get_io_cdb16(cmd, &cdb_info);
1957 break;
1958 default:
1959 /* Will never really reach here */
Christoph Hellwige61b0a82015-05-22 11:12:41 +02001960 res = -EIO;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001961 goto out;
1962 }
1963
1964 /* Calculate total length of transfer (in bytes) */
1965 if (hdr->iovec_count > 0) {
Vishal Verma5d0f6132013-03-04 18:40:58 -07001966 for (i = 0; i < hdr->iovec_count; i++) {
Vishal Verma8741ee42013-04-04 17:52:27 -06001967 not_copied = copy_from_user(&sgl, hdr->dxferp +
1968 i * sizeof(struct sg_iovec),
1969 sizeof(struct sg_iovec));
1970 if (not_copied)
1971 return -EFAULT;
1972 sum_iov_len += sgl.iov_len;
Vishal Verma5d0f6132013-03-04 18:40:58 -07001973 /* IO vector sizes should be multiples of block size */
Vishal Verma8741ee42013-04-04 17:52:27 -06001974 if (sgl.iov_len % (1 << ns->lba_shift) != 0) {
Vishal Verma5d0f6132013-03-04 18:40:58 -07001975 res = nvme_trans_completion(hdr,
1976 SAM_STAT_CHECK_CONDITION,
1977 ILLEGAL_REQUEST,
1978 SCSI_ASC_INVALID_PARAMETER,
1979 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
1980 goto out;
1981 }
1982 }
1983 } else {
1984 sum_iov_len = hdr->dxfer_len;
1985 }
1986
1987 /* As Per sg ioctl howto, if the lengths differ, use the lower one */
1988 xfer_bytes = min(((u64)hdr->dxfer_len), sum_iov_len);
1989
1990 /* If block count and actual data buffer size dont match, error out */
1991 if (xfer_bytes != (cdb_info.xfer_len << ns->lba_shift)) {
1992 res = -EINVAL;
1993 goto out;
1994 }
1995
1996 /* Check for 0 length transfer - it is not illegal */
1997 if (cdb_info.xfer_len == 0)
1998 goto out;
1999
2000 /* Send NVMe IO Command(s) */
2001 res = nvme_trans_do_nvme_io(ns, hdr, &cdb_info, is_write);
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002002 if (res)
Vishal Verma5d0f6132013-03-04 18:40:58 -07002003 goto out;
2004
2005 out:
2006 return res;
2007}
2008
2009static int nvme_trans_inquiry(struct nvme_ns *ns, struct sg_io_hdr *hdr,
2010 u8 *cmd)
2011{
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002012 int res = 0;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002013 u8 evpd;
2014 u8 page_code;
2015 int alloc_len;
2016 u8 *inq_response;
2017
Christoph Hellwig37268972015-05-22 11:12:42 +02002018 evpd = cmd[1] & 0x01;
2019 page_code = cmd[2];
2020 alloc_len = get_unaligned_be16(&cmd[3]);
Vishal Verma5d0f6132013-03-04 18:40:58 -07002021
Keith Busch4f1982b2015-02-19 13:42:14 -07002022 inq_response = kmalloc(alloc_len, GFP_KERNEL);
Vishal Verma5d0f6132013-03-04 18:40:58 -07002023 if (inq_response == NULL) {
2024 res = -ENOMEM;
2025 goto out_mem;
2026 }
2027
2028 if (evpd == 0) {
2029 if (page_code == INQ_STANDARD_INQUIRY_PAGE) {
2030 res = nvme_trans_standard_inquiry_page(ns, hdr,
2031 inq_response, alloc_len);
2032 } else {
2033 res = nvme_trans_completion(hdr,
2034 SAM_STAT_CHECK_CONDITION,
2035 ILLEGAL_REQUEST,
2036 SCSI_ASC_INVALID_CDB,
2037 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
2038 }
2039 } else {
2040 switch (page_code) {
2041 case VPD_SUPPORTED_PAGES:
2042 res = nvme_trans_supported_vpd_pages(ns, hdr,
2043 inq_response, alloc_len);
2044 break;
2045 case VPD_SERIAL_NUMBER:
2046 res = nvme_trans_unit_serial_page(ns, hdr, inq_response,
2047 alloc_len);
2048 break;
2049 case VPD_DEVICE_IDENTIFIERS:
2050 res = nvme_trans_device_id_page(ns, hdr, inq_response,
2051 alloc_len);
2052 break;
2053 case VPD_EXTENDED_INQUIRY:
2054 res = nvme_trans_ext_inq_page(ns, hdr, alloc_len);
2055 break;
Keith Busch7f749d92015-04-07 15:34:18 -06002056 case VPD_BLOCK_LIMITS:
2057 res = nvme_trans_bdev_limits_page(ns, hdr, inq_response,
2058 alloc_len);
2059 break;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002060 case VPD_BLOCK_DEV_CHARACTERISTICS:
2061 res = nvme_trans_bdev_char_page(ns, hdr, alloc_len);
2062 break;
2063 default:
2064 res = nvme_trans_completion(hdr,
2065 SAM_STAT_CHECK_CONDITION,
2066 ILLEGAL_REQUEST,
2067 SCSI_ASC_INVALID_CDB,
2068 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
2069 break;
2070 }
2071 }
2072 kfree(inq_response);
2073 out_mem:
2074 return res;
2075}
2076
2077static int nvme_trans_log_sense(struct nvme_ns *ns, struct sg_io_hdr *hdr,
2078 u8 *cmd)
2079{
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002080 int res;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002081 u16 alloc_len;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002082 u8 pc;
2083 u8 page_code;
2084
Christoph Hellwig37268972015-05-22 11:12:42 +02002085 if (cmd[1] != LOG_SENSE_CDB_SP_NOT_ENABLED) {
Vishal Verma5d0f6132013-03-04 18:40:58 -07002086 res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
2087 ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
2088 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
2089 goto out;
2090 }
Christoph Hellwig37268972015-05-22 11:12:42 +02002091
2092 page_code = cmd[2] & LOG_SENSE_CDB_PAGE_CODE_MASK;
2093 pc = (cmd[2] & LOG_SENSE_CDB_PC_MASK) >> LOG_SENSE_CDB_PC_SHIFT;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002094 if (pc != LOG_SENSE_CDB_PC_CUMULATIVE_VALUES) {
2095 res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
2096 ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
2097 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
2098 goto out;
2099 }
Christoph Hellwig37268972015-05-22 11:12:42 +02002100 alloc_len = get_unaligned_be16(&cmd[7]);
Vishal Verma5d0f6132013-03-04 18:40:58 -07002101 switch (page_code) {
2102 case LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE:
2103 res = nvme_trans_log_supp_pages(ns, hdr, alloc_len);
2104 break;
2105 case LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE:
2106 res = nvme_trans_log_info_exceptions(ns, hdr, alloc_len);
2107 break;
2108 case LOG_PAGE_TEMPERATURE_PAGE:
2109 res = nvme_trans_log_temperature(ns, hdr, alloc_len);
2110 break;
2111 default:
2112 res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
2113 ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
2114 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
2115 break;
2116 }
2117
2118 out:
2119 return res;
2120}
2121
2122static int nvme_trans_mode_select(struct nvme_ns *ns, struct sg_io_hdr *hdr,
2123 u8 *cmd)
2124{
Vishal Verma5d0f6132013-03-04 18:40:58 -07002125 u8 cdb10 = 0;
2126 u16 parm_list_len;
2127 u8 page_format;
2128 u8 save_pages;
2129
Christoph Hellwig37268972015-05-22 11:12:42 +02002130 page_format = cmd[1] & MODE_SELECT_CDB_PAGE_FORMAT_MASK;
2131 save_pages = cmd[1] & MODE_SELECT_CDB_SAVE_PAGES_MASK;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002132
Christoph Hellwig37268972015-05-22 11:12:42 +02002133 if (cmd[0] == MODE_SELECT) {
2134 parm_list_len = cmd[4];
Vishal Verma5d0f6132013-03-04 18:40:58 -07002135 } else {
Christoph Hellwig37268972015-05-22 11:12:42 +02002136 parm_list_len = cmd[7];
Vishal Verma5d0f6132013-03-04 18:40:58 -07002137 cdb10 = 1;
2138 }
2139
2140 if (parm_list_len != 0) {
2141 /*
2142 * According to SPC-4 r24, a paramter list length field of 0
2143 * shall not be considered an error
2144 */
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002145 return nvme_trans_modesel_data(ns, hdr, cmd, parm_list_len,
Vishal Verma5d0f6132013-03-04 18:40:58 -07002146 page_format, save_pages, cdb10);
2147 }
2148
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002149 return 0;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002150}
2151
2152static int nvme_trans_mode_sense(struct nvme_ns *ns, struct sg_io_hdr *hdr,
2153 u8 *cmd)
2154{
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002155 int res = 0;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002156 u16 alloc_len;
2157 u8 cdb10 = 0;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002158
Christoph Hellwig37268972015-05-22 11:12:42 +02002159 if (cmd[0] == MODE_SENSE) {
2160 alloc_len = cmd[4];
Vishal Verma5d0f6132013-03-04 18:40:58 -07002161 } else {
Christoph Hellwig37268972015-05-22 11:12:42 +02002162 alloc_len = get_unaligned_be16(&cmd[7]);
Vishal Verma5d0f6132013-03-04 18:40:58 -07002163 cdb10 = 1;
2164 }
2165
Christoph Hellwig37268972015-05-22 11:12:42 +02002166 if ((cmd[2] & MODE_SENSE_PAGE_CONTROL_MASK) !=
2167 MODE_SENSE_PC_CURRENT_VALUES) {
Vishal Verma5d0f6132013-03-04 18:40:58 -07002168 res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
2169 ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
2170 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
2171 goto out;
2172 }
2173
Christoph Hellwig37268972015-05-22 11:12:42 +02002174 switch (cmd[2] & MODE_SENSE_PAGE_CODE_MASK) {
Vishal Verma5d0f6132013-03-04 18:40:58 -07002175 case MODE_PAGE_CACHING:
2176 res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len,
2177 cdb10,
2178 &nvme_trans_fill_caching_page,
2179 MODE_PAGE_CACHING_LEN);
2180 break;
2181 case MODE_PAGE_CONTROL:
2182 res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len,
2183 cdb10,
2184 &nvme_trans_fill_control_page,
2185 MODE_PAGE_CONTROL_LEN);
2186 break;
2187 case MODE_PAGE_POWER_CONDITION:
2188 res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len,
2189 cdb10,
2190 &nvme_trans_fill_pow_cnd_page,
2191 MODE_PAGE_POW_CND_LEN);
2192 break;
2193 case MODE_PAGE_INFO_EXCEP:
2194 res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len,
2195 cdb10,
2196 &nvme_trans_fill_inf_exc_page,
2197 MODE_PAGE_INF_EXC_LEN);
2198 break;
2199 case MODE_PAGE_RETURN_ALL:
2200 res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len,
2201 cdb10,
2202 &nvme_trans_fill_all_pages,
2203 MODE_PAGE_ALL_LEN);
2204 break;
2205 default:
2206 res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
2207 ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
2208 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
2209 break;
2210 }
2211
2212 out:
2213 return res;
2214}
2215
2216static int nvme_trans_read_capacity(struct nvme_ns *ns, struct sg_io_hdr *hdr,
Christoph Hellwig37268972015-05-22 11:12:42 +02002217 u8 *cmd, u8 cdb16)
Vishal Verma5d0f6132013-03-04 18:40:58 -07002218{
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002219 int res;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002220 int nvme_sc;
Christoph Hellwig37268972015-05-22 11:12:42 +02002221 u32 alloc_len;
2222 u32 resp_size;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002223 u32 xfer_len;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002224 struct nvme_dev *dev = ns->dev;
2225 dma_addr_t dma_addr;
2226 void *mem;
2227 struct nvme_id_ns *id_ns;
2228 u8 *response;
2229
Vishal Verma5d0f6132013-03-04 18:40:58 -07002230 if (cdb16) {
Christoph Hellwig37268972015-05-22 11:12:42 +02002231 alloc_len = get_unaligned_be32(&cmd[10]);
Vishal Verma5d0f6132013-03-04 18:40:58 -07002232 resp_size = READ_CAP_16_RESP_SIZE;
Christoph Hellwig37268972015-05-22 11:12:42 +02002233 } else {
2234 alloc_len = READ_CAP_10_RESP_SIZE;
2235 resp_size = READ_CAP_10_RESP_SIZE;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002236 }
2237
Christoph Hellwige75ec752015-05-22 11:12:39 +02002238 mem = dma_alloc_coherent(dev->dev, sizeof(struct nvme_id_ns),
Vishal Verma5d0f6132013-03-04 18:40:58 -07002239 &dma_addr, GFP_KERNEL);
2240 if (mem == NULL) {
2241 res = -ENOMEM;
2242 goto out;
2243 }
2244 /* nvme ns identify */
2245 nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
2246 res = nvme_trans_status_code(hdr, nvme_sc);
2247 if (res)
2248 goto out_dma;
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002249
Vishal Verma5d0f6132013-03-04 18:40:58 -07002250 id_ns = mem;
2251
Tushar Behera03ea83e2013-06-10 10:20:55 +05302252 response = kzalloc(resp_size, GFP_KERNEL);
Vishal Verma5d0f6132013-03-04 18:40:58 -07002253 if (response == NULL) {
2254 res = -ENOMEM;
2255 goto out_dma;
2256 }
Vishal Verma5d0f6132013-03-04 18:40:58 -07002257 nvme_trans_fill_read_cap(response, id_ns, cdb16);
2258
2259 xfer_len = min(alloc_len, resp_size);
2260 res = nvme_trans_copy_to_user(hdr, response, xfer_len);
2261
2262 kfree(response);
2263 out_dma:
Christoph Hellwige75ec752015-05-22 11:12:39 +02002264 dma_free_coherent(dev->dev, sizeof(struct nvme_id_ns), mem, dma_addr);
Vishal Verma5d0f6132013-03-04 18:40:58 -07002265 out:
2266 return res;
2267}
2268
2269static int nvme_trans_report_luns(struct nvme_ns *ns, struct sg_io_hdr *hdr,
2270 u8 *cmd)
2271{
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002272 int res;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002273 int nvme_sc;
2274 u32 alloc_len, xfer_len, resp_size;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002275 u8 *response;
2276 struct nvme_dev *dev = ns->dev;
2277 dma_addr_t dma_addr;
2278 void *mem;
2279 struct nvme_id_ctrl *id_ctrl;
2280 u32 ll_length, lun_id;
2281 u8 lun_id_offset = REPORT_LUNS_FIRST_LUN_OFFSET;
Vishal Verma8741ee42013-04-04 17:52:27 -06002282 __be32 tmp_len;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002283
Christoph Hellwig37268972015-05-22 11:12:42 +02002284 switch (cmd[2]) {
2285 default:
2286 return nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
Vishal Verma5d0f6132013-03-04 18:40:58 -07002287 ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
2288 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
Christoph Hellwig37268972015-05-22 11:12:42 +02002289 case ALL_LUNS_RETURNED:
2290 case ALL_WELL_KNOWN_LUNS_RETURNED:
2291 case RESTRICTED_LUNS_RETURNED:
Vishal Verma5d0f6132013-03-04 18:40:58 -07002292 /* NVMe Controller Identify */
Christoph Hellwige75ec752015-05-22 11:12:39 +02002293 mem = dma_alloc_coherent(dev->dev, sizeof(struct nvme_id_ctrl),
Vishal Verma5d0f6132013-03-04 18:40:58 -07002294 &dma_addr, GFP_KERNEL);
2295 if (mem == NULL) {
2296 res = -ENOMEM;
2297 goto out;
2298 }
2299 nvme_sc = nvme_identify(dev, 0, 1, dma_addr);
2300 res = nvme_trans_status_code(hdr, nvme_sc);
2301 if (res)
2302 goto out_dma;
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002303
Vishal Verma5d0f6132013-03-04 18:40:58 -07002304 id_ctrl = mem;
Vishal Verma8741ee42013-04-04 17:52:27 -06002305 ll_length = le32_to_cpu(id_ctrl->nn) * LUN_ENTRY_SIZE;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002306 resp_size = ll_length + LUN_DATA_HEADER_SIZE;
2307
Christoph Hellwig37268972015-05-22 11:12:42 +02002308 alloc_len = get_unaligned_be32(&cmd[6]);
Vishal Verma5d0f6132013-03-04 18:40:58 -07002309 if (alloc_len < resp_size) {
2310 res = nvme_trans_completion(hdr,
2311 SAM_STAT_CHECK_CONDITION,
2312 ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
2313 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
2314 goto out_dma;
2315 }
2316
Tushar Behera03ea83e2013-06-10 10:20:55 +05302317 response = kzalloc(resp_size, GFP_KERNEL);
Vishal Verma5d0f6132013-03-04 18:40:58 -07002318 if (response == NULL) {
2319 res = -ENOMEM;
2320 goto out_dma;
2321 }
Vishal Verma5d0f6132013-03-04 18:40:58 -07002322
2323 /* The first LUN ID will always be 0 per the SAM spec */
Vishal Verma8741ee42013-04-04 17:52:27 -06002324 for (lun_id = 0; lun_id < le32_to_cpu(id_ctrl->nn); lun_id++) {
Vishal Verma5d0f6132013-03-04 18:40:58 -07002325 /*
2326 * Set the LUN Id and then increment to the next LUN
2327 * location in the parameter data.
2328 */
Vishal Verma8741ee42013-04-04 17:52:27 -06002329 __be64 tmp_id = cpu_to_be64(lun_id);
Vishal Verma5d0f6132013-03-04 18:40:58 -07002330 memcpy(&response[lun_id_offset], &tmp_id, sizeof(u64));
2331 lun_id_offset += LUN_ENTRY_SIZE;
2332 }
2333 tmp_len = cpu_to_be32(ll_length);
2334 memcpy(response, &tmp_len, sizeof(u32));
2335 }
2336
2337 xfer_len = min(alloc_len, resp_size);
2338 res = nvme_trans_copy_to_user(hdr, response, xfer_len);
2339
2340 kfree(response);
2341 out_dma:
Christoph Hellwige75ec752015-05-22 11:12:39 +02002342 dma_free_coherent(dev->dev, sizeof(struct nvme_id_ctrl), mem, dma_addr);
Vishal Verma5d0f6132013-03-04 18:40:58 -07002343 out:
2344 return res;
2345}
2346
2347static int nvme_trans_request_sense(struct nvme_ns *ns, struct sg_io_hdr *hdr,
2348 u8 *cmd)
2349{
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002350 int res;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002351 u8 alloc_len, xfer_len, resp_size;
2352 u8 desc_format;
2353 u8 *response;
2354
Christoph Hellwig37268972015-05-22 11:12:42 +02002355 desc_format = cmd[1] & 0x01;
2356 alloc_len = cmd[4];
Vishal Verma5d0f6132013-03-04 18:40:58 -07002357
2358 resp_size = ((desc_format) ? (DESC_FMT_SENSE_DATA_SIZE) :
2359 (FIXED_FMT_SENSE_DATA_SIZE));
Tushar Behera03ea83e2013-06-10 10:20:55 +05302360 response = kzalloc(resp_size, GFP_KERNEL);
Vishal Verma5d0f6132013-03-04 18:40:58 -07002361 if (response == NULL) {
2362 res = -ENOMEM;
2363 goto out;
2364 }
Vishal Verma5d0f6132013-03-04 18:40:58 -07002365
Christoph Hellwig37268972015-05-22 11:12:42 +02002366 if (desc_format) {
Vishal Verma5d0f6132013-03-04 18:40:58 -07002367 /* Descriptor Format Sense Data */
2368 response[0] = DESC_FORMAT_SENSE_DATA;
2369 response[1] = NO_SENSE;
2370 /* TODO How is LOW POWER CONDITION ON handled? (byte 2) */
2371 response[2] = SCSI_ASC_NO_SENSE;
2372 response[3] = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
2373 /* SDAT_OVFL = 0 | Additional Sense Length = 0 */
2374 } else {
2375 /* Fixed Format Sense Data */
2376 response[0] = FIXED_SENSE_DATA;
2377 /* Byte 1 = Obsolete */
2378 response[2] = NO_SENSE; /* FM, EOM, ILI, SDAT_OVFL = 0 */
2379 /* Bytes 3-6 - Information - set to zero */
2380 response[7] = FIXED_SENSE_DATA_ADD_LENGTH;
2381 /* Bytes 8-11 - Cmd Specific Information - set to zero */
2382 response[12] = SCSI_ASC_NO_SENSE;
2383 response[13] = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
2384 /* Byte 14 = Field Replaceable Unit Code = 0 */
2385 /* Bytes 15-17 - SKSV=0; Sense Key Specific = 0 */
2386 }
2387
2388 xfer_len = min(alloc_len, resp_size);
2389 res = nvme_trans_copy_to_user(hdr, response, xfer_len);
2390
2391 kfree(response);
2392 out:
2393 return res;
2394}
2395
2396static int nvme_trans_security_protocol(struct nvme_ns *ns,
2397 struct sg_io_hdr *hdr,
2398 u8 *cmd)
2399{
2400 return nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
2401 ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_COMMAND,
2402 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
2403}
2404
2405static int nvme_trans_start_stop(struct nvme_ns *ns, struct sg_io_hdr *hdr,
2406 u8 *cmd)
2407{
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002408 int res;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002409 int nvme_sc;
Keith Busch14385de2013-04-25 14:39:27 -06002410 struct nvme_command c;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002411 u8 immed, pcmod, pc, no_flush, start;
2412
Christoph Hellwig37268972015-05-22 11:12:42 +02002413 immed = cmd[1] & 0x01;
2414 pcmod = cmd[3] & 0x0f;
2415 pc = (cmd[4] & 0xf0) >> 4;
2416 no_flush = cmd[4] & 0x04;
2417 start = cmd[4] & 0x01;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002418
2419 if (immed != 0) {
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002420 return nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
Vishal Verma5d0f6132013-03-04 18:40:58 -07002421 ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
2422 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
2423 } else {
2424 if (no_flush == 0) {
2425 /* Issue NVME FLUSH command prior to START STOP UNIT */
Keith Busch14385de2013-04-25 14:39:27 -06002426 memset(&c, 0, sizeof(c));
2427 c.common.opcode = nvme_cmd_flush;
2428 c.common.nsid = cpu_to_le32(ns->ns_id);
2429
Christoph Hellwigf705f832015-05-22 11:12:38 +02002430 nvme_sc = nvme_submit_sync_cmd(ns->queue, &c);
Vishal Verma5d0f6132013-03-04 18:40:58 -07002431 res = nvme_trans_status_code(hdr, nvme_sc);
2432 if (res)
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002433 return res;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002434 }
2435 /* Setup the expected power state transition */
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002436 return nvme_trans_power_state(ns, hdr, pc, pcmod, start);
Vishal Verma5d0f6132013-03-04 18:40:58 -07002437 }
Vishal Verma5d0f6132013-03-04 18:40:58 -07002438}
2439
2440static int nvme_trans_synchronize_cache(struct nvme_ns *ns,
2441 struct sg_io_hdr *hdr, u8 *cmd)
2442{
Vishal Verma5d0f6132013-03-04 18:40:58 -07002443 int nvme_sc;
Keith Busch14385de2013-04-25 14:39:27 -06002444 struct nvme_command c;
Keith Busch14385de2013-04-25 14:39:27 -06002445
2446 memset(&c, 0, sizeof(c));
2447 c.common.opcode = nvme_cmd_flush;
2448 c.common.nsid = cpu_to_le32(ns->ns_id);
2449
Christoph Hellwigf705f832015-05-22 11:12:38 +02002450 nvme_sc = nvme_submit_sync_cmd(ns->queue, &c);
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002451 return nvme_trans_status_code(hdr, nvme_sc);
Vishal Verma5d0f6132013-03-04 18:40:58 -07002452}
2453
2454static int nvme_trans_format_unit(struct nvme_ns *ns, struct sg_io_hdr *hdr,
2455 u8 *cmd)
2456{
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002457 int res;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002458 u8 parm_hdr_len = 0;
2459 u8 nvme_pf_code = 0;
2460 u8 format_prot_info, long_list, format_data;
2461
Christoph Hellwig37268972015-05-22 11:12:42 +02002462 format_prot_info = (cmd[1] & 0xc0) >> 6;
2463 long_list = cmd[1] & 0x20;
2464 format_data = cmd[1] & 0x10;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002465
2466 if (format_data != 0) {
2467 if (format_prot_info != 0) {
2468 if (long_list == 0)
2469 parm_hdr_len = FORMAT_UNIT_SHORT_PARM_LIST_LEN;
2470 else
2471 parm_hdr_len = FORMAT_UNIT_LONG_PARM_LIST_LEN;
2472 }
2473 } else if (format_data == 0 && format_prot_info != 0) {
2474 res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
2475 ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
2476 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
2477 goto out;
2478 }
2479
2480 /* Get parm header from data-in/out buffer */
2481 /*
2482 * According to the translation spec, the only fields in the parameter
2483 * list we are concerned with are in the header. So allocate only that.
2484 */
2485 if (parm_hdr_len > 0) {
2486 res = nvme_trans_fmt_get_parm_header(hdr, parm_hdr_len,
2487 format_prot_info, &nvme_pf_code);
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002488 if (res)
Vishal Verma5d0f6132013-03-04 18:40:58 -07002489 goto out;
2490 }
2491
2492 /* Attempt to activate any previously downloaded firmware image */
Christoph Hellwigb90c48d2015-05-22 11:12:40 +02002493 res = nvme_trans_send_activate_fw_cmd(ns, hdr, 0);
Vishal Verma5d0f6132013-03-04 18:40:58 -07002494
2495 /* Determine Block size and count and send format command */
2496 res = nvme_trans_fmt_set_blk_size_count(ns, hdr);
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002497 if (res)
Vishal Verma5d0f6132013-03-04 18:40:58 -07002498 goto out;
2499
2500 res = nvme_trans_fmt_send_cmd(ns, hdr, nvme_pf_code);
2501
2502 out:
2503 return res;
2504}
2505
2506static int nvme_trans_test_unit_ready(struct nvme_ns *ns,
2507 struct sg_io_hdr *hdr,
2508 u8 *cmd)
2509{
Vishal Verma5d0f6132013-03-04 18:40:58 -07002510 struct nvme_dev *dev = ns->dev;
2511
2512 if (!(readl(&dev->bar->csts) & NVME_CSTS_RDY))
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002513 return nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
Vishal Verma5d0f6132013-03-04 18:40:58 -07002514 NOT_READY, SCSI_ASC_LUN_NOT_READY,
2515 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
2516 else
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002517 return nvme_trans_completion(hdr, SAM_STAT_GOOD, NO_SENSE, 0, 0);
Vishal Verma5d0f6132013-03-04 18:40:58 -07002518}
2519
2520static int nvme_trans_write_buffer(struct nvme_ns *ns, struct sg_io_hdr *hdr,
2521 u8 *cmd)
2522{
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002523 int res = 0;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002524 u32 buffer_offset, parm_list_length;
2525 u8 buffer_id, mode;
2526
Christoph Hellwig37268972015-05-22 11:12:42 +02002527 parm_list_length = get_unaligned_be24(&cmd[6]);
Vishal Verma5d0f6132013-03-04 18:40:58 -07002528 if (parm_list_length % BYTES_TO_DWORDS != 0) {
2529 /* NVMe expects Firmware file to be a whole number of DWORDS */
2530 res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
2531 ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
2532 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
2533 goto out;
2534 }
Christoph Hellwig37268972015-05-22 11:12:42 +02002535 buffer_id = cmd[2];
Vishal Verma5d0f6132013-03-04 18:40:58 -07002536 if (buffer_id > NVME_MAX_FIRMWARE_SLOT) {
2537 res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
2538 ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
2539 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
2540 goto out;
2541 }
Christoph Hellwig37268972015-05-22 11:12:42 +02002542 mode = cmd[1] & 0x1f;
2543 buffer_offset = get_unaligned_be24(&cmd[3]);
Vishal Verma5d0f6132013-03-04 18:40:58 -07002544
2545 switch (mode) {
2546 case DOWNLOAD_SAVE_ACTIVATE:
Christoph Hellwigb90c48d2015-05-22 11:12:40 +02002547 res = nvme_trans_send_download_fw_cmd(ns, hdr, nvme_admin_download_fw,
Vishal Verma5d0f6132013-03-04 18:40:58 -07002548 parm_list_length, buffer_offset,
2549 buffer_id);
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002550 if (res)
Vishal Verma5d0f6132013-03-04 18:40:58 -07002551 goto out;
Christoph Hellwigb90c48d2015-05-22 11:12:40 +02002552 res = nvme_trans_send_activate_fw_cmd(ns, hdr, buffer_id);
Vishal Verma5d0f6132013-03-04 18:40:58 -07002553 break;
2554 case DOWNLOAD_SAVE_DEFER_ACTIVATE:
Christoph Hellwigb90c48d2015-05-22 11:12:40 +02002555 res = nvme_trans_send_download_fw_cmd(ns, hdr, nvme_admin_download_fw,
Vishal Verma5d0f6132013-03-04 18:40:58 -07002556 parm_list_length, buffer_offset,
2557 buffer_id);
2558 break;
2559 case ACTIVATE_DEFERRED_MICROCODE:
Christoph Hellwigb90c48d2015-05-22 11:12:40 +02002560 res = nvme_trans_send_activate_fw_cmd(ns, hdr, buffer_id);
Vishal Verma5d0f6132013-03-04 18:40:58 -07002561 break;
2562 default:
2563 res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
2564 ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
2565 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
2566 break;
2567 }
2568
2569 out:
2570 return res;
2571}
2572
Keith Buschec503732013-04-24 15:44:24 -06002573struct scsi_unmap_blk_desc {
2574 __be64 slba;
2575 __be32 nlb;
2576 u32 resv;
2577};
2578
2579struct scsi_unmap_parm_list {
2580 __be16 unmap_data_len;
2581 __be16 unmap_blk_desc_data_len;
2582 u32 resv;
2583 struct scsi_unmap_blk_desc desc[0];
2584};
2585
2586static int nvme_trans_unmap(struct nvme_ns *ns, struct sg_io_hdr *hdr,
2587 u8 *cmd)
2588{
2589 struct nvme_dev *dev = ns->dev;
2590 struct scsi_unmap_parm_list *plist;
2591 struct nvme_dsm_range *range;
Keith Buschec503732013-04-24 15:44:24 -06002592 struct nvme_command c;
2593 int i, nvme_sc, res = -ENOMEM;
2594 u16 ndesc, list_len;
2595 dma_addr_t dma_addr;
2596
Christoph Hellwig37268972015-05-22 11:12:42 +02002597 list_len = get_unaligned_be16(&cmd[7]);
Keith Buschec503732013-04-24 15:44:24 -06002598 if (!list_len)
2599 return -EINVAL;
2600
2601 plist = kmalloc(list_len, GFP_KERNEL);
2602 if (!plist)
2603 return -ENOMEM;
2604
2605 res = nvme_trans_copy_from_user(hdr, plist, list_len);
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002606 if (res)
Keith Buschec503732013-04-24 15:44:24 -06002607 goto out;
2608
2609 ndesc = be16_to_cpu(plist->unmap_blk_desc_data_len) >> 4;
2610 if (!ndesc || ndesc > 256) {
2611 res = -EINVAL;
2612 goto out;
2613 }
2614
Christoph Hellwige75ec752015-05-22 11:12:39 +02002615 range = dma_alloc_coherent(dev->dev, ndesc * sizeof(*range),
Keith Buschec503732013-04-24 15:44:24 -06002616 &dma_addr, GFP_KERNEL);
2617 if (!range)
2618 goto out;
2619
2620 for (i = 0; i < ndesc; i++) {
2621 range[i].nlb = cpu_to_le32(be32_to_cpu(plist->desc[i].nlb));
2622 range[i].slba = cpu_to_le64(be64_to_cpu(plist->desc[i].slba));
2623 range[i].cattr = 0;
2624 }
2625
2626 memset(&c, 0, sizeof(c));
2627 c.dsm.opcode = nvme_cmd_dsm;
2628 c.dsm.nsid = cpu_to_le32(ns->ns_id);
2629 c.dsm.prp1 = cpu_to_le64(dma_addr);
2630 c.dsm.nr = cpu_to_le32(ndesc - 1);
2631 c.dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
2632
Christoph Hellwigf705f832015-05-22 11:12:38 +02002633 nvme_sc = nvme_submit_sync_cmd(ns->queue, &c);
Keith Buschec503732013-04-24 15:44:24 -06002634 res = nvme_trans_status_code(hdr, nvme_sc);
2635
Christoph Hellwige75ec752015-05-22 11:12:39 +02002636 dma_free_coherent(dev->dev, ndesc * sizeof(*range), range, dma_addr);
Keith Buschec503732013-04-24 15:44:24 -06002637 out:
2638 kfree(plist);
2639 return res;
2640}
2641
Vishal Verma5d0f6132013-03-04 18:40:58 -07002642static int nvme_scsi_translate(struct nvme_ns *ns, struct sg_io_hdr *hdr)
2643{
2644 u8 cmd[BLK_MAX_CDB];
2645 int retcode;
2646 unsigned int opcode;
2647
2648 if (hdr->cmdp == NULL)
2649 return -EMSGSIZE;
2650 if (copy_from_user(cmd, hdr->cmdp, hdr->cmd_len))
2651 return -EFAULT;
2652
Keith Busch695a4fe2014-08-27 13:55:39 -06002653 /*
2654 * Prime the hdr with good status for scsi commands that don't require
2655 * an nvme command for translation.
2656 */
2657 retcode = nvme_trans_status_code(hdr, NVME_SC_SUCCESS);
2658 if (retcode)
2659 return retcode;
2660
Vishal Verma5d0f6132013-03-04 18:40:58 -07002661 opcode = cmd[0];
2662
2663 switch (opcode) {
2664 case READ_6:
2665 case READ_10:
2666 case READ_12:
2667 case READ_16:
2668 retcode = nvme_trans_io(ns, hdr, 0, cmd);
2669 break;
2670 case WRITE_6:
2671 case WRITE_10:
2672 case WRITE_12:
2673 case WRITE_16:
2674 retcode = nvme_trans_io(ns, hdr, 1, cmd);
2675 break;
2676 case INQUIRY:
2677 retcode = nvme_trans_inquiry(ns, hdr, cmd);
2678 break;
2679 case LOG_SENSE:
2680 retcode = nvme_trans_log_sense(ns, hdr, cmd);
2681 break;
2682 case MODE_SELECT:
2683 case MODE_SELECT_10:
2684 retcode = nvme_trans_mode_select(ns, hdr, cmd);
2685 break;
2686 case MODE_SENSE:
2687 case MODE_SENSE_10:
2688 retcode = nvme_trans_mode_sense(ns, hdr, cmd);
2689 break;
2690 case READ_CAPACITY:
Christoph Hellwig37268972015-05-22 11:12:42 +02002691 retcode = nvme_trans_read_capacity(ns, hdr, cmd, 0);
Vishal Verma5d0f6132013-03-04 18:40:58 -07002692 break;
Hannes Reineckeeb846d92014-11-17 14:25:19 +01002693 case SERVICE_ACTION_IN_16:
Christoph Hellwig37268972015-05-22 11:12:42 +02002694 switch (cmd[1]) {
2695 case SAI_READ_CAPACITY_16:
2696 retcode = nvme_trans_read_capacity(ns, hdr, cmd, 1);
2697 break;
2698 default:
Vishal Verma5d0f6132013-03-04 18:40:58 -07002699 goto out;
Christoph Hellwig37268972015-05-22 11:12:42 +02002700 }
Vishal Verma5d0f6132013-03-04 18:40:58 -07002701 break;
2702 case REPORT_LUNS:
2703 retcode = nvme_trans_report_luns(ns, hdr, cmd);
2704 break;
2705 case REQUEST_SENSE:
2706 retcode = nvme_trans_request_sense(ns, hdr, cmd);
2707 break;
2708 case SECURITY_PROTOCOL_IN:
2709 case SECURITY_PROTOCOL_OUT:
2710 retcode = nvme_trans_security_protocol(ns, hdr, cmd);
2711 break;
2712 case START_STOP:
2713 retcode = nvme_trans_start_stop(ns, hdr, cmd);
2714 break;
2715 case SYNCHRONIZE_CACHE:
2716 retcode = nvme_trans_synchronize_cache(ns, hdr, cmd);
2717 break;
2718 case FORMAT_UNIT:
2719 retcode = nvme_trans_format_unit(ns, hdr, cmd);
2720 break;
2721 case TEST_UNIT_READY:
2722 retcode = nvme_trans_test_unit_ready(ns, hdr, cmd);
2723 break;
2724 case WRITE_BUFFER:
2725 retcode = nvme_trans_write_buffer(ns, hdr, cmd);
2726 break;
Keith Buschec503732013-04-24 15:44:24 -06002727 case UNMAP:
2728 retcode = nvme_trans_unmap(ns, hdr, cmd);
2729 break;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002730 default:
2731 out:
2732 retcode = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
2733 ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_COMMAND,
2734 SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
2735 break;
2736 }
2737 return retcode;
2738}
2739
2740int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr)
2741{
2742 struct sg_io_hdr hdr;
2743 int retcode;
2744
2745 if (!capable(CAP_SYS_ADMIN))
2746 return -EACCES;
2747 if (copy_from_user(&hdr, u_hdr, sizeof(hdr)))
2748 return -EFAULT;
2749 if (hdr.interface_id != 'S')
2750 return -EINVAL;
2751 if (hdr.cmd_len > BLK_MAX_CDB)
2752 return -EINVAL;
2753
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002754 /*
2755 * A positive return code means a NVMe status, which has been
2756 * translated to sense data.
2757 */
Vishal Verma5d0f6132013-03-04 18:40:58 -07002758 retcode = nvme_scsi_translate(ns, &hdr);
2759 if (retcode < 0)
2760 return retcode;
Vishal Verma8741ee42013-04-04 17:52:27 -06002761 if (copy_to_user(u_hdr, &hdr, sizeof(sg_io_hdr_t)) > 0)
Vishal Verma5d0f6132013-03-04 18:40:58 -07002762 return -EFAULT;
Christoph Hellwige61b0a82015-05-22 11:12:41 +02002763 return 0;
Vishal Verma5d0f6132013-03-04 18:40:58 -07002764}
2765
Vishal Verma5d0f6132013-03-04 18:40:58 -07002766int nvme_sg_get_version_num(int __user *ip)
2767{
2768 return put_user(sg_version_num, ip);
2769}