Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / cd042fe5c1f67a7b60e027802a0784b95c4dee6f / . / arch / arm / boot / dts / dra7.dtsi
blob: 881e49262d09bddff50182c9762433681284d992 [file] [log] [blame]
R Sricharan6e58b8f2013-08-14 19:08:20 +0530[diff] [blame]1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/dra.h>
12
13#include "skeleton.dtsi"
14
15/ {
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 compatible = "ti,dra7xx";
20 interrupt-parent = <&gic>;
21
22 aliases {
Nishanth Menon20b80942013-10-16 15:21:03 -0500[diff] [blame]23 i2c0 = &i2c1;
24 i2c1 = &i2c2;
25 i2c2 = &i2c3;
26 i2c3 = &i2c4;
27 i2c4 = &i2c5;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530[diff] [blame]28 serial0 = &uart1;
29 serial1 = &uart2;
30 serial2 = &uart3;
31 serial3 = &uart4;
32 serial4 = &uart5;
33 serial5 = &uart6;
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
J Keerthy22f1e7e2013-10-16 10:39:05 -0500[diff] [blame]40 cpu0: cpu@0 {
R Sricharan6e58b8f2013-08-14 19:08:20 +0530[diff] [blame]41 device_type = "cpu";
42 compatible = "arm,cortex-a15";
43 reg = <0>;
J Keerthy620c5162013-10-16 10:39:07 -0500[diff] [blame]44
45 operating-points = <
46 /* kHz uV */
47 1000000 1060000
48 1176000 1160000
49 >;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530[diff] [blame]50 };
51 cpu@1 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a15";
54 reg = <1>;
55 };
56 };
57
58 timer {
59 compatible = "arm,armv7-timer";
60 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
61 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
62 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
63 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
64 };
65
66 gic: interrupt-controller@48211000 {
67 compatible = "arm,cortex-a15-gic";
68 interrupt-controller;
69 #interrupt-cells = <3>;
70 reg = <0x48211000 0x1000>,
71 <0x48212000 0x1000>,
72 <0x48214000 0x2000>,
73 <0x48216000 0x2000>;
74 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
75 };
76
77 /*
78 * The soc node represents the soc top level view. It is uses for IPs
79 * that are not memory mapped in the MPU view or for the MPU itself.
80 */
81 soc {
82 compatible = "ti,omap-infra";
83 mpu {
84 compatible = "ti,omap5-mpu";
85 ti,hwmods = "mpu";
86 };
87 };
88
89 /*
90 * XXX: Use a flat representation of the SOC interconnect.
91 * The real OMAP interconnect network is quite complex.
92 * Since that will not bring real advantage to represent that in DT for
93 * the moment, just use a fake OCP bus entry to represent the whole bus
94 * hierarchy.
95 */
96 ocp {
97 compatible = "ti,omap4-l3-noc", "simple-bus";
98 #address-cells = <1>;
99 #size-cells = <1>;
100 ranges;
101 ti,hwmods = "l3_main_1", "l3_main_2";
102 reg = <0x44000000 0x2000>,
103 <0x44800000 0x3000>;
104 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
106
Tero Kristoee6c7502013-07-18 17:18:33 +0300[diff] [blame]107 prm: prm@4ae06000 {
108 compatible = "ti,dra7-prm";
109 reg = <0x4ae06000 0x3000>;
110
111 prm_clocks: clocks {
112 #address-cells = <1>;
113 #size-cells = <0>;
114 };
115
116 prm_clockdomains: clockdomains {
117 };
118 };
119
120 cm_core_aon: cm_core_aon@4a005000 {
121 compatible = "ti,dra7-cm-core-aon";
122 reg = <0x4a005000 0x2000>;
123
124 cm_core_aon_clocks: clocks {
125 #address-cells = <1>;
126 #size-cells = <0>;
127 };
128
129 cm_core_aon_clockdomains: clockdomains {
130 };
131 };
132
133 cm_core: cm_core@4a008000 {
134 compatible = "ti,dra7-cm-core";
135 reg = <0x4a008000 0x3000>;
136
137 cm_core_clocks: clocks {
138 #address-cells = <1>;
139 #size-cells = <0>;
140 };
141
142 cm_core_clockdomains: clockdomains {
143 };
144 };
145
R Sricharan6e58b8f2013-08-14 19:08:20 +0530[diff] [blame]146 counter32k: counter@4ae04000 {
147 compatible = "ti,omap-counter32k";
148 reg = <0x4ae04000 0x40>;
149 ti,hwmods = "counter_32k";
150 };
151
Balaji T Kcd042fe2014-02-19 20:26:40 +0530[diff] [blame^]152 dra7_ctrl_general: tisyscon@4a002e00 {
153 compatible = "syscon";
154 reg = <0x4a002e00 0x7c>;
155 };
156
157 pbias_regulator: pbias_regulator {
158 compatible = "ti,pbias-omap";
159 reg = <0 0x4>;
160 syscon = <&dra7_ctrl_general>;
161 pbias_mmc_reg: pbias_mmc_omap5 {
162 regulator-name = "pbias_mmc_omap5";
163 regulator-min-microvolt = <1800000>;
164 regulator-max-microvolt = <3000000>;
165 };
166 };
167
R Sricharan6e58b8f2013-08-14 19:08:20 +0530[diff] [blame]168 dra7_pmx_core: pinmux@4a003400 {
169 compatible = "pinctrl-single";
170 reg = <0x4a003400 0x0464>;
171 #address-cells = <1>;
172 #size-cells = <0>;
173 pinctrl-single,register-width = <32>;
174 pinctrl-single,function-mask = <0x3fffffff>;
175 };
176
177 sdma: dma-controller@4a056000 {
178 compatible = "ti,omap4430-sdma";
179 reg = <0x4a056000 0x1000>;
180 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
184 #dma-cells = <1>;
185 #dma-channels = <32>;
186 #dma-requests = <127>;
187 };
188
189 gpio1: gpio@4ae10000 {
190 compatible = "ti,omap4-gpio";
191 reg = <0x4ae10000 0x200>;
192 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
193 ti,hwmods = "gpio1";
194 gpio-controller;
195 #gpio-cells = <2>;
196 interrupt-controller;
197 #interrupt-cells = <1>;
198 };
199
200 gpio2: gpio@48055000 {
201 compatible = "ti,omap4-gpio";
202 reg = <0x48055000 0x200>;
203 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
204 ti,hwmods = "gpio2";
205 gpio-controller;
206 #gpio-cells = <2>;
207 interrupt-controller;
208 #interrupt-cells = <1>;
209 };
210
211 gpio3: gpio@48057000 {
212 compatible = "ti,omap4-gpio";
213 reg = <0x48057000 0x200>;
214 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
215 ti,hwmods = "gpio3";
216 gpio-controller;
217 #gpio-cells = <2>;
218 interrupt-controller;
219 #interrupt-cells = <1>;
220 };
221
222 gpio4: gpio@48059000 {
223 compatible = "ti,omap4-gpio";
224 reg = <0x48059000 0x200>;
225 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
226 ti,hwmods = "gpio4";
227 gpio-controller;
228 #gpio-cells = <2>;
229 interrupt-controller;
230 #interrupt-cells = <1>;
231 };
232
233 gpio5: gpio@4805b000 {
234 compatible = "ti,omap4-gpio";
235 reg = <0x4805b000 0x200>;
236 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
237 ti,hwmods = "gpio5";
238 gpio-controller;
239 #gpio-cells = <2>;
240 interrupt-controller;
241 #interrupt-cells = <1>;
242 };
243
244 gpio6: gpio@4805d000 {
245 compatible = "ti,omap4-gpio";
246 reg = <0x4805d000 0x200>;
247 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
248 ti,hwmods = "gpio6";
249 gpio-controller;
250 #gpio-cells = <2>;
251 interrupt-controller;
252 #interrupt-cells = <1>;
253 };
254
255 gpio7: gpio@48051000 {
256 compatible = "ti,omap4-gpio";
257 reg = <0x48051000 0x200>;
258 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
259 ti,hwmods = "gpio7";
260 gpio-controller;
261 #gpio-cells = <2>;
262 interrupt-controller;
263 #interrupt-cells = <1>;
264 };
265
266 gpio8: gpio@48053000 {
267 compatible = "ti,omap4-gpio";
268 reg = <0x48053000 0x200>;
269 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
270 ti,hwmods = "gpio8";
271 gpio-controller;
272 #gpio-cells = <2>;
273 interrupt-controller;
274 #interrupt-cells = <1>;
275 };
276
277 uart1: serial@4806a000 {
278 compatible = "ti,omap4-uart";
279 reg = <0x4806a000 0x100>;
280 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
281 ti,hwmods = "uart1";
282 clock-frequency = <48000000>;
283 status = "disabled";
284 };
285
286 uart2: serial@4806c000 {
287 compatible = "ti,omap4-uart";
288 reg = <0x4806c000 0x100>;
289 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
290 ti,hwmods = "uart2";
291 clock-frequency = <48000000>;
292 status = "disabled";
293 };
294
295 uart3: serial@48020000 {
296 compatible = "ti,omap4-uart";
297 reg = <0x48020000 0x100>;
298 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
299 ti,hwmods = "uart3";
300 clock-frequency = <48000000>;
301 status = "disabled";
302 };
303
304 uart4: serial@4806e000 {
305 compatible = "ti,omap4-uart";
306 reg = <0x4806e000 0x100>;
307 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
308 ti,hwmods = "uart4";
309 clock-frequency = <48000000>;
310 status = "disabled";
311 };
312
313 uart5: serial@48066000 {
314 compatible = "ti,omap4-uart";
315 reg = <0x48066000 0x100>;
316 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
317 ti,hwmods = "uart5";
318 clock-frequency = <48000000>;
319 status = "disabled";
320 };
321
322 uart6: serial@48068000 {
323 compatible = "ti,omap4-uart";
324 reg = <0x48068000 0x100>;
325 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
326 ti,hwmods = "uart6";
327 clock-frequency = <48000000>;
328 status = "disabled";
329 };
330
331 uart7: serial@48420000 {
332 compatible = "ti,omap4-uart";
333 reg = <0x48420000 0x100>;
334 ti,hwmods = "uart7";
335 clock-frequency = <48000000>;
336 status = "disabled";
337 };
338
339 uart8: serial@48422000 {
340 compatible = "ti,omap4-uart";
341 reg = <0x48422000 0x100>;
342 ti,hwmods = "uart8";
343 clock-frequency = <48000000>;
344 status = "disabled";
345 };
346
347 uart9: serial@48424000 {
348 compatible = "ti,omap4-uart";
349 reg = <0x48424000 0x100>;
350 ti,hwmods = "uart9";
351 clock-frequency = <48000000>;
352 status = "disabled";
353 };
354
355 uart10: serial@4ae2b000 {
356 compatible = "ti,omap4-uart";
357 reg = <0x4ae2b000 0x100>;
358 ti,hwmods = "uart10";
359 clock-frequency = <48000000>;
360 status = "disabled";
361 };
362
363 timer1: timer@4ae18000 {
364 compatible = "ti,omap5430-timer";
365 reg = <0x4ae18000 0x80>;
366 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
367 ti,hwmods = "timer1";
368 ti,timer-alwon;
369 };
370
371 timer2: timer@48032000 {
372 compatible = "ti,omap5430-timer";
373 reg = <0x48032000 0x80>;
374 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
375 ti,hwmods = "timer2";
376 };
377
378 timer3: timer@48034000 {
379 compatible = "ti,omap5430-timer";
380 reg = <0x48034000 0x80>;
381 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
382 ti,hwmods = "timer3";
383 };
384
385 timer4: timer@48036000 {
386 compatible = "ti,omap5430-timer";
387 reg = <0x48036000 0x80>;
388 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
389 ti,hwmods = "timer4";
390 };
391
392 timer5: timer@48820000 {
393 compatible = "ti,omap5430-timer";
394 reg = <0x48820000 0x80>;
395 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
396 ti,hwmods = "timer5";
397 ti,timer-dsp;
398 };
399
400 timer6: timer@48822000 {
401 compatible = "ti,omap5430-timer";
402 reg = <0x48822000 0x80>;
403 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
404 ti,hwmods = "timer6";
405 ti,timer-dsp;
406 ti,timer-pwm;
407 };
408
409 timer7: timer@48824000 {
410 compatible = "ti,omap5430-timer";
411 reg = <0x48824000 0x80>;
412 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
413 ti,hwmods = "timer7";
414 ti,timer-dsp;
415 };
416
417 timer8: timer@48826000 {
418 compatible = "ti,omap5430-timer";
419 reg = <0x48826000 0x80>;
420 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
421 ti,hwmods = "timer8";
422 ti,timer-dsp;
423 ti,timer-pwm;
424 };
425
426 timer9: timer@4803e000 {
427 compatible = "ti,omap5430-timer";
428 reg = <0x4803e000 0x80>;
429 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
430 ti,hwmods = "timer9";
431 };
432
433 timer10: timer@48086000 {
434 compatible = "ti,omap5430-timer";
435 reg = <0x48086000 0x80>;
436 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
437 ti,hwmods = "timer10";
438 };
439
440 timer11: timer@48088000 {
441 compatible = "ti,omap5430-timer";
442 reg = <0x48088000 0x80>;
443 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
444 ti,hwmods = "timer11";
445 ti,timer-pwm;
446 };
447
448 timer13: timer@48828000 {
449 compatible = "ti,omap5430-timer";
450 reg = <0x48828000 0x80>;
451 ti,hwmods = "timer13";
452 status = "disabled";
453 };
454
455 timer14: timer@4882a000 {
456 compatible = "ti,omap5430-timer";
457 reg = <0x4882a000 0x80>;
458 ti,hwmods = "timer14";
459 status = "disabled";
460 };
461
462 timer15: timer@4882c000 {
463 compatible = "ti,omap5430-timer";
464 reg = <0x4882c000 0x80>;
465 ti,hwmods = "timer15";
466 status = "disabled";
467 };
468
469 timer16: timer@4882e000 {
470 compatible = "ti,omap5430-timer";
471 reg = <0x4882e000 0x80>;
472 ti,hwmods = "timer16";
473 status = "disabled";
474 };
475
476 wdt2: wdt@4ae14000 {
477 compatible = "ti,omap4-wdt";
478 reg = <0x4ae14000 0x80>;
479 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
480 ti,hwmods = "wd_timer2";
481 };
482
483 i2c1: i2c@48070000 {
484 compatible = "ti,omap4-i2c";
485 reg = <0x48070000 0x100>;
486 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
487 #address-cells = <1>;
488 #size-cells = <0>;
489 ti,hwmods = "i2c1";
490 status = "disabled";
491 };
492
493 i2c2: i2c@48072000 {
494 compatible = "ti,omap4-i2c";
495 reg = <0x48072000 0x100>;
496 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
497 #address-cells = <1>;
498 #size-cells = <0>;
499 ti,hwmods = "i2c2";
500 status = "disabled";
501 };
502
503 i2c3: i2c@48060000 {
504 compatible = "ti,omap4-i2c";
505 reg = <0x48060000 0x100>;
506 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
507 #address-cells = <1>;
508 #size-cells = <0>;
509 ti,hwmods = "i2c3";
510 status = "disabled";
511 };
512
513 i2c4: i2c@4807a000 {
514 compatible = "ti,omap4-i2c";
515 reg = <0x4807a000 0x100>;
516 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
517 #address-cells = <1>;
518 #size-cells = <0>;
519 ti,hwmods = "i2c4";
520 status = "disabled";
521 };
522
523 i2c5: i2c@4807c000 {
524 compatible = "ti,omap4-i2c";
525 reg = <0x4807c000 0x100>;
526 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
527 #address-cells = <1>;
528 #size-cells = <0>;
529 ti,hwmods = "i2c5";
530 status = "disabled";
531 };
532
533 mmc1: mmc@4809c000 {
534 compatible = "ti,omap4-hsmmc";
535 reg = <0x4809c000 0x400>;
536 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
537 ti,hwmods = "mmc1";
538 ti,dual-volt;
539 ti,needs-special-reset;
540 dmas = <&sdma 61>, <&sdma 62>;
541 dma-names = "tx", "rx";
542 status = "disabled";
Balaji T Kcd042fe2014-02-19 20:26:40 +0530[diff] [blame^]543 pbias-supply = <&pbias_mmc_reg>;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530[diff] [blame]544 };
545
546 mmc2: mmc@480b4000 {
547 compatible = "ti,omap4-hsmmc";
548 reg = <0x480b4000 0x400>;
549 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
550 ti,hwmods = "mmc2";
551 ti,needs-special-reset;
552 dmas = <&sdma 47>, <&sdma 48>;
553 dma-names = "tx", "rx";
554 status = "disabled";
555 };
556
557 mmc3: mmc@480ad000 {
558 compatible = "ti,omap4-hsmmc";
559 reg = <0x480ad000 0x400>;
560 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
561 ti,hwmods = "mmc3";
562 ti,needs-special-reset;
563 dmas = <&sdma 77>, <&sdma 78>;
564 dma-names = "tx", "rx";
565 status = "disabled";
566 };
567
568 mmc4: mmc@480d1000 {
569 compatible = "ti,omap4-hsmmc";
570 reg = <0x480d1000 0x400>;
571 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
572 ti,hwmods = "mmc4";
573 ti,needs-special-reset;
574 dmas = <&sdma 57>, <&sdma 58>;
575 dma-names = "tx", "rx";
576 status = "disabled";
577 };
578
579 mcspi1: spi@48098000 {
580 compatible = "ti,omap4-mcspi";
581 reg = <0x48098000 0x200>;
582 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
583 #address-cells = <1>;
584 #size-cells = <0>;
585 ti,hwmods = "mcspi1";
586 ti,spi-num-cs = <4>;
587 dmas = <&sdma 35>,
588 <&sdma 36>,
589 <&sdma 37>,
590 <&sdma 38>,
591 <&sdma 39>,
592 <&sdma 40>,
593 <&sdma 41>,
594 <&sdma 42>;
595 dma-names = "tx0", "rx0", "tx1", "rx1",
596 "tx2", "rx2", "tx3", "rx3";
597 status = "disabled";
598 };
599
600 mcspi2: spi@4809a000 {
601 compatible = "ti,omap4-mcspi";
602 reg = <0x4809a000 0x200>;
603 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
604 #address-cells = <1>;
605 #size-cells = <0>;
606 ti,hwmods = "mcspi2";
607 ti,spi-num-cs = <2>;
608 dmas = <&sdma 43>,
609 <&sdma 44>,
610 <&sdma 45>,
611 <&sdma 46>;
612 dma-names = "tx0", "rx0", "tx1", "rx1";
613 status = "disabled";
614 };
615
616 mcspi3: spi@480b8000 {
617 compatible = "ti,omap4-mcspi";
618 reg = <0x480b8000 0x200>;
619 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
620 #address-cells = <1>;
621 #size-cells = <0>;
622 ti,hwmods = "mcspi3";
623 ti,spi-num-cs = <2>;
624 dmas = <&sdma 15>, <&sdma 16>;
625 dma-names = "tx0", "rx0";
626 status = "disabled";
627 };
628
629 mcspi4: spi@480ba000 {
630 compatible = "ti,omap4-mcspi";
631 reg = <0x480ba000 0x200>;
632 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
633 #address-cells = <1>;
634 #size-cells = <0>;
635 ti,hwmods = "mcspi4";
636 ti,spi-num-cs = <1>;
637 dmas = <&sdma 70>, <&sdma 71>;
638 dma-names = "tx0", "rx0";
639 status = "disabled";
640 };
641 };
642};
Tero Kristoee6c7502013-07-18 17:18:33 +0300[diff] [blame]643
644/include/ "dra7xx-clocks.dtsi"