blob: 2a5090fb9113f5d876f6bc0fe8f20504ba803f48 [file] [log] [blame]
Catalin Marinas6170a972012-03-05 11:49:29 +00001/*
2 * Copyright (C) 2012 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __ASM_FUTEX_H
17#define __ASM_FUTEX_H
18
19#ifdef __KERNEL__
20
21#include <linux/futex.h>
22#include <linux/uaccess.h>
James Morse338d4f42015-07-22 19:05:54 +010023
24#include <asm/alternative.h>
25#include <asm/cpufeature.h>
Catalin Marinas6170a972012-03-05 11:49:29 +000026#include <asm/errno.h>
James Morse338d4f42015-07-22 19:05:54 +010027#include <asm/sysreg.h>
Catalin Marinas6170a972012-03-05 11:49:29 +000028
29#define __futex_atomic_op(insn, ret, oldval, uaddr, tmp, oparg) \
30 asm volatile( \
James Morse338d4f42015-07-22 19:05:54 +010031 ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, \
32 CONFIG_ARM64_PAN) \
Will Deacon0ea366f2015-05-29 13:31:10 +010033" prfm pstl1strm, %2\n" \
Will Deacon8e86f0b2014-02-04 12:29:12 +000034"1: ldxr %w1, %2\n" \
Catalin Marinas6170a972012-03-05 11:49:29 +000035 insn "\n" \
36"2: stlxr %w3, %w0, %2\n" \
37" cbnz %w3, 1b\n" \
Will Deacon8e86f0b2014-02-04 12:29:12 +000038" dmb ish\n" \
Catalin Marinas6170a972012-03-05 11:49:29 +000039"3:\n" \
40" .pushsection .fixup,\"ax\"\n" \
Will Deacon4da7a562013-11-06 19:31:24 +000041" .align 2\n" \
Catalin Marinas6170a972012-03-05 11:49:29 +000042"4: mov %w0, %w5\n" \
43" b 3b\n" \
44" .popsection\n" \
Ard Biesheuvel6c94f272016-01-01 15:02:12 +010045 _ASM_EXTABLE(1b, 4b) \
46 _ASM_EXTABLE(2b, 4b) \
James Morse338d4f42015-07-22 19:05:54 +010047 ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, \
48 CONFIG_ARM64_PAN) \
Catalin Marinas6170a972012-03-05 11:49:29 +000049 : "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp) \
50 : "r" (oparg), "Ir" (-EFAULT) \
Will Deacon95c41892014-02-04 12:29:13 +000051 : "memory")
Catalin Marinas6170a972012-03-05 11:49:29 +000052
53static inline int
Jiri Slaby81da9f82017-08-24 09:31:05 +020054arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
Catalin Marinas6170a972012-03-05 11:49:29 +000055{
Catalin Marinas6170a972012-03-05 11:49:29 +000056 int oldval = 0, ret, tmp;
Catalin Marinas6170a972012-03-05 11:49:29 +000057
David Hildenbrand2f09b222015-05-11 17:52:17 +020058 pagefault_disable();
Catalin Marinas6170a972012-03-05 11:49:29 +000059
60 switch (op) {
61 case FUTEX_OP_SET:
62 __futex_atomic_op("mov %w0, %w4",
63 ret, oldval, uaddr, tmp, oparg);
64 break;
65 case FUTEX_OP_ADD:
66 __futex_atomic_op("add %w0, %w1, %w4",
67 ret, oldval, uaddr, tmp, oparg);
68 break;
69 case FUTEX_OP_OR:
70 __futex_atomic_op("orr %w0, %w1, %w4",
71 ret, oldval, uaddr, tmp, oparg);
72 break;
73 case FUTEX_OP_ANDN:
74 __futex_atomic_op("and %w0, %w1, %w4",
75 ret, oldval, uaddr, tmp, ~oparg);
76 break;
77 case FUTEX_OP_XOR:
78 __futex_atomic_op("eor %w0, %w1, %w4",
79 ret, oldval, uaddr, tmp, oparg);
80 break;
81 default:
82 ret = -ENOSYS;
83 }
84
David Hildenbrand2f09b222015-05-11 17:52:17 +020085 pagefault_enable();
Catalin Marinas6170a972012-03-05 11:49:29 +000086
Jiri Slaby81da9f82017-08-24 09:31:05 +020087 if (!ret)
88 *oval = oldval;
89
Catalin Marinas6170a972012-03-05 11:49:29 +000090 return ret;
91}
92
93static inline int
Will Deacon1cd969f2018-02-05 15:34:24 +000094futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *_uaddr,
Catalin Marinas6170a972012-03-05 11:49:29 +000095 u32 oldval, u32 newval)
96{
97 int ret = 0;
98 u32 val, tmp;
Will Deacon1cd969f2018-02-05 15:34:24 +000099 u32 __user *uaddr;
Catalin Marinas6170a972012-03-05 11:49:29 +0000100
Will Deacon1cd969f2018-02-05 15:34:24 +0000101 if (!access_ok(VERIFY_WRITE, _uaddr, sizeof(u32)))
Catalin Marinas6170a972012-03-05 11:49:29 +0000102 return -EFAULT;
103
Will Deacon1cd969f2018-02-05 15:34:24 +0000104 uaddr = __uaccess_mask_ptr(_uaddr);
Catalin Marinas6170a972012-03-05 11:49:29 +0000105 asm volatile("// futex_atomic_cmpxchg_inatomic\n"
James Morse811d61e2016-02-02 15:53:59 +0000106ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, CONFIG_ARM64_PAN)
Will Deacon0ea366f2015-05-29 13:31:10 +0100107" prfm pstl1strm, %2\n"
Will Deacon8e86f0b2014-02-04 12:29:12 +0000108"1: ldxr %w1, %2\n"
Catalin Marinas6170a972012-03-05 11:49:29 +0000109" sub %w3, %w1, %w4\n"
110" cbnz %w3, 3f\n"
111"2: stlxr %w3, %w5, %2\n"
112" cbnz %w3, 1b\n"
Will Deacon8e86f0b2014-02-04 12:29:12 +0000113" dmb ish\n"
Catalin Marinas6170a972012-03-05 11:49:29 +0000114"3:\n"
115" .pushsection .fixup,\"ax\"\n"
116"4: mov %w0, %w6\n"
117" b 3b\n"
118" .popsection\n"
Ard Biesheuvel6c94f272016-01-01 15:02:12 +0100119 _ASM_EXTABLE(1b, 4b)
120 _ASM_EXTABLE(2b, 4b)
James Morse811d61e2016-02-02 15:53:59 +0000121ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, CONFIG_ARM64_PAN)
Catalin Marinas6170a972012-03-05 11:49:29 +0000122 : "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp)
123 : "r" (oldval), "r" (newval), "Ir" (-EFAULT)
Will Deacon95c41892014-02-04 12:29:13 +0000124 : "memory");
Catalin Marinas6170a972012-03-05 11:49:29 +0000125
126 *uval = val;
127 return ret;
128}
129
130#endif /* __KERNEL__ */
131#endif /* __ASM_FUTEX_H */