Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 1 | /* |
| 2 | * PCIe host controller driver for Samsung EXYNOS SoCs |
| 3 | * |
| 4 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. |
| 5 | * http://www.samsung.com |
| 6 | * |
| 7 | * Author: Jingoo Han <jg1.han@samsung.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/clk.h> |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/gpio.h> |
| 17 | #include <linux/interrupt.h> |
| 18 | #include <linux/kernel.h> |
Paul Gortmaker | caf5548 | 2016-08-22 17:59:47 -0400 | [diff] [blame] | 19 | #include <linux/init.h> |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 20 | #include <linux/of_gpio.h> |
| 21 | #include <linux/pci.h> |
| 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/resource.h> |
| 24 | #include <linux/signal.h> |
| 25 | #include <linux/types.h> |
| 26 | |
| 27 | #include "pcie-designware.h" |
| 28 | |
| 29 | #define to_exynos_pcie(x) container_of(x, struct exynos_pcie, pp) |
| 30 | |
| 31 | struct exynos_pcie { |
Bjorn Helgaas | 6b1f185 | 2016-10-06 13:33:40 -0500 | [diff] [blame] | 32 | struct pcie_port pp; |
| 33 | void __iomem *elbi_base; /* DT 0th resource */ |
| 34 | void __iomem *phy_base; /* DT 1st resource */ |
| 35 | void __iomem *block_base; /* DT 2nd resource */ |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 36 | int reset_gpio; |
| 37 | struct clk *clk; |
| 38 | struct clk *bus_clk; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 39 | }; |
| 40 | |
| 41 | /* PCIe ELBI registers */ |
| 42 | #define PCIE_IRQ_PULSE 0x000 |
| 43 | #define IRQ_INTA_ASSERT (0x1 << 0) |
| 44 | #define IRQ_INTB_ASSERT (0x1 << 2) |
| 45 | #define IRQ_INTC_ASSERT (0x1 << 4) |
| 46 | #define IRQ_INTD_ASSERT (0x1 << 6) |
| 47 | #define PCIE_IRQ_LEVEL 0x004 |
| 48 | #define PCIE_IRQ_SPECIAL 0x008 |
| 49 | #define PCIE_IRQ_EN_PULSE 0x00c |
| 50 | #define PCIE_IRQ_EN_LEVEL 0x010 |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 51 | #define IRQ_MSI_ENABLE (0x1 << 2) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 52 | #define PCIE_IRQ_EN_SPECIAL 0x014 |
| 53 | #define PCIE_PWR_RESET 0x018 |
| 54 | #define PCIE_CORE_RESET 0x01c |
| 55 | #define PCIE_CORE_RESET_ENABLE (0x1 << 0) |
| 56 | #define PCIE_STICKY_RESET 0x020 |
| 57 | #define PCIE_NONSTICKY_RESET 0x024 |
| 58 | #define PCIE_APP_INIT_RESET 0x028 |
| 59 | #define PCIE_APP_LTSSM_ENABLE 0x02c |
| 60 | #define PCIE_ELBI_RDLH_LINKUP 0x064 |
| 61 | #define PCIE_ELBI_LTSSM_ENABLE 0x1 |
| 62 | #define PCIE_ELBI_SLV_AWMISC 0x11c |
| 63 | #define PCIE_ELBI_SLV_ARMISC 0x120 |
| 64 | #define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21) |
| 65 | |
| 66 | /* PCIe Purple registers */ |
| 67 | #define PCIE_PHY_GLOBAL_RESET 0x000 |
| 68 | #define PCIE_PHY_COMMON_RESET 0x004 |
| 69 | #define PCIE_PHY_CMN_REG 0x008 |
| 70 | #define PCIE_PHY_MAC_RESET 0x00c |
| 71 | #define PCIE_PHY_PLL_LOCKED 0x010 |
| 72 | #define PCIE_PHY_TRSVREG_RESET 0x020 |
| 73 | #define PCIE_PHY_TRSV_RESET 0x024 |
| 74 | |
| 75 | /* PCIe PHY registers */ |
| 76 | #define PCIE_PHY_IMPEDANCE 0x004 |
| 77 | #define PCIE_PHY_PLL_DIV_0 0x008 |
| 78 | #define PCIE_PHY_PLL_BIAS 0x00c |
| 79 | #define PCIE_PHY_DCC_FEEDBACK 0x014 |
| 80 | #define PCIE_PHY_PLL_DIV_1 0x05c |
Jingoo Han | f62b878 | 2013-09-06 17:21:45 +0900 | [diff] [blame] | 81 | #define PCIE_PHY_COMMON_POWER 0x064 |
| 82 | #define PCIE_PHY_COMMON_PD_CMN (0x1 << 3) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 83 | #define PCIE_PHY_TRSV0_EMP_LVL 0x084 |
| 84 | #define PCIE_PHY_TRSV0_DRV_LVL 0x088 |
| 85 | #define PCIE_PHY_TRSV0_RXCDR 0x0ac |
Jingoo Han | f62b878 | 2013-09-06 17:21:45 +0900 | [diff] [blame] | 86 | #define PCIE_PHY_TRSV0_POWER 0x0c4 |
| 87 | #define PCIE_PHY_TRSV0_PD_TSV (0x1 << 7) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 88 | #define PCIE_PHY_TRSV0_LVCC 0x0dc |
| 89 | #define PCIE_PHY_TRSV1_EMP_LVL 0x144 |
| 90 | #define PCIE_PHY_TRSV1_RXCDR 0x16c |
Jingoo Han | f62b878 | 2013-09-06 17:21:45 +0900 | [diff] [blame] | 91 | #define PCIE_PHY_TRSV1_POWER 0x184 |
| 92 | #define PCIE_PHY_TRSV1_PD_TSV (0x1 << 7) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 93 | #define PCIE_PHY_TRSV1_LVCC 0x19c |
| 94 | #define PCIE_PHY_TRSV2_EMP_LVL 0x204 |
| 95 | #define PCIE_PHY_TRSV2_RXCDR 0x22c |
Jingoo Han | f62b878 | 2013-09-06 17:21:45 +0900 | [diff] [blame] | 96 | #define PCIE_PHY_TRSV2_POWER 0x244 |
| 97 | #define PCIE_PHY_TRSV2_PD_TSV (0x1 << 7) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 98 | #define PCIE_PHY_TRSV2_LVCC 0x25c |
| 99 | #define PCIE_PHY_TRSV3_EMP_LVL 0x2c4 |
| 100 | #define PCIE_PHY_TRSV3_RXCDR 0x2ec |
Jingoo Han | f62b878 | 2013-09-06 17:21:45 +0900 | [diff] [blame] | 101 | #define PCIE_PHY_TRSV3_POWER 0x304 |
| 102 | #define PCIE_PHY_TRSV3_PD_TSV (0x1 << 7) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 103 | #define PCIE_PHY_TRSV3_LVCC 0x31c |
| 104 | |
Bjorn Helgaas | 10284bf | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 105 | static void exynos_elb_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg) |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 106 | { |
Bjorn Helgaas | 10284bf | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 107 | writel(val, exynos_pcie->elbi_base + reg); |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 108 | } |
| 109 | |
Bjorn Helgaas | 10284bf | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 110 | static u32 exynos_elb_readl(struct exynos_pcie *exynos_pcie, u32 reg) |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 111 | { |
Bjorn Helgaas | 10284bf | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 112 | return readl(exynos_pcie->elbi_base + reg); |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 113 | } |
| 114 | |
Bjorn Helgaas | 10284bf | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 115 | static void exynos_phy_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg) |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 116 | { |
Bjorn Helgaas | 10284bf | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 117 | writel(val, exynos_pcie->phy_base + reg); |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 118 | } |
| 119 | |
Bjorn Helgaas | 10284bf | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 120 | static u32 exynos_phy_readl(struct exynos_pcie *exynos_pcie, u32 reg) |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 121 | { |
Bjorn Helgaas | 10284bf | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 122 | return readl(exynos_pcie->phy_base + reg); |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 123 | } |
| 124 | |
Bjorn Helgaas | 10284bf | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 125 | static void exynos_blk_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg) |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 126 | { |
Bjorn Helgaas | 10284bf | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 127 | writel(val, exynos_pcie->block_base + reg); |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 128 | } |
| 129 | |
Bjorn Helgaas | 10284bf | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 130 | static u32 exynos_blk_readl(struct exynos_pcie *exynos_pcie, u32 reg) |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 131 | { |
Bjorn Helgaas | 10284bf | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 132 | return readl(exynos_pcie->block_base + reg); |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 133 | } |
| 134 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 135 | static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *exynos_pcie, |
| 136 | bool on) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 137 | { |
| 138 | u32 val; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 139 | |
| 140 | if (on) { |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 141 | val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 142 | val |= PCIE_ELBI_SLV_DBI_ENABLE; |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 143 | exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 144 | } else { |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 145 | val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 146 | val &= ~PCIE_ELBI_SLV_DBI_ENABLE; |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 147 | exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 148 | } |
| 149 | } |
| 150 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 151 | static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *exynos_pcie, |
| 152 | bool on) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 153 | { |
| 154 | u32 val; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 155 | |
| 156 | if (on) { |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 157 | val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 158 | val |= PCIE_ELBI_SLV_DBI_ENABLE; |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 159 | exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 160 | } else { |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 161 | val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 162 | val &= ~PCIE_ELBI_SLV_DBI_ENABLE; |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 163 | exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 164 | } |
| 165 | } |
| 166 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 167 | static void exynos_pcie_assert_core_reset(struct exynos_pcie *exynos_pcie) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 168 | { |
| 169 | u32 val; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 170 | |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 171 | val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 172 | val &= ~PCIE_CORE_RESET_ENABLE; |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 173 | exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET); |
| 174 | exynos_elb_writel(exynos_pcie, 0, PCIE_PWR_RESET); |
| 175 | exynos_elb_writel(exynos_pcie, 0, PCIE_STICKY_RESET); |
| 176 | exynos_elb_writel(exynos_pcie, 0, PCIE_NONSTICKY_RESET); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 177 | } |
| 178 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 179 | static void exynos_pcie_deassert_core_reset(struct exynos_pcie *exynos_pcie) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 180 | { |
| 181 | u32 val; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 182 | |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 183 | val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 184 | val |= PCIE_CORE_RESET_ENABLE; |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 185 | |
| 186 | exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET); |
| 187 | exynos_elb_writel(exynos_pcie, 1, PCIE_STICKY_RESET); |
| 188 | exynos_elb_writel(exynos_pcie, 1, PCIE_NONSTICKY_RESET); |
| 189 | exynos_elb_writel(exynos_pcie, 1, PCIE_APP_INIT_RESET); |
| 190 | exynos_elb_writel(exynos_pcie, 0, PCIE_APP_INIT_RESET); |
| 191 | exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_MAC_RESET); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 192 | } |
| 193 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 194 | static void exynos_pcie_assert_phy_reset(struct exynos_pcie *exynos_pcie) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 195 | { |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 196 | exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_MAC_RESET); |
| 197 | exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_GLOBAL_RESET); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 198 | } |
| 199 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 200 | static void exynos_pcie_deassert_phy_reset(struct exynos_pcie *exynos_pcie) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 201 | { |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 202 | exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_GLOBAL_RESET); |
| 203 | exynos_elb_writel(exynos_pcie, 1, PCIE_PWR_RESET); |
| 204 | exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET); |
| 205 | exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_CMN_REG); |
| 206 | exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSVREG_RESET); |
| 207 | exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSV_RESET); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 208 | } |
| 209 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 210 | static void exynos_pcie_power_on_phy(struct exynos_pcie *exynos_pcie) |
Jingoo Han | f62b878 | 2013-09-06 17:21:45 +0900 | [diff] [blame] | 211 | { |
| 212 | u32 val; |
Jingoo Han | f62b878 | 2013-09-06 17:21:45 +0900 | [diff] [blame] | 213 | |
| 214 | val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER); |
| 215 | val &= ~PCIE_PHY_COMMON_PD_CMN; |
| 216 | exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER); |
| 217 | |
| 218 | val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER); |
| 219 | val &= ~PCIE_PHY_TRSV0_PD_TSV; |
| 220 | exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER); |
| 221 | |
| 222 | val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER); |
| 223 | val &= ~PCIE_PHY_TRSV1_PD_TSV; |
| 224 | exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER); |
| 225 | |
| 226 | val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER); |
| 227 | val &= ~PCIE_PHY_TRSV2_PD_TSV; |
| 228 | exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER); |
| 229 | |
| 230 | val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER); |
| 231 | val &= ~PCIE_PHY_TRSV3_PD_TSV; |
| 232 | exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER); |
| 233 | } |
| 234 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 235 | static void exynos_pcie_power_off_phy(struct exynos_pcie *exynos_pcie) |
Jingoo Han | f62b878 | 2013-09-06 17:21:45 +0900 | [diff] [blame] | 236 | { |
| 237 | u32 val; |
Jingoo Han | f62b878 | 2013-09-06 17:21:45 +0900 | [diff] [blame] | 238 | |
| 239 | val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER); |
| 240 | val |= PCIE_PHY_COMMON_PD_CMN; |
| 241 | exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER); |
| 242 | |
| 243 | val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER); |
| 244 | val |= PCIE_PHY_TRSV0_PD_TSV; |
| 245 | exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER); |
| 246 | |
| 247 | val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER); |
| 248 | val |= PCIE_PHY_TRSV1_PD_TSV; |
| 249 | exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER); |
| 250 | |
| 251 | val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER); |
| 252 | val |= PCIE_PHY_TRSV2_PD_TSV; |
| 253 | exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER); |
| 254 | |
| 255 | val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER); |
| 256 | val |= PCIE_PHY_TRSV3_PD_TSV; |
| 257 | exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER); |
| 258 | } |
| 259 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 260 | static void exynos_pcie_init_phy(struct exynos_pcie *exynos_pcie) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 261 | { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 262 | /* DCC feedback control off */ |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 263 | exynos_phy_writel(exynos_pcie, 0x29, PCIE_PHY_DCC_FEEDBACK); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 264 | |
| 265 | /* set TX/RX impedance */ |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 266 | exynos_phy_writel(exynos_pcie, 0xd5, PCIE_PHY_IMPEDANCE); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 267 | |
| 268 | /* set 50Mhz PHY clock */ |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 269 | exynos_phy_writel(exynos_pcie, 0x14, PCIE_PHY_PLL_DIV_0); |
| 270 | exynos_phy_writel(exynos_pcie, 0x12, PCIE_PHY_PLL_DIV_1); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 271 | |
| 272 | /* set TX Differential output for lane 0 */ |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 273 | exynos_phy_writel(exynos_pcie, 0x7f, PCIE_PHY_TRSV0_DRV_LVL); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 274 | |
| 275 | /* set TX Pre-emphasis Level Control for lane 0 to minimum */ |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 276 | exynos_phy_writel(exynos_pcie, 0x0, PCIE_PHY_TRSV0_EMP_LVL); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 277 | |
| 278 | /* set RX clock and data recovery bandwidth */ |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 279 | exynos_phy_writel(exynos_pcie, 0xe7, PCIE_PHY_PLL_BIAS); |
| 280 | exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV0_RXCDR); |
| 281 | exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV1_RXCDR); |
| 282 | exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV2_RXCDR); |
| 283 | exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV3_RXCDR); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 284 | |
| 285 | /* change TX Pre-emphasis Level Control for lanes */ |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 286 | exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV0_EMP_LVL); |
| 287 | exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV1_EMP_LVL); |
| 288 | exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV2_EMP_LVL); |
| 289 | exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV3_EMP_LVL); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 290 | |
| 291 | /* set LVCC */ |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 292 | exynos_phy_writel(exynos_pcie, 0x20, PCIE_PHY_TRSV0_LVCC); |
| 293 | exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV1_LVCC); |
| 294 | exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV2_LVCC); |
| 295 | exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV3_LVCC); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 296 | } |
| 297 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 298 | static void exynos_pcie_assert_reset(struct exynos_pcie *exynos_pcie) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 299 | { |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 300 | struct pcie_port *pp = &exynos_pcie->pp; |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 301 | struct device *dev = pp->dev; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 302 | |
| 303 | if (exynos_pcie->reset_gpio >= 0) |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 304 | devm_gpio_request_one(dev, exynos_pcie->reset_gpio, |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 305 | GPIOF_OUT_INIT_HIGH, "RESET"); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 306 | } |
| 307 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 308 | static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 309 | { |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 310 | struct pcie_port *pp = &exynos_pcie->pp; |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 311 | struct device *dev = pp->dev; |
Bjorn Helgaas | 6cbb247 | 2015-06-02 16:47:17 -0500 | [diff] [blame] | 312 | u32 val; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 313 | |
| 314 | if (dw_pcie_link_up(pp)) { |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 315 | dev_err(dev, "Link already up\n"); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 316 | return 0; |
| 317 | } |
| 318 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 319 | exynos_pcie_assert_core_reset(exynos_pcie); |
| 320 | exynos_pcie_assert_phy_reset(exynos_pcie); |
| 321 | exynos_pcie_deassert_phy_reset(exynos_pcie); |
| 322 | exynos_pcie_power_on_phy(exynos_pcie); |
| 323 | exynos_pcie_init_phy(exynos_pcie); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 324 | |
| 325 | /* pulse for common reset */ |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 326 | exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_COMMON_RESET); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 327 | udelay(500); |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 328 | exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 329 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 330 | exynos_pcie_deassert_core_reset(exynos_pcie); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 331 | dw_pcie_setup_rc(pp); |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 332 | exynos_pcie_assert_reset(exynos_pcie); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 333 | |
| 334 | /* assert LTSSM enable */ |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 335 | exynos_elb_writel(exynos_pcie, PCIE_ELBI_LTSSM_ENABLE, |
| 336 | PCIE_APP_LTSSM_ENABLE); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 337 | |
| 338 | /* check if the link is up or not */ |
Joao Pinto | 886bc5c | 2016-03-10 14:44:35 -0600 | [diff] [blame] | 339 | if (!dw_pcie_wait_for_link(pp)) |
| 340 | return 0; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 341 | |
Bjorn Helgaas | 6cbb247 | 2015-06-02 16:47:17 -0500 | [diff] [blame] | 342 | while (exynos_phy_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED) == 0) { |
| 343 | val = exynos_blk_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED); |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 344 | dev_info(dev, "PLL Locked: 0x%x\n", val); |
Bjorn Helgaas | 6cbb247 | 2015-06-02 16:47:17 -0500 | [diff] [blame] | 345 | } |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 346 | exynos_pcie_power_off_phy(exynos_pcie); |
Joao Pinto | 886bc5c | 2016-03-10 14:44:35 -0600 | [diff] [blame] | 347 | return -ETIMEDOUT; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 348 | } |
| 349 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 350 | static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *exynos_pcie) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 351 | { |
| 352 | u32 val; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 353 | |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 354 | val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_PULSE); |
| 355 | exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_PULSE); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 356 | } |
| 357 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 358 | static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *exynos_pcie) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 359 | { |
| 360 | u32 val; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 361 | |
| 362 | /* enable INTX interrupt */ |
| 363 | val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | |
Jaehoon Chung | 01d06a9 | 2015-03-25 14:13:12 +0900 | [diff] [blame] | 364 | IRQ_INTC_ASSERT | IRQ_INTD_ASSERT; |
Seungwon Jeon | 058dd01 | 2013-08-29 21:35:56 +0900 | [diff] [blame] | 365 | exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_PULSE); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 366 | } |
| 367 | |
| 368 | static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) |
| 369 | { |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 370 | struct exynos_pcie *exynos_pcie = arg; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 371 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 372 | exynos_pcie_clear_irq_pulse(exynos_pcie); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 373 | return IRQ_HANDLED; |
| 374 | } |
| 375 | |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 376 | static irqreturn_t exynos_pcie_msi_irq_handler(int irq, void *arg) |
| 377 | { |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 378 | struct exynos_pcie *exynos_pcie = arg; |
| 379 | struct pcie_port *pp = &exynos_pcie->pp; |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 380 | |
Lucas Stach | 7f4f16e | 2014-03-28 17:52:58 +0100 | [diff] [blame] | 381 | return dw_handle_msi_irq(pp); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 382 | } |
| 383 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 384 | static void exynos_pcie_msi_init(struct exynos_pcie *exynos_pcie) |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 385 | { |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 386 | struct pcie_port *pp = &exynos_pcie->pp; |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 387 | u32 val; |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 388 | |
| 389 | dw_pcie_msi_init(pp); |
| 390 | |
| 391 | /* enable MSI interrupt */ |
| 392 | val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_EN_LEVEL); |
| 393 | val |= IRQ_MSI_ENABLE; |
| 394 | exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_LEVEL); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 395 | } |
| 396 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 397 | static void exynos_pcie_enable_interrupts(struct exynos_pcie *exynos_pcie) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 398 | { |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 399 | exynos_pcie_enable_irq_pulse(exynos_pcie); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 400 | |
| 401 | if (IS_ENABLED(CONFIG_PCI_MSI)) |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 402 | exynos_pcie_msi_init(exynos_pcie); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 403 | } |
| 404 | |
Bjorn Helgaas | 53e5bff1 | 2016-10-10 07:50:07 -0500 | [diff] [blame] | 405 | static u32 exynos_pcie_readl_rc(struct pcie_port *pp, u32 reg) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 406 | { |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 407 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
Bjorn Helgaas | 446fc23 | 2016-08-17 14:17:58 -0500 | [diff] [blame] | 408 | u32 val; |
| 409 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 410 | exynos_pcie_sideband_dbi_r_mode(exynos_pcie, true); |
Bjorn Helgaas | 7e00dfd | 2016-10-06 13:25:46 -0500 | [diff] [blame] | 411 | val = readl(pp->dbi_base + reg); |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 412 | exynos_pcie_sideband_dbi_r_mode(exynos_pcie, false); |
Bjorn Helgaas | 446fc23 | 2016-08-17 14:17:58 -0500 | [diff] [blame] | 413 | return val; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 414 | } |
| 415 | |
Bjorn Helgaas | 53e5bff1 | 2016-10-10 07:50:07 -0500 | [diff] [blame] | 416 | static void exynos_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 417 | { |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 418 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
| 419 | |
| 420 | exynos_pcie_sideband_dbi_w_mode(exynos_pcie, true); |
Bjorn Helgaas | 7e00dfd | 2016-10-06 13:25:46 -0500 | [diff] [blame] | 421 | writel(val, pp->dbi_base + reg); |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 422 | exynos_pcie_sideband_dbi_w_mode(exynos_pcie, false); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 423 | } |
| 424 | |
| 425 | static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, |
| 426 | u32 *val) |
| 427 | { |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 428 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 429 | int ret; |
| 430 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 431 | exynos_pcie_sideband_dbi_r_mode(exynos_pcie, true); |
Gabriele Paoloni | 4c45852 | 2015-10-08 14:27:48 -0500 | [diff] [blame] | 432 | ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val); |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 433 | exynos_pcie_sideband_dbi_r_mode(exynos_pcie, false); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 434 | return ret; |
| 435 | } |
| 436 | |
| 437 | static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, |
| 438 | u32 val) |
| 439 | { |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 440 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 441 | int ret; |
| 442 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 443 | exynos_pcie_sideband_dbi_w_mode(exynos_pcie, true); |
Gabriele Paoloni | 4c45852 | 2015-10-08 14:27:48 -0500 | [diff] [blame] | 444 | ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val); |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 445 | exynos_pcie_sideband_dbi_w_mode(exynos_pcie, false); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 446 | return ret; |
| 447 | } |
| 448 | |
| 449 | static int exynos_pcie_link_up(struct pcie_port *pp) |
| 450 | { |
| 451 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 452 | u32 val; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 453 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 454 | val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_RDLH_LINKUP); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 455 | if (val == PCIE_ELBI_LTSSM_ENABLE) |
| 456 | return 1; |
| 457 | |
| 458 | return 0; |
| 459 | } |
| 460 | |
| 461 | static void exynos_pcie_host_init(struct pcie_port *pp) |
| 462 | { |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 463 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
| 464 | |
| 465 | exynos_pcie_establish_link(exynos_pcie); |
| 466 | exynos_pcie_enable_interrupts(exynos_pcie); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 467 | } |
| 468 | |
| 469 | static struct pcie_host_ops exynos_pcie_host_ops = { |
| 470 | .readl_rc = exynos_pcie_readl_rc, |
| 471 | .writel_rc = exynos_pcie_writel_rc, |
| 472 | .rd_own_conf = exynos_pcie_rd_own_conf, |
| 473 | .wr_own_conf = exynos_pcie_wr_own_conf, |
| 474 | .link_up = exynos_pcie_link_up, |
| 475 | .host_init = exynos_pcie_host_init, |
| 476 | }; |
| 477 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 478 | static int __init exynos_add_pcie_port(struct exynos_pcie *exynos_pcie, |
Jingoo Han | 70b3e89 | 2014-10-22 13:58:49 +0900 | [diff] [blame] | 479 | struct platform_device *pdev) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 480 | { |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 481 | struct pcie_port *pp = &exynos_pcie->pp; |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 482 | struct device *dev = pp->dev; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 483 | int ret; |
| 484 | |
| 485 | pp->irq = platform_get_irq(pdev, 1); |
| 486 | if (!pp->irq) { |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 487 | dev_err(dev, "failed to get irq\n"); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 488 | return -ENODEV; |
| 489 | } |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 490 | ret = devm_request_irq(dev, pp->irq, exynos_pcie_irq_handler, |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 491 | IRQF_SHARED, "exynos-pcie", exynos_pcie); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 492 | if (ret) { |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 493 | dev_err(dev, "failed to request irq\n"); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 494 | return ret; |
| 495 | } |
| 496 | |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 497 | if (IS_ENABLED(CONFIG_PCI_MSI)) { |
| 498 | pp->msi_irq = platform_get_irq(pdev, 0); |
| 499 | if (!pp->msi_irq) { |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 500 | dev_err(dev, "failed to get msi irq\n"); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 501 | return -ENODEV; |
| 502 | } |
| 503 | |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 504 | ret = devm_request_irq(dev, pp->msi_irq, |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 505 | exynos_pcie_msi_irq_handler, |
Grygorii Strashko | 8ff0ef9 | 2015-12-10 21:18:20 +0200 | [diff] [blame] | 506 | IRQF_SHARED | IRQF_NO_THREAD, |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 507 | "exynos-pcie", exynos_pcie); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 508 | if (ret) { |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 509 | dev_err(dev, "failed to request msi irq\n"); |
Jingoo Han | f342d94 | 2013-09-06 15:54:59 +0900 | [diff] [blame] | 510 | return ret; |
| 511 | } |
| 512 | } |
| 513 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 514 | pp->root_bus_nr = -1; |
| 515 | pp->ops = &exynos_pcie_host_ops; |
| 516 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 517 | ret = dw_pcie_host_init(pp); |
| 518 | if (ret) { |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 519 | dev_err(dev, "failed to initialize host\n"); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 520 | return ret; |
| 521 | } |
| 522 | |
| 523 | return 0; |
| 524 | } |
| 525 | |
| 526 | static int __init exynos_pcie_probe(struct platform_device *pdev) |
| 527 | { |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 528 | struct device *dev = &pdev->dev; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 529 | struct exynos_pcie *exynos_pcie; |
| 530 | struct pcie_port *pp; |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 531 | struct device_node *np = dev->of_node; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 532 | struct resource *elbi_base; |
| 533 | struct resource *phy_base; |
| 534 | struct resource *block_base; |
| 535 | int ret; |
| 536 | |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 537 | exynos_pcie = devm_kzalloc(dev, sizeof(*exynos_pcie), GFP_KERNEL); |
Jingoo Han | 755ba5e | 2014-05-09 14:31:25 +0900 | [diff] [blame] | 538 | if (!exynos_pcie) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 539 | return -ENOMEM; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 540 | |
| 541 | pp = &exynos_pcie->pp; |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 542 | pp->dev = dev; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 543 | |
| 544 | exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); |
| 545 | |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 546 | exynos_pcie->clk = devm_clk_get(dev, "pcie"); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 547 | if (IS_ERR(exynos_pcie->clk)) { |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 548 | dev_err(dev, "Failed to get pcie rc clock\n"); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 549 | return PTR_ERR(exynos_pcie->clk); |
| 550 | } |
| 551 | ret = clk_prepare_enable(exynos_pcie->clk); |
| 552 | if (ret) |
| 553 | return ret; |
| 554 | |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 555 | exynos_pcie->bus_clk = devm_clk_get(dev, "pcie_bus"); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 556 | if (IS_ERR(exynos_pcie->bus_clk)) { |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 557 | dev_err(dev, "Failed to get pcie bus clock\n"); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 558 | ret = PTR_ERR(exynos_pcie->bus_clk); |
| 559 | goto fail_clk; |
| 560 | } |
| 561 | ret = clk_prepare_enable(exynos_pcie->bus_clk); |
| 562 | if (ret) |
| 563 | goto fail_clk; |
| 564 | |
| 565 | elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 566 | exynos_pcie->elbi_base = devm_ioremap_resource(dev, elbi_base); |
Wei Yongjun | f8db3c9 | 2013-09-29 10:29:11 +0800 | [diff] [blame] | 567 | if (IS_ERR(exynos_pcie->elbi_base)) { |
| 568 | ret = PTR_ERR(exynos_pcie->elbi_base); |
| 569 | goto fail_bus_clk; |
| 570 | } |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 571 | |
| 572 | phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 573 | exynos_pcie->phy_base = devm_ioremap_resource(dev, phy_base); |
Wei Yongjun | f8db3c9 | 2013-09-29 10:29:11 +0800 | [diff] [blame] | 574 | if (IS_ERR(exynos_pcie->phy_base)) { |
| 575 | ret = PTR_ERR(exynos_pcie->phy_base); |
| 576 | goto fail_bus_clk; |
| 577 | } |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 578 | |
| 579 | block_base = platform_get_resource(pdev, IORESOURCE_MEM, 2); |
Bjorn Helgaas | fae68d6 | 2016-10-06 13:33:41 -0500 | [diff] [blame] | 580 | exynos_pcie->block_base = devm_ioremap_resource(dev, block_base); |
Wei Yongjun | f8db3c9 | 2013-09-29 10:29:11 +0800 | [diff] [blame] | 581 | if (IS_ERR(exynos_pcie->block_base)) { |
| 582 | ret = PTR_ERR(exynos_pcie->block_base); |
| 583 | goto fail_bus_clk; |
| 584 | } |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 585 | |
Bjorn Helgaas | cc08e82 | 2016-10-06 13:33:39 -0500 | [diff] [blame] | 586 | ret = exynos_add_pcie_port(exynos_pcie, pdev); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 587 | if (ret < 0) |
| 588 | goto fail_bus_clk; |
| 589 | |
| 590 | platform_set_drvdata(pdev, exynos_pcie); |
| 591 | return 0; |
| 592 | |
| 593 | fail_bus_clk: |
| 594 | clk_disable_unprepare(exynos_pcie->bus_clk); |
| 595 | fail_clk: |
| 596 | clk_disable_unprepare(exynos_pcie->clk); |
| 597 | return ret; |
| 598 | } |
| 599 | |
| 600 | static int __exit exynos_pcie_remove(struct platform_device *pdev) |
| 601 | { |
| 602 | struct exynos_pcie *exynos_pcie = platform_get_drvdata(pdev); |
| 603 | |
| 604 | clk_disable_unprepare(exynos_pcie->bus_clk); |
| 605 | clk_disable_unprepare(exynos_pcie->clk); |
| 606 | |
| 607 | return 0; |
| 608 | } |
| 609 | |
| 610 | static const struct of_device_id exynos_pcie_of_match[] = { |
| 611 | { .compatible = "samsung,exynos5440-pcie", }, |
| 612 | {}, |
| 613 | }; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 614 | |
| 615 | static struct platform_driver exynos_pcie_driver = { |
| 616 | .remove = __exit_p(exynos_pcie_remove), |
| 617 | .driver = { |
| 618 | .name = "exynos-pcie", |
Sachin Kamat | eb36309 | 2013-10-21 14:36:43 +0530 | [diff] [blame] | 619 | .of_match_table = exynos_pcie_of_match, |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 620 | }, |
| 621 | }; |
| 622 | |
| 623 | /* Exynos PCIe driver does not allow module unload */ |
| 624 | |
Jingoo Han | 70b3e89 | 2014-10-22 13:58:49 +0900 | [diff] [blame] | 625 | static int __init exynos_pcie_init(void) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 626 | { |
| 627 | return platform_driver_probe(&exynos_pcie_driver, exynos_pcie_probe); |
| 628 | } |
Jingoo Han | 70b3e89 | 2014-10-22 13:58:49 +0900 | [diff] [blame] | 629 | subsys_initcall(exynos_pcie_init); |