blob: cb2da11c16dc5ca40db93de112ae9947db4d1f83 [file] [log] [blame]
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001config ARM64
2 def_bool y
Arun Chandran92980402014-10-10 12:31:24 +01003 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01004 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
Riku Voipio957e3fa2014-12-12 16:57:44 -08005 select ARCH_HAS_GCOV_PROFILE_ALL
Laura Abbott308c09f2014-08-08 14:23:25 -07006 select ARCH_HAS_SG_CHAIN
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +01007 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
Sudeep Hollac63c8702014-05-09 10:33:01 +01008 select ARCH_USE_CMPXCHG_LOCKREF
Peter Zijlstra4badad32014-06-06 19:53:16 +02009 select ARCH_SUPPORTS_ATOMIC_RMW
Arnd Bergmann91701002013-02-21 11:42:57 +010010 select ARCH_WANT_OPTIONAL_GPIOLIB
Will Deacon6212a512012-11-07 14:16:28 +000011 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
Catalin Marinasb6f35982013-01-29 18:25:41 +000012 select ARCH_WANT_FRAME_POINTERS
Catalin Marinas25c92a32012-12-18 15:26:13 +000013 select ARM_AMBA
Mark Rutland1aee5d72012-11-20 10:06:00 +000014 select ARM_ARCH_TIMER
Catalin Marinasc4188ed2013-01-14 12:39:31 +000015 select ARM_GIC
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010016 select AUDIT_ARCH_COMPAT_GENERIC
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000017 select ARM_GIC_V2M if PCI_MSI
Marc Zyngier021f6532014-06-30 16:01:31 +010018 select ARM_GIC_V3
Marc Zyngier19812722014-11-24 14:35:19 +000019 select ARM_GIC_V3_ITS if PCI_MSI
Will Deaconadace892013-05-08 17:29:24 +010020 select BUILDTIME_EXTABLE_SORT
Catalin Marinasdb2789b2012-12-18 15:27:25 +000021 select CLONE_BACKWARDS
Deepak Saxena7ca2ef32012-09-22 10:33:36 -070022 select COMMON_CLK
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +000023 select CPU_PM if (SUSPEND || CPU_IDLE)
Will Deacon7bc13fd2013-11-06 19:32:13 +000024 select DCACHE_WORD_ACCESS
Laura Abbottd4932f92014-10-09 15:26:44 -070025 select GENERIC_ALLOCATOR
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010026 select GENERIC_CLOCKEVENTS
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +010027 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
Ard Biesheuvel3be1a5c2014-03-04 01:10:04 +000028 select GENERIC_CPU_AUTOPROBE
Mark Salterbf4b5582014-04-07 15:39:52 -070029 select GENERIC_EARLY_IOREMAP
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010030 select GENERIC_IRQ_PROBE
31 select GENERIC_IRQ_SHOW
Arnd Bergmanncb61f672014-11-19 14:09:07 +010032 select GENERIC_PCI_IOMAP
Stephen Boyd65cd4f62013-07-18 16:21:18 -070033 select GENERIC_SCHED_CLOCK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010034 select GENERIC_SMP_IDLE_THREAD
Will Deacon12a0ef72013-11-06 17:20:22 +000035 select GENERIC_STRNCPY_FROM_USER
36 select GENERIC_STRNLEN_USER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010037 select GENERIC_TIME_VSYSCALL
Marc Zyngiera1ddc742014-08-26 11:03:17 +010038 select HANDLE_DOMAIN_IRQ
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010039 select HARDIRQS_SW_RESEND
Steve Capper5284e1b2014-10-24 13:22:20 +010040 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010041 select HAVE_ARCH_AUDITSYSCALL
Jiang Liu9732caf2014-01-07 22:17:13 +080042 select HAVE_ARCH_JUMP_LABEL
Vijaya Kumar K95292472014-01-28 11:20:22 +000043 select HAVE_ARCH_KGDB
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +000044 select HAVE_ARCH_SECCOMP_FILTER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010045 select HAVE_ARCH_TRACEHOOK
Zi Shen Lime54bcde2014-08-26 21:15:30 -070046 select HAVE_BPF_JIT
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010047 select HAVE_C_RECORDMCOUNT
Laura Abbottc0c264a2014-06-25 23:55:03 +010048 select HAVE_CC_STACKPROTECTOR
Steve Capper5284e1b2014-10-24 13:22:20 +010049 select HAVE_CMPXCHG_DOUBLE
Catalin Marinas9b2a60c2012-10-08 16:28:13 -070050 select HAVE_DEBUG_BUGVERBOSE
Catalin Marinasb69ec422012-10-08 16:28:11 -070051 select HAVE_DEBUG_KMEMLEAK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010052 select HAVE_DMA_API_DEBUG
53 select HAVE_DMA_ATTRS
Laura Abbott6ac21042013-12-12 19:28:33 +000054 select HAVE_DMA_CONTIGUOUS
AKASHI Takahirobd7d38d2014-04-30 10:54:34 +010055 select HAVE_DYNAMIC_FTRACE
Will Deacon50afc332013-12-16 17:50:08 +000056 select HAVE_EFFICIENT_UNALIGNED_ACCESS
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010057 select HAVE_FTRACE_MCOUNT_RECORD
AKASHI Takahiro819e50e2014-04-30 18:54:33 +090058 select HAVE_FUNCTION_TRACER
59 select HAVE_FUNCTION_GRAPH_TRACER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010060 select HAVE_GENERIC_DMA_COHERENT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010061 select HAVE_HW_BREAKPOINT if PERF_EVENTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010062 select HAVE_MEMBLOCK
Mark Rutland55834a72014-02-07 17:12:45 +000063 select HAVE_PATA_PLATFORM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010064 select HAVE_PERF_EVENTS
Jean Pihet2ee0d7f2014-02-03 19:18:27 +010065 select HAVE_PERF_REGS
66 select HAVE_PERF_USER_STACK_DUMP
Steve Capper5e5f6dc2014-10-09 15:29:23 -070067 select HAVE_RCU_TABLE_FREE
AKASHI Takahiro055b1212014-04-30 10:54:36 +010068 select HAVE_SYSCALL_TRACEPOINTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010069 select IRQ_DOMAIN
Catalin Marinasfea2aca2012-10-16 11:26:57 +010070 select MODULES_USE_ELF_RELA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010071 select NO_BOOTMEM
72 select OF
73 select OF_EARLY_FLATTREE
Marek Szyprowski9bf14b72014-02-28 14:42:55 +010074 select OF_RESERVED_MEM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010075 select PERF_USE_VMALLOC
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +000076 select POWER_RESET
77 select POWER_SUPPLY
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010078 select RTC_LIB
79 select SPARSE_IRQ
Catalin Marinas7ac57a82012-10-08 16:28:16 -070080 select SYSCTL_EXCEPTION_TRACE
Larry Bassel6c81fe72014-05-30 12:34:15 -070081 select HAVE_CONTEXT_TRACKING
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010082 help
83 ARM 64-bit (AArch64) Linux support.
84
85config 64BIT
86 def_bool y
87
88config ARCH_PHYS_ADDR_T_64BIT
89 def_bool y
90
91config MMU
92 def_bool y
93
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -070094config NO_IOPORT_MAP
Liviu Dudaud1e6dc92014-09-29 15:29:31 +010095 def_bool y if !PCI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010096
97config STACKTRACE_SUPPORT
98 def_bool y
99
100config LOCKDEP_SUPPORT
101 def_bool y
102
103config TRACE_IRQFLAGS_SUPPORT
104 def_bool y
105
Will Deaconc209f792014-03-14 17:47:05 +0000106config RWSEM_XCHGADD_ALGORITHM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100107 def_bool y
108
109config GENERIC_HWEIGHT
110 def_bool y
111
112config GENERIC_CSUM
113 def_bool y
114
115config GENERIC_CALIBRATE_DELAY
116 def_bool y
117
Catalin Marinas19e76402014-02-27 12:09:22 +0000118config ZONE_DMA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100119 def_bool y
120
Steve Capper29e56942014-10-09 15:29:25 -0700121config HAVE_GENERIC_RCU_GUP
122 def_bool y
123
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100124config ARCH_DMA_ADDR_T_64BIT
125 def_bool y
126
127config NEED_DMA_MAP_STATE
128 def_bool y
129
130config NEED_SG_DMA_LENGTH
131 def_bool y
132
133config SWIOTLB
134 def_bool y
135
136config IOMMU_HELPER
137 def_bool SWIOTLB
138
Ard Biesheuvel4cfb3612013-07-09 14:18:12 +0100139config KERNEL_MODE_NEON
140 def_bool y
141
Rob Herring92cc15f2014-04-18 17:19:59 -0500142config FIX_EARLYCON_MEM
143 def_bool y
144
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100145source "init/Kconfig"
146
147source "kernel/Kconfig.freezer"
148
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100149menu "Platform selection"
150
Suravee Suthikulpanit41904362014-11-26 11:51:09 +0700151config ARCH_SEATTLE
152 bool "AMD Seattle SoC Family"
153 help
154 This enables support for AMD Seattle SOC Family
155
Paul Walmsleyd035fdf2015-01-07 01:17:33 -0700156config ARCH_TEGRA
157 bool "NVIDIA Tegra SoC Family"
158 select ARCH_HAS_RESET_CONTROLLER
159 select ARCH_REQUIRE_GPIOLIB
160 select CLKDEV_LOOKUP
161 select CLKSRC_MMIO
162 select CLKSRC_OF
163 select GENERIC_CLOCKEVENTS
164 select HAVE_CLK
165 select HAVE_SMP
166 select PINCTRL
167 select RESET_CONTROLLER
168 help
169 This enables support for the NVIDIA Tegra SoC family.
170
171config ARCH_TEGRA_132_SOC
172 bool "NVIDIA Tegra132 SoC"
173 depends on ARCH_TEGRA
174 select PINCTRL_TEGRA124
175 select USB_ARCH_HAS_EHCI if USB_SUPPORT
176 select USB_ULPI if USB_PHY
177 select USB_ULPI_VIEWPORT if USB_PHY
178 help
179 Enable support for NVIDIA Tegra132 SoC, based on the Denver
180 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
181 but contains an NVIDIA Denver CPU complex in place of
182 Tegra124's "4+1" Cortex-A15 CPU complex.
183
Radha Mohan Chintakuntla28f74202014-04-08 18:47:51 +0530184config ARCH_THUNDER
185 bool "Cavium Inc. Thunder SoC Family"
186 help
187 This enables support for Cavium's Thunder Family of SoCs.
188
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100189config ARCH_VEXPRESS
190 bool "ARMv8 software model (Versatile Express)"
191 select ARCH_REQUIRE_GPIOLIB
192 select COMMON_CLK_VERSATILE
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +0000193 select POWER_RESET_VEXPRESS
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100194 select VEXPRESS_CONFIG
195 help
196 This enables support for the ARMv8 software model (Versatile
197 Express).
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100198
Vinayak Kale15942852013-04-24 10:06:57 +0100199config ARCH_XGENE
200 bool "AppliedMicro X-Gene SOC Family"
201 help
202 This enables support for AppliedMicro X-Gene SOC Family
203
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100204endmenu
205
206menu "Bus support"
207
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100208config PCI
209 bool "PCI support"
210 help
211 This feature enables support for PCI bus system. If you say Y
212 here, the kernel will include drivers and infrastructure code
213 to support PCI bus devices.
214
215config PCI_DOMAINS
216 def_bool PCI
217
218config PCI_DOMAINS_GENERIC
219 def_bool PCI
220
221config PCI_SYSCALL
222 def_bool PCI
223
224source "drivers/pci/Kconfig"
225source "drivers/pci/pcie/Kconfig"
226source "drivers/pci/hotplug/Kconfig"
227
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100228endmenu
229
230menu "Kernel Features"
231
Andre Przywarac0a01b82014-11-14 15:54:12 +0000232menu "ARM errata workarounds via the alternatives framework"
233
234config ARM64_ERRATUM_826319
235 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
236 default y
237 help
238 This option adds an alternative code sequence to work around ARM
239 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
240 AXI master interface and an L2 cache.
241
242 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
243 and is unable to accept a certain write via this interface, it will
244 not progress on read data presented on the read data channel and the
245 system can deadlock.
246
247 The workaround promotes data cache clean instructions to
248 data cache clean-and-invalidate.
249 Please note that this does not necessarily enable the workaround,
250 as it depends on the alternative framework, which will only patch
251 the kernel if an affected CPU is detected.
252
253 If unsure, say Y.
254
255config ARM64_ERRATUM_827319
256 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
257 default y
258 help
259 This option adds an alternative code sequence to work around ARM
260 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
261 master interface and an L2 cache.
262
263 Under certain conditions this erratum can cause a clean line eviction
264 to occur at the same time as another transaction to the same address
265 on the AMBA 5 CHI interface, which can cause data corruption if the
266 interconnect reorders the two transactions.
267
268 The workaround promotes data cache clean instructions to
269 data cache clean-and-invalidate.
270 Please note that this does not necessarily enable the workaround,
271 as it depends on the alternative framework, which will only patch
272 the kernel if an affected CPU is detected.
273
274 If unsure, say Y.
275
276config ARM64_ERRATUM_824069
277 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
278 default y
279 help
280 This option adds an alternative code sequence to work around ARM
281 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
282 to a coherent interconnect.
283
284 If a Cortex-A53 processor is executing a store or prefetch for
285 write instruction at the same time as a processor in another
286 cluster is executing a cache maintenance operation to the same
287 address, then this erratum might cause a clean cache line to be
288 incorrectly marked as dirty.
289
290 The workaround promotes data cache clean instructions to
291 data cache clean-and-invalidate.
292 Please note that this option does not necessarily enable the
293 workaround, as it depends on the alternative framework, which will
294 only patch the kernel if an affected CPU is detected.
295
296 If unsure, say Y.
297
298config ARM64_ERRATUM_819472
299 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
300 default y
301 help
302 This option adds an alternative code sequence to work around ARM
303 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
304 present when it is connected to a coherent interconnect.
305
306 If the processor is executing a load and store exclusive sequence at
307 the same time as a processor in another cluster is executing a cache
308 maintenance operation to the same address, then this erratum might
309 cause data corruption.
310
311 The workaround promotes data cache clean instructions to
312 data cache clean-and-invalidate.
313 Please note that this does not necessarily enable the workaround,
314 as it depends on the alternative framework, which will only patch
315 the kernel if an affected CPU is detected.
316
317 If unsure, say Y.
318
319config ARM64_ERRATUM_832075
320 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
321 default y
322 help
323 This option adds an alternative code sequence to work around ARM
324 erratum 832075 on Cortex-A57 parts up to r1p2.
325
326 Affected Cortex-A57 parts might deadlock when exclusive load/store
327 instructions to Write-Back memory are mixed with Device loads.
328
329 The workaround is to promote device loads to use Load-Acquire
330 semantics.
331 Please note that this does not necessarily enable the workaround,
332 as it depends on the alternative framework, which will only patch
333 the kernel if an affected CPU is detected.
334
335 If unsure, say Y.
336
337endmenu
338
339
Jungseok Leee41ceed2014-05-12 10:40:38 +0100340choice
341 prompt "Page size"
342 default ARM64_4K_PAGES
343 help
344 Page size (translation granule) configuration.
345
346config ARM64_4K_PAGES
347 bool "4KB"
348 help
349 This feature enables 4KB pages support.
350
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100351config ARM64_64K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100352 bool "64KB"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100353 help
354 This feature enables 64KB pages support (4KB by default)
355 allowing only two levels of page tables and faster TLB
356 look-up. AArch32 emulation is not available when this feature
357 is enabled.
358
Jungseok Leee41ceed2014-05-12 10:40:38 +0100359endchoice
360
361choice
362 prompt "Virtual address space size"
363 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
364 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
365 help
366 Allows choosing one of multiple possible virtual address
367 space sizes. The level of translation table is determined by
368 a combination of page size and virtual address space size.
369
370config ARM64_VA_BITS_39
371 bool "39-bit"
372 depends on ARM64_4K_PAGES
373
374config ARM64_VA_BITS_42
375 bool "42-bit"
376 depends on ARM64_64K_PAGES
377
Jungseok Leec79b9542014-05-12 18:40:51 +0900378config ARM64_VA_BITS_48
379 bool "48-bit"
Christoffer Dall04f905a2014-10-10 11:14:30 +0100380 depends on !ARM_SMMU
Jungseok Leec79b9542014-05-12 18:40:51 +0900381
Jungseok Leee41ceed2014-05-12 10:40:38 +0100382endchoice
383
384config ARM64_VA_BITS
385 int
386 default 39 if ARM64_VA_BITS_39
387 default 42 if ARM64_VA_BITS_42
Jungseok Leec79b9542014-05-12 18:40:51 +0900388 default 48 if ARM64_VA_BITS_48
Jungseok Leee41ceed2014-05-12 10:40:38 +0100389
Catalin Marinasabe669d2014-07-15 15:37:21 +0100390config ARM64_PGTABLE_LEVELS
391 int
392 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
Catalin Marinas383c2792014-07-21 15:54:50 +0100393 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
Catalin Marinasabe669d2014-07-15 15:37:21 +0100394 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
395 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
Jungseok Leec79b9542014-05-12 18:40:51 +0900396
Will Deacona8720132013-10-11 14:52:19 +0100397config CPU_BIG_ENDIAN
398 bool "Build big-endian kernel"
399 help
400 Say Y if you plan on running a kernel in big-endian mode.
401
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100402config SMP
403 bool "Symmetric Multi-Processing"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100404 help
405 This enables support for systems with more than one CPU. If
406 you say N here, the kernel will run on single and
407 multiprocessor machines, but will use only one CPU of a
408 multiprocessor machine. If you say Y here, the kernel will run
409 on many, but not all, single processor machines. On a single
410 processor machine, the kernel will run faster if you say N
411 here.
412
413 If you don't know what to do here, say N.
414
Mark Brownf6e763b2014-03-04 07:51:17 +0000415config SCHED_MC
416 bool "Multi-core scheduler support"
417 depends on SMP
418 help
419 Multi-core scheduler support improves the CPU scheduler's decision
420 making when dealing with multi-core CPU chips at a cost of slightly
421 increased overhead in some places. If unsure say N here.
422
423config SCHED_SMT
424 bool "SMT scheduler support"
425 depends on SMP
426 help
427 Improves the CPU scheduler's decision making when dealing with
428 MultiThreading at a cost of slightly increased overhead in some
429 places. If unsure say N here.
430
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100431config NR_CPUS
Robert Richtere3672642014-09-08 12:44:48 +0100432 int "Maximum number of CPUs (2-64)"
433 range 2 64
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100434 depends on SMP
Vinayak Kale15942852013-04-24 10:06:57 +0100435 # These have to remain sorted largest to smallest
Robert Richtere3672642014-09-08 12:44:48 +0100436 default "64"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100437
Mark Rutland9327e2c2013-10-24 20:30:18 +0100438config HOTPLUG_CPU
439 bool "Support for hot-pluggable CPUs"
440 depends on SMP
441 help
442 Say Y here to experiment with turning CPUs off and on. CPUs
443 can be controlled through /sys/devices/system/cpu.
444
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100445source kernel/Kconfig.preempt
446
447config HZ
448 int
449 default 100
450
451config ARCH_HAS_HOLES_MEMORYMODEL
452 def_bool y if SPARSEMEM
453
454config ARCH_SPARSEMEM_ENABLE
455 def_bool y
456 select SPARSEMEM_VMEMMAP_ENABLE
457
458config ARCH_SPARSEMEM_DEFAULT
459 def_bool ARCH_SPARSEMEM_ENABLE
460
461config ARCH_SELECT_MEMORY_MODEL
462 def_bool ARCH_SPARSEMEM_ENABLE
463
464config HAVE_ARCH_PFN_VALID
465 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
466
467config HW_PERF_EVENTS
468 bool "Enable hardware performance counter support for perf events"
469 depends on PERF_EVENTS
470 default y
471 help
472 Enable hardware performance counter support for perf events. If
473 disabled, perf events will use software events only.
474
Steve Capper084bd292013-04-10 13:48:00 +0100475config SYS_SUPPORTS_HUGETLBFS
476 def_bool y
477
478config ARCH_WANT_GENERAL_HUGETLB
479 def_bool y
480
481config ARCH_WANT_HUGE_PMD_SHARE
482 def_bool y if !ARM64_64K_PAGES
483
Steve Capperaf074842013-04-19 16:23:57 +0100484config HAVE_ARCH_TRANSPARENT_HUGEPAGE
485 def_bool y
486
Catalin Marinasa41dc0e2014-04-03 17:48:54 +0100487config ARCH_HAS_CACHE_LINE_SIZE
488 def_bool y
489
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100490source "mm/Kconfig"
491
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +0000492config SECCOMP
493 bool "Enable seccomp to safely compute untrusted bytecode"
494 ---help---
495 This kernel feature is useful for number crunching applications
496 that may need to compute untrusted bytecode during their
497 execution. By using pipes or other transports made available to
498 the process as file descriptors supporting the read/write
499 syscalls, it's possible to isolate those applications in
500 their own address space using seccomp. Once seccomp is
501 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
502 and the task is only allowed to execute a few safe syscalls
503 defined by each seccomp mode.
504
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000505config XEN_DOM0
506 def_bool y
507 depends on XEN
508
509config XEN
Julien Grallc2ba1f72014-09-17 14:07:06 -0700510 bool "Xen guest support on ARM64"
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000511 depends on ARM64 && OF
Stefano Stabellini83862cc2013-10-10 13:40:44 +0000512 select SWIOTLB_XEN
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000513 help
514 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
515
Steve Capperd03bb142013-04-25 15:19:21 +0100516config FORCE_MAX_ZONEORDER
517 int
518 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
519 default "11"
520
Will Deacon1b907f42014-11-20 16:51:10 +0000521menuconfig ARMV8_DEPRECATED
522 bool "Emulate deprecated/obsolete ARMv8 instructions"
523 depends on COMPAT
524 help
525 Legacy software support may require certain instructions
526 that have been deprecated or obsoleted in the architecture.
527
528 Enable this config to enable selective emulation of these
529 features.
530
531 If unsure, say Y
532
533if ARMV8_DEPRECATED
534
535config SWP_EMULATION
536 bool "Emulate SWP/SWPB instructions"
537 help
538 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
539 they are always undefined. Say Y here to enable software
540 emulation of these instructions for userspace using LDXR/STXR.
541
542 In some older versions of glibc [<=2.8] SWP is used during futex
543 trylock() operations with the assumption that the code will not
544 be preempted. This invalid assumption may be more likely to fail
545 with SWP emulation enabled, leading to deadlock of the user
546 application.
547
548 NOTE: when accessing uncached shared regions, LDXR/STXR rely
549 on an external transaction monitoring block called a global
550 monitor to maintain update atomicity. If your system does not
551 implement a global monitor, this option can cause programs that
552 perform SWP operations to uncached memory to deadlock.
553
554 If unsure, say Y
555
556config CP15_BARRIER_EMULATION
557 bool "Emulate CP15 Barrier instructions"
558 help
559 The CP15 barrier instructions - CP15ISB, CP15DSB, and
560 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
561 strongly recommended to use the ISB, DSB, and DMB
562 instructions instead.
563
564 Say Y here to enable software emulation of these
565 instructions for AArch32 userspace code. When this option is
566 enabled, CP15 barrier usage is traced which can help
567 identify software that needs updating.
568
569 If unsure, say Y
570
571endif
572
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100573endmenu
574
575menu "Boot options"
576
577config CMDLINE
578 string "Default kernel command string"
579 default ""
580 help
581 Provide a set of default command-line options at build time by
582 entering them here. As a minimum, you should specify the the
583 root device (e.g. root=/dev/nfs).
584
585config CMDLINE_FORCE
586 bool "Always use the default kernel command string"
587 help
588 Always use the default kernel command string, even if the boot
589 loader passes other arguments to the kernel.
590 This is useful if you cannot or don't want to change the
591 command-line options your boot loader passes to the kernel.
592
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200593config EFI_STUB
594 bool
595
Mark Salterf84d0272014-04-15 21:59:30 -0400596config EFI
597 bool "UEFI runtime support"
598 depends on OF && !CPU_BIG_ENDIAN
599 select LIBFDT
600 select UCS2_STRING
601 select EFI_PARAMS_FROM_FDT
Ard Biesheuvele15dd492014-07-04 19:41:53 +0200602 select EFI_RUNTIME_WRAPPERS
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200603 select EFI_STUB
604 select EFI_ARMSTUB
Mark Salterf84d0272014-04-15 21:59:30 -0400605 default y
606 help
607 This option provides support for runtime services provided
608 by UEFI firmware (such as non-volatile variables, realtime
Mark Salter3c7f2552014-04-15 22:47:52 -0400609 clock, and platform reset). A UEFI stub is also provided to
610 allow the kernel to be booted as an EFI application. This
611 is only useful on systems that have UEFI firmware.
Mark Salterf84d0272014-04-15 21:59:30 -0400612
Yi Lid1ae8c02014-10-04 23:46:43 +0800613config DMI
614 bool "Enable support for SMBIOS (DMI) tables"
615 depends on EFI
616 default y
617 help
618 This enables SMBIOS/DMI feature for systems.
619
620 This option is only useful on systems that have UEFI firmware.
621 However, even with this option, the resultant kernel should
622 continue to boot on existing non-UEFI platforms.
623
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100624endmenu
625
626menu "Userspace binary formats"
627
628source "fs/Kconfig.binfmt"
629
630config COMPAT
631 bool "Kernel support for 32-bit EL0"
632 depends on !ARM64_64K_PAGES
633 select COMPAT_BINFMT_ELF
Catalin Marinasaf1839e2012-10-08 16:28:08 -0700634 select HAVE_UID16
Al Viro84b9e9b2012-12-25 16:29:11 -0500635 select OLD_SIGSUSPEND3
Al Viro51682032012-12-25 19:31:29 -0500636 select COMPAT_OLD_SIGACTION
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100637 help
638 This option enables support for a 32-bit EL0 running under a 64-bit
639 kernel at EL1. AArch32-specific components such as system calls,
640 the user helper functions, VFP support and the ptrace interface are
641 handled appropriately by the kernel.
642
643 If you want to execute 32-bit userspace applications, say Y.
644
645config SYSVIPC_COMPAT
646 def_bool y
647 depends on COMPAT && SYSVIPC
648
649endmenu
650
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000651menu "Power management options"
652
653source "kernel/power/Kconfig"
654
655config ARCH_SUSPEND_POSSIBLE
656 def_bool y
657
658config ARM64_CPU_SUSPEND
659 def_bool PM_SLEEP
660
661endmenu
662
Lorenzo Pieralisi13072202013-07-17 14:54:21 +0100663menu "CPU Power Management"
664
665source "drivers/cpuidle/Kconfig"
666
Rob Herring52e7e812014-02-24 11:27:57 +0900667source "drivers/cpufreq/Kconfig"
668
669endmenu
670
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100671source "net/Kconfig"
672
673source "drivers/Kconfig"
674
Mark Salterf84d0272014-04-15 21:59:30 -0400675source "drivers/firmware/Kconfig"
676
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100677source "fs/Kconfig"
678
Marc Zyngierc3eb5b12013-07-04 13:34:32 +0100679source "arch/arm64/kvm/Kconfig"
680
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100681source "arch/arm64/Kconfig.debug"
682
683source "security/Kconfig"
684
685source "crypto/Kconfig"
Ard Biesheuvel2c988332014-03-06 16:23:33 +0800686if CRYPTO
687source "arch/arm64/crypto/Kconfig"
688endif
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100689
690source "lib/Kconfig"