Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 1 | /* |
| 2 | * drivers/net/ethernet/mellanox/mlxsw/spectrum.h |
| 3 | * Copyright (c) 2015 Mellanox Technologies. All rights reserved. |
| 4 | * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com> |
| 5 | * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com> |
| 6 | * Copyright (c) 2015 Elad Raz <eladr@mellanox.com> |
| 7 | * |
| 8 | * Redistribution and use in source and binary forms, with or without |
| 9 | * modification, are permitted provided that the following conditions are met: |
| 10 | * |
| 11 | * 1. Redistributions of source code must retain the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer. |
| 13 | * 2. Redistributions in binary form must reproduce the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer in the |
| 15 | * documentation and/or other materials provided with the distribution. |
| 16 | * 3. Neither the names of the copyright holders nor the names of its |
| 17 | * contributors may be used to endorse or promote products derived from |
| 18 | * this software without specific prior written permission. |
| 19 | * |
| 20 | * Alternatively, this software may be distributed under the terms of the |
| 21 | * GNU General Public License ("GPL") version 2 as published by the Free |
| 22 | * Software Foundation. |
| 23 | * |
| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 27 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| 28 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 29 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 30 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 31 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 32 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 33 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 34 | * POSSIBILITY OF SUCH DAMAGE. |
| 35 | */ |
| 36 | |
| 37 | #ifndef _MLXSW_SPECTRUM_H |
| 38 | #define _MLXSW_SPECTRUM_H |
| 39 | |
| 40 | #include <linux/types.h> |
| 41 | #include <linux/netdevice.h> |
| 42 | #include <linux/bitops.h> |
| 43 | #include <linux/if_vlan.h> |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 44 | #include <linux/list.h> |
Ido Schimmel | 8e8dfe9 | 2016-04-06 17:10:10 +0200 | [diff] [blame] | 45 | #include <linux/dcbnl.h> |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 46 | #include <net/switchdev.h> |
| 47 | |
Elad Raz | 3a49b4f | 2016-01-10 21:06:28 +0100 | [diff] [blame] | 48 | #include "port.h" |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 49 | #include "core.h" |
| 50 | |
| 51 | #define MLXSW_SP_VFID_BASE VLAN_N_VID |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 52 | #define MLXSW_SP_VFID_PORT_MAX 512 /* Non-bridged VLAN interfaces */ |
Ido Schimmel | b555cf4 | 2016-04-05 10:20:02 +0200 | [diff] [blame] | 53 | #define MLXSW_SP_VFID_BR_MAX 6144 /* Bridged VLAN interfaces */ |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 54 | #define MLXSW_SP_VFID_MAX (MLXSW_SP_VFID_PORT_MAX + MLXSW_SP_VFID_BR_MAX) |
| 55 | |
Jiri Pirko | 0d65fc1 | 2015-12-03 12:12:28 +0100 | [diff] [blame] | 56 | #define MLXSW_SP_LAG_MAX 64 |
| 57 | #define MLXSW_SP_PORT_PER_LAG_MAX 16 |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 58 | |
Elad Raz | 53ae628 | 2016-01-10 21:06:26 +0100 | [diff] [blame] | 59 | #define MLXSW_SP_MID_MAX 7000 |
| 60 | |
Ido Schimmel | 18f1e70 | 2016-02-26 17:32:31 +0100 | [diff] [blame] | 61 | #define MLXSW_SP_PORTS_PER_CLUSTER_MAX 4 |
| 62 | |
| 63 | #define MLXSW_SP_PORT_BASE_SPEED 25000 /* Mb/s */ |
| 64 | |
Ido Schimmel | 1a19844 | 2016-04-06 17:10:02 +0200 | [diff] [blame] | 65 | #define MLXSW_SP_BYTES_PER_CELL 96 |
| 66 | |
| 67 | #define MLXSW_SP_BYTES_TO_CELLS(b) DIV_ROUND_UP(b, MLXSW_SP_BYTES_PER_CELL) |
Jiri Pirko | 0f433fa | 2016-04-14 18:19:24 +0200 | [diff] [blame] | 68 | #define MLXSW_SP_CELLS_TO_BYTES(c) (c * MLXSW_SP_BYTES_PER_CELL) |
Ido Schimmel | 1a19844 | 2016-04-06 17:10:02 +0200 | [diff] [blame] | 69 | |
Ido Schimmel | 9f7ec05 | 2016-04-06 17:10:14 +0200 | [diff] [blame] | 70 | /* Maximum delay buffer needed in case of PAUSE frames, in cells. |
| 71 | * Assumes 100m cable and maximum MTU. |
| 72 | */ |
| 73 | #define MLXSW_SP_PAUSE_DELAY 612 |
| 74 | |
Ido Schimmel | d81a6bd | 2016-04-06 17:10:16 +0200 | [diff] [blame] | 75 | #define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */ |
| 76 | |
| 77 | static inline u16 mlxsw_sp_pfc_delay_get(int mtu, u16 delay) |
| 78 | { |
| 79 | delay = MLXSW_SP_BYTES_TO_CELLS(DIV_ROUND_UP(delay, BITS_PER_BYTE)); |
| 80 | return MLXSW_SP_CELL_FACTOR * delay + MLXSW_SP_BYTES_TO_CELLS(mtu); |
| 81 | } |
| 82 | |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 83 | struct mlxsw_sp_port; |
| 84 | |
Jiri Pirko | 0d65fc1 | 2015-12-03 12:12:28 +0100 | [diff] [blame] | 85 | struct mlxsw_sp_upper { |
| 86 | struct net_device *dev; |
| 87 | unsigned int ref_count; |
| 88 | }; |
| 89 | |
Ido Schimmel | d0ec875 | 2016-06-20 23:04:12 +0200 | [diff] [blame^] | 90 | struct mlxsw_sp_fid { |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 91 | struct list_head list; |
Ido Schimmel | d0ec875 | 2016-06-20 23:04:12 +0200 | [diff] [blame^] | 92 | unsigned int ref_count; |
| 93 | struct net_device *dev; |
| 94 | u16 fid; |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 95 | u16 vid; |
| 96 | }; |
| 97 | |
Elad Raz | 3a49b4f | 2016-01-10 21:06:28 +0100 | [diff] [blame] | 98 | struct mlxsw_sp_mid { |
| 99 | struct list_head list; |
| 100 | unsigned char addr[ETH_ALEN]; |
| 101 | u16 vid; |
| 102 | u16 mid; |
| 103 | unsigned int ref_count; |
| 104 | }; |
| 105 | |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 106 | static inline u16 mlxsw_sp_vfid_to_fid(u16 vfid) |
| 107 | { |
| 108 | return MLXSW_SP_VFID_BASE + vfid; |
| 109 | } |
| 110 | |
Ido Schimmel | aac78a4 | 2015-12-15 16:03:42 +0100 | [diff] [blame] | 111 | static inline u16 mlxsw_sp_fid_to_vfid(u16 fid) |
| 112 | { |
| 113 | return fid - MLXSW_SP_VFID_BASE; |
| 114 | } |
| 115 | |
| 116 | static inline bool mlxsw_sp_fid_is_vfid(u16 fid) |
| 117 | { |
| 118 | return fid >= MLXSW_SP_VFID_BASE; |
| 119 | } |
| 120 | |
Jiri Pirko | 078f9c7 | 2016-04-14 18:19:19 +0200 | [diff] [blame] | 121 | struct mlxsw_sp_sb_pr { |
| 122 | enum mlxsw_reg_sbpr_mode mode; |
| 123 | u32 size; |
| 124 | }; |
| 125 | |
Jiri Pirko | 2d0ed39 | 2016-04-14 18:19:30 +0200 | [diff] [blame] | 126 | struct mlxsw_cp_sb_occ { |
| 127 | u32 cur; |
| 128 | u32 max; |
| 129 | }; |
| 130 | |
Jiri Pirko | 078f9c7 | 2016-04-14 18:19:19 +0200 | [diff] [blame] | 131 | struct mlxsw_sp_sb_cm { |
| 132 | u32 min_buff; |
| 133 | u32 max_buff; |
| 134 | u8 pool; |
Jiri Pirko | 2d0ed39 | 2016-04-14 18:19:30 +0200 | [diff] [blame] | 135 | struct mlxsw_cp_sb_occ occ; |
Jiri Pirko | 078f9c7 | 2016-04-14 18:19:19 +0200 | [diff] [blame] | 136 | }; |
| 137 | |
| 138 | struct mlxsw_sp_sb_pm { |
| 139 | u32 min_buff; |
| 140 | u32 max_buff; |
Jiri Pirko | 2d0ed39 | 2016-04-14 18:19:30 +0200 | [diff] [blame] | 141 | struct mlxsw_cp_sb_occ occ; |
Jiri Pirko | 078f9c7 | 2016-04-14 18:19:19 +0200 | [diff] [blame] | 142 | }; |
| 143 | |
| 144 | #define MLXSW_SP_SB_POOL_COUNT 4 |
| 145 | #define MLXSW_SP_SB_TC_COUNT 8 |
| 146 | |
| 147 | struct mlxsw_sp_sb { |
| 148 | struct mlxsw_sp_sb_pr prs[2][MLXSW_SP_SB_POOL_COUNT]; |
| 149 | struct { |
| 150 | struct mlxsw_sp_sb_cm cms[2][MLXSW_SP_SB_TC_COUNT]; |
| 151 | struct mlxsw_sp_sb_pm pms[2][MLXSW_SP_SB_POOL_COUNT]; |
| 152 | } ports[MLXSW_PORT_MAX_PORTS]; |
| 153 | }; |
| 154 | |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 155 | struct mlxsw_sp { |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 156 | struct { |
| 157 | struct list_head list; |
Ido Schimmel | d8651fd | 2016-06-20 23:04:07 +0200 | [diff] [blame] | 158 | DECLARE_BITMAP(mapped, MLXSW_SP_VFID_PORT_MAX); |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 159 | } port_vfids; |
Ido Schimmel | 26f0e7f | 2015-12-15 16:03:44 +0100 | [diff] [blame] | 160 | struct { |
| 161 | struct list_head list; |
Ido Schimmel | d8651fd | 2016-06-20 23:04:07 +0200 | [diff] [blame] | 162 | DECLARE_BITMAP(mapped, MLXSW_SP_VFID_BR_MAX); |
Ido Schimmel | 26f0e7f | 2015-12-15 16:03:44 +0100 | [diff] [blame] | 163 | } br_vfids; |
Elad Raz | 3a49b4f | 2016-01-10 21:06:28 +0100 | [diff] [blame] | 164 | struct { |
| 165 | struct list_head list; |
Ido Schimmel | d8651fd | 2016-06-20 23:04:07 +0200 | [diff] [blame] | 166 | DECLARE_BITMAP(mapped, MLXSW_SP_MID_MAX); |
Elad Raz | 3a49b4f | 2016-01-10 21:06:28 +0100 | [diff] [blame] | 167 | } br_mids; |
Ido Schimmel | d8651fd | 2016-06-20 23:04:07 +0200 | [diff] [blame] | 168 | DECLARE_BITMAP(active_fids, VLAN_N_VID); |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 169 | struct mlxsw_sp_port **ports; |
| 170 | struct mlxsw_core *core; |
| 171 | const struct mlxsw_bus_info *bus_info; |
| 172 | unsigned char base_mac[ETH_ALEN]; |
| 173 | struct { |
| 174 | struct delayed_work dw; |
| 175 | #define MLXSW_SP_DEFAULT_LEARNING_INTERVAL 100 |
| 176 | unsigned int interval; /* ms */ |
| 177 | } fdb_notify; |
Ido Schimmel | 869f63a | 2016-03-08 12:59:33 -0800 | [diff] [blame] | 178 | #define MLXSW_SP_MIN_AGEING_TIME 10 |
| 179 | #define MLXSW_SP_MAX_AGEING_TIME 1000000 |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 180 | #define MLXSW_SP_DEFAULT_AGEING_TIME 300 |
| 181 | u32 ageing_time; |
Jiri Pirko | 0d65fc1 | 2015-12-03 12:12:28 +0100 | [diff] [blame] | 182 | struct mlxsw_sp_upper master_bridge; |
| 183 | struct mlxsw_sp_upper lags[MLXSW_SP_LAG_MAX]; |
Ido Schimmel | 558c2d5 | 2016-02-26 17:32:29 +0100 | [diff] [blame] | 184 | u8 port_to_module[MLXSW_PORT_MAX_PORTS]; |
Jiri Pirko | 078f9c7 | 2016-04-14 18:19:19 +0200 | [diff] [blame] | 185 | struct mlxsw_sp_sb sb; |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 186 | }; |
| 187 | |
Jiri Pirko | 0d65fc1 | 2015-12-03 12:12:28 +0100 | [diff] [blame] | 188 | static inline struct mlxsw_sp_upper * |
| 189 | mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id) |
| 190 | { |
| 191 | return &mlxsw_sp->lags[lag_id]; |
| 192 | } |
| 193 | |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 194 | struct mlxsw_sp_port_pcpu_stats { |
| 195 | u64 rx_packets; |
| 196 | u64 rx_bytes; |
| 197 | u64 tx_packets; |
| 198 | u64 tx_bytes; |
| 199 | struct u64_stats_sync syncp; |
| 200 | u32 tx_dropped; |
| 201 | }; |
| 202 | |
| 203 | struct mlxsw_sp_port { |
Jiri Pirko | 932762b | 2016-04-08 19:11:21 +0200 | [diff] [blame] | 204 | struct mlxsw_core_port core_port; /* must be first */ |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 205 | struct net_device *dev; |
| 206 | struct mlxsw_sp_port_pcpu_stats __percpu *pcpu_stats; |
| 207 | struct mlxsw_sp *mlxsw_sp; |
| 208 | u8 local_port; |
| 209 | u8 stp_state; |
Jiri Pirko | 0d9b970 | 2015-10-28 10:16:56 +0100 | [diff] [blame] | 210 | u8 learning:1, |
| 211 | learning_sync:1, |
Ido Schimmel | 0293038 | 2015-10-28 10:16:58 +0100 | [diff] [blame] | 212 | uc_flood:1, |
Jiri Pirko | 0d65fc1 | 2015-12-03 12:12:28 +0100 | [diff] [blame] | 213 | bridged:1, |
Ido Schimmel | 18f1e70 | 2016-02-26 17:32:31 +0100 | [diff] [blame] | 214 | lagged:1, |
| 215 | split:1; |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 216 | u16 pvid; |
Jiri Pirko | 0d65fc1 | 2015-12-03 12:12:28 +0100 | [diff] [blame] | 217 | u16 lag_id; |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 218 | struct { |
| 219 | struct list_head list; |
Ido Schimmel | d0ec875 | 2016-06-20 23:04:12 +0200 | [diff] [blame^] | 220 | struct mlxsw_sp_fid *f; |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 221 | u16 vid; |
| 222 | } vport; |
Ido Schimmel | 8e8dfe9 | 2016-04-06 17:10:10 +0200 | [diff] [blame] | 223 | struct { |
Ido Schimmel | 9f7ec05 | 2016-04-06 17:10:14 +0200 | [diff] [blame] | 224 | u8 tx_pause:1, |
| 225 | rx_pause:1; |
| 226 | } link; |
| 227 | struct { |
Ido Schimmel | 8e8dfe9 | 2016-04-06 17:10:10 +0200 | [diff] [blame] | 228 | struct ieee_ets *ets; |
Ido Schimmel | cc7cf51 | 2016-04-06 17:10:11 +0200 | [diff] [blame] | 229 | struct ieee_maxrate *maxrate; |
Ido Schimmel | d81a6bd | 2016-04-06 17:10:16 +0200 | [diff] [blame] | 230 | struct ieee_pfc *pfc; |
Ido Schimmel | 8e8dfe9 | 2016-04-06 17:10:10 +0200 | [diff] [blame] | 231 | } dcb; |
Ido Schimmel | d664b41 | 2016-06-09 09:51:40 +0200 | [diff] [blame] | 232 | struct { |
| 233 | u8 module; |
| 234 | u8 width; |
| 235 | u8 lane; |
| 236 | } mapping; |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 237 | /* 802.1Q bridge VLANs */ |
Ido Schimmel | bd40e9d | 2015-12-15 16:03:36 +0100 | [diff] [blame] | 238 | unsigned long *active_vlans; |
Elad Raz | fc1273a | 2016-01-06 13:01:11 +0100 | [diff] [blame] | 239 | unsigned long *untagged_vlans; |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 240 | /* VLAN interfaces */ |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 241 | struct list_head vports_list; |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 242 | }; |
| 243 | |
Ido Schimmel | 9f7ec05 | 2016-04-06 17:10:14 +0200 | [diff] [blame] | 244 | static inline bool |
| 245 | mlxsw_sp_port_is_pause_en(const struct mlxsw_sp_port *mlxsw_sp_port) |
| 246 | { |
| 247 | return mlxsw_sp_port->link.tx_pause || mlxsw_sp_port->link.rx_pause; |
| 248 | } |
| 249 | |
Jiri Pirko | 0d65fc1 | 2015-12-03 12:12:28 +0100 | [diff] [blame] | 250 | static inline struct mlxsw_sp_port * |
| 251 | mlxsw_sp_port_lagged_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id, u8 port_index) |
| 252 | { |
| 253 | struct mlxsw_sp_port *mlxsw_sp_port; |
| 254 | u8 local_port; |
| 255 | |
| 256 | local_port = mlxsw_core_lag_mapping_get(mlxsw_sp->core, |
| 257 | lag_id, port_index); |
| 258 | mlxsw_sp_port = mlxsw_sp->ports[local_port]; |
| 259 | return mlxsw_sp_port && mlxsw_sp_port->lagged ? mlxsw_sp_port : NULL; |
| 260 | } |
| 261 | |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 262 | static inline bool |
| 263 | mlxsw_sp_port_is_vport(const struct mlxsw_sp_port *mlxsw_sp_port) |
| 264 | { |
Ido Schimmel | d0ec875 | 2016-06-20 23:04:12 +0200 | [diff] [blame^] | 265 | return mlxsw_sp_port->vport.f; |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 266 | } |
| 267 | |
Ido Schimmel | 26f0e7f | 2015-12-15 16:03:44 +0100 | [diff] [blame] | 268 | static inline struct net_device * |
| 269 | mlxsw_sp_vport_br_get(const struct mlxsw_sp_port *mlxsw_sp_vport) |
| 270 | { |
Ido Schimmel | d0ec875 | 2016-06-20 23:04:12 +0200 | [diff] [blame^] | 271 | return mlxsw_sp_vport->vport.f->dev; |
Ido Schimmel | 26f0e7f | 2015-12-15 16:03:44 +0100 | [diff] [blame] | 272 | } |
| 273 | |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 274 | static inline u16 |
| 275 | mlxsw_sp_vport_vid_get(const struct mlxsw_sp_port *mlxsw_sp_vport) |
| 276 | { |
| 277 | return mlxsw_sp_vport->vport.vid; |
| 278 | } |
| 279 | |
| 280 | static inline u16 |
Ido Schimmel | d0ec875 | 2016-06-20 23:04:12 +0200 | [diff] [blame^] | 281 | mlxsw_sp_vport_fid_get(const struct mlxsw_sp_port *mlxsw_sp_vport) |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 282 | { |
Ido Schimmel | d0ec875 | 2016-06-20 23:04:12 +0200 | [diff] [blame^] | 283 | return mlxsw_sp_vport->vport.f->fid; |
Ido Schimmel | 7f71eb4 | 2015-12-15 16:03:37 +0100 | [diff] [blame] | 284 | } |
| 285 | |
| 286 | static inline struct mlxsw_sp_port * |
| 287 | mlxsw_sp_port_vport_find(const struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) |
| 288 | { |
| 289 | struct mlxsw_sp_port *mlxsw_sp_vport; |
| 290 | |
| 291 | list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list, |
| 292 | vport.list) { |
| 293 | if (mlxsw_sp_vport_vid_get(mlxsw_sp_vport) == vid) |
| 294 | return mlxsw_sp_vport; |
| 295 | } |
| 296 | |
| 297 | return NULL; |
| 298 | } |
| 299 | |
Ido Schimmel | aac78a4 | 2015-12-15 16:03:42 +0100 | [diff] [blame] | 300 | static inline struct mlxsw_sp_port * |
Ido Schimmel | d0ec875 | 2016-06-20 23:04:12 +0200 | [diff] [blame^] | 301 | mlxsw_sp_port_vport_find_by_fid(const struct mlxsw_sp_port *mlxsw_sp_port, |
| 302 | u16 fid) |
Ido Schimmel | aac78a4 | 2015-12-15 16:03:42 +0100 | [diff] [blame] | 303 | { |
| 304 | struct mlxsw_sp_port *mlxsw_sp_vport; |
| 305 | |
| 306 | list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list, |
| 307 | vport.list) { |
Ido Schimmel | d0ec875 | 2016-06-20 23:04:12 +0200 | [diff] [blame^] | 308 | if (mlxsw_sp_vport_fid_get(mlxsw_sp_vport) == fid) |
Ido Schimmel | aac78a4 | 2015-12-15 16:03:42 +0100 | [diff] [blame] | 309 | return mlxsw_sp_vport; |
| 310 | } |
| 311 | |
| 312 | return NULL; |
| 313 | } |
| 314 | |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 315 | enum mlxsw_sp_flood_table { |
| 316 | MLXSW_SP_FLOOD_TABLE_UC, |
| 317 | MLXSW_SP_FLOOD_TABLE_BM, |
| 318 | }; |
| 319 | |
| 320 | int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp); |
Jiri Pirko | 0f433fa | 2016-04-14 18:19:24 +0200 | [diff] [blame] | 321 | void mlxsw_sp_buffers_fini(struct mlxsw_sp *mlxsw_sp); |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 322 | int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port); |
Jiri Pirko | 0f433fa | 2016-04-14 18:19:24 +0200 | [diff] [blame] | 323 | int mlxsw_sp_sb_pool_get(struct mlxsw_core *mlxsw_core, |
| 324 | unsigned int sb_index, u16 pool_index, |
| 325 | struct devlink_sb_pool_info *pool_info); |
| 326 | int mlxsw_sp_sb_pool_set(struct mlxsw_core *mlxsw_core, |
| 327 | unsigned int sb_index, u16 pool_index, u32 size, |
| 328 | enum devlink_sb_threshold_type threshold_type); |
| 329 | int mlxsw_sp_sb_port_pool_get(struct mlxsw_core_port *mlxsw_core_port, |
| 330 | unsigned int sb_index, u16 pool_index, |
| 331 | u32 *p_threshold); |
| 332 | int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port *mlxsw_core_port, |
| 333 | unsigned int sb_index, u16 pool_index, |
| 334 | u32 threshold); |
| 335 | int mlxsw_sp_sb_tc_pool_bind_get(struct mlxsw_core_port *mlxsw_core_port, |
| 336 | unsigned int sb_index, u16 tc_index, |
| 337 | enum devlink_sb_pool_type pool_type, |
| 338 | u16 *p_pool_index, u32 *p_threshold); |
| 339 | int mlxsw_sp_sb_tc_pool_bind_set(struct mlxsw_core_port *mlxsw_core_port, |
| 340 | unsigned int sb_index, u16 tc_index, |
| 341 | enum devlink_sb_pool_type pool_type, |
| 342 | u16 pool_index, u32 threshold); |
Jiri Pirko | 2d0ed39 | 2016-04-14 18:19:30 +0200 | [diff] [blame] | 343 | int mlxsw_sp_sb_occ_snapshot(struct mlxsw_core *mlxsw_core, |
| 344 | unsigned int sb_index); |
| 345 | int mlxsw_sp_sb_occ_max_clear(struct mlxsw_core *mlxsw_core, |
| 346 | unsigned int sb_index); |
| 347 | int mlxsw_sp_sb_occ_port_pool_get(struct mlxsw_core_port *mlxsw_core_port, |
| 348 | unsigned int sb_index, u16 pool_index, |
| 349 | u32 *p_cur, u32 *p_max); |
| 350 | int mlxsw_sp_sb_occ_tc_port_bind_get(struct mlxsw_core_port *mlxsw_core_port, |
| 351 | unsigned int sb_index, u16 tc_index, |
| 352 | enum devlink_sb_pool_type pool_type, |
| 353 | u32 *p_cur, u32 *p_max); |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 354 | |
| 355 | int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp); |
| 356 | void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp); |
| 357 | int mlxsw_sp_port_vlan_init(struct mlxsw_sp_port *mlxsw_sp_port); |
| 358 | void mlxsw_sp_port_switchdev_init(struct mlxsw_sp_port *mlxsw_sp_port); |
| 359 | void mlxsw_sp_port_switchdev_fini(struct mlxsw_sp_port *mlxsw_sp_port); |
| 360 | int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port, |
| 361 | enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid, |
| 362 | u16 vid); |
| 363 | int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin, |
| 364 | u16 vid_end, bool is_member, bool untagged); |
| 365 | int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto, |
| 366 | u16 vid); |
| 367 | int mlxsw_sp_port_kill_vid(struct net_device *dev, |
| 368 | __be16 __always_unused proto, u16 vid); |
Ido Schimmel | e606002 | 2016-06-20 23:04:11 +0200 | [diff] [blame] | 369 | int mlxsw_sp_vport_flood_set(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid, |
Ido Schimmel | 47a0a9e | 2016-06-20 23:04:08 +0200 | [diff] [blame] | 370 | bool set); |
Ido Schimmel | 4dc236c | 2016-01-27 15:20:16 +0100 | [diff] [blame] | 371 | void mlxsw_sp_port_active_vlans_del(struct mlxsw_sp_port *mlxsw_sp_port); |
Ido Schimmel | 28a01d2 | 2016-02-18 11:30:02 +0100 | [diff] [blame] | 372 | int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid); |
Ido Schimmel | 8e8dfe9 | 2016-04-06 17:10:10 +0200 | [diff] [blame] | 373 | int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port, |
| 374 | enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index, |
| 375 | bool dwrr, u8 dwrr_weight); |
| 376 | int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port, |
| 377 | u8 switch_prio, u8 tclass); |
| 378 | int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu, |
Ido Schimmel | d81a6bd | 2016-04-06 17:10:16 +0200 | [diff] [blame] | 379 | u8 *prio_tc, bool pause_en, |
| 380 | struct ieee_pfc *my_pfc); |
Ido Schimmel | cc7cf51 | 2016-04-06 17:10:11 +0200 | [diff] [blame] | 381 | int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port, |
| 382 | enum mlxsw_reg_qeec_hr hr, u8 index, |
| 383 | u8 next_index, u32 maxrate); |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 384 | |
Ido Schimmel | f00817d | 2016-04-06 17:10:09 +0200 | [diff] [blame] | 385 | #ifdef CONFIG_MLXSW_SPECTRUM_DCB |
| 386 | |
| 387 | int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port); |
| 388 | void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port); |
| 389 | |
| 390 | #else |
| 391 | |
| 392 | static inline int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port) |
| 393 | { |
| 394 | return 0; |
| 395 | } |
| 396 | |
| 397 | static inline void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port) |
| 398 | {} |
| 399 | |
| 400 | #endif |
| 401 | |
Jiri Pirko | 56ade8f | 2015-10-16 14:01:37 +0200 | [diff] [blame] | 402 | #endif |