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Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _MLXSW_SPECTRUM_H
38#define _MLXSW_SPECTRUM_H
39
40#include <linux/types.h>
41#include <linux/netdevice.h>
42#include <linux/bitops.h>
43#include <linux/if_vlan.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010044#include <linux/list.h>
Ido Schimmel8e8dfe92016-04-06 17:10:10 +020045#include <linux/dcbnl.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020046#include <net/switchdev.h>
Jiri Pirkoc4745502016-02-26 17:32:26 +010047#include <net/devlink.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020048
Elad Raz3a49b4f2016-01-10 21:06:28 +010049#include "port.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020050#include "core.h"
51
52#define MLXSW_SP_VFID_BASE VLAN_N_VID
Ido Schimmel7f71eb42015-12-15 16:03:37 +010053#define MLXSW_SP_VFID_PORT_MAX 512 /* Non-bridged VLAN interfaces */
Ido Schimmelb555cf42016-04-05 10:20:02 +020054#define MLXSW_SP_VFID_BR_MAX 6144 /* Bridged VLAN interfaces */
Ido Schimmel7f71eb42015-12-15 16:03:37 +010055#define MLXSW_SP_VFID_MAX (MLXSW_SP_VFID_PORT_MAX + MLXSW_SP_VFID_BR_MAX)
56
Jiri Pirko0d65fc12015-12-03 12:12:28 +010057#define MLXSW_SP_LAG_MAX 64
58#define MLXSW_SP_PORT_PER_LAG_MAX 16
Jiri Pirko56ade8f2015-10-16 14:01:37 +020059
Elad Raz53ae6282016-01-10 21:06:26 +010060#define MLXSW_SP_MID_MAX 7000
61
Ido Schimmel18f1e702016-02-26 17:32:31 +010062#define MLXSW_SP_PORTS_PER_CLUSTER_MAX 4
63
64#define MLXSW_SP_PORT_BASE_SPEED 25000 /* Mb/s */
65
Ido Schimmel1a198442016-04-06 17:10:02 +020066#define MLXSW_SP_BYTES_PER_CELL 96
67
68#define MLXSW_SP_BYTES_TO_CELLS(b) DIV_ROUND_UP(b, MLXSW_SP_BYTES_PER_CELL)
69
Ido Schimmel9f7ec052016-04-06 17:10:14 +020070/* Maximum delay buffer needed in case of PAUSE frames, in cells.
71 * Assumes 100m cable and maximum MTU.
72 */
73#define MLXSW_SP_PAUSE_DELAY 612
74
Ido Schimmeld81a6bd2016-04-06 17:10:16 +020075#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
76
77static inline u16 mlxsw_sp_pfc_delay_get(int mtu, u16 delay)
78{
79 delay = MLXSW_SP_BYTES_TO_CELLS(DIV_ROUND_UP(delay, BITS_PER_BYTE));
80 return MLXSW_SP_CELL_FACTOR * delay + MLXSW_SP_BYTES_TO_CELLS(mtu);
81}
82
Jiri Pirko56ade8f2015-10-16 14:01:37 +020083struct mlxsw_sp_port;
84
Jiri Pirko0d65fc12015-12-03 12:12:28 +010085struct mlxsw_sp_upper {
86 struct net_device *dev;
87 unsigned int ref_count;
88};
89
Ido Schimmel7f71eb42015-12-15 16:03:37 +010090struct mlxsw_sp_vfid {
91 struct list_head list;
92 u16 nr_vports;
93 u16 vfid; /* Starting at 0 */
Ido Schimmel26f0e7f2015-12-15 16:03:44 +010094 struct net_device *br_dev;
Ido Schimmel7f71eb42015-12-15 16:03:37 +010095 u16 vid;
96};
97
Elad Raz3a49b4f2016-01-10 21:06:28 +010098struct mlxsw_sp_mid {
99 struct list_head list;
100 unsigned char addr[ETH_ALEN];
101 u16 vid;
102 u16 mid;
103 unsigned int ref_count;
104};
105
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100106static inline u16 mlxsw_sp_vfid_to_fid(u16 vfid)
107{
108 return MLXSW_SP_VFID_BASE + vfid;
109}
110
Ido Schimmelaac78a42015-12-15 16:03:42 +0100111static inline u16 mlxsw_sp_fid_to_vfid(u16 fid)
112{
113 return fid - MLXSW_SP_VFID_BASE;
114}
115
116static inline bool mlxsw_sp_fid_is_vfid(u16 fid)
117{
118 return fid >= MLXSW_SP_VFID_BASE;
119}
120
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200121struct mlxsw_sp {
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100122 struct {
123 struct list_head list;
124 unsigned long mapped[BITS_TO_LONGS(MLXSW_SP_VFID_PORT_MAX)];
125 } port_vfids;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +0100126 struct {
127 struct list_head list;
128 unsigned long mapped[BITS_TO_LONGS(MLXSW_SP_VFID_BR_MAX)];
129 } br_vfids;
Elad Raz3a49b4f2016-01-10 21:06:28 +0100130 struct {
131 struct list_head list;
132 unsigned long mapped[BITS_TO_LONGS(MLXSW_SP_MID_MAX)];
133 } br_mids;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200134 unsigned long active_fids[BITS_TO_LONGS(VLAN_N_VID)];
135 struct mlxsw_sp_port **ports;
136 struct mlxsw_core *core;
137 const struct mlxsw_bus_info *bus_info;
138 unsigned char base_mac[ETH_ALEN];
139 struct {
140 struct delayed_work dw;
141#define MLXSW_SP_DEFAULT_LEARNING_INTERVAL 100
142 unsigned int interval; /* ms */
143 } fdb_notify;
Ido Schimmel869f63a2016-03-08 12:59:33 -0800144#define MLXSW_SP_MIN_AGEING_TIME 10
145#define MLXSW_SP_MAX_AGEING_TIME 1000000
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200146#define MLXSW_SP_DEFAULT_AGEING_TIME 300
147 u32 ageing_time;
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100148 struct mlxsw_sp_upper master_bridge;
149 struct mlxsw_sp_upper lags[MLXSW_SP_LAG_MAX];
Ido Schimmel558c2d52016-02-26 17:32:29 +0100150 u8 port_to_module[MLXSW_PORT_MAX_PORTS];
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200151};
152
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100153static inline struct mlxsw_sp_upper *
154mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
155{
156 return &mlxsw_sp->lags[lag_id];
157}
158
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200159struct mlxsw_sp_port_pcpu_stats {
160 u64 rx_packets;
161 u64 rx_bytes;
162 u64 tx_packets;
163 u64 tx_bytes;
164 struct u64_stats_sync syncp;
165 u32 tx_dropped;
166};
167
168struct mlxsw_sp_port {
169 struct net_device *dev;
170 struct mlxsw_sp_port_pcpu_stats __percpu *pcpu_stats;
171 struct mlxsw_sp *mlxsw_sp;
172 u8 local_port;
173 u8 stp_state;
Jiri Pirko0d9b9702015-10-28 10:16:56 +0100174 u8 learning:1,
175 learning_sync:1,
Ido Schimmel02930382015-10-28 10:16:58 +0100176 uc_flood:1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100177 bridged:1,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100178 lagged:1,
179 split:1;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200180 u16 pvid;
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100181 u16 lag_id;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100182 struct {
183 struct list_head list;
184 struct mlxsw_sp_vfid *vfid;
185 u16 vid;
186 } vport;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200187 struct {
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200188 u8 tx_pause:1,
189 rx_pause:1;
190 } link;
191 struct {
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200192 struct ieee_ets *ets;
Ido Schimmelcc7cf512016-04-06 17:10:11 +0200193 struct ieee_maxrate *maxrate;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200194 struct ieee_pfc *pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200195 } dcb;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200196 /* 802.1Q bridge VLANs */
Ido Schimmelbd40e9d2015-12-15 16:03:36 +0100197 unsigned long *active_vlans;
Elad Razfc1273a2016-01-06 13:01:11 +0100198 unsigned long *untagged_vlans;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200199 /* VLAN interfaces */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100200 struct list_head vports_list;
Jiri Pirkoc4745502016-02-26 17:32:26 +0100201 struct devlink_port devlink_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200202};
203
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200204static inline bool
205mlxsw_sp_port_is_pause_en(const struct mlxsw_sp_port *mlxsw_sp_port)
206{
207 return mlxsw_sp_port->link.tx_pause || mlxsw_sp_port->link.rx_pause;
208}
209
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100210static inline struct mlxsw_sp_port *
211mlxsw_sp_port_lagged_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id, u8 port_index)
212{
213 struct mlxsw_sp_port *mlxsw_sp_port;
214 u8 local_port;
215
216 local_port = mlxsw_core_lag_mapping_get(mlxsw_sp->core,
217 lag_id, port_index);
218 mlxsw_sp_port = mlxsw_sp->ports[local_port];
219 return mlxsw_sp_port && mlxsw_sp_port->lagged ? mlxsw_sp_port : NULL;
220}
221
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100222static inline bool
223mlxsw_sp_port_is_vport(const struct mlxsw_sp_port *mlxsw_sp_port)
224{
225 return mlxsw_sp_port->vport.vfid;
226}
227
Ido Schimmel26f0e7f2015-12-15 16:03:44 +0100228static inline struct net_device *
229mlxsw_sp_vport_br_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
230{
231 return mlxsw_sp_vport->vport.vfid->br_dev;
232}
233
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100234static inline u16
235mlxsw_sp_vport_vid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
236{
237 return mlxsw_sp_vport->vport.vid;
238}
239
240static inline u16
241mlxsw_sp_vport_vfid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
242{
243 return mlxsw_sp_vport->vport.vfid->vfid;
244}
245
246static inline struct mlxsw_sp_port *
247mlxsw_sp_port_vport_find(const struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
248{
249 struct mlxsw_sp_port *mlxsw_sp_vport;
250
251 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
252 vport.list) {
253 if (mlxsw_sp_vport_vid_get(mlxsw_sp_vport) == vid)
254 return mlxsw_sp_vport;
255 }
256
257 return NULL;
258}
259
Ido Schimmelaac78a42015-12-15 16:03:42 +0100260static inline struct mlxsw_sp_port *
261mlxsw_sp_port_vport_find_by_vfid(const struct mlxsw_sp_port *mlxsw_sp_port,
262 u16 vfid)
263{
264 struct mlxsw_sp_port *mlxsw_sp_vport;
265
266 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
267 vport.list) {
268 if (mlxsw_sp_vport_vfid_get(mlxsw_sp_vport) == vfid)
269 return mlxsw_sp_vport;
270 }
271
272 return NULL;
273}
274
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200275enum mlxsw_sp_flood_table {
276 MLXSW_SP_FLOOD_TABLE_UC,
277 MLXSW_SP_FLOOD_TABLE_BM,
278};
279
280int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp);
281int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port);
282
283int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp);
284void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp);
285int mlxsw_sp_port_vlan_init(struct mlxsw_sp_port *mlxsw_sp_port);
286void mlxsw_sp_port_switchdev_init(struct mlxsw_sp_port *mlxsw_sp_port);
287void mlxsw_sp_port_switchdev_fini(struct mlxsw_sp_port *mlxsw_sp_port);
288int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
289 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
290 u16 vid);
291int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
292 u16 vid_end, bool is_member, bool untagged);
293int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
294 u16 vid);
295int mlxsw_sp_port_kill_vid(struct net_device *dev,
296 __be16 __always_unused proto, u16 vid);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100297int mlxsw_sp_vport_flood_set(struct mlxsw_sp_port *mlxsw_sp_vport, u16 vfid,
Ido Schimmel19ae6122015-12-15 16:03:39 +0100298 bool set, bool only_uc);
Ido Schimmel4dc236c2016-01-27 15:20:16 +0100299void mlxsw_sp_port_active_vlans_del(struct mlxsw_sp_port *mlxsw_sp_port);
Ido Schimmel28a01d22016-02-18 11:30:02 +0100300int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200301int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
302 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
303 bool dwrr, u8 dwrr_weight);
304int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
305 u8 switch_prio, u8 tclass);
306int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200307 u8 *prio_tc, bool pause_en,
308 struct ieee_pfc *my_pfc);
Ido Schimmelcc7cf512016-04-06 17:10:11 +0200309int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
310 enum mlxsw_reg_qeec_hr hr, u8 index,
311 u8 next_index, u32 maxrate);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200312
Ido Schimmelf00817d2016-04-06 17:10:09 +0200313#ifdef CONFIG_MLXSW_SPECTRUM_DCB
314
315int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port);
316void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port);
317
318#else
319
320static inline int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port)
321{
322 return 0;
323}
324
325static inline void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port)
326{}
327
328#endif
329
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200330#endif