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Paul Mackerras14cf11a2005-09-26 16:04:21 +10001/*
2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
3 */
Stephen Rothwellbbeb3f42005-09-27 13:51:59 +10004#ifndef _ASM_POWERPC_SYSTEM_H
5#define _ASM_POWERPC_SYSTEM_H
Paul Mackerras14cf11a2005-09-26 16:04:21 +10006
Paul Mackerras14cf11a2005-09-26 16:04:21 +10007#include <linux/kernel.h>
8
9#include <asm/hw_irq.h>
Paul Mackerras40ef8cb2005-10-10 22:50:37 +100010#include <asm/atomic.h>
Paul Mackerras14cf11a2005-09-26 16:04:21 +100011
12/*
13 * Memory barrier.
14 * The sync instruction guarantees that all memory accesses initiated
15 * by this processor have been performed (with respect to all other
16 * mechanisms that access memory). The eieio instruction is a barrier
17 * providing an ordering (separately) for (a) cacheable stores and (b)
18 * loads and stores to non-cacheable memory (e.g. I/O devices).
19 *
20 * mb() prevents loads and stores being reordered across this point.
21 * rmb() prevents loads being reordered across this point.
22 * wmb() prevents stores being reordered across this point.
23 * read_barrier_depends() prevents data-dependent loads being reordered
24 * across this point (nop on PPC).
25 *
26 * We have to use the sync instructions for mb(), since lwsync doesn't
27 * order loads with respect to previous stores. Lwsync is fine for
Andy Fleminge0da0da2006-10-27 14:31:07 -050028 * rmb(), though. Note that rmb() actually uses a sync on 32-bit
29 * architectures.
Paul Mackerras14cf11a2005-09-26 16:04:21 +100030 *
31 * For wmb(), we use sync since wmb is used in drivers to order
32 * stores to system memory with respect to writes to the device.
33 * However, smp_wmb() can be a lighter-weight eieio barrier on
34 * SMP since it is only used to order updates to system memory.
35 */
36#define mb() __asm__ __volatile__ ("sync" : : : "memory")
Andy Fleminge0da0da2006-10-27 14:31:07 -050037#define rmb() __asm__ __volatile__ (__stringify(LWSYNC) : : : "memory")
Paul Mackerras14cf11a2005-09-26 16:04:21 +100038#define wmb() __asm__ __volatile__ ("sync" : : : "memory")
39#define read_barrier_depends() do { } while(0)
40
41#define set_mb(var, value) do { var = value; mb(); } while (0)
Paul Mackerras14cf11a2005-09-26 16:04:21 +100042
Arnd Bergmann88ced032005-12-16 22:43:46 +010043#ifdef __KERNEL__
Paul Mackerras14cf11a2005-09-26 16:04:21 +100044#ifdef CONFIG_SMP
45#define smp_mb() mb()
46#define smp_rmb() rmb()
47#define smp_wmb() __asm__ __volatile__ ("eieio" : : : "memory")
48#define smp_read_barrier_depends() read_barrier_depends()
49#else
50#define smp_mb() barrier()
51#define smp_rmb() barrier()
52#define smp_wmb() barrier()
53#define smp_read_barrier_depends() do { } while(0)
54#endif /* CONFIG_SMP */
55
Nathan Lynch5db9fa92006-08-22 20:36:05 -050056/*
57 * This is a barrier which prevents following instructions from being
58 * started until the value of the argument x is known. For example, if
59 * x is a variable loaded from memory, this prevents following
60 * instructions from being executed until the load has been performed.
61 */
62#define data_barrier(x) \
63 asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
64
Paul Mackerras14cf11a2005-09-26 16:04:21 +100065struct task_struct;
66struct pt_regs;
67
68#ifdef CONFIG_DEBUGGER
69
70extern int (*__debugger)(struct pt_regs *regs);
71extern int (*__debugger_ipi)(struct pt_regs *regs);
72extern int (*__debugger_bpt)(struct pt_regs *regs);
73extern int (*__debugger_sstep)(struct pt_regs *regs);
74extern int (*__debugger_iabr_match)(struct pt_regs *regs);
75extern int (*__debugger_dabr_match)(struct pt_regs *regs);
76extern int (*__debugger_fault_handler)(struct pt_regs *regs);
77
78#define DEBUGGER_BOILERPLATE(__NAME) \
79static inline int __NAME(struct pt_regs *regs) \
80{ \
81 if (unlikely(__ ## __NAME)) \
82 return __ ## __NAME(regs); \
83 return 0; \
84}
85
86DEBUGGER_BOILERPLATE(debugger)
87DEBUGGER_BOILERPLATE(debugger_ipi)
88DEBUGGER_BOILERPLATE(debugger_bpt)
89DEBUGGER_BOILERPLATE(debugger_sstep)
90DEBUGGER_BOILERPLATE(debugger_iabr_match)
91DEBUGGER_BOILERPLATE(debugger_dabr_match)
92DEBUGGER_BOILERPLATE(debugger_fault_handler)
93
Paul Mackerras14cf11a2005-09-26 16:04:21 +100094#else
95static inline int debugger(struct pt_regs *regs) { return 0; }
96static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
97static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
98static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
99static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
100static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
101static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
102#endif
103
104extern int set_dabr(unsigned long dabr);
105extern void print_backtrace(unsigned long *);
106extern void show_regs(struct pt_regs * regs);
107extern void flush_instruction_cache(void);
108extern void hard_reset_now(void);
109extern void poweroff_now(void);
110
111#ifdef CONFIG_6xx
112extern long _get_L2CR(void);
113extern long _get_L3CR(void);
114extern void _set_L2CR(unsigned long);
115extern void _set_L3CR(unsigned long);
116#else
117#define _get_L2CR() 0L
118#define _get_L3CR() 0L
119#define _set_L2CR(val) do { } while(0)
120#define _set_L3CR(val) do { } while(0)
121#endif
122
123extern void via_cuda_init(void);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000124extern void read_rtc_time(void);
125extern void pmac_find_display(void);
126extern void giveup_fpu(struct task_struct *);
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000127extern void disable_kernel_fp(void);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000128extern void enable_kernel_fp(void);
129extern void flush_fp_to_thread(struct task_struct *);
130extern void enable_kernel_altivec(void);
131extern void giveup_altivec(struct task_struct *);
132extern void load_up_altivec(struct task_struct *);
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000133extern int emulate_altivec(struct pt_regs *);
Johannes Bergd169d142007-04-28 08:00:03 +1000134extern void enable_kernel_spe(void);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000135extern void giveup_spe(struct task_struct *);
136extern void load_up_spe(struct task_struct *);
137extern int fix_alignment(struct pt_regs *);
David Gibson25c8a782005-10-27 16:27:25 +1000138extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
139extern void cvt_df(double *from, float *to, struct thread_struct *thread);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000140
Paul Mackerras5388fb12006-01-11 22:11:39 +1100141#ifndef CONFIG_SMP
142extern void discard_lazy_cpu_state(void);
143#else
144static inline void discard_lazy_cpu_state(void)
145{
146}
147#endif
148
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000149#ifdef CONFIG_ALTIVEC
150extern void flush_altivec_to_thread(struct task_struct *);
151#else
152static inline void flush_altivec_to_thread(struct task_struct *t)
153{
154}
155#endif
156
157#ifdef CONFIG_SPE
158extern void flush_spe_to_thread(struct task_struct *);
159#else
160static inline void flush_spe_to_thread(struct task_struct *t)
161{
162}
163#endif
164
165extern int call_rtas(const char *, int, int, unsigned long *, ...);
166extern void cacheable_memzero(void *p, unsigned int nb);
167extern void *cacheable_memcpy(void *, const void *, unsigned int);
168extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
169extern void bad_page_fault(struct pt_regs *, unsigned long, int);
170extern int die(const char *, struct pt_regs *, long);
171extern void _exception(int, struct pt_regs *, int, unsigned long);
172#ifdef CONFIG_BOOKE_WDT
173extern u32 booke_wdt_enabled;
174extern u32 booke_wdt_period;
175#endif /* CONFIG_BOOKE_WDT */
176
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000177struct device_node;
178extern void note_scsi_host(struct device_node *, void *);
179
180extern struct task_struct *__switch_to(struct task_struct *,
181 struct task_struct *);
182#define switch_to(prev, next, last) ((last) = __switch_to((prev), (next)))
183
184struct thread_struct;
185extern struct task_struct *_switch(struct thread_struct *prev,
186 struct thread_struct *next);
187
Ingo Molnar4dc7a0b2006-01-12 01:05:27 -0800188/*
189 * On SMP systems, when the scheduler does migration-cost autodetection,
190 * it needs a way to flush as much of the CPU's caches as possible.
191 *
192 * TODO: fill this in!
193 */
194static inline void sched_cacheflush(void)
195{
196}
197
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000198extern unsigned int rtas_data;
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000199extern int mem_init_done; /* set on boot once kmalloc can be called */
Paul Mackerrascf00a8d2005-10-31 13:07:02 +1100200extern unsigned long memory_limit;
Paul Mackerras49b09852005-11-10 15:53:40 +1100201extern unsigned long klimit;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000202
Paul Mackerras17a63922005-10-20 21:10:09 +1000203extern int powersave_nap; /* set if nap mode can be used in idle loop */
204
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000205/*
206 * Atomic exchange
207 *
208 * Changes the memory location '*ptr' to be val and returns
209 * the previous value stored there.
210 */
211static __inline__ unsigned long
212__xchg_u32(volatile void *p, unsigned long val)
213{
214 unsigned long prev;
215
216 __asm__ __volatile__(
Anton Blanchard144b9c12006-01-13 15:37:17 +1100217 LWSYNC_ON_SMP
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000218"1: lwarx %0,0,%2 \n"
219 PPC405_ERR77(0,%2)
220" stwcx. %3,0,%2 \n\
221 bne- 1b"
222 ISYNC_ON_SMP
Linus Torvaldse2a3d402006-07-08 15:00:28 -0700223 : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
224 : "r" (p), "r" (val)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000225 : "cc", "memory");
226
227 return prev;
228}
229
230#ifdef CONFIG_PPC64
231static __inline__ unsigned long
232__xchg_u64(volatile void *p, unsigned long val)
233{
234 unsigned long prev;
235
236 __asm__ __volatile__(
Anton Blanchard144b9c12006-01-13 15:37:17 +1100237 LWSYNC_ON_SMP
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000238"1: ldarx %0,0,%2 \n"
239 PPC405_ERR77(0,%2)
240" stdcx. %3,0,%2 \n\
241 bne- 1b"
242 ISYNC_ON_SMP
Linus Torvaldse2a3d402006-07-08 15:00:28 -0700243 : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
244 : "r" (p), "r" (val)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000245 : "cc", "memory");
246
247 return prev;
248}
249#endif
250
251/*
252 * This function doesn't exist, so you'll get a linker error
253 * if something tries to do an invalid xchg().
254 */
255extern void __xchg_called_with_bad_pointer(void);
256
257static __inline__ unsigned long
258__xchg(volatile void *ptr, unsigned long x, unsigned int size)
259{
260 switch (size) {
261 case 4:
262 return __xchg_u32(ptr, x);
263#ifdef CONFIG_PPC64
264 case 8:
265 return __xchg_u64(ptr, x);
266#endif
267 }
268 __xchg_called_with_bad_pointer();
269 return x;
270}
271
272#define xchg(ptr,x) \
273 ({ \
274 __typeof__(*(ptr)) _x_ = (x); \
275 (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
276 })
277
278#define tas(ptr) (xchg((ptr),1))
279
280/*
281 * Compare and exchange - if *p == old, set it to new,
282 * and return the old value of *p.
283 */
284#define __HAVE_ARCH_CMPXCHG 1
285
286static __inline__ unsigned long
287__cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
288{
289 unsigned int prev;
290
291 __asm__ __volatile__ (
Anton Blanchard144b9c12006-01-13 15:37:17 +1100292 LWSYNC_ON_SMP
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000293"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
294 cmpw 0,%0,%3\n\
295 bne- 2f\n"
296 PPC405_ERR77(0,%2)
297" stwcx. %4,0,%2\n\
298 bne- 1b"
299 ISYNC_ON_SMP
300 "\n\
3012:"
Linus Torvaldse2a3d402006-07-08 15:00:28 -0700302 : "=&r" (prev), "+m" (*p)
303 : "r" (p), "r" (old), "r" (new)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000304 : "cc", "memory");
305
306 return prev;
307}
308
309#ifdef CONFIG_PPC64
310static __inline__ unsigned long
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100311__cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000312{
313 unsigned long prev;
314
315 __asm__ __volatile__ (
Anton Blanchard144b9c12006-01-13 15:37:17 +1100316 LWSYNC_ON_SMP
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000317"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
318 cmpd 0,%0,%3\n\
319 bne- 2f\n\
320 stdcx. %4,0,%2\n\
321 bne- 1b"
322 ISYNC_ON_SMP
323 "\n\
3242:"
Linus Torvaldse2a3d402006-07-08 15:00:28 -0700325 : "=&r" (prev), "+m" (*p)
326 : "r" (p), "r" (old), "r" (new)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000327 : "cc", "memory");
328
329 return prev;
330}
331#endif
332
333/* This function doesn't exist, so you'll get a linker error
334 if something tries to do an invalid cmpxchg(). */
335extern void __cmpxchg_called_with_bad_pointer(void);
336
337static __inline__ unsigned long
338__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
339 unsigned int size)
340{
341 switch (size) {
342 case 4:
343 return __cmpxchg_u32(ptr, old, new);
344#ifdef CONFIG_PPC64
345 case 8:
346 return __cmpxchg_u64(ptr, old, new);
347#endif
348 }
349 __cmpxchg_called_with_bad_pointer();
350 return old;
351}
352
353#define cmpxchg(ptr,o,n) \
354 ({ \
355 __typeof__(*(ptr)) _o_ = (o); \
356 __typeof__(*(ptr)) _n_ = (n); \
357 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
358 (unsigned long)_n_, sizeof(*(ptr))); \
359 })
360
361#ifdef CONFIG_PPC64
362/*
363 * We handle most unaligned accesses in hardware. On the other hand
364 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
365 * powers of 2 writes until it reaches sufficient alignment).
366 *
367 * Based on this we disable the IP header alignment in network drivers.
Anton Blanchard025be812006-03-31 02:27:06 -0800368 * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
369 * cacheline alignment of buffers.
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000370 */
Anton Blanchard025be812006-03-31 02:27:06 -0800371#define NET_IP_ALIGN 0
372#define NET_SKB_PAD L1_CACHE_BYTES
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000373#endif
374
375#define arch_align_stack(x) (x)
376
Paul Mackerras9b6b5632005-10-06 12:06:20 +1000377/* Used in very early kernel initialization. */
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000378extern unsigned long reloc_offset(void);
Paul Mackerras9b6b5632005-10-06 12:06:20 +1000379extern unsigned long add_reloc_offset(unsigned long);
380extern void reloc_got2(unsigned long);
381
382#define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x)))
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000383
Michael Ellermanc87ef112005-11-03 17:57:53 +1100384static inline void create_instruction(unsigned long addr, unsigned int instr)
385{
386 unsigned int *p;
387 p = (unsigned int *)addr;
388 *p = instr;
389 asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (p));
390}
391
392/* Flags for create_branch:
393 * "b" == create_branch(addr, target, 0);
394 * "ba" == create_branch(addr, target, BRANCH_ABSOLUTE);
395 * "bl" == create_branch(addr, target, BRANCH_SET_LINK);
396 * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK);
397 */
398#define BRANCH_SET_LINK 0x1
399#define BRANCH_ABSOLUTE 0x2
400
401static inline void create_branch(unsigned long addr,
402 unsigned long target, int flags)
403{
404 unsigned int instruction;
405
406 if (! (flags & BRANCH_ABSOLUTE))
407 target = target - addr;
408
409 /* Mask out the flags and target, so they don't step on each other. */
410 instruction = 0x48000000 | (flags & 0x3) | (target & 0x03FFFFFC);
411
412 create_instruction(addr, instruction);
413}
414
415static inline void create_function_call(unsigned long addr, void * func)
416{
417 unsigned long func_addr;
418
419#ifdef CONFIG_PPC64
420 /*
421 * On PPC64 the function pointer actually points to the function's
422 * descriptor. The first entry in the descriptor is the address
423 * of the function text.
424 */
425 func_addr = *(unsigned long *)func;
426#else
427 func_addr = (unsigned long)func;
428#endif
429 create_branch(addr, func_addr, BRANCH_SET_LINK);
430}
431
Paul Mackerrasc6622f62006-02-24 10:06:59 +1100432#ifdef CONFIG_VIRT_CPU_ACCOUNTING
433extern void account_system_vtime(struct task_struct *);
434#endif
435
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000436#endif /* __KERNEL__ */
Stephen Rothwellbbeb3f42005-09-27 13:51:59 +1000437#endif /* _ASM_POWERPC_SYSTEM_H */