blob: 4b6628ea381e45be866e571683b38cf1d45a5177 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001config FRV
2 bool
3 default y
Sam Ravnborgec7748b2008-02-09 10:46:40 +01004 select HAVE_IDE
David Howells4a3b9892009-06-11 13:05:24 +01005 select HAVE_ARCH_TRACEHOOK
Ingo Molnarcdd6c482009-09-21 12:02:48 +02006 select HAVE_PERF_EVENTS
Catalin Marinasaf1839e2012-10-08 16:28:08 -07007 select HAVE_UID16
Thomas Gleixnerf39b02d2011-01-19 20:32:04 +01008 select HAVE_GENERIC_HARDIRQS
Stephen Rothwell4febd952013-03-07 15:48:16 +11009 select VIRT_TO_BUS
Thomas Gleixner3062aa52011-03-29 14:05:13 +010010 select GENERIC_IRQ_SHOW
Catalin Marinas9b2a60c2012-10-08 16:28:13 -070011 select HAVE_DEBUG_BUGVERBOSE
Huang Yingdf013ff2011-07-13 13:14:22 +080012 select ARCH_HAVE_NMI_SAFE_CMPXCHG
Ben Hutchings9f13a1f2012-01-10 03:04:32 +000013 select GENERIC_CPU_DEVICES
Will Deaconc1d7e012012-07-30 14:42:46 -070014 select ARCH_WANT_IPC_PARSE_VERSION
Al Viro39e08a92012-12-25 16:27:55 -050015 select OLD_SIGSUSPEND3
Al Viro177b6702012-12-25 19:30:17 -050016 select OLD_SIGACTION
Dave Hansend1a1dc02013-07-01 13:04:42 -070017 select HAVE_DEBUG_STACKOVERFLOW
Linus Torvalds1da177e2005-04-16 15:20:36 -070018
Christoph Lameter66701b12007-02-10 01:43:09 -080019config ZONE_DMA
20 bool
21 default y
22
Linus Torvalds1da177e2005-04-16 15:20:36 -070023config RWSEM_GENERIC_SPINLOCK
24 bool
25 default y
26
27config RWSEM_XCHGADD_ALGORITHM
28 bool
29
Akinobu Mita1f6d7a92006-03-26 01:39:22 -080030config GENERIC_HWEIGHT
31 bool
32 default y
33
Linus Torvalds1da177e2005-04-16 15:20:36 -070034config GENERIC_CALIBRATE_DELAY
35 bool
36 default n
37
Ingo Molnar06027bd2006-02-14 13:53:15 -080038config TIME_LOW_RES
39 bool
40 default y
41
Christoph Lameter8defab32007-05-09 02:32:48 -070042config QUICKLIST
43 bool
44 default y
45
David Howellsf0d1b0b2006-12-08 02:37:49 -080046config ARCH_HAS_ILOG2_U32
47 bool
48 default y
49
50config ARCH_HAS_ILOG2_U64
51 bool
52 default y
53
H. Peter Anvinbdc80782008-02-08 04:21:26 -080054config HZ
55 int
56 default 1000
57
Linus Torvalds1da177e2005-04-16 15:20:36 -070058source "init/Kconfig"
59
Matt Helsleydc52ddc2008-10-18 20:27:21 -070060source "kernel/Kconfig.freezer"
61
Linus Torvalds1da177e2005-04-16 15:20:36 -070062
63menu "Fujitsu FR-V system setup"
64
65config MMU
66 bool "MMU support"
67 help
68 This options switches on and off support for the FR-V MMU
69 (effectively switching between vmlinux and uClinux). Not all FR-V
70 CPUs support this. Currently only the FR451 has a sufficiently
71 featured MMU.
72
73config FRV_OUTOFLINE_ATOMIC_OPS
74 bool "Out-of-line the FRV atomic operations"
75 default n
76 help
77 Setting this option causes the FR-V atomic operations to be mostly
78 implemented out-of-line.
79
Adrian Bunk0868ff72008-02-03 15:54:28 +020080 See Documentation/frv/atomic-ops.txt for more information.
Linus Torvalds1da177e2005-04-16 15:20:36 -070081
82config HIGHMEM
83 bool "High memory support"
84 depends on MMU
85 default y
86 help
87 If you wish to use more than 256MB of memory with your MMU based
88 system, you will need to select this option. The kernel can only see
89 the memory between 0xC0000000 and 0xD0000000 directly... everything
90 else must be kmapped.
91
92 The arch is, however, capable of supporting up to 3GB of SDRAM.
93
94config HIGHPTE
95 bool "Allocate page tables in highmem"
96 depends on HIGHMEM
97 default y
98 help
99 The VM uses one page of memory for each page table. For systems
100 with a lot of RAM, this can be wasteful of precious low memory.
101 Setting this option will put user-space page tables in high memory.
102
Dave Hansen3f22ab22005-06-23 00:07:43 -0700103source "mm/Kconfig"
104
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105choice
106 prompt "uClinux kernel load address"
107 depends on !MMU
108 default UCPAGE_OFFSET_C0000000
109 help
110 This option sets the base address for the uClinux kernel. The kernel
111 will rearrange the SDRAM layout to start at this address, and move
112 itself to start there. It must be greater than 0, and it must be
113 sufficiently less than 0xE0000000 that the SDRAM does not intersect
114 the I/O region.
115
116 The base address must also be aligned such that the SDRAM controller
117 can decode it. For instance, a 512MB SDRAM bank must be 512MB aligned.
118
119config UCPAGE_OFFSET_20000000
120 bool "0x20000000"
121
122config UCPAGE_OFFSET_40000000
123 bool "0x40000000"
124
125config UCPAGE_OFFSET_60000000
126 bool "0x60000000"
127
128config UCPAGE_OFFSET_80000000
129 bool "0x80000000"
130
131config UCPAGE_OFFSET_A0000000
132 bool "0xA0000000"
133
134config UCPAGE_OFFSET_C0000000
135 bool "0xC0000000 (Recommended)"
136
137endchoice
138
David Howells70382202008-02-04 22:29:53 -0800139config PAGE_OFFSET
140 hex
141 default 0x20000000 if UCPAGE_OFFSET_20000000
142 default 0x40000000 if UCPAGE_OFFSET_40000000
143 default 0x60000000 if UCPAGE_OFFSET_60000000
144 default 0x80000000 if UCPAGE_OFFSET_80000000
145 default 0xA0000000 if UCPAGE_OFFSET_A0000000
146 default 0xC0000000
147
Linus Torvalds1da177e2005-04-16 15:20:36 -0700148config PROTECT_KERNEL
149 bool "Protect core kernel against userspace"
150 depends on !MMU
151 default y
152 help
153 Selecting this option causes the uClinux kernel to change the
154 permittivity of DAMPR register covering the core kernel image to
155 prevent userspace accessing the underlying memory directly.
156
157choice
158 prompt "CPU Caching mode"
159 default FRV_DEFL_CACHE_WBACK
160 help
161 This option determines the default caching mode for the kernel.
162
163 Write-Back caching mode involves the all reads and writes causing
164 the affected cacheline to be read into the cache first before being
165 operated upon. Memory is not then updated by a write until the cache
166 is filled and a cacheline needs to be displaced from the cache to
167 make room. Only at that point is it written back.
168
169 Write-Behind caching is similar to Write-Back caching, except that a
170 write won't fetch a cacheline into the cache if there isn't already
171 one there; it will write directly to memory instead.
172
173 Write-Through caching only fetches cachelines from memory on a
174 read. Writes always get written directly to memory. If the affected
175 cacheline is also in cache, it will be updated too.
176
177 The final option is to turn of caching entirely.
178
179 Note that not all CPUs support Write-Behind caching. If the CPU on
180 which the kernel is running doesn't, it'll fall back to Write-Back
181 caching.
182
183config FRV_DEFL_CACHE_WBACK
184 bool "Write-Back"
185
186config FRV_DEFL_CACHE_WBEHIND
187 bool "Write-Behind"
188
189config FRV_DEFL_CACHE_WTHRU
190 bool "Write-Through"
191
192config FRV_DEFL_CACHE_DISABLED
193 bool "Disabled"
194
195endchoice
196
197menu "CPU core support"
198
199config CPU_FR401
200 bool "Include FR401 core support"
201 depends on !MMU
202 default y
203 help
204 This enables support for the FR401, FR401A and FR403 CPUs
205
206config CPU_FR405
207 bool "Include FR405 core support"
208 depends on !MMU
209 default y
210 help
211 This enables support for the FR405 CPU
212
213config CPU_FR451
214 bool "Include FR451 core support"
215 default y
216 help
217 This enables support for the FR451 CPU
218
219config CPU_FR451_COMPILE
220 bool "Specifically compile for FR451 core"
221 depends on CPU_FR451 && !CPU_FR401 && !CPU_FR405 && !CPU_FR551
222 default y
223 help
224 This causes appropriate flags to be passed to the compiler to
225 optimise for the FR451 CPU
226
227config CPU_FR551
228 bool "Include FR551 core support"
229 depends on !MMU
230 default y
231 help
232 This enables support for the FR555 CPU
233
234config CPU_FR551_COMPILE
235 bool "Specifically compile for FR551 core"
236 depends on CPU_FR551 && !CPU_FR401 && !CPU_FR405 && !CPU_FR451
237 default y
238 help
239 This causes appropriate flags to be passed to the compiler to
240 optimise for the FR555 CPU
241
242config FRV_L1_CACHE_SHIFT
243 int
244 default "5" if CPU_FR401 || CPU_FR405 || CPU_FR451
245 default "6" if CPU_FR551
246
247endmenu
248
249choice
250 prompt "System support"
251 default MB93091_VDK
252
253config MB93091_VDK
254 bool "MB93091 CPU board with or without motherboard"
255
256config MB93093_PDK
257 bool "MB93093 PDK unit"
258
259endchoice
260
261if MB93091_VDK
262choice
263 prompt "Motherboard support"
264 default MB93090_MB00
265
266config MB93090_MB00
267 bool "Use the MB93090-MB00 motherboard"
268 help
269 Select this option if the MB93091 CPU board is going to be used with
270 a MB93090-MB00 VDK motherboard
271
272config MB93091_NO_MB
273 bool "Use standalone"
274 help
275 Select this option if the MB93091 CPU board is going to be used
276 without a motherboard
277
278endchoice
279endif
280
David Howells1bcbba32006-09-25 23:32:04 -0700281config FUJITSU_MB93493
282 bool "MB93493 Multimedia chip"
283 help
284 Select this option if the MB93493 multimedia chip is going to be
285 used.
286
Linus Torvalds1da177e2005-04-16 15:20:36 -0700287choice
288 prompt "GP-Relative data support"
289 default GPREL_DATA_8
290 help
291 This option controls what data, if any, should be placed in the GP
292 relative data sections. Using this means that the compiler can
293 generate accesses to the data using GR16-relative addressing which
294 is faster than absolute instructions and saves space (2 instructions
295 per access).
296
297 However, the GPREL region is limited in size because the immediate
298 value used in the load and store instructions is limited to a 12-bit
299 signed number.
300
301 So if the linker starts complaining that accesses to GPREL data are
302 out of range, try changing this option from the default.
303
304 Note that modules will always be compiled with this feature disabled
305 as the module data will not be in range of the GP base address.
306
307config GPREL_DATA_8
308 bool "Put data objects of up to 8 bytes into GP-REL"
309
310config GPREL_DATA_4
311 bool "Put data objects of up to 4 bytes into GP-REL"
312
313config GPREL_DATA_NONE
314 bool "Don't use GP-REL"
315
316endchoice
317
David Howellsf8aec752006-01-08 01:01:23 -0800318config FRV_ONCPU_SERIAL
319 bool "Use on-CPU serial ports"
320 select SERIAL_8250
321 default y
322
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323config PCI
324 bool "Use PCI"
325 depends on MB93090_MB00
326 default y
Michael S. Tsirkin53224182011-11-29 21:20:06 +0200327 select GENERIC_PCI_IOMAP
Linus Torvalds1da177e2005-04-16 15:20:36 -0700328 help
329 Some FR-V systems (such as the MB93090-MB00 VDK) have PCI
330 onboard. If you have one of these boards and you wish to use the PCI
331 facilities, say Y here.
332
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333config RESERVE_DMA_COHERENT
334 bool "Reserve DMA coherent memory"
335 depends on PCI && !MMU
336 default y
337 help
338 Many PCI drivers require access to uncached memory for DMA device
339 communications (such as is done with some Ethernet buffer rings). If
340 a fully featured MMU is available, this can be done through page
341 table settings, but if not, a region has to be set aside and marked
342 with a special DAMPR register.
343
344 Setting this option causes uClinux to set aside a portion of the
345 available memory for use in this manner. The memory will then be
346 unavailable for normal kernel use.
347
348source "drivers/pci/Kconfig"
349
David Howells7a758312006-01-08 01:01:22 -0800350source "drivers/pcmcia/Kconfig"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351
Linus Torvalds1da177e2005-04-16 15:20:36 -0700352menu "Power management options"
Johannes Bergf4cb5702007-12-08 02:14:00 +0100353
354config ARCH_SUSPEND_POSSIBLE
355 def_bool y
Johannes Bergf4cb5702007-12-08 02:14:00 +0100356
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357source kernel/power/Kconfig
358endmenu
359
360endmenu
361
362
363menu "Executable formats"
364
365source "fs/Kconfig.binfmt"
366
367endmenu
368
Sam Ravnborgd5950b42005-07-11 21:03:49 -0700369source "net/Kconfig"
370
Linus Torvalds1da177e2005-04-16 15:20:36 -0700371source "drivers/Kconfig"
372
373source "fs/Kconfig"
374
Linus Torvalds1da177e2005-04-16 15:20:36 -0700375source "arch/frv/Kconfig.debug"
376
377source "security/Kconfig"
378
379source "crypto/Kconfig"
380
381source "lib/Kconfig"