blob: b1f9a20a367746d7ed7436b82ae0e257335fd3d9 [file] [log] [blame]
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001config ARM64
2 def_bool y
Arun Chandran92980402014-10-10 12:31:24 +01003 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01004 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
Riku Voipio957e3fa2014-12-12 16:57:44 -08005 select ARCH_HAS_GCOV_PROFILE_ALL
Laura Abbott308c09f2014-08-08 14:23:25 -07006 select ARCH_HAS_SG_CHAIN
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +01007 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
Sudeep Hollac63c8702014-05-09 10:33:01 +01008 select ARCH_USE_CMPXCHG_LOCKREF
Peter Zijlstra4badad32014-06-06 19:53:16 +02009 select ARCH_SUPPORTS_ATOMIC_RMW
Arnd Bergmann91701002013-02-21 11:42:57 +010010 select ARCH_WANT_OPTIONAL_GPIOLIB
Will Deacon6212a512012-11-07 14:16:28 +000011 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
Catalin Marinasb6f35982013-01-29 18:25:41 +000012 select ARCH_WANT_FRAME_POINTERS
Catalin Marinas25c92a32012-12-18 15:26:13 +000013 select ARM_AMBA
Mark Rutland1aee5d72012-11-20 10:06:00 +000014 select ARM_ARCH_TIMER
Catalin Marinasc4188ed2013-01-14 12:39:31 +000015 select ARM_GIC
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010016 select AUDIT_ARCH_COMPAT_GENERIC
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000017 select ARM_GIC_V2M if PCI_MSI
Marc Zyngier021f6532014-06-30 16:01:31 +010018 select ARM_GIC_V3
Marc Zyngier19812722014-11-24 14:35:19 +000019 select ARM_GIC_V3_ITS if PCI_MSI
Will Deaconadace892013-05-08 17:29:24 +010020 select BUILDTIME_EXTABLE_SORT
Catalin Marinasdb2789b2012-12-18 15:27:25 +000021 select CLONE_BACKWARDS
Deepak Saxena7ca2ef32012-09-22 10:33:36 -070022 select COMMON_CLK
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +000023 select CPU_PM if (SUSPEND || CPU_IDLE)
Will Deacon7bc13fd2013-11-06 19:32:13 +000024 select DCACHE_WORD_ACCESS
Laura Abbottd4932f92014-10-09 15:26:44 -070025 select GENERIC_ALLOCATOR
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010026 select GENERIC_CLOCKEVENTS
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +010027 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
Ard Biesheuvel3be1a5c2014-03-04 01:10:04 +000028 select GENERIC_CPU_AUTOPROBE
Mark Salterbf4b5582014-04-07 15:39:52 -070029 select GENERIC_EARLY_IOREMAP
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010030 select GENERIC_IRQ_PROBE
31 select GENERIC_IRQ_SHOW
Arnd Bergmanncb61f672014-11-19 14:09:07 +010032 select GENERIC_PCI_IOMAP
Stephen Boyd65cd4f62013-07-18 16:21:18 -070033 select GENERIC_SCHED_CLOCK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010034 select GENERIC_SMP_IDLE_THREAD
Will Deacon12a0ef72013-11-06 17:20:22 +000035 select GENERIC_STRNCPY_FROM_USER
36 select GENERIC_STRNLEN_USER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010037 select GENERIC_TIME_VSYSCALL
Marc Zyngiera1ddc742014-08-26 11:03:17 +010038 select HANDLE_DOMAIN_IRQ
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010039 select HARDIRQS_SW_RESEND
Steve Capper5284e1b2014-10-24 13:22:20 +010040 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010041 select HAVE_ARCH_AUDITSYSCALL
Jiang Liu9732caf2014-01-07 22:17:13 +080042 select HAVE_ARCH_JUMP_LABEL
Vijaya Kumar K95292472014-01-28 11:20:22 +000043 select HAVE_ARCH_KGDB
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +000044 select HAVE_ARCH_SECCOMP_FILTER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010045 select HAVE_ARCH_TRACEHOOK
Zi Shen Lime54bcde2014-08-26 21:15:30 -070046 select HAVE_BPF_JIT
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010047 select HAVE_C_RECORDMCOUNT
Laura Abbottc0c264a2014-06-25 23:55:03 +010048 select HAVE_CC_STACKPROTECTOR
Steve Capper5284e1b2014-10-24 13:22:20 +010049 select HAVE_CMPXCHG_DOUBLE
Catalin Marinas9b2a60c2012-10-08 16:28:13 -070050 select HAVE_DEBUG_BUGVERBOSE
Catalin Marinasb69ec422012-10-08 16:28:11 -070051 select HAVE_DEBUG_KMEMLEAK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010052 select HAVE_DMA_API_DEBUG
53 select HAVE_DMA_ATTRS
Laura Abbott6ac21042013-12-12 19:28:33 +000054 select HAVE_DMA_CONTIGUOUS
AKASHI Takahirobd7d38d2014-04-30 10:54:34 +010055 select HAVE_DYNAMIC_FTRACE
Will Deacon50afc332013-12-16 17:50:08 +000056 select HAVE_EFFICIENT_UNALIGNED_ACCESS
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010057 select HAVE_FTRACE_MCOUNT_RECORD
AKASHI Takahiro819e50e2014-04-30 18:54:33 +090058 select HAVE_FUNCTION_TRACER
59 select HAVE_FUNCTION_GRAPH_TRACER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010060 select HAVE_GENERIC_DMA_COHERENT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010061 select HAVE_HW_BREAKPOINT if PERF_EVENTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010062 select HAVE_MEMBLOCK
Mark Rutland55834a72014-02-07 17:12:45 +000063 select HAVE_PATA_PLATFORM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010064 select HAVE_PERF_EVENTS
Jean Pihet2ee0d7f2014-02-03 19:18:27 +010065 select HAVE_PERF_REGS
66 select HAVE_PERF_USER_STACK_DUMP
Steve Capper5e5f6dc2014-10-09 15:29:23 -070067 select HAVE_RCU_TABLE_FREE
AKASHI Takahiro055b1212014-04-30 10:54:36 +010068 select HAVE_SYSCALL_TRACEPOINTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010069 select IRQ_DOMAIN
Catalin Marinasfea2aca2012-10-16 11:26:57 +010070 select MODULES_USE_ELF_RELA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010071 select NO_BOOTMEM
72 select OF
73 select OF_EARLY_FLATTREE
Marek Szyprowski9bf14b72014-02-28 14:42:55 +010074 select OF_RESERVED_MEM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010075 select PERF_USE_VMALLOC
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +000076 select POWER_RESET
77 select POWER_SUPPLY
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010078 select RTC_LIB
79 select SPARSE_IRQ
Catalin Marinas7ac57a82012-10-08 16:28:16 -070080 select SYSCTL_EXCEPTION_TRACE
Larry Bassel6c81fe72014-05-30 12:34:15 -070081 select HAVE_CONTEXT_TRACKING
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010082 help
83 ARM 64-bit (AArch64) Linux support.
84
85config 64BIT
86 def_bool y
87
88config ARCH_PHYS_ADDR_T_64BIT
89 def_bool y
90
91config MMU
92 def_bool y
93
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -070094config NO_IOPORT_MAP
Liviu Dudaud1e6dc92014-09-29 15:29:31 +010095 def_bool y if !PCI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010096
97config STACKTRACE_SUPPORT
98 def_bool y
99
100config LOCKDEP_SUPPORT
101 def_bool y
102
103config TRACE_IRQFLAGS_SUPPORT
104 def_bool y
105
Will Deaconc209f792014-03-14 17:47:05 +0000106config RWSEM_XCHGADD_ALGORITHM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100107 def_bool y
108
109config GENERIC_HWEIGHT
110 def_bool y
111
112config GENERIC_CSUM
113 def_bool y
114
115config GENERIC_CALIBRATE_DELAY
116 def_bool y
117
Catalin Marinas19e76402014-02-27 12:09:22 +0000118config ZONE_DMA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100119 def_bool y
120
Steve Capper29e56942014-10-09 15:29:25 -0700121config HAVE_GENERIC_RCU_GUP
122 def_bool y
123
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100124config ARCH_DMA_ADDR_T_64BIT
125 def_bool y
126
127config NEED_DMA_MAP_STATE
128 def_bool y
129
130config NEED_SG_DMA_LENGTH
131 def_bool y
132
133config SWIOTLB
134 def_bool y
135
136config IOMMU_HELPER
137 def_bool SWIOTLB
138
Ard Biesheuvel4cfb3612013-07-09 14:18:12 +0100139config KERNEL_MODE_NEON
140 def_bool y
141
Rob Herring92cc15f2014-04-18 17:19:59 -0500142config FIX_EARLYCON_MEM
143 def_bool y
144
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100145source "init/Kconfig"
146
147source "kernel/Kconfig.freezer"
148
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100149menu "Platform selection"
150
Suravee Suthikulpanit41904362014-11-26 11:51:09 +0700151config ARCH_SEATTLE
152 bool "AMD Seattle SoC Family"
153 help
154 This enables support for AMD Seattle SOC Family
155
Radha Mohan Chintakuntla28f74202014-04-08 18:47:51 +0530156config ARCH_THUNDER
157 bool "Cavium Inc. Thunder SoC Family"
158 help
159 This enables support for Cavium's Thunder Family of SoCs.
160
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100161config ARCH_VEXPRESS
162 bool "ARMv8 software model (Versatile Express)"
163 select ARCH_REQUIRE_GPIOLIB
164 select COMMON_CLK_VERSATILE
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +0000165 select POWER_RESET_VEXPRESS
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100166 select VEXPRESS_CONFIG
167 help
168 This enables support for the ARMv8 software model (Versatile
169 Express).
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100170
Vinayak Kale15942852013-04-24 10:06:57 +0100171config ARCH_XGENE
172 bool "AppliedMicro X-Gene SOC Family"
173 help
174 This enables support for AppliedMicro X-Gene SOC Family
175
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100176endmenu
177
178menu "Bus support"
179
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100180config PCI
181 bool "PCI support"
182 help
183 This feature enables support for PCI bus system. If you say Y
184 here, the kernel will include drivers and infrastructure code
185 to support PCI bus devices.
186
187config PCI_DOMAINS
188 def_bool PCI
189
190config PCI_DOMAINS_GENERIC
191 def_bool PCI
192
193config PCI_SYSCALL
194 def_bool PCI
195
196source "drivers/pci/Kconfig"
197source "drivers/pci/pcie/Kconfig"
198source "drivers/pci/hotplug/Kconfig"
199
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100200endmenu
201
202menu "Kernel Features"
203
Andre Przywarac0a01b82014-11-14 15:54:12 +0000204menu "ARM errata workarounds via the alternatives framework"
205
206config ARM64_ERRATUM_826319
207 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
208 default y
209 help
210 This option adds an alternative code sequence to work around ARM
211 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
212 AXI master interface and an L2 cache.
213
214 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
215 and is unable to accept a certain write via this interface, it will
216 not progress on read data presented on the read data channel and the
217 system can deadlock.
218
219 The workaround promotes data cache clean instructions to
220 data cache clean-and-invalidate.
221 Please note that this does not necessarily enable the workaround,
222 as it depends on the alternative framework, which will only patch
223 the kernel if an affected CPU is detected.
224
225 If unsure, say Y.
226
227config ARM64_ERRATUM_827319
228 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
229 default y
230 help
231 This option adds an alternative code sequence to work around ARM
232 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
233 master interface and an L2 cache.
234
235 Under certain conditions this erratum can cause a clean line eviction
236 to occur at the same time as another transaction to the same address
237 on the AMBA 5 CHI interface, which can cause data corruption if the
238 interconnect reorders the two transactions.
239
240 The workaround promotes data cache clean instructions to
241 data cache clean-and-invalidate.
242 Please note that this does not necessarily enable the workaround,
243 as it depends on the alternative framework, which will only patch
244 the kernel if an affected CPU is detected.
245
246 If unsure, say Y.
247
248config ARM64_ERRATUM_824069
249 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
250 default y
251 help
252 This option adds an alternative code sequence to work around ARM
253 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
254 to a coherent interconnect.
255
256 If a Cortex-A53 processor is executing a store or prefetch for
257 write instruction at the same time as a processor in another
258 cluster is executing a cache maintenance operation to the same
259 address, then this erratum might cause a clean cache line to be
260 incorrectly marked as dirty.
261
262 The workaround promotes data cache clean instructions to
263 data cache clean-and-invalidate.
264 Please note that this option does not necessarily enable the
265 workaround, as it depends on the alternative framework, which will
266 only patch the kernel if an affected CPU is detected.
267
268 If unsure, say Y.
269
270config ARM64_ERRATUM_819472
271 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
272 default y
273 help
274 This option adds an alternative code sequence to work around ARM
275 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
276 present when it is connected to a coherent interconnect.
277
278 If the processor is executing a load and store exclusive sequence at
279 the same time as a processor in another cluster is executing a cache
280 maintenance operation to the same address, then this erratum might
281 cause data corruption.
282
283 The workaround promotes data cache clean instructions to
284 data cache clean-and-invalidate.
285 Please note that this does not necessarily enable the workaround,
286 as it depends on the alternative framework, which will only patch
287 the kernel if an affected CPU is detected.
288
289 If unsure, say Y.
290
291config ARM64_ERRATUM_832075
292 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
293 default y
294 help
295 This option adds an alternative code sequence to work around ARM
296 erratum 832075 on Cortex-A57 parts up to r1p2.
297
298 Affected Cortex-A57 parts might deadlock when exclusive load/store
299 instructions to Write-Back memory are mixed with Device loads.
300
301 The workaround is to promote device loads to use Load-Acquire
302 semantics.
303 Please note that this does not necessarily enable the workaround,
304 as it depends on the alternative framework, which will only patch
305 the kernel if an affected CPU is detected.
306
307 If unsure, say Y.
308
309endmenu
310
311
Jungseok Leee41ceed2014-05-12 10:40:38 +0100312choice
313 prompt "Page size"
314 default ARM64_4K_PAGES
315 help
316 Page size (translation granule) configuration.
317
318config ARM64_4K_PAGES
319 bool "4KB"
320 help
321 This feature enables 4KB pages support.
322
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100323config ARM64_64K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100324 bool "64KB"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100325 help
326 This feature enables 64KB pages support (4KB by default)
327 allowing only two levels of page tables and faster TLB
328 look-up. AArch32 emulation is not available when this feature
329 is enabled.
330
Jungseok Leee41ceed2014-05-12 10:40:38 +0100331endchoice
332
333choice
334 prompt "Virtual address space size"
335 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
336 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
337 help
338 Allows choosing one of multiple possible virtual address
339 space sizes. The level of translation table is determined by
340 a combination of page size and virtual address space size.
341
342config ARM64_VA_BITS_39
343 bool "39-bit"
344 depends on ARM64_4K_PAGES
345
346config ARM64_VA_BITS_42
347 bool "42-bit"
348 depends on ARM64_64K_PAGES
349
Jungseok Leec79b9542014-05-12 18:40:51 +0900350config ARM64_VA_BITS_48
351 bool "48-bit"
Christoffer Dall04f905a2014-10-10 11:14:30 +0100352 depends on !ARM_SMMU
Jungseok Leec79b9542014-05-12 18:40:51 +0900353
Jungseok Leee41ceed2014-05-12 10:40:38 +0100354endchoice
355
356config ARM64_VA_BITS
357 int
358 default 39 if ARM64_VA_BITS_39
359 default 42 if ARM64_VA_BITS_42
Jungseok Leec79b9542014-05-12 18:40:51 +0900360 default 48 if ARM64_VA_BITS_48
Jungseok Leee41ceed2014-05-12 10:40:38 +0100361
Catalin Marinasabe669d2014-07-15 15:37:21 +0100362config ARM64_PGTABLE_LEVELS
363 int
364 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
Catalin Marinas383c2792014-07-21 15:54:50 +0100365 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
Catalin Marinasabe669d2014-07-15 15:37:21 +0100366 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
367 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
Jungseok Leec79b9542014-05-12 18:40:51 +0900368
Will Deacona8720132013-10-11 14:52:19 +0100369config CPU_BIG_ENDIAN
370 bool "Build big-endian kernel"
371 help
372 Say Y if you plan on running a kernel in big-endian mode.
373
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100374config SMP
375 bool "Symmetric Multi-Processing"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100376 help
377 This enables support for systems with more than one CPU. If
378 you say N here, the kernel will run on single and
379 multiprocessor machines, but will use only one CPU of a
380 multiprocessor machine. If you say Y here, the kernel will run
381 on many, but not all, single processor machines. On a single
382 processor machine, the kernel will run faster if you say N
383 here.
384
385 If you don't know what to do here, say N.
386
Mark Brownf6e763b2014-03-04 07:51:17 +0000387config SCHED_MC
388 bool "Multi-core scheduler support"
389 depends on SMP
390 help
391 Multi-core scheduler support improves the CPU scheduler's decision
392 making when dealing with multi-core CPU chips at a cost of slightly
393 increased overhead in some places. If unsure say N here.
394
395config SCHED_SMT
396 bool "SMT scheduler support"
397 depends on SMP
398 help
399 Improves the CPU scheduler's decision making when dealing with
400 MultiThreading at a cost of slightly increased overhead in some
401 places. If unsure say N here.
402
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100403config NR_CPUS
Robert Richtere3672642014-09-08 12:44:48 +0100404 int "Maximum number of CPUs (2-64)"
405 range 2 64
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100406 depends on SMP
Vinayak Kale15942852013-04-24 10:06:57 +0100407 # These have to remain sorted largest to smallest
Robert Richtere3672642014-09-08 12:44:48 +0100408 default "64"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100409
Mark Rutland9327e2c2013-10-24 20:30:18 +0100410config HOTPLUG_CPU
411 bool "Support for hot-pluggable CPUs"
412 depends on SMP
413 help
414 Say Y here to experiment with turning CPUs off and on. CPUs
415 can be controlled through /sys/devices/system/cpu.
416
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100417source kernel/Kconfig.preempt
418
419config HZ
420 int
421 default 100
422
423config ARCH_HAS_HOLES_MEMORYMODEL
424 def_bool y if SPARSEMEM
425
426config ARCH_SPARSEMEM_ENABLE
427 def_bool y
428 select SPARSEMEM_VMEMMAP_ENABLE
429
430config ARCH_SPARSEMEM_DEFAULT
431 def_bool ARCH_SPARSEMEM_ENABLE
432
433config ARCH_SELECT_MEMORY_MODEL
434 def_bool ARCH_SPARSEMEM_ENABLE
435
436config HAVE_ARCH_PFN_VALID
437 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
438
439config HW_PERF_EVENTS
440 bool "Enable hardware performance counter support for perf events"
441 depends on PERF_EVENTS
442 default y
443 help
444 Enable hardware performance counter support for perf events. If
445 disabled, perf events will use software events only.
446
Steve Capper084bd292013-04-10 13:48:00 +0100447config SYS_SUPPORTS_HUGETLBFS
448 def_bool y
449
450config ARCH_WANT_GENERAL_HUGETLB
451 def_bool y
452
453config ARCH_WANT_HUGE_PMD_SHARE
454 def_bool y if !ARM64_64K_PAGES
455
Steve Capperaf074842013-04-19 16:23:57 +0100456config HAVE_ARCH_TRANSPARENT_HUGEPAGE
457 def_bool y
458
Catalin Marinasa41dc0e2014-04-03 17:48:54 +0100459config ARCH_HAS_CACHE_LINE_SIZE
460 def_bool y
461
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100462source "mm/Kconfig"
463
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +0000464config SECCOMP
465 bool "Enable seccomp to safely compute untrusted bytecode"
466 ---help---
467 This kernel feature is useful for number crunching applications
468 that may need to compute untrusted bytecode during their
469 execution. By using pipes or other transports made available to
470 the process as file descriptors supporting the read/write
471 syscalls, it's possible to isolate those applications in
472 their own address space using seccomp. Once seccomp is
473 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
474 and the task is only allowed to execute a few safe syscalls
475 defined by each seccomp mode.
476
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000477config XEN_DOM0
478 def_bool y
479 depends on XEN
480
481config XEN
Julien Grallc2ba1f72014-09-17 14:07:06 -0700482 bool "Xen guest support on ARM64"
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000483 depends on ARM64 && OF
Stefano Stabellini83862cc2013-10-10 13:40:44 +0000484 select SWIOTLB_XEN
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000485 help
486 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
487
Steve Capperd03bb142013-04-25 15:19:21 +0100488config FORCE_MAX_ZONEORDER
489 int
490 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
491 default "11"
492
Will Deacon1b907f42014-11-20 16:51:10 +0000493menuconfig ARMV8_DEPRECATED
494 bool "Emulate deprecated/obsolete ARMv8 instructions"
495 depends on COMPAT
496 help
497 Legacy software support may require certain instructions
498 that have been deprecated or obsoleted in the architecture.
499
500 Enable this config to enable selective emulation of these
501 features.
502
503 If unsure, say Y
504
505if ARMV8_DEPRECATED
506
507config SWP_EMULATION
508 bool "Emulate SWP/SWPB instructions"
509 help
510 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
511 they are always undefined. Say Y here to enable software
512 emulation of these instructions for userspace using LDXR/STXR.
513
514 In some older versions of glibc [<=2.8] SWP is used during futex
515 trylock() operations with the assumption that the code will not
516 be preempted. This invalid assumption may be more likely to fail
517 with SWP emulation enabled, leading to deadlock of the user
518 application.
519
520 NOTE: when accessing uncached shared regions, LDXR/STXR rely
521 on an external transaction monitoring block called a global
522 monitor to maintain update atomicity. If your system does not
523 implement a global monitor, this option can cause programs that
524 perform SWP operations to uncached memory to deadlock.
525
526 If unsure, say Y
527
528config CP15_BARRIER_EMULATION
529 bool "Emulate CP15 Barrier instructions"
530 help
531 The CP15 barrier instructions - CP15ISB, CP15DSB, and
532 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
533 strongly recommended to use the ISB, DSB, and DMB
534 instructions instead.
535
536 Say Y here to enable software emulation of these
537 instructions for AArch32 userspace code. When this option is
538 enabled, CP15 barrier usage is traced which can help
539 identify software that needs updating.
540
541 If unsure, say Y
542
543endif
544
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100545endmenu
546
547menu "Boot options"
548
549config CMDLINE
550 string "Default kernel command string"
551 default ""
552 help
553 Provide a set of default command-line options at build time by
554 entering them here. As a minimum, you should specify the the
555 root device (e.g. root=/dev/nfs).
556
557config CMDLINE_FORCE
558 bool "Always use the default kernel command string"
559 help
560 Always use the default kernel command string, even if the boot
561 loader passes other arguments to the kernel.
562 This is useful if you cannot or don't want to change the
563 command-line options your boot loader passes to the kernel.
564
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200565config EFI_STUB
566 bool
567
Mark Salterf84d0272014-04-15 21:59:30 -0400568config EFI
569 bool "UEFI runtime support"
570 depends on OF && !CPU_BIG_ENDIAN
571 select LIBFDT
572 select UCS2_STRING
573 select EFI_PARAMS_FROM_FDT
Ard Biesheuvele15dd492014-07-04 19:41:53 +0200574 select EFI_RUNTIME_WRAPPERS
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200575 select EFI_STUB
576 select EFI_ARMSTUB
Mark Salterf84d0272014-04-15 21:59:30 -0400577 default y
578 help
579 This option provides support for runtime services provided
580 by UEFI firmware (such as non-volatile variables, realtime
Mark Salter3c7f2552014-04-15 22:47:52 -0400581 clock, and platform reset). A UEFI stub is also provided to
582 allow the kernel to be booted as an EFI application. This
583 is only useful on systems that have UEFI firmware.
Mark Salterf84d0272014-04-15 21:59:30 -0400584
Yi Lid1ae8c02014-10-04 23:46:43 +0800585config DMI
586 bool "Enable support for SMBIOS (DMI) tables"
587 depends on EFI
588 default y
589 help
590 This enables SMBIOS/DMI feature for systems.
591
592 This option is only useful on systems that have UEFI firmware.
593 However, even with this option, the resultant kernel should
594 continue to boot on existing non-UEFI platforms.
595
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100596endmenu
597
598menu "Userspace binary formats"
599
600source "fs/Kconfig.binfmt"
601
602config COMPAT
603 bool "Kernel support for 32-bit EL0"
604 depends on !ARM64_64K_PAGES
605 select COMPAT_BINFMT_ELF
Catalin Marinasaf1839e2012-10-08 16:28:08 -0700606 select HAVE_UID16
Al Viro84b9e9b2012-12-25 16:29:11 -0500607 select OLD_SIGSUSPEND3
Al Viro51682032012-12-25 19:31:29 -0500608 select COMPAT_OLD_SIGACTION
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100609 help
610 This option enables support for a 32-bit EL0 running under a 64-bit
611 kernel at EL1. AArch32-specific components such as system calls,
612 the user helper functions, VFP support and the ptrace interface are
613 handled appropriately by the kernel.
614
615 If you want to execute 32-bit userspace applications, say Y.
616
617config SYSVIPC_COMPAT
618 def_bool y
619 depends on COMPAT && SYSVIPC
620
621endmenu
622
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000623menu "Power management options"
624
625source "kernel/power/Kconfig"
626
627config ARCH_SUSPEND_POSSIBLE
628 def_bool y
629
630config ARM64_CPU_SUSPEND
631 def_bool PM_SLEEP
632
633endmenu
634
Lorenzo Pieralisi13072202013-07-17 14:54:21 +0100635menu "CPU Power Management"
636
637source "drivers/cpuidle/Kconfig"
638
Rob Herring52e7e812014-02-24 11:27:57 +0900639source "drivers/cpufreq/Kconfig"
640
641endmenu
642
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100643source "net/Kconfig"
644
645source "drivers/Kconfig"
646
Mark Salterf84d0272014-04-15 21:59:30 -0400647source "drivers/firmware/Kconfig"
648
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100649source "fs/Kconfig"
650
Marc Zyngierc3eb5b12013-07-04 13:34:32 +0100651source "arch/arm64/kvm/Kconfig"
652
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100653source "arch/arm64/Kconfig.debug"
654
655source "security/Kconfig"
656
657source "crypto/Kconfig"
Ard Biesheuvel2c988332014-03-06 16:23:33 +0800658if CRYPTO
659source "arch/arm64/crypto/Kconfig"
660endif
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100661
662source "lib/Kconfig"