blob: c43c3d2baf73c2e7663d367ad35aa97be8c6ba33 [file] [log] [blame]
Thomas Petazzonifddddb52013-03-21 17:59:14 +01001/*
2 * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
3 * 370/XP, Dove, Orion5x and MV78xx0)
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 *
9 * The Marvell EBU SoCs have a configurable physical address space:
10 * the physical address at which certain devices (PCIe, NOR, NAND,
11 * etc.) sit can be configured. The configuration takes place through
12 * two sets of registers:
13 *
14 * - One to configure the access of the CPU to the devices. Depending
15 * on the families, there are between 8 and 20 configurable windows,
16 * each can be use to create a physical memory window that maps to a
17 * specific device. Devices are identified by a tuple (target,
18 * attribute).
19 *
20 * - One to configure the access to the CPU to the SDRAM. There are
21 * either 2 (for Dove) or 4 (for other families) windows to map the
22 * SDRAM into the physical address space.
23 *
24 * This driver:
25 *
26 * - Reads out the SDRAM address decoding windows at initialization
27 * time, and fills the mvebu_mbus_dram_info structure with these
28 * informations. The exported function mv_mbus_dram_info() allow
29 * device drivers to get those informations related to the SDRAM
30 * address decoding windows. This is because devices also have their
31 * own windows (configured through registers that are part of each
32 * device register space), and therefore the drivers for Marvell
33 * devices have to configure those device -> SDRAM windows to ensure
34 * that DMA works properly.
35 *
36 * - Provides an API for platform code or device drivers to
37 * dynamically add or remove address decoding windows for the CPU ->
Thomas Petazzoni6275afe2013-07-26 10:17:52 -030038 * device accesses. This API is mvebu_mbus_add_window_by_id(),
39 * mvebu_mbus_add_window_remap_by_id() and
40 * mvebu_mbus_del_window().
Thomas Petazzonifddddb52013-03-21 17:59:14 +010041 *
42 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
43 * see the list of CPU -> SDRAM windows and their configuration
44 * (file 'sdram') and the list of CPU -> devices windows and their
45 * configuration (file 'devices').
46 */
47
Ezequiel Garciab15d0b52013-06-07 13:47:38 -030048#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
49
Thomas Petazzonifddddb52013-03-21 17:59:14 +010050#include <linux/kernel.h>
51#include <linux/module.h>
52#include <linux/init.h>
53#include <linux/mbus.h>
54#include <linux/io.h>
55#include <linux/ioport.h>
56#include <linux/of.h>
57#include <linux/of_address.h>
58#include <linux/debugfs.h>
Jason Gunthorpe09752a12014-04-18 14:19:51 +020059#include <linux/log2.h>
Thomas Petazzonibfa1ce52015-05-28 11:40:54 +020060#include <linux/memblock.h>
Thomas Petazzonia0e89c02014-11-21 17:00:03 +010061#include <linux/syscore_ops.h>
Thomas Petazzonifddddb52013-03-21 17:59:14 +010062
63/*
64 * DDR target is the same on all platforms.
65 */
66#define TARGET_DDR 0
67
68/*
69 * CPU Address Decode Windows registers
70 */
71#define WIN_CTRL_OFF 0x0000
72#define WIN_CTRL_ENABLE BIT(0)
Nicolas Schichan8c9e06e2015-05-28 10:40:12 +020073/* Only on HW I/O coherency capable platforms */
Thomas Petazzonia0b5cd42015-01-16 17:11:28 +010074#define WIN_CTRL_SYNCBARRIER BIT(1)
Thomas Petazzonifddddb52013-03-21 17:59:14 +010075#define WIN_CTRL_TGT_MASK 0xf0
76#define WIN_CTRL_TGT_SHIFT 4
77#define WIN_CTRL_ATTR_MASK 0xff00
78#define WIN_CTRL_ATTR_SHIFT 8
79#define WIN_CTRL_SIZE_MASK 0xffff0000
80#define WIN_CTRL_SIZE_SHIFT 16
81#define WIN_BASE_OFF 0x0004
82#define WIN_BASE_LOW 0xffff0000
83#define WIN_BASE_HIGH 0xf
84#define WIN_REMAP_LO_OFF 0x0008
85#define WIN_REMAP_LOW 0xffff0000
86#define WIN_REMAP_HI_OFF 0x000c
87
Thomas Petazzonia0b5cd42015-01-16 17:11:28 +010088#define UNIT_SYNC_BARRIER_OFF 0x84
89#define UNIT_SYNC_BARRIER_ALL 0xFFFF
90
Thomas Petazzonifddddb52013-03-21 17:59:14 +010091#define ATTR_HW_COHERENCY (0x1 << 4)
92
93#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
94#define DDR_BASE_CS_HIGH_MASK 0xf
95#define DDR_BASE_CS_LOW_MASK 0xff000000
96#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
97#define DDR_SIZE_ENABLED BIT(0)
98#define DDR_SIZE_CS_MASK 0x1c
99#define DDR_SIZE_CS_SHIFT 2
100#define DDR_SIZE_MASK 0xff000000
101
102#define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
103
Thomas Petazzonia0e89c02014-11-21 17:00:03 +0100104/* Relative to mbusbridge_base */
105#define MBUS_BRIDGE_CTRL_OFF 0x0
106#define MBUS_BRIDGE_BASE_OFF 0x4
107
108/* Maximum number of windows, for all known platforms */
109#define MBUS_WINS_MAX 20
110
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100111struct mvebu_mbus_state;
112
113struct mvebu_mbus_soc_data {
114 unsigned int num_wins;
Thomas Petazzonia0e89c02014-11-21 17:00:03 +0100115 bool has_mbus_bridge;
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100116 unsigned int (*win_cfg_offset)(const int win);
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100117 unsigned int (*win_remap_offset)(const int win);
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100118 void (*setup_cpu_target)(struct mvebu_mbus_state *s);
Thomas Petazzoni4749c022014-11-21 17:00:04 +0100119 int (*save_cpu_target)(struct mvebu_mbus_state *s,
120 u32 *store_addr);
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100121 int (*show_cpu_target)(struct mvebu_mbus_state *s,
122 struct seq_file *seq, void *v);
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100123};
124
Thomas Petazzonia0e89c02014-11-21 17:00:03 +0100125/*
126 * Used to store the state of one MBus window accross suspend/resume.
127 */
128struct mvebu_mbus_win_data {
129 u32 ctrl;
130 u32 base;
131 u32 remap_lo;
132 u32 remap_hi;
133};
134
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100135struct mvebu_mbus_state {
136 void __iomem *mbuswins_base;
137 void __iomem *sdramwins_base;
Thomas Petazzonia0e89c02014-11-21 17:00:03 +0100138 void __iomem *mbusbridge_base;
Thomas Petazzoni4749c022014-11-21 17:00:04 +0100139 phys_addr_t sdramwins_phys_base;
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100140 struct dentry *debugfs_root;
141 struct dentry *debugfs_sdram;
142 struct dentry *debugfs_devs;
Ezequiel Garcia79d94682013-07-26 10:17:47 -0300143 struct resource pcie_mem_aperture;
144 struct resource pcie_io_aperture;
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100145 const struct mvebu_mbus_soc_data *soc;
146 int hw_io_coherency;
Thomas Petazzonia0e89c02014-11-21 17:00:03 +0100147
148 /* Used during suspend/resume */
149 u32 mbus_bridge_ctrl;
150 u32 mbus_bridge_base;
151 struct mvebu_mbus_win_data wins[MBUS_WINS_MAX];
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100152};
153
154static struct mvebu_mbus_state mbus_state;
155
Thomas Petazzonibfa1ce52015-05-28 11:40:54 +0200156/*
157 * We provide two variants of the mv_mbus_dram_info() function:
158 *
159 * - The normal one, where the described DRAM ranges may overlap with
160 * the I/O windows, but for which the DRAM ranges are guaranteed to
161 * have a power of two size. Such ranges are suitable for the DMA
162 * masters that only DMA between the RAM and the device, which is
163 * actually all devices except the crypto engines.
164 *
165 * - The 'nooverlap' one, where the described DRAM ranges are
166 * guaranteed to not overlap with the I/O windows, but for which the
167 * DRAM ranges will not have power of two sizes. They will only be
168 * aligned on a 64 KB boundary, and have a size multiple of 64
169 * KB. Such ranges are suitable for the DMA masters that DMA between
170 * the crypto SRAM (which is mapped through an I/O window) and a
171 * device. This is the case for the crypto engines.
172 */
173
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100174static struct mbus_dram_target_info mvebu_mbus_dram_info;
Thomas Petazzonibfa1ce52015-05-28 11:40:54 +0200175static struct mbus_dram_target_info mvebu_mbus_dram_info_nooverlap;
176
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100177const struct mbus_dram_target_info *mv_mbus_dram_info(void)
178{
179 return &mvebu_mbus_dram_info;
180}
181EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
182
Thomas Petazzonibfa1ce52015-05-28 11:40:54 +0200183const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void)
184{
185 return &mvebu_mbus_dram_info_nooverlap;
186}
187EXPORT_SYMBOL_GPL(mv_mbus_dram_info_nooverlap);
188
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100189/* Checks whether the given window has remap capability */
190static bool mvebu_mbus_window_is_remappable(struct mvebu_mbus_state *mbus,
191 const int win)
192{
193 return mbus->soc->win_remap_offset(win) != MVEBU_MBUS_NO_REMAP;
194}
195
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100196/*
197 * Functions to manipulate the address decoding windows
198 */
199
200static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
201 int win, int *enabled, u64 *base,
202 u32 *size, u8 *target, u8 *attr,
203 u64 *remap)
204{
205 void __iomem *addr = mbus->mbuswins_base +
206 mbus->soc->win_cfg_offset(win);
207 u32 basereg = readl(addr + WIN_BASE_OFF);
208 u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
209
210 if (!(ctrlreg & WIN_CTRL_ENABLE)) {
211 *enabled = 0;
212 return;
213 }
214
215 *enabled = 1;
216 *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
217 *base |= (basereg & WIN_BASE_LOW);
218 *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
219
220 if (target)
221 *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
222
223 if (attr)
224 *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
225
226 if (remap) {
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100227 if (mvebu_mbus_window_is_remappable(mbus, win)) {
228 u32 remap_low, remap_hi;
229 void __iomem *addr_rmp = mbus->mbuswins_base +
230 mbus->soc->win_remap_offset(win);
231 remap_low = readl(addr_rmp + WIN_REMAP_LO_OFF);
232 remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF);
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100233 *remap = ((u64)remap_hi << 32) | remap_low;
234 } else
235 *remap = 0;
236 }
237}
238
239static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
240 int win)
241{
242 void __iomem *addr;
243
244 addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100245 writel(0, addr + WIN_BASE_OFF);
246 writel(0, addr + WIN_CTRL_OFF);
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100247
248 if (mvebu_mbus_window_is_remappable(mbus, win)) {
249 addr = mbus->mbuswins_base + mbus->soc->win_remap_offset(win);
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100250 writel(0, addr + WIN_REMAP_LO_OFF);
251 writel(0, addr + WIN_REMAP_HI_OFF);
252 }
253}
254
255/* Checks whether the given window number is available */
Andrew Lunn38bdf452015-01-18 09:46:10 -0600256
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100257static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
258 const int win)
259{
260 void __iomem *addr = mbus->mbuswins_base +
261 mbus->soc->win_cfg_offset(win);
262 u32 ctrl = readl(addr + WIN_CTRL_OFF);
Andrew Lunn38bdf452015-01-18 09:46:10 -0600263
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100264 return !(ctrl & WIN_CTRL_ENABLE);
265}
266
267/*
268 * Checks whether the given (base, base+size) area doesn't overlap an
269 * existing region
270 */
271static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
272 phys_addr_t base, size_t size,
273 u8 target, u8 attr)
274{
275 u64 end = (u64)base + size;
276 int win;
277
278 for (win = 0; win < mbus->soc->num_wins; win++) {
279 u64 wbase, wend;
280 u32 wsize;
281 u8 wtarget, wattr;
282 int enabled;
283
284 mvebu_mbus_read_window(mbus, win,
285 &enabled, &wbase, &wsize,
286 &wtarget, &wattr, NULL);
287
288 if (!enabled)
289 continue;
290
291 wend = wbase + wsize;
292
293 /*
294 * Check if the current window overlaps with the
295 * proposed physical range
296 */
297 if ((u64)base < wend && end > wbase)
298 return 0;
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100299 }
300
301 return 1;
302}
303
304static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
305 phys_addr_t base, size_t size)
306{
307 int win;
308
309 for (win = 0; win < mbus->soc->num_wins; win++) {
310 u64 wbase;
311 u32 wsize;
312 int enabled;
313
314 mvebu_mbus_read_window(mbus, win,
315 &enabled, &wbase, &wsize,
316 NULL, NULL, NULL);
317
318 if (!enabled)
319 continue;
320
321 if (base == wbase && size == wsize)
322 return win;
323 }
324
325 return -ENODEV;
326}
327
328static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
329 int win, phys_addr_t base, size_t size,
330 phys_addr_t remap, u8 target,
331 u8 attr)
332{
333 void __iomem *addr = mbus->mbuswins_base +
334 mbus->soc->win_cfg_offset(win);
335 u32 ctrl, remap_addr;
336
Jason Gunthorpe09752a12014-04-18 14:19:51 +0200337 if (!is_power_of_2(size)) {
338 WARN(true, "Invalid MBus window size: 0x%zx\n", size);
339 return -EINVAL;
340 }
341
342 if ((base & (phys_addr_t)(size - 1)) != 0) {
343 WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base,
344 size);
345 return -EINVAL;
346 }
347
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100348 ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
349 (attr << WIN_CTRL_ATTR_SHIFT) |
350 (target << WIN_CTRL_TGT_SHIFT) |
351 WIN_CTRL_ENABLE;
Nicolas Schichan8c9e06e2015-05-28 10:40:12 +0200352 if (mbus->hw_io_coherency)
353 ctrl |= WIN_CTRL_SYNCBARRIER;
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100354
355 writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
356 writel(ctrl, addr + WIN_CTRL_OFF);
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100357
358 if (mvebu_mbus_window_is_remappable(mbus, win)) {
359 void __iomem *addr_rmp = mbus->mbuswins_base +
360 mbus->soc->win_remap_offset(win);
361
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100362 if (remap == MVEBU_MBUS_NO_REMAP)
363 remap_addr = base;
364 else
365 remap_addr = remap;
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100366 writel(remap_addr & WIN_REMAP_LOW, addr_rmp + WIN_REMAP_LO_OFF);
367 writel(0, addr_rmp + WIN_REMAP_HI_OFF);
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100368 }
369
370 return 0;
371}
372
373static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
374 phys_addr_t base, size_t size,
375 phys_addr_t remap, u8 target,
376 u8 attr)
377{
378 int win;
379
380 if (remap == MVEBU_MBUS_NO_REMAP) {
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100381 for (win = 0; win < mbus->soc->num_wins; win++) {
382 if (mvebu_mbus_window_is_remappable(mbus, win))
383 continue;
384
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100385 if (mvebu_mbus_window_is_free(mbus, win))
386 return mvebu_mbus_setup_window(mbus, win, base,
387 size, remap,
388 target, attr);
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100389 }
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100390 }
391
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100392 for (win = 0; win < mbus->soc->num_wins; win++) {
393 /* Skip window if need remap but is not supported */
394 if ((remap != MVEBU_MBUS_NO_REMAP) &&
395 !mvebu_mbus_window_is_remappable(mbus, win))
396 continue;
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100397
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100398 if (mvebu_mbus_window_is_free(mbus, win))
399 return mvebu_mbus_setup_window(mbus, win, base, size,
400 remap, target, attr);
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100401 }
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100402
403 return -ENOMEM;
404}
405
406/*
407 * Debugfs debugging
408 */
409
410/* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */
411static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus,
412 struct seq_file *seq, void *v)
413{
414 int i;
415
416 for (i = 0; i < 4; i++) {
417 u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
418 u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
419 u64 base;
420 u32 size;
421
422 if (!(sizereg & DDR_SIZE_ENABLED)) {
423 seq_printf(seq, "[%d] disabled\n", i);
424 continue;
425 }
426
427 base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32;
428 base |= basereg & DDR_BASE_CS_LOW_MASK;
429 size = (sizereg | ~DDR_SIZE_MASK);
430
431 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
432 i, (unsigned long long)base,
433 (unsigned long long)base + size + 1,
434 (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT);
435 }
436
437 return 0;
438}
439
440/* Special function for Dove */
441static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus,
442 struct seq_file *seq, void *v)
443{
444 int i;
445
446 for (i = 0; i < 2; i++) {
447 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
448 u64 base;
449 u32 size;
450
451 if (!(map & 1)) {
452 seq_printf(seq, "[%d] disabled\n", i);
453 continue;
454 }
455
456 base = map & 0xff800000;
457 size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
458
459 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
460 i, (unsigned long long)base,
461 (unsigned long long)base + size, i);
462 }
463
464 return 0;
465}
466
467static int mvebu_sdram_debug_show(struct seq_file *seq, void *v)
468{
469 struct mvebu_mbus_state *mbus = &mbus_state;
470 return mbus->soc->show_cpu_target(mbus, seq, v);
471}
472
473static int mvebu_sdram_debug_open(struct inode *inode, struct file *file)
474{
475 return single_open(file, mvebu_sdram_debug_show, inode->i_private);
476}
477
478static const struct file_operations mvebu_sdram_debug_fops = {
479 .open = mvebu_sdram_debug_open,
480 .read = seq_read,
481 .llseek = seq_lseek,
482 .release = single_release,
483};
484
485static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
486{
487 struct mvebu_mbus_state *mbus = &mbus_state;
488 int win;
489
490 for (win = 0; win < mbus->soc->num_wins; win++) {
491 u64 wbase, wremap;
492 u32 wsize;
493 u8 wtarget, wattr;
Thomas Petazzonied843a72013-07-26 10:17:51 -0300494 int enabled;
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100495
496 mvebu_mbus_read_window(mbus, win,
497 &enabled, &wbase, &wsize,
498 &wtarget, &wattr, &wremap);
499
500 if (!enabled) {
501 seq_printf(seq, "[%02d] disabled\n", win);
502 continue;
503 }
504
Thomas Petazzonied843a72013-07-26 10:17:51 -0300505 seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x",
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100506 win, (unsigned long long)wbase,
Thomas Petazzonied843a72013-07-26 10:17:51 -0300507 (unsigned long long)(wbase + wsize), wtarget, wattr);
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100508
Jason Gunthorpe09752a12014-04-18 14:19:51 +0200509 if (!is_power_of_2(wsize) ||
510 ((wbase & (u64)(wsize - 1)) != 0))
511 seq_puts(seq, " (Invalid base/size!!)");
512
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100513 if (mvebu_mbus_window_is_remappable(mbus, win)) {
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100514 seq_printf(seq, " (remap %016llx)\n",
515 (unsigned long long)wremap);
516 } else
517 seq_printf(seq, "\n");
518 }
519
520 return 0;
521}
522
523static int mvebu_devs_debug_open(struct inode *inode, struct file *file)
524{
525 return single_open(file, mvebu_devs_debug_show, inode->i_private);
526}
527
528static const struct file_operations mvebu_devs_debug_fops = {
529 .open = mvebu_devs_debug_open,
530 .read = seq_read,
531 .llseek = seq_lseek,
532 .release = single_release,
533};
534
535/*
536 * SoC-specific functions and definitions
537 */
538
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100539static unsigned int generic_mbus_win_cfg_offset(int win)
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100540{
541 return win << 4;
542}
543
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100544static unsigned int armada_370_xp_mbus_win_cfg_offset(int win)
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100545{
546 /* The register layout is a bit annoying and the below code
547 * tries to cope with it.
548 * - At offset 0x0, there are the registers for the first 8
549 * windows, with 4 registers of 32 bits per window (ctrl,
550 * base, remap low, remap high)
551 * - Then at offset 0x80, there is a hole of 0x10 bytes for
552 * the internal registers base address and internal units
553 * sync barrier register.
554 * - Then at offset 0x90, there the registers for 12
555 * windows, with only 2 registers of 32 bits per window
556 * (ctrl, base).
557 */
558 if (win < 8)
559 return win << 4;
560 else
561 return 0x90 + ((win - 8) << 3);
562}
563
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100564static unsigned int mv78xx0_mbus_win_cfg_offset(int win)
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100565{
566 if (win < 8)
567 return win << 4;
568 else
569 return 0x900 + ((win - 8) << 4);
570}
571
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100572static unsigned int generic_mbus_win_remap_2_offset(int win)
573{
574 if (win < 2)
575 return generic_mbus_win_cfg_offset(win);
576 else
577 return MVEBU_MBUS_NO_REMAP;
578}
579
580static unsigned int generic_mbus_win_remap_4_offset(int win)
581{
582 if (win < 4)
583 return generic_mbus_win_cfg_offset(win);
584 else
585 return MVEBU_MBUS_NO_REMAP;
586}
587
588static unsigned int generic_mbus_win_remap_8_offset(int win)
589{
590 if (win < 8)
591 return generic_mbus_win_cfg_offset(win);
592 else
593 return MVEBU_MBUS_NO_REMAP;
594}
595
596static unsigned int armada_xp_mbus_win_remap_offset(int win)
597{
598 if (win < 8)
599 return generic_mbus_win_cfg_offset(win);
600 else if (win == 13)
601 return 0xF0 - WIN_REMAP_LO_OFF;
602 else
603 return MVEBU_MBUS_NO_REMAP;
604}
605
Thomas Petazzonibfa1ce52015-05-28 11:40:54 +0200606/*
607 * Use the memblock information to find the MBus bridge hole in the
608 * physical address space.
609 */
610static void __init
611mvebu_mbus_find_bridge_hole(uint64_t *start, uint64_t *end)
612{
613 struct memblock_region *r;
614 uint64_t s = 0;
615
616 for_each_memblock(memory, r) {
617 /*
618 * This part of the memory is above 4 GB, so we don't
619 * care for the MBus bridge hole.
620 */
621 if (r->base >= 0x100000000ULL)
622 continue;
623
624 /*
625 * The MBus bridge hole is at the end of the RAM under
626 * the 4 GB limit.
627 */
628 if (r->base + r->size > s)
629 s = r->base + r->size;
630 }
631
632 *start = s;
633 *end = 0x100000000ULL;
634}
635
636/*
637 * This function fills in the mvebu_mbus_dram_info_nooverlap data
638 * structure, by looking at the mvebu_mbus_dram_info data, and
639 * removing the parts of it that overlap with I/O windows.
640 */
641static void __init
642mvebu_mbus_setup_cpu_target_nooverlap(struct mvebu_mbus_state *mbus)
643{
644 uint64_t mbus_bridge_base, mbus_bridge_end;
645 int cs_nooverlap = 0;
646 int i;
647
648 mvebu_mbus_find_bridge_hole(&mbus_bridge_base, &mbus_bridge_end);
649
650 for (i = 0; i < mvebu_mbus_dram_info.num_cs; i++) {
651 struct mbus_dram_window *w;
652 u64 base, size, end;
653
654 w = &mvebu_mbus_dram_info.cs[i];
655 base = w->base;
656 size = w->size;
657 end = base + size;
658
659 /*
660 * The CS is fully enclosed inside the MBus bridge
661 * area, so ignore it.
662 */
663 if (base >= mbus_bridge_base && end <= mbus_bridge_end)
664 continue;
665
666 /*
667 * Beginning of CS overlaps with end of MBus, raise CS
668 * base address, and shrink its size.
669 */
670 if (base >= mbus_bridge_base && end > mbus_bridge_end) {
671 size -= mbus_bridge_end - base;
672 base = mbus_bridge_end;
673 }
674
675 /*
676 * End of CS overlaps with beginning of MBus, shrink
677 * CS size.
678 */
679 if (base < mbus_bridge_base && end > mbus_bridge_base)
680 size -= end - mbus_bridge_base;
681
682 w = &mvebu_mbus_dram_info_nooverlap.cs[cs_nooverlap++];
683 w->cs_index = i;
684 w->mbus_attr = 0xf & ~(1 << i);
685 if (mbus->hw_io_coherency)
686 w->mbus_attr |= ATTR_HW_COHERENCY;
687 w->base = base;
688 w->size = size;
689 }
690
691 mvebu_mbus_dram_info_nooverlap.mbus_dram_target_id = TARGET_DDR;
692 mvebu_mbus_dram_info_nooverlap.num_cs = cs_nooverlap;
693}
694
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100695static void __init
696mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
697{
698 int i;
699 int cs;
700
701 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
702
703 for (i = 0, cs = 0; i < 4; i++) {
Thomas Petazzoni885dbd12015-05-28 10:40:13 +0200704 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
705 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100706
707 /*
Thomas Petazzoni885dbd12015-05-28 10:40:13 +0200708 * We only take care of entries for which the chip
709 * select is enabled, and that don't have high base
710 * address bits set (devices can only access the first
711 * 32 bits of the memory).
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100712 */
Thomas Petazzoni885dbd12015-05-28 10:40:13 +0200713 if ((size & DDR_SIZE_ENABLED) &&
714 !(base & DDR_BASE_CS_HIGH_MASK)) {
715 struct mbus_dram_window *w;
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100716
Thomas Petazzoni885dbd12015-05-28 10:40:13 +0200717 w = &mvebu_mbus_dram_info.cs[cs++];
718 w->cs_index = i;
719 w->mbus_attr = 0xf & ~(1 << i);
720 if (mbus->hw_io_coherency)
721 w->mbus_attr |= ATTR_HW_COHERENCY;
722 w->base = base & DDR_BASE_CS_LOW_MASK;
723 w->size = (size | ~DDR_SIZE_MASK) + 1;
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100724 }
725 }
726 mvebu_mbus_dram_info.num_cs = cs;
727}
728
Thomas Petazzoni4749c022014-11-21 17:00:04 +0100729static int
730mvebu_mbus_default_save_cpu_target(struct mvebu_mbus_state *mbus,
731 u32 *store_addr)
732{
733 int i;
734
735 for (i = 0; i < 4; i++) {
736 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
737 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
738
739 writel(mbus->sdramwins_phys_base + DDR_BASE_CS_OFF(i),
740 store_addr++);
741 writel(base, store_addr++);
742 writel(mbus->sdramwins_phys_base + DDR_SIZE_CS_OFF(i),
743 store_addr++);
744 writel(size, store_addr++);
745 }
746
747 /* We've written 16 words to the store address */
748 return 16;
749}
750
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100751static void __init
752mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
753{
754 int i;
755 int cs;
756
757 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
758
759 for (i = 0, cs = 0; i < 2; i++) {
760 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
761
762 /*
763 * Chip select enabled?
764 */
765 if (map & 1) {
766 struct mbus_dram_window *w;
767
768 w = &mvebu_mbus_dram_info.cs[cs++];
769 w->cs_index = i;
770 w->mbus_attr = 0; /* CS address decoding done inside */
771 /* the DDR controller, no need to */
772 /* provide attributes */
773 w->base = map & 0xff800000;
774 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
775 }
776 }
777
778 mvebu_mbus_dram_info.num_cs = cs;
779}
780
Thomas Petazzoni4749c022014-11-21 17:00:04 +0100781static int
782mvebu_mbus_dove_save_cpu_target(struct mvebu_mbus_state *mbus,
783 u32 *store_addr)
784{
785 int i;
786
787 for (i = 0; i < 2; i++) {
788 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
789
790 writel(mbus->sdramwins_phys_base + DOVE_DDR_BASE_CS_OFF(i),
791 store_addr++);
792 writel(map, store_addr++);
793 }
794
795 /* We've written 4 words to the store address */
796 return 4;
797}
798
799int mvebu_mbus_save_cpu_target(u32 *store_addr)
800{
801 return mbus_state.soc->save_cpu_target(&mbus_state, store_addr);
802}
803
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100804static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100805 .num_wins = 20,
Thomas Petazzonia0e89c02014-11-21 17:00:03 +0100806 .has_mbus_bridge = true,
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100807 .win_cfg_offset = armada_370_xp_mbus_win_cfg_offset,
808 .win_remap_offset = generic_mbus_win_remap_8_offset,
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100809 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
810 .show_cpu_target = mvebu_sdram_debug_show_orion,
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100811 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
812};
813
814static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
815 .num_wins = 20,
816 .has_mbus_bridge = true,
817 .win_cfg_offset = armada_370_xp_mbus_win_cfg_offset,
818 .win_remap_offset = armada_xp_mbus_win_remap_offset,
819 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
820 .show_cpu_target = mvebu_sdram_debug_show_orion,
821 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100822};
823
824static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
825 .num_wins = 8,
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100826 .win_cfg_offset = generic_mbus_win_cfg_offset,
Thomas Petazzoni4749c022014-11-21 17:00:04 +0100827 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100828 .win_remap_offset = generic_mbus_win_remap_4_offset,
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100829 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
830 .show_cpu_target = mvebu_sdram_debug_show_orion,
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100831};
832
833static const struct mvebu_mbus_soc_data dove_mbus_data = {
834 .num_wins = 8,
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100835 .win_cfg_offset = generic_mbus_win_cfg_offset,
Thomas Petazzoni4749c022014-11-21 17:00:04 +0100836 .save_cpu_target = mvebu_mbus_dove_save_cpu_target,
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100837 .win_remap_offset = generic_mbus_win_remap_4_offset,
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100838 .setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
839 .show_cpu_target = mvebu_sdram_debug_show_dove,
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100840};
841
842/*
843 * Some variants of Orion5x have 4 remappable windows, some other have
844 * only two of them.
845 */
846static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
847 .num_wins = 8,
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100848 .win_cfg_offset = generic_mbus_win_cfg_offset,
Thomas Petazzoni4749c022014-11-21 17:00:04 +0100849 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100850 .win_remap_offset = generic_mbus_win_remap_4_offset,
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100851 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
852 .show_cpu_target = mvebu_sdram_debug_show_orion,
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100853};
854
855static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
856 .num_wins = 8,
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100857 .win_cfg_offset = generic_mbus_win_cfg_offset,
Thomas Petazzoni4749c022014-11-21 17:00:04 +0100858 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100859 .win_remap_offset = generic_mbus_win_remap_2_offset,
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100860 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
861 .show_cpu_target = mvebu_sdram_debug_show_orion,
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100862};
863
864static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
865 .num_wins = 14,
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100866 .win_cfg_offset = mv78xx0_mbus_win_cfg_offset,
Thomas Petazzoni4749c022014-11-21 17:00:04 +0100867 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100868 .win_remap_offset = generic_mbus_win_remap_8_offset,
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100869 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
870 .show_cpu_target = mvebu_sdram_debug_show_orion,
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100871};
872
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100873static const struct of_device_id of_mvebu_mbus_ids[] = {
874 { .compatible = "marvell,armada370-mbus",
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100875 .data = &armada_370_mbus_data, },
876 { .compatible = "marvell,armada375-mbus",
877 .data = &armada_xp_mbus_data, },
878 { .compatible = "marvell,armada380-mbus",
879 .data = &armada_xp_mbus_data, },
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100880 { .compatible = "marvell,armadaxp-mbus",
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100881 .data = &armada_xp_mbus_data, },
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100882 { .compatible = "marvell,kirkwood-mbus",
883 .data = &kirkwood_mbus_data, },
884 { .compatible = "marvell,dove-mbus",
885 .data = &dove_mbus_data, },
886 { .compatible = "marvell,orion5x-88f5281-mbus",
887 .data = &orion5x_4win_mbus_data, },
888 { .compatible = "marvell,orion5x-88f5182-mbus",
889 .data = &orion5x_2win_mbus_data, },
890 { .compatible = "marvell,orion5x-88f5181-mbus",
891 .data = &orion5x_2win_mbus_data, },
892 { .compatible = "marvell,orion5x-88f6183-mbus",
893 .data = &orion5x_4win_mbus_data, },
894 { .compatible = "marvell,mv78xx0-mbus",
895 .data = &mv78xx0_mbus_data, },
896 { },
897};
898
899/*
900 * Public API of the driver
901 */
Thomas Petazzoni6a63b092013-07-26 10:17:39 -0300902int mvebu_mbus_add_window_remap_by_id(unsigned int target,
903 unsigned int attribute,
904 phys_addr_t base, size_t size,
905 phys_addr_t remap)
906{
907 struct mvebu_mbus_state *s = &mbus_state;
908
909 if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
910 pr_err("cannot add window '%x:%x', conflicts with another window\n",
911 target, attribute);
912 return -EINVAL;
913 }
914
915 return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
916}
917
Thomas Petazzoni6a63b092013-07-26 10:17:39 -0300918int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
919 phys_addr_t base, size_t size)
920{
921 return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
922 size, MVEBU_MBUS_NO_REMAP);
923}
924
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100925int mvebu_mbus_del_window(phys_addr_t base, size_t size)
926{
927 int win;
928
929 win = mvebu_mbus_find_window(&mbus_state, base, size);
930 if (win < 0)
931 return win;
932
933 mvebu_mbus_disable_window(&mbus_state, win);
934 return 0;
935}
936
Ezequiel Garcia79d94682013-07-26 10:17:47 -0300937void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
938{
939 if (!res)
940 return;
941 *res = mbus_state.pcie_mem_aperture;
942}
943
944void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
945{
946 if (!res)
947 return;
948 *res = mbus_state.pcie_io_aperture;
949}
950
Thomas Petazzonifddddb52013-03-21 17:59:14 +0100951static __init int mvebu_mbus_debugfs_init(void)
952{
953 struct mvebu_mbus_state *s = &mbus_state;
954
955 /*
956 * If no base has been initialized, doesn't make sense to
957 * register the debugfs entries. We may be on a multiplatform
958 * kernel that isn't running a Marvell EBU SoC.
959 */
960 if (!s->mbuswins_base)
961 return 0;
962
963 s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL);
964 if (s->debugfs_root) {
965 s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO,
966 s->debugfs_root, NULL,
967 &mvebu_sdram_debug_fops);
968 s->debugfs_devs = debugfs_create_file("devices", S_IRUGO,
969 s->debugfs_root, NULL,
970 &mvebu_devs_debug_fops);
971 }
972
973 return 0;
974}
975fs_initcall(mvebu_mbus_debugfs_init);
976
Thomas Petazzonia0e89c02014-11-21 17:00:03 +0100977static int mvebu_mbus_suspend(void)
978{
979 struct mvebu_mbus_state *s = &mbus_state;
980 int win;
981
982 if (!s->mbusbridge_base)
983 return -ENODEV;
984
985 for (win = 0; win < s->soc->num_wins; win++) {
986 void __iomem *addr = s->mbuswins_base +
987 s->soc->win_cfg_offset(win);
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100988 void __iomem *addr_rmp;
Thomas Petazzonia0e89c02014-11-21 17:00:03 +0100989
990 s->wins[win].base = readl(addr + WIN_BASE_OFF);
991 s->wins[win].ctrl = readl(addr + WIN_CTRL_OFF);
992
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100993 if (!mvebu_mbus_window_is_remappable(s, win))
Thomas Petazzonia0e89c02014-11-21 17:00:03 +0100994 continue;
995
Michal Mazur7fdf3d82014-12-30 13:43:43 +0100996 addr_rmp = s->mbuswins_base +
997 s->soc->win_remap_offset(win);
998
999 s->wins[win].remap_lo = readl(addr_rmp + WIN_REMAP_LO_OFF);
1000 s->wins[win].remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF);
Thomas Petazzonia0e89c02014-11-21 17:00:03 +01001001 }
1002
1003 s->mbus_bridge_ctrl = readl(s->mbusbridge_base +
1004 MBUS_BRIDGE_CTRL_OFF);
1005 s->mbus_bridge_base = readl(s->mbusbridge_base +
1006 MBUS_BRIDGE_BASE_OFF);
1007
1008 return 0;
1009}
1010
1011static void mvebu_mbus_resume(void)
1012{
1013 struct mvebu_mbus_state *s = &mbus_state;
1014 int win;
1015
1016 writel(s->mbus_bridge_ctrl,
1017 s->mbusbridge_base + MBUS_BRIDGE_CTRL_OFF);
1018 writel(s->mbus_bridge_base,
1019 s->mbusbridge_base + MBUS_BRIDGE_BASE_OFF);
1020
1021 for (win = 0; win < s->soc->num_wins; win++) {
1022 void __iomem *addr = s->mbuswins_base +
1023 s->soc->win_cfg_offset(win);
Michal Mazur7fdf3d82014-12-30 13:43:43 +01001024 void __iomem *addr_rmp;
Thomas Petazzonia0e89c02014-11-21 17:00:03 +01001025
1026 writel(s->wins[win].base, addr + WIN_BASE_OFF);
1027 writel(s->wins[win].ctrl, addr + WIN_CTRL_OFF);
1028
Michal Mazur7fdf3d82014-12-30 13:43:43 +01001029 if (!mvebu_mbus_window_is_remappable(s, win))
Thomas Petazzonia0e89c02014-11-21 17:00:03 +01001030 continue;
1031
Michal Mazur7fdf3d82014-12-30 13:43:43 +01001032 addr_rmp = s->mbuswins_base +
1033 s->soc->win_remap_offset(win);
1034
1035 writel(s->wins[win].remap_lo, addr_rmp + WIN_REMAP_LO_OFF);
1036 writel(s->wins[win].remap_hi, addr_rmp + WIN_REMAP_HI_OFF);
Thomas Petazzonia0e89c02014-11-21 17:00:03 +01001037 }
1038}
1039
1040struct syscore_ops mvebu_mbus_syscore_ops = {
1041 .suspend = mvebu_mbus_suspend,
1042 .resume = mvebu_mbus_resume,
1043};
1044
Ezequiel Garcia6bd6b3c2013-07-26 10:17:44 -03001045static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
1046 phys_addr_t mbuswins_phys_base,
1047 size_t mbuswins_size,
1048 phys_addr_t sdramwins_phys_base,
Thomas Petazzonia0e89c02014-11-21 17:00:03 +01001049 size_t sdramwins_size,
1050 phys_addr_t mbusbridge_phys_base,
Thomas Petazzonia0b5cd42015-01-16 17:11:28 +01001051 size_t mbusbridge_size,
1052 bool is_coherent)
Thomas Petazzonifddddb52013-03-21 17:59:14 +01001053{
Thomas Petazzonifddddb52013-03-21 17:59:14 +01001054 int win;
1055
Thomas Petazzonifddddb52013-03-21 17:59:14 +01001056 mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
1057 if (!mbus->mbuswins_base)
1058 return -ENOMEM;
1059
1060 mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);
1061 if (!mbus->sdramwins_base) {
1062 iounmap(mbus_state.mbuswins_base);
1063 return -ENOMEM;
1064 }
1065
Thomas Petazzoni4749c022014-11-21 17:00:04 +01001066 mbus->sdramwins_phys_base = sdramwins_phys_base;
1067
Thomas Petazzonia0e89c02014-11-21 17:00:03 +01001068 if (mbusbridge_phys_base) {
1069 mbus->mbusbridge_base = ioremap(mbusbridge_phys_base,
1070 mbusbridge_size);
1071 if (!mbus->mbusbridge_base) {
1072 iounmap(mbus->sdramwins_base);
1073 iounmap(mbus->mbuswins_base);
1074 return -ENOMEM;
1075 }
1076 } else
1077 mbus->mbusbridge_base = NULL;
1078
Thomas Petazzonifddddb52013-03-21 17:59:14 +01001079 for (win = 0; win < mbus->soc->num_wins; win++)
1080 mvebu_mbus_disable_window(mbus, win);
1081
1082 mbus->soc->setup_cpu_target(mbus);
Thomas Petazzonibfa1ce52015-05-28 11:40:54 +02001083 mvebu_mbus_setup_cpu_target_nooverlap(mbus);
Thomas Petazzonifddddb52013-03-21 17:59:14 +01001084
Thomas Petazzonia0b5cd42015-01-16 17:11:28 +01001085 if (is_coherent)
1086 writel(UNIT_SYNC_BARRIER_ALL,
1087 mbus->mbuswins_base + UNIT_SYNC_BARRIER_OFF);
1088
Thomas Petazzonia0e89c02014-11-21 17:00:03 +01001089 register_syscore_ops(&mvebu_mbus_syscore_ops);
1090
Thomas Petazzonifddddb52013-03-21 17:59:14 +01001091 return 0;
1092}
Ezequiel Garcia6bd6b3c2013-07-26 10:17:44 -03001093
1094int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
1095 size_t mbuswins_size,
1096 phys_addr_t sdramwins_phys_base,
1097 size_t sdramwins_size)
1098{
1099 const struct of_device_id *of_id;
1100
Dan Carpenter7663cfd2013-11-13 10:50:24 +03001101 for (of_id = of_mvebu_mbus_ids; of_id->compatible[0]; of_id++)
Ezequiel Garcia6bd6b3c2013-07-26 10:17:44 -03001102 if (!strcmp(of_id->compatible, soc))
1103 break;
1104
Dan Carpenter7663cfd2013-11-13 10:50:24 +03001105 if (!of_id->compatible[0]) {
Ezequiel Garcia6bd6b3c2013-07-26 10:17:44 -03001106 pr_err("could not find a matching SoC family\n");
1107 return -ENODEV;
1108 }
1109
1110 mbus_state.soc = of_id->data;
1111
1112 return mvebu_mbus_common_init(&mbus_state,
1113 mbuswins_phys_base,
1114 mbuswins_size,
1115 sdramwins_phys_base,
Thomas Petazzonia0b5cd42015-01-16 17:11:28 +01001116 sdramwins_size, 0, 0, false);
Ezequiel Garcia6bd6b3c2013-07-26 10:17:44 -03001117}
Ezequiel Garcia6839cfa2013-07-26 10:17:45 -03001118
1119#ifdef CONFIG_OF
Ezequiel Garciabb24cab2013-07-26 10:17:46 -03001120/*
1121 * The window IDs in the ranges DT property have the following format:
1122 * - bits 28 to 31: MBus custom field
1123 * - bits 24 to 27: window target ID
1124 * - bits 16 to 23: window attribute ID
1125 * - bits 0 to 15: unused
1126 */
1127#define CUSTOM(id) (((id) & 0xF0000000) >> 24)
1128#define TARGET(id) (((id) & 0x0F000000) >> 24)
1129#define ATTR(id) (((id) & 0x00FF0000) >> 16)
1130
1131static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
1132 u32 base, u32 size,
1133 u8 target, u8 attr)
1134{
Ezequiel Garciabb24cab2013-07-26 10:17:46 -03001135 if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
Thomas Petazzonied843a72013-07-26 10:17:51 -03001136 pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
1137 target, attr);
Ezequiel Garciabb24cab2013-07-26 10:17:46 -03001138 return -EBUSY;
1139 }
1140
1141 if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
1142 target, attr)) {
Thomas Petazzonied843a72013-07-26 10:17:51 -03001143 pr_err("cannot add window '%04x:%04x', too many windows\n",
1144 target, attr);
Ezequiel Garciabb24cab2013-07-26 10:17:46 -03001145 return -ENOMEM;
1146 }
1147 return 0;
1148}
1149
1150static int __init
1151mbus_parse_ranges(struct device_node *node,
1152 int *addr_cells, int *c_addr_cells, int *c_size_cells,
1153 int *cell_count, const __be32 **ranges_start,
1154 const __be32 **ranges_end)
1155{
1156 const __be32 *prop;
1157 int ranges_len, tuple_len;
1158
1159 /* Allow a node with no 'ranges' property */
1160 *ranges_start = of_get_property(node, "ranges", &ranges_len);
1161 if (*ranges_start == NULL) {
1162 *addr_cells = *c_addr_cells = *c_size_cells = *cell_count = 0;
1163 *ranges_start = *ranges_end = NULL;
1164 return 0;
1165 }
1166 *ranges_end = *ranges_start + ranges_len / sizeof(__be32);
1167
1168 *addr_cells = of_n_addr_cells(node);
1169
1170 prop = of_get_property(node, "#address-cells", NULL);
1171 *c_addr_cells = be32_to_cpup(prop);
1172
1173 prop = of_get_property(node, "#size-cells", NULL);
1174 *c_size_cells = be32_to_cpup(prop);
1175
1176 *cell_count = *addr_cells + *c_addr_cells + *c_size_cells;
1177 tuple_len = (*cell_count) * sizeof(__be32);
1178
1179 if (ranges_len % tuple_len) {
1180 pr_warn("malformed ranges entry '%s'\n", node->name);
1181 return -EINVAL;
1182 }
1183 return 0;
1184}
1185
1186static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus,
1187 struct device_node *np)
1188{
1189 int addr_cells, c_addr_cells, c_size_cells;
1190 int i, ret, cell_count;
1191 const __be32 *r, *ranges_start, *ranges_end;
1192
1193 ret = mbus_parse_ranges(np, &addr_cells, &c_addr_cells,
1194 &c_size_cells, &cell_count,
1195 &ranges_start, &ranges_end);
1196 if (ret < 0)
1197 return ret;
1198
1199 for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) {
1200 u32 windowid, base, size;
1201 u8 target, attr;
1202
1203 /*
1204 * An entry with a non-zero custom field do not
1205 * correspond to a static window, so skip it.
1206 */
1207 windowid = of_read_number(r, 1);
1208 if (CUSTOM(windowid))
1209 continue;
1210
1211 target = TARGET(windowid);
1212 attr = ATTR(windowid);
1213
1214 base = of_read_number(r + c_addr_cells, addr_cells);
1215 size = of_read_number(r + c_addr_cells + addr_cells,
1216 c_size_cells);
1217 ret = mbus_dt_setup_win(mbus, base, size, target, attr);
1218 if (ret < 0)
1219 return ret;
1220 }
1221 return 0;
1222}
1223
Ezequiel Garcia79d94682013-07-26 10:17:47 -03001224static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
1225 struct resource *mem,
1226 struct resource *io)
1227{
1228 u32 reg[2];
1229 int ret;
1230
1231 /*
Jason Gunthorpe8553bca2013-09-17 14:11:04 -06001232 * These are optional, so we make sure that resource_size(x) will
1233 * return 0.
Ezequiel Garcia79d94682013-07-26 10:17:47 -03001234 */
1235 memset(mem, 0, sizeof(struct resource));
Jason Gunthorpe8553bca2013-09-17 14:11:04 -06001236 mem->end = -1;
Ezequiel Garcia79d94682013-07-26 10:17:47 -03001237 memset(io, 0, sizeof(struct resource));
Jason Gunthorpe8553bca2013-09-17 14:11:04 -06001238 io->end = -1;
Ezequiel Garcia79d94682013-07-26 10:17:47 -03001239
1240 ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
1241 if (!ret) {
1242 mem->start = reg[0];
Jason Gunthorpea723e752014-02-12 15:57:07 -07001243 mem->end = mem->start + reg[1] - 1;
Ezequiel Garcia79d94682013-07-26 10:17:47 -03001244 mem->flags = IORESOURCE_MEM;
1245 }
1246
1247 ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));
1248 if (!ret) {
1249 io->start = reg[0];
Jason Gunthorpea723e752014-02-12 15:57:07 -07001250 io->end = io->start + reg[1] - 1;
Ezequiel Garcia79d94682013-07-26 10:17:47 -03001251 io->flags = IORESOURCE_IO;
1252 }
1253}
1254
Thomas Petazzoni5686a1e2014-04-14 15:47:01 +02001255int __init mvebu_mbus_dt_init(bool is_coherent)
Ezequiel Garcia6839cfa2013-07-26 10:17:45 -03001256{
Thomas Petazzonia0e89c02014-11-21 17:00:03 +01001257 struct resource mbuswins_res, sdramwins_res, mbusbridge_res;
Ezequiel Garcia6839cfa2013-07-26 10:17:45 -03001258 struct device_node *np, *controller;
1259 const struct of_device_id *of_id;
1260 const __be32 *prop;
1261 int ret;
1262
Josh Cartwright087a4ab2014-02-11 10:24:00 -06001263 np = of_find_matching_node_and_match(NULL, of_mvebu_mbus_ids, &of_id);
Ezequiel Garcia6839cfa2013-07-26 10:17:45 -03001264 if (!np) {
1265 pr_err("could not find a matching SoC family\n");
1266 return -ENODEV;
1267 }
1268
Ezequiel Garcia6839cfa2013-07-26 10:17:45 -03001269 mbus_state.soc = of_id->data;
1270
1271 prop = of_get_property(np, "controller", NULL);
1272 if (!prop) {
1273 pr_err("required 'controller' property missing\n");
1274 return -EINVAL;
1275 }
1276
1277 controller = of_find_node_by_phandle(be32_to_cpup(prop));
1278 if (!controller) {
1279 pr_err("could not find an 'mbus-controller' node\n");
1280 return -ENODEV;
1281 }
1282
1283 if (of_address_to_resource(controller, 0, &mbuswins_res)) {
1284 pr_err("cannot get MBUS register address\n");
1285 return -EINVAL;
1286 }
1287
1288 if (of_address_to_resource(controller, 1, &sdramwins_res)) {
1289 pr_err("cannot get SDRAM register address\n");
1290 return -EINVAL;
1291 }
1292
Thomas Petazzonia0e89c02014-11-21 17:00:03 +01001293 /*
1294 * Set the resource to 0 so that it can be left unmapped by
1295 * mvebu_mbus_common_init() if the DT doesn't carry the
1296 * necessary information. This is needed to preserve backward
1297 * compatibility.
1298 */
1299 memset(&mbusbridge_res, 0, sizeof(mbusbridge_res));
1300
1301 if (mbus_state.soc->has_mbus_bridge) {
1302 if (of_address_to_resource(controller, 2, &mbusbridge_res))
1303 pr_warn(FW_WARN "deprecated mbus-mvebu Device Tree, suspend/resume will not work\n");
1304 }
1305
Thomas Petazzoni5686a1e2014-04-14 15:47:01 +02001306 mbus_state.hw_io_coherency = is_coherent;
1307
Ezequiel Garcia79d94682013-07-26 10:17:47 -03001308 /* Get optional pcie-{mem,io}-aperture properties */
1309 mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
1310 &mbus_state.pcie_io_aperture);
1311
Ezequiel Garcia6839cfa2013-07-26 10:17:45 -03001312 ret = mvebu_mbus_common_init(&mbus_state,
1313 mbuswins_res.start,
1314 resource_size(&mbuswins_res),
1315 sdramwins_res.start,
Thomas Petazzonia0e89c02014-11-21 17:00:03 +01001316 resource_size(&sdramwins_res),
1317 mbusbridge_res.start,
Thomas Petazzonia0b5cd42015-01-16 17:11:28 +01001318 resource_size(&mbusbridge_res),
1319 is_coherent);
Ezequiel Garciabb24cab2013-07-26 10:17:46 -03001320 if (ret)
1321 return ret;
1322
1323 /* Setup statically declared windows in the DT */
1324 return mbus_dt_setup(&mbus_state, np);
Ezequiel Garcia6839cfa2013-07-26 10:17:45 -03001325}
1326#endif