Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. |
| 3 | * Copyright (c) 2013 Linaro Ltd. |
| 4 | * Author: Thomas Abraham <thomas.ab@samsung.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * Common Clock Framework support for Exynos5250 SoC. |
| 11 | */ |
| 12 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 13 | #include <dt-bindings/clock/exynos5250.h> |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 14 | #include <linux/clk.h> |
| 15 | #include <linux/clkdev.h> |
| 16 | #include <linux/clk-provider.h> |
| 17 | #include <linux/of.h> |
| 18 | #include <linux/of_address.h> |
Tomasz Figa | c3b6c1d | 2014-02-14 08:16:00 +0900 | [diff] [blame] | 19 | #include <linux/syscore_ops.h> |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 20 | |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 21 | #include "clk.h" |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 22 | |
Yadwinder Singh Brar | 8dac353 | 2013-06-11 15:01:08 +0530 | [diff] [blame] | 23 | #define APLL_LOCK 0x0 |
| 24 | #define APLL_CON0 0x100 |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 25 | #define SRC_CPU 0x200 |
| 26 | #define DIV_CPU0 0x500 |
Yadwinder Singh Brar | 8dac353 | 2013-06-11 15:01:08 +0530 | [diff] [blame] | 27 | #define MPLL_LOCK 0x4000 |
| 28 | #define MPLL_CON0 0x4100 |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 29 | #define SRC_CORE1 0x4204 |
Abhilash Kesavan | 3bf3466 | 2013-12-12 08:32:00 +0530 | [diff] [blame] | 30 | #define GATE_IP_ACP 0x8800 |
Yadwinder Singh Brar | 8dac353 | 2013-06-11 15:01:08 +0530 | [diff] [blame] | 31 | #define CPLL_LOCK 0x10020 |
| 32 | #define EPLL_LOCK 0x10030 |
| 33 | #define VPLL_LOCK 0x10040 |
| 34 | #define GPLL_LOCK 0x10050 |
| 35 | #define CPLL_CON0 0x10120 |
| 36 | #define EPLL_CON0 0x10130 |
| 37 | #define VPLL_CON0 0x10140 |
| 38 | #define GPLL_CON0 0x10150 |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 39 | #define SRC_TOP0 0x10210 |
| 40 | #define SRC_TOP2 0x10218 |
Tomasz Figa | 796d1f4 | 2013-10-15 19:41:17 +0200 | [diff] [blame] | 41 | #define SRC_TOP3 0x1021c |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 42 | #define SRC_GSCL 0x10220 |
| 43 | #define SRC_DISP1_0 0x1022c |
| 44 | #define SRC_MAU 0x10240 |
| 45 | #define SRC_FSYS 0x10244 |
| 46 | #define SRC_GEN 0x10248 |
| 47 | #define SRC_PERIC0 0x10250 |
| 48 | #define SRC_PERIC1 0x10254 |
| 49 | #define SRC_MASK_GSCL 0x10320 |
| 50 | #define SRC_MASK_DISP1_0 0x1032c |
| 51 | #define SRC_MASK_MAU 0x10334 |
| 52 | #define SRC_MASK_FSYS 0x10340 |
| 53 | #define SRC_MASK_GEN 0x10344 |
| 54 | #define SRC_MASK_PERIC0 0x10350 |
| 55 | #define SRC_MASK_PERIC1 0x10354 |
| 56 | #define DIV_TOP0 0x10510 |
| 57 | #define DIV_TOP1 0x10514 |
| 58 | #define DIV_GSCL 0x10520 |
| 59 | #define DIV_DISP1_0 0x1052c |
| 60 | #define DIV_GEN 0x1053c |
| 61 | #define DIV_MAU 0x10544 |
| 62 | #define DIV_FSYS0 0x10548 |
| 63 | #define DIV_FSYS1 0x1054c |
| 64 | #define DIV_FSYS2 0x10550 |
| 65 | #define DIV_PERIC0 0x10558 |
| 66 | #define DIV_PERIC1 0x1055c |
| 67 | #define DIV_PERIC2 0x10560 |
| 68 | #define DIV_PERIC3 0x10564 |
| 69 | #define DIV_PERIC4 0x10568 |
| 70 | #define DIV_PERIC5 0x1056c |
| 71 | #define GATE_IP_GSCL 0x10920 |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 72 | #define GATE_IP_DISP1 0x10928 |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 73 | #define GATE_IP_MFC 0x1092c |
| 74 | #define GATE_IP_GEN 0x10934 |
| 75 | #define GATE_IP_FSYS 0x10944 |
| 76 | #define GATE_IP_PERIC 0x10950 |
| 77 | #define GATE_IP_PERIS 0x10960 |
Yadwinder Singh Brar | 8dac353 | 2013-06-11 15:01:08 +0530 | [diff] [blame] | 78 | #define BPLL_LOCK 0x20010 |
| 79 | #define BPLL_CON0 0x20110 |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 80 | #define SRC_CDREX 0x20200 |
| 81 | #define PLL_DIV2_SEL 0x20a24 |
| 82 | |
Yadwinder Singh Brar | 8dac353 | 2013-06-11 15:01:08 +0530 | [diff] [blame] | 83 | /* list of PLLs to be registered */ |
| 84 | enum exynos5250_plls { |
| 85 | apll, mpll, cpll, epll, vpll, gpll, bpll, |
| 86 | nr_plls /* number of PLLs */ |
| 87 | }; |
| 88 | |
Tomasz Figa | c3b6c1d | 2014-02-14 08:16:00 +0900 | [diff] [blame] | 89 | static void __iomem *reg_base; |
| 90 | |
| 91 | #ifdef CONFIG_PM_SLEEP |
| 92 | static struct samsung_clk_reg_dump *exynos5250_save; |
| 93 | |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 94 | /* |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 95 | * list of controller registers to be saved and restored during a |
| 96 | * suspend/resume cycle. |
| 97 | */ |
Sachin Kamat | b6993ec | 2013-08-07 10:18:38 +0530 | [diff] [blame] | 98 | static unsigned long exynos5250_clk_regs[] __initdata = { |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 99 | SRC_CPU, |
| 100 | DIV_CPU0, |
| 101 | SRC_CORE1, |
| 102 | SRC_TOP0, |
| 103 | SRC_TOP2, |
Tomasz Figa | 796d1f4 | 2013-10-15 19:41:17 +0200 | [diff] [blame] | 104 | SRC_TOP3, |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 105 | SRC_GSCL, |
| 106 | SRC_DISP1_0, |
| 107 | SRC_MAU, |
| 108 | SRC_FSYS, |
| 109 | SRC_GEN, |
| 110 | SRC_PERIC0, |
| 111 | SRC_PERIC1, |
| 112 | SRC_MASK_GSCL, |
| 113 | SRC_MASK_DISP1_0, |
| 114 | SRC_MASK_MAU, |
| 115 | SRC_MASK_FSYS, |
| 116 | SRC_MASK_GEN, |
| 117 | SRC_MASK_PERIC0, |
| 118 | SRC_MASK_PERIC1, |
| 119 | DIV_TOP0, |
| 120 | DIV_TOP1, |
| 121 | DIV_GSCL, |
| 122 | DIV_DISP1_0, |
| 123 | DIV_GEN, |
| 124 | DIV_MAU, |
| 125 | DIV_FSYS0, |
| 126 | DIV_FSYS1, |
| 127 | DIV_FSYS2, |
| 128 | DIV_PERIC0, |
| 129 | DIV_PERIC1, |
| 130 | DIV_PERIC2, |
| 131 | DIV_PERIC3, |
| 132 | DIV_PERIC4, |
| 133 | DIV_PERIC5, |
| 134 | GATE_IP_GSCL, |
| 135 | GATE_IP_MFC, |
| 136 | GATE_IP_GEN, |
| 137 | GATE_IP_FSYS, |
| 138 | GATE_IP_PERIC, |
| 139 | GATE_IP_PERIS, |
| 140 | SRC_CDREX, |
| 141 | PLL_DIV2_SEL, |
Leela Krishna Amudala | 17d4cac | 2013-04-04 15:44:40 +0900 | [diff] [blame] | 142 | GATE_IP_DISP1, |
Sachin Kamat | 406c598 | 2013-07-05 14:12:27 +0530 | [diff] [blame] | 143 | GATE_IP_ACP, |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 144 | }; |
| 145 | |
Tomasz Figa | c3b6c1d | 2014-02-14 08:16:00 +0900 | [diff] [blame] | 146 | static int exynos5250_clk_suspend(void) |
| 147 | { |
| 148 | samsung_clk_save(reg_base, exynos5250_save, |
| 149 | ARRAY_SIZE(exynos5250_clk_regs)); |
| 150 | |
| 151 | return 0; |
| 152 | } |
| 153 | |
| 154 | static void exynos5250_clk_resume(void) |
| 155 | { |
| 156 | samsung_clk_restore(reg_base, exynos5250_save, |
| 157 | ARRAY_SIZE(exynos5250_clk_regs)); |
| 158 | } |
| 159 | |
| 160 | static struct syscore_ops exynos5250_clk_syscore_ops = { |
| 161 | .suspend = exynos5250_clk_suspend, |
| 162 | .resume = exynos5250_clk_resume, |
| 163 | }; |
| 164 | |
| 165 | static void exynos5250_clk_sleep_init(void) |
| 166 | { |
| 167 | exynos5250_save = samsung_clk_alloc_reg_dump(exynos5250_clk_regs, |
| 168 | ARRAY_SIZE(exynos5250_clk_regs)); |
| 169 | if (!exynos5250_save) { |
| 170 | pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", |
| 171 | __func__); |
| 172 | return; |
| 173 | } |
| 174 | |
| 175 | register_syscore_ops(&exynos5250_clk_syscore_ops); |
| 176 | } |
| 177 | #else |
| 178 | static void exynos5250_clk_sleep_init(void) {} |
| 179 | #endif |
| 180 | |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 181 | /* list of all parent clock list */ |
| 182 | PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; |
Tomasz Figa | 38ee375 | 2013-10-15 19:41:16 +0200 | [diff] [blame] | 183 | PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", }; |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 184 | PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" }; |
| 185 | PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" }; |
| 186 | PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" }; |
| 187 | PNAME(mout_bpll_p) = { "fin_pll", "mout_bpll_fout" }; |
| 188 | PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" }; |
| 189 | PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" }; |
| 190 | PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" }; |
| 191 | PNAME(mout_epll_p) = { "fin_pll", "fout_epll" }; |
Tomasz Figa | 38ee375 | 2013-10-15 19:41:16 +0200 | [diff] [blame] | 192 | PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" }; |
| 193 | PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" }; |
| 194 | PNAME(mout_aclk166_p) = { "mout_cpll", "mout_mpll_user" }; |
| 195 | PNAME(mout_aclk200_p) = { "mout_mpll_user", "mout_bpll_user" }; |
Tomasz Figa | 3818f11 | 2013-10-15 19:41:18 +0200 | [diff] [blame] | 196 | PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" }; |
Tomasz Figa | 796d1f4 | 2013-10-15 19:41:17 +0200 | [diff] [blame] | 197 | PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" }; |
Tomasz Figa | 96987de | 2013-10-15 19:41:21 +0200 | [diff] [blame] | 198 | PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" }; |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 199 | PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" }; |
Tomasz Figa | 38ee375 | 2013-10-15 19:41:16 +0200 | [diff] [blame] | 200 | PNAME(mout_usb3_p) = { "mout_mpll_user", "mout_cpll" }; |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 201 | PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m", |
| 202 | "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy", |
Tomasz Figa | 38ee375 | 2013-10-15 19:41:16 +0200 | [diff] [blame] | 203 | "mout_mpll_user", "mout_epll", "mout_vpll", |
Tomasz Figa | 256dd64 | 2013-10-15 19:41:19 +0200 | [diff] [blame] | 204 | "mout_cpll", "none", "none", |
| 205 | "none", "none", "none", |
| 206 | "none" }; |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 207 | PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", |
Tomasz Figa | bfeb9f2 | 2013-10-15 19:41:20 +0200 | [diff] [blame] | 208 | "sclk_uhostphy", "fin_pll", |
Tomasz Figa | 38ee375 | 2013-10-15 19:41:16 +0200 | [diff] [blame] | 209 | "mout_mpll_user", "mout_epll", "mout_vpll", |
Tomasz Figa | 256dd64 | 2013-10-15 19:41:19 +0200 | [diff] [blame] | 210 | "mout_cpll", "none", "none", |
| 211 | "none", "none", "none", |
| 212 | "none" }; |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 213 | PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", |
Tomasz Figa | bfeb9f2 | 2013-10-15 19:41:20 +0200 | [diff] [blame] | 214 | "sclk_uhostphy", "fin_pll", |
Tomasz Figa | 38ee375 | 2013-10-15 19:41:16 +0200 | [diff] [blame] | 215 | "mout_mpll_user", "mout_epll", "mout_vpll", |
Tomasz Figa | 256dd64 | 2013-10-15 19:41:19 +0200 | [diff] [blame] | 216 | "mout_cpll", "none", "none", |
| 217 | "none", "none", "none", |
| 218 | "none" }; |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 219 | PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", |
Tomasz Figa | bfeb9f2 | 2013-10-15 19:41:20 +0200 | [diff] [blame] | 220 | "sclk_uhostphy", "fin_pll", |
Tomasz Figa | 38ee375 | 2013-10-15 19:41:16 +0200 | [diff] [blame] | 221 | "mout_mpll_user", "mout_epll", "mout_vpll", |
Tomasz Figa | 256dd64 | 2013-10-15 19:41:19 +0200 | [diff] [blame] | 222 | "mout_cpll", "none", "none", |
| 223 | "none", "none", "none", |
| 224 | "none" }; |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 225 | PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2", |
| 226 | "spdif_extclk" }; |
| 227 | |
| 228 | /* fixed rate clocks generated outside the soc */ |
Sachin Kamat | b95e71c | 2013-07-18 15:31:19 +0530 | [diff] [blame] | 229 | static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = { |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 230 | FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0), |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 231 | }; |
| 232 | |
| 233 | /* fixed rate clocks generated inside the soc */ |
Sachin Kamat | b95e71c | 2013-07-18 15:31:19 +0530 | [diff] [blame] | 234 | static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = { |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 235 | FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), |
| 236 | FRATE(0, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000), |
| 237 | FRATE(0, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000), |
| 238 | FRATE(0, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000), |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 239 | }; |
| 240 | |
Sachin Kamat | b95e71c | 2013-07-18 15:31:19 +0530 | [diff] [blame] | 241 | static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = { |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 242 | FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0), |
| 243 | FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0), |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 244 | }; |
| 245 | |
Vikas Sajjan | 8bc2eeb | 2013-06-11 15:01:15 +0530 | [diff] [blame] | 246 | static struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = { |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 247 | MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1), |
Vikas Sajjan | 8bc2eeb | 2013-06-11 15:01:15 +0530 | [diff] [blame] | 248 | }; |
| 249 | |
Sachin Kamat | b95e71c | 2013-07-18 15:31:19 +0530 | [diff] [blame] | 250 | static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 251 | /* |
| 252 | * NOTE: Following table is sorted by (clock domain, register address, |
| 253 | * bitfield shift) triplet in ascending order. When adding new entries, |
| 254 | * please make sure that the order is kept, to avoid merge conflicts |
| 255 | * and make further work with defined data easier. |
| 256 | */ |
| 257 | |
| 258 | /* |
| 259 | * CMU_CPU |
| 260 | */ |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 261 | MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, |
Sachin Kamat | e86ffc4 | 2013-12-19 14:03:39 +0530 | [diff] [blame] | 262 | CLK_SET_RATE_PARENT, 0, "mout_apll"), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 263 | MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 264 | |
| 265 | /* |
| 266 | * CMU_CORE |
| 267 | */ |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 268 | MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 269 | |
| 270 | /* |
| 271 | * CMU_TOP |
| 272 | */ |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 273 | MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1), |
| 274 | MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1), |
| 275 | MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 276 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 277 | MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1), |
| 278 | MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1), |
| 279 | MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1), |
| 280 | MUX(0, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1), |
| 281 | MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 282 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 283 | MUX(0, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1), |
| 284 | MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1), |
| 285 | MUX(0, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1), |
Tomasz Figa | 796d1f4 | 2013-10-15 19:41:17 +0200 | [diff] [blame] | 286 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 287 | MUX(0, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4), |
| 288 | MUX(0, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4), |
| 289 | MUX(0, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4), |
| 290 | MUX(0, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4), |
| 291 | MUX(0, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 292 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 293 | MUX(0, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4), |
| 294 | MUX(0, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4), |
| 295 | MUX(0, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4), |
| 296 | MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 297 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 298 | MUX(0, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 299 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 300 | MUX(0, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4), |
| 301 | MUX(0, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4), |
| 302 | MUX(0, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4), |
| 303 | MUX(0, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4), |
| 304 | MUX(0, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1), |
| 305 | MUX(0, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 306 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 307 | MUX(0, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 308 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 309 | MUX(0, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4), |
| 310 | MUX(0, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4), |
| 311 | MUX(0, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4), |
| 312 | MUX(0, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4), |
| 313 | MUX(0, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 314 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 315 | MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4), |
| 316 | MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4), |
| 317 | MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2), |
| 318 | MUX(0, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4), |
| 319 | MUX(0, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4), |
| 320 | MUX(0, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 321 | |
| 322 | /* |
| 323 | * CMU_CDREX |
| 324 | */ |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 325 | MUX(0, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 326 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 327 | MUX(0, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1), |
| 328 | MUX(0, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1), |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 329 | }; |
| 330 | |
Sachin Kamat | b95e71c | 2013-07-18 15:31:19 +0530 | [diff] [blame] | 331 | static struct samsung_div_clock exynos5250_div_clks[] __initdata = { |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 332 | /* |
| 333 | * NOTE: Following table is sorted by (clock domain, register address, |
| 334 | * bitfield shift) triplet in ascending order. When adding new entries, |
| 335 | * please make sure that the order is kept, to avoid merge conflicts |
| 336 | * and make further work with defined data easier. |
| 337 | */ |
| 338 | |
| 339 | /* |
| 340 | * CMU_CPU |
| 341 | */ |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 342 | DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), |
| 343 | DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3), |
| 344 | DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 345 | |
| 346 | /* |
| 347 | * CMU_TOP |
| 348 | */ |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 349 | DIV(0, "div_aclk66", "div_aclk66_pre", DIV_TOP0, 0, 3), |
| 350 | DIV(0, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3), |
| 351 | DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3), |
| 352 | DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3), |
| 353 | DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 354 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 355 | DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 356 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 357 | DIV(0, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4), |
| 358 | DIV(0, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4), |
| 359 | DIV(0, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4), |
| 360 | DIV(0, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4), |
| 361 | DIV(0, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 362 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 363 | DIV(0, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4), |
| 364 | DIV(0, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4), |
| 365 | DIV_F(0, "div_mipi1_pre", "div_mipi1", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 366 | DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 367 | DIV(0, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4), |
| 368 | DIV(CLK_SCLK_PIXEL, "div_hdmi_pixel", "mout_vpll", DIV_DISP1_0, 28, 4), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 369 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 370 | DIV(0, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 371 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 372 | DIV(0, "div_audio0", "mout_audio0", DIV_MAU, 0, 4), |
Andrew Bresticker | 35399dd | 2013-09-25 14:12:49 -0700 | [diff] [blame] | 373 | DIV(CLK_DIV_PCM0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 374 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 375 | DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), |
| 376 | DIV(0, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 377 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 378 | DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), |
| 379 | DIV_F(0, "div_mmc_pre0", "div_mmc0", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 380 | DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 381 | DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), |
| 382 | DIV_F(0, "div_mmc_pre1", "div_mmc1", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 383 | DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0), |
| 384 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 385 | DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), |
| 386 | DIV_F(0, "div_mmc_pre2", "div_mmc2", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 387 | DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 388 | DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), |
| 389 | DIV_F(0, "div_mmc_pre3", "div_mmc3", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 390 | DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0), |
| 391 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 392 | DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4), |
| 393 | DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4), |
| 394 | DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4), |
| 395 | DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 396 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 397 | DIV(0, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4), |
| 398 | DIV_F(0, "div_spi_pre0", "div_spi0", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 399 | DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 400 | DIV(0, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4), |
| 401 | DIV_F(0, "div_spi_pre1", "div_spi1", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 402 | DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0), |
| 403 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 404 | DIV(0, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4), |
| 405 | DIV_F(0, "div_spi_pre2", "div_spi2", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 406 | DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0), |
| 407 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 408 | DIV(0, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 409 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 410 | DIV(0, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4), |
| 411 | DIV(0, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8), |
| 412 | DIV(0, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4), |
| 413 | DIV(0, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 414 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 415 | DIV(CLK_DIV_I2S1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6), |
| 416 | DIV(CLK_DIV_I2S2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6), |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 417 | }; |
| 418 | |
Sachin Kamat | b95e71c | 2013-07-18 15:31:19 +0530 | [diff] [blame] | 419 | static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 420 | /* |
| 421 | * NOTE: Following table is sorted by (clock domain, register address, |
| 422 | * bitfield shift) triplet in ascending order. When adding new entries, |
| 423 | * please make sure that the order is kept, to avoid merge conflicts |
| 424 | * and make further work with defined data easier. |
| 425 | */ |
| 426 | |
| 427 | /* |
| 428 | * CMU_ACP |
| 429 | */ |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 430 | GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0), |
| 431 | GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0), |
| 432 | GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 433 | |
| 434 | /* |
| 435 | * CMU_TOP |
| 436 | */ |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 437 | GATE(CLK_SCLK_CAM_BAYER, "sclk_cam_bayer", "div_cam_bayer", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 438 | SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 439 | GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 440 | SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 441 | GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 442 | SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 443 | GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "div_gscl_wa", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 444 | SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 445 | GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "div_gscl_wb", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 446 | SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0), |
| 447 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 448 | GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 449 | SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 450 | GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi1", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 451 | SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 452 | GATE(CLK_SCLK_DP, "sclk_dp", "div_dp", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 453 | SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 454 | GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 455 | SRC_MASK_DISP1_0, 20, 0, 0), |
| 456 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 457 | GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 458 | SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0), |
| 459 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 460 | GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 461 | SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 462 | GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 463 | SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 464 | GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 465 | SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 466 | GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 467 | SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 468 | GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 469 | SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 470 | GATE(CLK_SCLK_USB3, "sclk_usb3", "div_usb3", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 471 | SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0), |
| 472 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 473 | GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 474 | SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0), |
| 475 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 476 | GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 477 | SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 478 | GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 479 | SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 480 | GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 481 | SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 482 | GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 483 | SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 484 | GATE(CLK_SCLK_PWM, "sclk_pwm", "div_pwm", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 485 | SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0), |
| 486 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 487 | GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 488 | SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 489 | GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 490 | SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 491 | GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 492 | SRC_MASK_PERIC1, 4, 0, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 493 | GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 494 | SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 495 | GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 496 | SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 497 | GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 498 | SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0), |
| 499 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 500 | GATE(CLK_GSCL0, "gscl0", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 0, 0, |
| 501 | 0), |
| 502 | GATE(CLK_GSCL1, "gscl1", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 1, 0, |
| 503 | 0), |
| 504 | GATE(CLK_GSCL2, "gscl2", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 2, 0, |
| 505 | 0), |
| 506 | GATE(CLK_GSCL3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0, |
| 507 | 0), |
| 508 | GATE(CLK_GSCL_WA, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0), |
| 509 | GATE(CLK_GSCL_WB, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0), |
| 510 | GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "mout_aclk266_gscl_sub", |
Tomasz Figa | 796d1f4 | 2013-10-15 19:41:17 +0200 | [diff] [blame] | 511 | GATE_IP_GSCL, 7, 0, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 512 | GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "mout_aclk266_gscl_sub", |
Tomasz Figa | 796d1f4 | 2013-10-15 19:41:17 +0200 | [diff] [blame] | 513 | GATE_IP_GSCL, 8, 0, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 514 | GATE(CLK_SMMU_GSCL2, "smmu_gscl2", "mout_aclk266_gscl_sub", |
Tomasz Figa | 796d1f4 | 2013-10-15 19:41:17 +0200 | [diff] [blame] | 515 | GATE_IP_GSCL, 9, 0, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 516 | GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub", |
Tomasz Figa | 796d1f4 | 2013-10-15 19:41:17 +0200 | [diff] [blame] | 517 | GATE_IP_GSCL, 10, 0, 0), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 518 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 519 | GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0, |
| 520 | 0), |
| 521 | GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0, |
| 522 | 0), |
| 523 | GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0, |
| 524 | 0), |
| 525 | GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0), |
| 526 | GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0, |
| 527 | 0), |
| 528 | GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0, |
| 529 | 0), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 530 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 531 | GATE(CLK_MFC, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0), |
| 532 | GATE(CLK_SMMU_MFCR, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0, |
| 533 | 0), |
| 534 | GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0, |
| 535 | 0), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 536 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 537 | GATE(CLK_ROTATOR, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0), |
| 538 | GATE(CLK_JPEG, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0), |
| 539 | GATE(CLK_MDMA1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0), |
| 540 | GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "div_aclk266", GATE_IP_GEN, 6, 0, |
| 541 | 0), |
| 542 | GATE(CLK_SMMU_JPEG, "smmu_jpeg", "div_aclk166", GATE_IP_GEN, 7, 0, 0), |
| 543 | GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "div_aclk266", GATE_IP_GEN, 9, 0, 0), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 544 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 545 | GATE(CLK_PDMA0, "pdma0", "div_aclk200", GATE_IP_FSYS, 1, 0, 0), |
| 546 | GATE(CLK_PDMA1, "pdma1", "div_aclk200", GATE_IP_FSYS, 2, 0, 0), |
| 547 | GATE(CLK_SATA, "sata", "div_aclk200", GATE_IP_FSYS, 6, 0, 0), |
| 548 | GATE(CLK_USBOTG, "usbotg", "div_aclk200", GATE_IP_FSYS, 7, 0, 0), |
| 549 | GATE(CLK_MIPI_HSI, "mipi_hsi", "div_aclk200", GATE_IP_FSYS, 8, 0, 0), |
| 550 | GATE(CLK_SDMMC0, "sdmmc0", "div_aclk200", GATE_IP_FSYS, 12, 0, 0), |
| 551 | GATE(CLK_SDMMC1, "sdmmc1", "div_aclk200", GATE_IP_FSYS, 13, 0, 0), |
| 552 | GATE(CLK_SDMMC2, "sdmmc2", "div_aclk200", GATE_IP_FSYS, 14, 0, 0), |
| 553 | GATE(CLK_SDMMC3, "sdmmc3", "div_aclk200", GATE_IP_FSYS, 15, 0, 0), |
| 554 | GATE(CLK_SROMC, "sromc", "div_aclk200", GATE_IP_FSYS, 17, 0, 0), |
| 555 | GATE(CLK_USB2, "usb2", "div_aclk200", GATE_IP_FSYS, 18, 0, 0), |
| 556 | GATE(CLK_USB3, "usb3", "div_aclk200", GATE_IP_FSYS, 19, 0, 0), |
| 557 | GATE(CLK_SATA_PHYCTRL, "sata_phyctrl", "div_aclk200", |
Tomasz Figa | 38ee375 | 2013-10-15 19:41:16 +0200 | [diff] [blame] | 558 | GATE_IP_FSYS, 24, 0, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 559 | GATE(CLK_SATA_PHYI2C, "sata_phyi2c", "div_aclk200", GATE_IP_FSYS, 25, 0, |
| 560 | 0), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 561 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 562 | GATE(CLK_UART0, "uart0", "div_aclk66", GATE_IP_PERIC, 0, 0, 0), |
| 563 | GATE(CLK_UART1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0), |
| 564 | GATE(CLK_UART2, "uart2", "div_aclk66", GATE_IP_PERIC, 2, 0, 0), |
| 565 | GATE(CLK_UART3, "uart3", "div_aclk66", GATE_IP_PERIC, 3, 0, 0), |
| 566 | GATE(CLK_UART4, "uart4", "div_aclk66", GATE_IP_PERIC, 4, 0, 0), |
| 567 | GATE(CLK_I2C0, "i2c0", "div_aclk66", GATE_IP_PERIC, 6, 0, 0), |
| 568 | GATE(CLK_I2C1, "i2c1", "div_aclk66", GATE_IP_PERIC, 7, 0, 0), |
| 569 | GATE(CLK_I2C2, "i2c2", "div_aclk66", GATE_IP_PERIC, 8, 0, 0), |
| 570 | GATE(CLK_I2C3, "i2c3", "div_aclk66", GATE_IP_PERIC, 9, 0, 0), |
| 571 | GATE(CLK_I2C4, "i2c4", "div_aclk66", GATE_IP_PERIC, 10, 0, 0), |
| 572 | GATE(CLK_I2C5, "i2c5", "div_aclk66", GATE_IP_PERIC, 11, 0, 0), |
| 573 | GATE(CLK_I2C6, "i2c6", "div_aclk66", GATE_IP_PERIC, 12, 0, 0), |
| 574 | GATE(CLK_I2C7, "i2c7", "div_aclk66", GATE_IP_PERIC, 13, 0, 0), |
| 575 | GATE(CLK_I2C_HDMI, "i2c_hdmi", "div_aclk66", GATE_IP_PERIC, 14, 0, 0), |
| 576 | GATE(CLK_ADC, "adc", "div_aclk66", GATE_IP_PERIC, 15, 0, 0), |
| 577 | GATE(CLK_SPI0, "spi0", "div_aclk66", GATE_IP_PERIC, 16, 0, 0), |
| 578 | GATE(CLK_SPI1, "spi1", "div_aclk66", GATE_IP_PERIC, 17, 0, 0), |
| 579 | GATE(CLK_SPI2, "spi2", "div_aclk66", GATE_IP_PERIC, 18, 0, 0), |
| 580 | GATE(CLK_I2S1, "i2s1", "div_aclk66", GATE_IP_PERIC, 20, 0, 0), |
| 581 | GATE(CLK_I2S2, "i2s2", "div_aclk66", GATE_IP_PERIC, 21, 0, 0), |
| 582 | GATE(CLK_PCM1, "pcm1", "div_aclk66", GATE_IP_PERIC, 22, 0, 0), |
| 583 | GATE(CLK_PCM2, "pcm2", "div_aclk66", GATE_IP_PERIC, 23, 0, 0), |
| 584 | GATE(CLK_PWM, "pwm", "div_aclk66", GATE_IP_PERIC, 24, 0, 0), |
| 585 | GATE(CLK_SPDIF, "spdif", "div_aclk66", GATE_IP_PERIC, 26, 0, 0), |
| 586 | GATE(CLK_AC97, "ac97", "div_aclk66", GATE_IP_PERIC, 27, 0, 0), |
| 587 | GATE(CLK_HSI2C0, "hsi2c0", "div_aclk66", GATE_IP_PERIC, 28, 0, 0), |
| 588 | GATE(CLK_HSI2C1, "hsi2c1", "div_aclk66", GATE_IP_PERIC, 29, 0, 0), |
| 589 | GATE(CLK_HSI2C2, "hsi2c2", "div_aclk66", GATE_IP_PERIC, 30, 0, 0), |
| 590 | GATE(CLK_HSI2C3, "hsi2c3", "div_aclk66", GATE_IP_PERIC, 31, 0, 0), |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 591 | |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 592 | GATE(CLK_CHIPID, "chipid", "div_aclk66", GATE_IP_PERIS, 0, 0, 0), |
| 593 | GATE(CLK_SYSREG, "sysreg", "div_aclk66", |
Abhilash Kesavan | 2feed5a | 2013-12-11 17:27:05 +0530 | [diff] [blame] | 594 | GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 595 | GATE(CLK_PMU, "pmu", "div_aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, |
| 596 | 0), |
| 597 | GATE(CLK_CMU_TOP, "cmu_top", "div_aclk66", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 598 | GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 599 | GATE(CLK_CMU_CORE, "cmu_core", "div_aclk66", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 600 | GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 601 | GATE(CLK_CMU_MEM, "cmu_mem", "div_aclk66", |
Tomasz Figa | 2786c96 | 2013-10-15 19:41:15 +0200 | [diff] [blame] | 602 | GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 603 | GATE(CLK_TZPC0, "tzpc0", "div_aclk66", GATE_IP_PERIS, 6, 0, 0), |
| 604 | GATE(CLK_TZPC1, "tzpc1", "div_aclk66", GATE_IP_PERIS, 7, 0, 0), |
| 605 | GATE(CLK_TZPC2, "tzpc2", "div_aclk66", GATE_IP_PERIS, 8, 0, 0), |
| 606 | GATE(CLK_TZPC3, "tzpc3", "div_aclk66", GATE_IP_PERIS, 9, 0, 0), |
| 607 | GATE(CLK_TZPC4, "tzpc4", "div_aclk66", GATE_IP_PERIS, 10, 0, 0), |
| 608 | GATE(CLK_TZPC5, "tzpc5", "div_aclk66", GATE_IP_PERIS, 11, 0, 0), |
| 609 | GATE(CLK_TZPC6, "tzpc6", "div_aclk66", GATE_IP_PERIS, 12, 0, 0), |
| 610 | GATE(CLK_TZPC7, "tzpc7", "div_aclk66", GATE_IP_PERIS, 13, 0, 0), |
| 611 | GATE(CLK_TZPC8, "tzpc8", "div_aclk66", GATE_IP_PERIS, 14, 0, 0), |
| 612 | GATE(CLK_TZPC9, "tzpc9", "div_aclk66", GATE_IP_PERIS, 15, 0, 0), |
| 613 | GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk66", GATE_IP_PERIS, 16, 0, 0), |
| 614 | GATE(CLK_MCT, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0), |
| 615 | GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0), |
| 616 | GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0), |
| 617 | GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0), |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 618 | }; |
| 619 | |
Sachin Kamat | b6993ec | 2013-08-07 10:18:38 +0530 | [diff] [blame] | 620 | static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { |
Vikas Sajjan | d2127ac | 2013-06-11 15:01:16 +0530 | [diff] [blame] | 621 | /* sorted in descending order */ |
| 622 | /* PLL_36XX_RATE(rate, m, p, s, k) */ |
| 623 | PLL_36XX_RATE(266000000, 266, 3, 3, 0), |
| 624 | /* Not in UM, but need for eDP on snow */ |
| 625 | PLL_36XX_RATE(70500000, 94, 2, 4, 0), |
| 626 | { }, |
| 627 | }; |
| 628 | |
Sachin Kamat | b6993ec | 2013-08-07 10:18:38 +0530 | [diff] [blame] | 629 | static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = { |
Vikas Sajjan | d2127ac | 2013-06-11 15:01:16 +0530 | [diff] [blame] | 630 | /* sorted in descending order */ |
| 631 | /* PLL_36XX_RATE(rate, m, p, s, k) */ |
| 632 | PLL_36XX_RATE(192000000, 64, 2, 2, 0), |
| 633 | PLL_36XX_RATE(180633600, 90, 3, 2, 20762), |
| 634 | PLL_36XX_RATE(180000000, 90, 3, 2, 0), |
| 635 | PLL_36XX_RATE(73728000, 98, 2, 4, 19923), |
| 636 | PLL_36XX_RATE(67737600, 90, 2, 4, 20762), |
| 637 | PLL_36XX_RATE(49152000, 98, 3, 4, 19923), |
| 638 | PLL_36XX_RATE(45158400, 90, 3, 4, 20762), |
| 639 | PLL_36XX_RATE(32768000, 131, 3, 5, 4719), |
| 640 | { }, |
| 641 | }; |
| 642 | |
Andrew Bresticker | f521ac8 | 2013-11-08 15:44:08 +0530 | [diff] [blame] | 643 | static struct samsung_pll_rate_table apll_24mhz_tbl[] __initdata = { |
| 644 | /* sorted in descending order */ |
| 645 | /* PLL_35XX_RATE(rate, m, p, s) */ |
| 646 | PLL_35XX_RATE(1700000000, 425, 6, 0), |
| 647 | PLL_35XX_RATE(1600000000, 200, 3, 0), |
| 648 | PLL_35XX_RATE(1500000000, 250, 4, 0), |
| 649 | PLL_35XX_RATE(1400000000, 175, 3, 0), |
| 650 | PLL_35XX_RATE(1300000000, 325, 6, 0), |
| 651 | PLL_35XX_RATE(1200000000, 200, 4, 0), |
| 652 | PLL_35XX_RATE(1100000000, 275, 6, 0), |
| 653 | PLL_35XX_RATE(1000000000, 125, 3, 0), |
| 654 | PLL_35XX_RATE(900000000, 150, 4, 0), |
| 655 | PLL_35XX_RATE(800000000, 100, 3, 0), |
| 656 | PLL_35XX_RATE(700000000, 175, 3, 1), |
| 657 | PLL_35XX_RATE(600000000, 200, 4, 1), |
| 658 | PLL_35XX_RATE(500000000, 125, 3, 1), |
| 659 | PLL_35XX_RATE(400000000, 100, 3, 1), |
| 660 | PLL_35XX_RATE(300000000, 200, 4, 2), |
| 661 | PLL_35XX_RATE(200000000, 100, 3, 2), |
| 662 | }; |
| 663 | |
Sachin Kamat | b6993ec | 2013-08-07 10:18:38 +0530 | [diff] [blame] | 664 | static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = { |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 665 | [apll] = PLL_A(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", |
| 666 | APLL_LOCK, APLL_CON0, "fout_apll", NULL), |
| 667 | [mpll] = PLL_A(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", |
| 668 | MPLL_LOCK, MPLL_CON0, "fout_mpll", NULL), |
| 669 | [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, |
Yadwinder Singh Brar | 3ff6e0d | 2013-06-11 15:01:12 +0530 | [diff] [blame] | 670 | BPLL_CON0, NULL), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 671 | [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK, |
Yadwinder Singh Brar | 3ff6e0d | 2013-06-11 15:01:12 +0530 | [diff] [blame] | 672 | GPLL_CON0, NULL), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 673 | [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, |
Yadwinder Singh Brar | 3ff6e0d | 2013-06-11 15:01:12 +0530 | [diff] [blame] | 674 | CPLL_CON0, NULL), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 675 | [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, |
Yadwinder Singh Brar | 3ff6e0d | 2013-06-11 15:01:12 +0530 | [diff] [blame] | 676 | EPLL_CON0, NULL), |
Andrzej Hajda | 2fe8f00 | 2014-01-07 15:47:34 +0100 | [diff] [blame] | 677 | [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc", |
Yadwinder Singh Brar | 3ff6e0d | 2013-06-11 15:01:12 +0530 | [diff] [blame] | 678 | VPLL_LOCK, VPLL_CON0, NULL), |
Yadwinder Singh Brar | 8dac353 | 2013-06-11 15:01:08 +0530 | [diff] [blame] | 679 | }; |
| 680 | |
Sachin Kamat | b6993ec | 2013-08-07 10:18:38 +0530 | [diff] [blame] | 681 | static struct of_device_id ext_clk_match[] __initdata = { |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 682 | { .compatible = "samsung,clock-xxti", .data = (void *)0, }, |
| 683 | { }, |
| 684 | }; |
| 685 | |
| 686 | /* register exynox5250 clocks */ |
Sachin Kamat | b95e71c | 2013-07-18 15:31:19 +0530 | [diff] [blame] | 687 | static void __init exynos5250_clk_init(struct device_node *np) |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 688 | { |
Rahul Sharma | 976face | 2014-03-12 20:26:44 +0530 | [diff] [blame] | 689 | struct samsung_clk_provider *ctx; |
| 690 | |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 691 | if (np) { |
| 692 | reg_base = of_iomap(np, 0); |
| 693 | if (!reg_base) |
| 694 | panic("%s: failed to map registers\n", __func__); |
| 695 | } else { |
| 696 | panic("%s: unable to determine soc\n", __func__); |
| 697 | } |
| 698 | |
Rahul Sharma | 976face | 2014-03-12 20:26:44 +0530 | [diff] [blame] | 699 | ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); |
| 700 | if (!ctx) |
| 701 | panic("%s: unable to allocate context.\n", __func__); |
| 702 | samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks, |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 703 | ARRAY_SIZE(exynos5250_fixed_rate_ext_clks), |
| 704 | ext_clk_match); |
Rahul Sharma | 976face | 2014-03-12 20:26:44 +0530 | [diff] [blame] | 705 | samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks, |
Vikas Sajjan | 8bc2eeb | 2013-06-11 15:01:15 +0530 | [diff] [blame] | 706 | ARRAY_SIZE(exynos5250_pll_pmux_clks)); |
Vikas Sajjan | d2127ac | 2013-06-11 15:01:16 +0530 | [diff] [blame] | 707 | |
Andrew Bresticker | f521ac8 | 2013-11-08 15:44:08 +0530 | [diff] [blame] | 708 | if (_get_rate("fin_pll") == 24 * MHZ) { |
Vikas Sajjan | d2127ac | 2013-06-11 15:01:16 +0530 | [diff] [blame] | 709 | exynos5250_plls[epll].rate_table = epll_24mhz_tbl; |
Andrew Bresticker | f521ac8 | 2013-11-08 15:44:08 +0530 | [diff] [blame] | 710 | exynos5250_plls[apll].rate_table = apll_24mhz_tbl; |
| 711 | } |
Vikas Sajjan | d2127ac | 2013-06-11 15:01:16 +0530 | [diff] [blame] | 712 | |
Tomasz Figa | 22e9e75 | 2013-08-26 19:09:11 +0200 | [diff] [blame] | 713 | if (_get_rate("mout_vpllsrc") == 24 * MHZ) |
Vikas Sajjan | d2127ac | 2013-06-11 15:01:16 +0530 | [diff] [blame] | 714 | exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl; |
| 715 | |
Rahul Sharma | 976face | 2014-03-12 20:26:44 +0530 | [diff] [blame] | 716 | samsung_clk_register_pll(ctx, exynos5250_plls, |
| 717 | ARRAY_SIZE(exynos5250_plls), |
| 718 | reg_base); |
| 719 | samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks, |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 720 | ARRAY_SIZE(exynos5250_fixed_rate_clks)); |
Rahul Sharma | 976face | 2014-03-12 20:26:44 +0530 | [diff] [blame] | 721 | samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks, |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 722 | ARRAY_SIZE(exynos5250_fixed_factor_clks)); |
Rahul Sharma | 976face | 2014-03-12 20:26:44 +0530 | [diff] [blame] | 723 | samsung_clk_register_mux(ctx, exynos5250_mux_clks, |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 724 | ARRAY_SIZE(exynos5250_mux_clks)); |
Rahul Sharma | 976face | 2014-03-12 20:26:44 +0530 | [diff] [blame] | 725 | samsung_clk_register_div(ctx, exynos5250_div_clks, |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 726 | ARRAY_SIZE(exynos5250_div_clks)); |
Rahul Sharma | 976face | 2014-03-12 20:26:44 +0530 | [diff] [blame] | 727 | samsung_clk_register_gate(ctx, exynos5250_gate_clks, |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 728 | ARRAY_SIZE(exynos5250_gate_clks)); |
| 729 | |
Tomasz Figa | c3b6c1d | 2014-02-14 08:16:00 +0900 | [diff] [blame] | 730 | exynos5250_clk_sleep_init(); |
| 731 | |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 732 | pr_info("Exynos5250: clock setup completed, armclk=%ld\n", |
Tomasz Figa | 38ee375 | 2013-10-15 19:41:16 +0200 | [diff] [blame] | 733 | _get_rate("div_arm2")); |
Thomas Abraham | 6e3ad268 | 2013-03-09 17:02:57 +0900 | [diff] [blame] | 734 | } |
| 735 | CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init); |