Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 2 | * Copyright © 2006 Intel Corporation |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 21 | * SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #ifndef _I830_BIOS_H_ |
| 29 | #define _I830_BIOS_H_ |
| 30 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 31 | #include <drm/drmP.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 32 | |
| 33 | struct vbt_header { |
| 34 | u8 signature[20]; /**< Always starts with 'VBT$' */ |
| 35 | u16 version; /**< decimal */ |
| 36 | u16 header_size; /**< in bytes */ |
| 37 | u16 vbt_size; /**< in bytes */ |
| 38 | u8 vbt_checksum; |
| 39 | u8 reserved0; |
| 40 | u32 bdb_offset; /**< from beginning of VBT */ |
| 41 | u32 aim_offset[4]; /**< from beginning of VBT */ |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 42 | } __packed; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 43 | |
| 44 | struct bdb_header { |
| 45 | u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */ |
| 46 | u16 version; /**< decimal */ |
| 47 | u16 header_size; /**< in bytes */ |
| 48 | u16 bdb_size; /**< in bytes */ |
| 49 | }; |
| 50 | |
| 51 | /* strictly speaking, this is a "skip" block, but it has interesting info */ |
| 52 | struct vbios_data { |
| 53 | u8 type; /* 0 == desktop, 1 == mobile */ |
| 54 | u8 relstage; |
| 55 | u8 chipset; |
| 56 | u8 lvds_present:1; |
| 57 | u8 tv_present:1; |
| 58 | u8 rsvd2:6; /* finish byte */ |
| 59 | u8 rsvd3[4]; |
| 60 | u8 signon[155]; |
| 61 | u8 copyright[61]; |
| 62 | u16 code_segment; |
| 63 | u8 dos_boot_mode; |
| 64 | u8 bandwidth_percent; |
| 65 | u8 rsvd4; /* popup memory size */ |
| 66 | u8 resize_pci_bios; |
| 67 | u8 rsvd5; /* is crt already on ddc2 */ |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 68 | } __packed; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 69 | |
| 70 | /* |
| 71 | * There are several types of BIOS data blocks (BDBs), each block has |
| 72 | * an ID and size in the first 3 bytes (ID in first, size in next 2). |
| 73 | * Known types are listed below. |
| 74 | */ |
| 75 | #define BDB_GENERAL_FEATURES 1 |
| 76 | #define BDB_GENERAL_DEFINITIONS 2 |
| 77 | #define BDB_OLD_TOGGLE_LIST 3 |
| 78 | #define BDB_MODE_SUPPORT_LIST 4 |
| 79 | #define BDB_GENERIC_MODE_TABLE 5 |
| 80 | #define BDB_EXT_MMIO_REGS 6 |
| 81 | #define BDB_SWF_IO 7 |
| 82 | #define BDB_SWF_MMIO 8 |
| 83 | #define BDB_DOT_CLOCK_TABLE 9 |
| 84 | #define BDB_MODE_REMOVAL_TABLE 10 |
| 85 | #define BDB_CHILD_DEVICE_TABLE 11 |
| 86 | #define BDB_DRIVER_FEATURES 12 |
| 87 | #define BDB_DRIVER_PERSISTENCE 13 |
| 88 | #define BDB_EXT_TABLE_PTRS 14 |
| 89 | #define BDB_DOT_CLOCK_OVERRIDE 15 |
| 90 | #define BDB_DISPLAY_SELECT 16 |
| 91 | /* 17 rsvd */ |
| 92 | #define BDB_DRIVER_ROTATION 18 |
| 93 | #define BDB_DISPLAY_REMOVE 19 |
| 94 | #define BDB_OEM_CUSTOM 20 |
| 95 | #define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */ |
| 96 | #define BDB_SDVO_LVDS_OPTIONS 22 |
| 97 | #define BDB_SDVO_PANEL_DTDS 23 |
| 98 | #define BDB_SDVO_LVDS_PNP_IDS 24 |
| 99 | #define BDB_SDVO_LVDS_POWER_SEQ 25 |
| 100 | #define BDB_TV_OPTIONS 26 |
Zhenyu Wang | 500a8cc | 2010-01-13 11:19:52 +0800 | [diff] [blame] | 101 | #define BDB_EDP 27 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 102 | #define BDB_LVDS_OPTIONS 40 |
| 103 | #define BDB_LVDS_LFP_DATA_PTRS 41 |
| 104 | #define BDB_LVDS_LFP_DATA 42 |
| 105 | #define BDB_LVDS_BACKLIGHT 43 |
| 106 | #define BDB_LVDS_POWER 44 |
Shobhit Kumar | ea9a6ba | 2014-02-28 11:18:46 +0530 | [diff] [blame] | 107 | #define BDB_MIPI_CONFIG 52 |
| 108 | #define BDB_MIPI_SEQUENCE 53 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 109 | #define BDB_SKIP 254 /* VBIOS private block, ignore */ |
| 110 | |
| 111 | struct bdb_general_features { |
| 112 | /* bits 1 */ |
| 113 | u8 panel_fitting:2; |
| 114 | u8 flexaim:1; |
| 115 | u8 msg_enable:1; |
| 116 | u8 clear_screen:3; |
| 117 | u8 color_flip:1; |
| 118 | |
| 119 | /* bits 2 */ |
| 120 | u8 download_ext_vbt:1; |
| 121 | u8 enable_ssc:1; |
| 122 | u8 ssc_freq:1; |
| 123 | u8 enable_lfp_on_override:1; |
| 124 | u8 disable_ssc_ddt:1; |
Keith Packard | abd0686 | 2011-09-26 14:24:14 -0700 | [diff] [blame] | 125 | u8 rsvd7:1; |
| 126 | u8 display_clock_mode:1; |
| 127 | u8 rsvd8:1; /* finish byte */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 128 | |
| 129 | /* bits 3 */ |
| 130 | u8 disable_smooth_vision:1; |
| 131 | u8 single_dvi:1; |
Paulo Zanoni | 3f704fa | 2013-04-08 15:48:07 -0300 | [diff] [blame] | 132 | u8 rsvd9:1; |
| 133 | u8 fdi_rx_polarity_inverted:1; |
| 134 | u8 rsvd10:4; /* finish byte */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 135 | |
| 136 | /* bits 4 */ |
| 137 | u8 legacy_monitor_detect; |
| 138 | |
| 139 | /* bits 5 */ |
| 140 | u8 int_crt_support:1; |
| 141 | u8 int_tv_support:1; |
Keith Packard | d2830bd | 2011-09-26 14:25:57 -0700 | [diff] [blame] | 142 | u8 int_efp_support:1; |
| 143 | u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */ |
| 144 | u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ |
| 145 | u8 rsvd11:3; /* finish byte */ |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 146 | } __packed; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 147 | |
yakui_zhao | 59a036c | 2009-05-31 17:16:22 +0800 | [diff] [blame] | 148 | /* pre-915 */ |
| 149 | #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ |
| 150 | #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ |
| 151 | #define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ |
| 152 | #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ |
| 153 | |
| 154 | /* Pre 915 */ |
| 155 | #define DEVICE_TYPE_NONE 0x00 |
| 156 | #define DEVICE_TYPE_CRT 0x01 |
| 157 | #define DEVICE_TYPE_TV 0x09 |
| 158 | #define DEVICE_TYPE_EFP 0x12 |
| 159 | #define DEVICE_TYPE_LFP 0x22 |
| 160 | /* On 915+ */ |
| 161 | #define DEVICE_TYPE_CRT_DPMS 0x6001 |
| 162 | #define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 |
| 163 | #define DEVICE_TYPE_TV_COMPOSITE 0x0209 |
| 164 | #define DEVICE_TYPE_TV_MACROVISION 0x0289 |
| 165 | #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c |
| 166 | #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 |
| 167 | #define DEVICE_TYPE_TV_SCART 0x0209 |
| 168 | #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 |
| 169 | #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 |
| 170 | #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 |
| 171 | #define DEVICE_TYPE_EFP_DVI_I 0x6053 |
| 172 | #define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 |
| 173 | #define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 |
| 174 | #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 |
| 175 | #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 |
| 176 | #define DEVICE_TYPE_LFP_PANELLINK 0x5012 |
| 177 | #define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 |
| 178 | #define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 |
| 179 | #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 |
| 180 | #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 |
| 181 | |
| 182 | #define DEVICE_CFG_NONE 0x00 |
| 183 | #define DEVICE_CFG_12BIT_DVOB 0x01 |
| 184 | #define DEVICE_CFG_12BIT_DVOC 0x02 |
| 185 | #define DEVICE_CFG_24BIT_DVOBC 0x09 |
| 186 | #define DEVICE_CFG_24BIT_DVOCB 0x0a |
| 187 | #define DEVICE_CFG_DUAL_DVOB 0x11 |
| 188 | #define DEVICE_CFG_DUAL_DVOC 0x12 |
| 189 | #define DEVICE_CFG_DUAL_DVOBC 0x13 |
| 190 | #define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 |
| 191 | #define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a |
| 192 | |
| 193 | #define DEVICE_WIRE_NONE 0x00 |
| 194 | #define DEVICE_WIRE_DVOB 0x01 |
| 195 | #define DEVICE_WIRE_DVOC 0x02 |
| 196 | #define DEVICE_WIRE_DVOBC 0x03 |
| 197 | #define DEVICE_WIRE_DVOBB 0x05 |
| 198 | #define DEVICE_WIRE_DVOCC 0x06 |
| 199 | #define DEVICE_WIRE_DVOB_MASTER 0x0d |
| 200 | #define DEVICE_WIRE_DVOC_MASTER 0x0e |
| 201 | |
| 202 | #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ |
| 203 | #define DEVICE_PORT_DVOB 0x01 |
| 204 | #define DEVICE_PORT_DVOC 0x02 |
| 205 | |
Paulo Zanoni | 768f69c | 2013-09-11 18:02:47 -0300 | [diff] [blame] | 206 | /* We used to keep this struct but without any version control. We should avoid |
| 207 | * using it in the future, but it should be safe to keep using it in the old |
| 208 | * code. */ |
| 209 | struct old_child_dev_config { |
yakui_zhao | 59a036c | 2009-05-31 17:16:22 +0800 | [diff] [blame] | 210 | u16 handle; |
| 211 | u16 device_type; |
Adam Jackson | 46eb303 | 2011-06-16 16:36:23 -0400 | [diff] [blame] | 212 | u8 device_id[10]; /* ascii string */ |
yakui_zhao | 59a036c | 2009-05-31 17:16:22 +0800 | [diff] [blame] | 213 | u16 addin_offset; |
| 214 | u8 dvo_port; /* See Device_PORT_* above */ |
| 215 | u8 i2c_pin; |
| 216 | u8 slave_addr; |
| 217 | u8 ddc_pin; |
| 218 | u16 edid_ptr; |
| 219 | u8 dvo_cfg; /* See DEVICE_CFG_* above */ |
| 220 | u8 dvo2_port; |
| 221 | u8 i2c2_pin; |
| 222 | u8 slave2_addr; |
| 223 | u8 ddc2_pin; |
| 224 | u8 capabilities; |
| 225 | u8 dvo_wiring;/* See DEVICE_WIRE_* above */ |
| 226 | u8 dvo2_wiring; |
| 227 | u16 extended_type; |
| 228 | u8 dvo_function; |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 229 | } __packed; |
yakui_zhao | 59a036c | 2009-05-31 17:16:22 +0800 | [diff] [blame] | 230 | |
Paulo Zanoni | 768f69c | 2013-09-11 18:02:47 -0300 | [diff] [blame] | 231 | /* This one contains field offsets that are known to be common for all BDB |
| 232 | * versions. Notice that the meaning of the contents contents may still change, |
| 233 | * but at least the offsets are consistent. */ |
| 234 | struct common_child_dev_config { |
| 235 | u16 handle; |
| 236 | u16 device_type; |
| 237 | u8 not_common1[12]; |
| 238 | u8 dvo_port; |
| 239 | u8 not_common2[2]; |
| 240 | u8 ddc_pin; |
| 241 | u16 edid_ptr; |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 242 | } __packed; |
Paulo Zanoni | 768f69c | 2013-09-11 18:02:47 -0300 | [diff] [blame] | 243 | |
| 244 | /* This field changes depending on the BDB version, so the most reliable way to |
| 245 | * read it is by checking the BDB version and reading the raw pointer. */ |
| 246 | union child_device_config { |
| 247 | /* This one is safe to be used anywhere, but the code should still check |
| 248 | * the BDB version. */ |
| 249 | u8 raw[33]; |
| 250 | /* This one should only be kept for legacy code. */ |
| 251 | struct old_child_dev_config old; |
| 252 | /* This one should also be safe to use anywhere, even without version |
| 253 | * checks. */ |
| 254 | struct common_child_dev_config common; |
| 255 | }; |
| 256 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 257 | struct bdb_general_definitions { |
| 258 | /* DDC GPIO */ |
| 259 | u8 crt_ddc_gmbus_pin; |
| 260 | |
| 261 | /* DPMS bits */ |
| 262 | u8 dpms_acpi:1; |
| 263 | u8 skip_boot_crt_detect:1; |
| 264 | u8 dpms_aim:1; |
| 265 | u8 rsvd1:5; /* finish byte */ |
| 266 | |
| 267 | /* boot device bits */ |
| 268 | u8 boot_display[2]; |
| 269 | u8 child_dev_size; |
| 270 | |
yakui_zhao | 59a036c | 2009-05-31 17:16:22 +0800 | [diff] [blame] | 271 | /* |
| 272 | * Device info: |
| 273 | * If TV is present, it'll be at devices[0]. |
| 274 | * LVDS will be next, either devices[0] or [1], if present. |
| 275 | * On some platforms the number of device is 6. But could be as few as |
| 276 | * 4 if both TV and LVDS are missing. |
| 277 | * And the device num is related with the size of general definition |
| 278 | * block. It is obtained by using the following formula: |
| 279 | * number = (block_size - sizeof(bdb_general_definitions))/ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 280 | * sizeof(child_device_config); |
yakui_zhao | 59a036c | 2009-05-31 17:16:22 +0800 | [diff] [blame] | 281 | */ |
Paulo Zanoni | 768f69c | 2013-09-11 18:02:47 -0300 | [diff] [blame] | 282 | union child_device_config devices[0]; |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 283 | } __packed; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 284 | |
Pradeep Bhat | 83a7280 | 2014-03-28 10:14:57 +0530 | [diff] [blame] | 285 | /* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */ |
| 286 | #define MODE_MASK 0x3 |
| 287 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 288 | struct bdb_lvds_options { |
| 289 | u8 panel_type; |
| 290 | u8 rsvd1; |
| 291 | /* LVDS capabilities, stored in a dword */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 292 | u8 pfit_mode:2; |
Li Peng | 2b5cde2 | 2009-03-13 10:25:07 +0800 | [diff] [blame] | 293 | u8 pfit_text_mode_enhanced:1; |
| 294 | u8 pfit_gfx_mode_enhanced:1; |
| 295 | u8 pfit_ratio_auto:1; |
| 296 | u8 pixel_dither:1; |
| 297 | u8 lvds_edid:1; |
| 298 | u8 rsvd2:1; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 299 | u8 rsvd4; |
Pradeep Bhat | 83a7280 | 2014-03-28 10:14:57 +0530 | [diff] [blame] | 300 | /* LVDS Panel channel bits stored here */ |
| 301 | u32 lvds_panel_channel_bits; |
| 302 | /* LVDS SSC (Spread Spectrum Clock) bits stored here. */ |
| 303 | u16 ssc_bits; |
| 304 | u16 ssc_freq; |
| 305 | u16 ssc_ddt; |
| 306 | /* Panel color depth defined here */ |
| 307 | u16 panel_color_depth; |
| 308 | /* LVDS panel type bits stored here */ |
| 309 | u32 dps_panel_type_bits; |
| 310 | /* LVDS backlight control type bits stored here */ |
| 311 | u32 blt_control_type_bits; |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 312 | } __packed; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 313 | |
| 314 | /* LFP pointer table contains entries to the struct below */ |
| 315 | struct bdb_lvds_lfp_data_ptr { |
| 316 | u16 fp_timing_offset; /* offsets are from start of bdb */ |
| 317 | u8 fp_table_size; |
| 318 | u16 dvo_timing_offset; |
| 319 | u8 dvo_table_size; |
| 320 | u16 panel_pnp_id_offset; |
| 321 | u8 pnp_table_size; |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 322 | } __packed; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 323 | |
| 324 | struct bdb_lvds_lfp_data_ptrs { |
| 325 | u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */ |
| 326 | struct bdb_lvds_lfp_data_ptr ptr[16]; |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 327 | } __packed; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 328 | |
| 329 | /* LFP data has 3 blocks per entry */ |
| 330 | struct lvds_fp_timing { |
| 331 | u16 x_res; |
| 332 | u16 y_res; |
| 333 | u32 lvds_reg; |
| 334 | u32 lvds_reg_val; |
| 335 | u32 pp_on_reg; |
| 336 | u32 pp_on_reg_val; |
| 337 | u32 pp_off_reg; |
| 338 | u32 pp_off_reg_val; |
| 339 | u32 pp_cycle_reg; |
| 340 | u32 pp_cycle_reg_val; |
| 341 | u32 pfit_reg; |
| 342 | u32 pfit_reg_val; |
| 343 | u16 terminator; |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 344 | } __packed; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 345 | |
| 346 | struct lvds_dvo_timing { |
| 347 | u16 clock; /**< In 10khz */ |
| 348 | u8 hactive_lo; |
| 349 | u8 hblank_lo; |
| 350 | u8 hblank_hi:4; |
| 351 | u8 hactive_hi:4; |
| 352 | u8 vactive_lo; |
| 353 | u8 vblank_lo; |
| 354 | u8 vblank_hi:4; |
| 355 | u8 vactive_hi:4; |
| 356 | u8 hsync_off_lo; |
| 357 | u8 hsync_pulse_width; |
| 358 | u8 vsync_pulse_width:4; |
| 359 | u8 vsync_off:4; |
| 360 | u8 rsvd0:6; |
| 361 | u8 hsync_off_hi:2; |
| 362 | u8 h_image; |
| 363 | u8 v_image; |
| 364 | u8 max_hv; |
| 365 | u8 h_border; |
| 366 | u8 v_border; |
| 367 | u8 rsvd1:3; |
| 368 | u8 digital:2; |
| 369 | u8 vsync_positive:1; |
| 370 | u8 hsync_positive:1; |
| 371 | u8 rsvd2:1; |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 372 | } __packed; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 373 | |
| 374 | struct lvds_pnp_id { |
| 375 | u16 mfg_name; |
| 376 | u16 product_code; |
| 377 | u32 serial; |
| 378 | u8 mfg_week; |
| 379 | u8 mfg_year; |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 380 | } __packed; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 381 | |
| 382 | struct bdb_lvds_lfp_data_entry { |
| 383 | struct lvds_fp_timing fp_timing; |
| 384 | struct lvds_dvo_timing dvo_timing; |
| 385 | struct lvds_pnp_id pnp_id; |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 386 | } __packed; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 387 | |
| 388 | struct bdb_lvds_lfp_data { |
| 389 | struct bdb_lvds_lfp_data_entry data[16]; |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 390 | } __packed; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 391 | |
Jani Nikula | f00076d | 2013-12-14 20:38:29 -0200 | [diff] [blame] | 392 | struct bdb_lfp_backlight_data_entry { |
| 393 | u8 type:2; |
| 394 | u8 active_low_pwm:1; |
| 395 | u8 obsolete1:5; |
| 396 | u16 pwm_freq_hz; |
| 397 | u8 min_brightness; |
| 398 | u8 obsolete2; |
| 399 | u8 obsolete3; |
| 400 | } __packed; |
| 401 | |
| 402 | struct bdb_lfp_backlight_data { |
| 403 | u8 entry_size; |
| 404 | struct bdb_lfp_backlight_data_entry data[16]; |
| 405 | u8 level[16]; |
| 406 | } __packed; |
| 407 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 408 | struct aimdb_header { |
| 409 | char signature[16]; |
| 410 | char oem_device[20]; |
| 411 | u16 aimdb_version; |
| 412 | u16 aimdb_header_size; |
| 413 | u16 aimdb_size; |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 414 | } __packed; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 415 | |
| 416 | struct aimdb_block { |
| 417 | u8 aimdb_id; |
| 418 | u16 aimdb_size; |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 419 | } __packed; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 420 | |
| 421 | struct vch_panel_data { |
| 422 | u16 fp_timing_offset; |
| 423 | u8 fp_timing_size; |
| 424 | u16 dvo_timing_offset; |
| 425 | u8 dvo_timing_size; |
| 426 | u16 text_fitting_offset; |
| 427 | u8 text_fitting_size; |
| 428 | u16 graphics_fitting_offset; |
| 429 | u8 graphics_fitting_size; |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 430 | } __packed; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 431 | |
| 432 | struct vch_bdb_22 { |
| 433 | struct aimdb_block aimdb_block; |
| 434 | struct vch_panel_data panels[16]; |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 435 | } __packed; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 436 | |
Ma Ling | 8863170 | 2009-05-13 11:19:55 +0800 | [diff] [blame] | 437 | struct bdb_sdvo_lvds_options { |
| 438 | u8 panel_backlight; |
| 439 | u8 h40_set_panel_type; |
| 440 | u8 panel_type; |
| 441 | u8 ssc_clk_freq; |
| 442 | u16 als_low_trip; |
| 443 | u16 als_high_trip; |
| 444 | u8 sclalarcoeff_tab_row_num; |
| 445 | u8 sclalarcoeff_tab_row_size; |
| 446 | u8 coefficient[8]; |
| 447 | u8 panel_misc_bits_1; |
| 448 | u8 panel_misc_bits_2; |
| 449 | u8 panel_misc_bits_3; |
| 450 | u8 panel_misc_bits_4; |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 451 | } __packed; |
Ma Ling | 8863170 | 2009-05-13 11:19:55 +0800 | [diff] [blame] | 452 | |
| 453 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 454 | #define BDB_DRIVER_FEATURE_NO_LVDS 0 |
| 455 | #define BDB_DRIVER_FEATURE_INT_LVDS 1 |
| 456 | #define BDB_DRIVER_FEATURE_SDVO_LVDS 2 |
| 457 | #define BDB_DRIVER_FEATURE_EDP 3 |
| 458 | |
| 459 | struct bdb_driver_features { |
| 460 | u8 boot_dev_algorithm:1; |
| 461 | u8 block_display_switch:1; |
| 462 | u8 allow_display_switch:1; |
| 463 | u8 hotplug_dvo:1; |
| 464 | u8 dual_view_zoom:1; |
| 465 | u8 int15h_hook:1; |
| 466 | u8 sprite_in_clone:1; |
| 467 | u8 primary_lfp_id:1; |
| 468 | |
| 469 | u16 boot_mode_x; |
| 470 | u16 boot_mode_y; |
| 471 | u8 boot_mode_bpp; |
| 472 | u8 boot_mode_refresh; |
| 473 | |
| 474 | u16 enable_lfp_primary:1; |
| 475 | u16 selective_mode_pruning:1; |
| 476 | u16 dual_frequency:1; |
| 477 | u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ |
| 478 | u16 nt_clone_support:1; |
| 479 | u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ |
| 480 | u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ |
| 481 | u16 cui_aspect_scaling:1; |
| 482 | u16 preserve_aspect_ratio:1; |
| 483 | u16 sdvo_device_power_down:1; |
| 484 | u16 crt_hotplug:1; |
| 485 | u16 lvds_config:2; |
| 486 | u16 tv_hotplug:1; |
| 487 | u16 hdmi_config:2; |
| 488 | |
| 489 | u8 static_display:1; |
| 490 | u8 reserved2:7; |
| 491 | u16 legacy_crt_max_x; |
| 492 | u16 legacy_crt_max_y; |
| 493 | u8 legacy_crt_max_refresh; |
| 494 | |
| 495 | u8 hdmi_termination; |
| 496 | u8 custom_vbt_version; |
Pradeep Bhat | 83a7280 | 2014-03-28 10:14:57 +0530 | [diff] [blame] | 497 | /* Driver features data block */ |
| 498 | u16 rmpm_enabled:1; |
| 499 | u16 s2ddt_enabled:1; |
| 500 | u16 dpst_enabled:1; |
| 501 | u16 bltclt_enabled:1; |
| 502 | u16 adb_enabled:1; |
| 503 | u16 drrs_enabled:1; |
| 504 | u16 grs_enabled:1; |
| 505 | u16 gpmt_enabled:1; |
| 506 | u16 tbt_enabled:1; |
| 507 | u16 psr_enabled:1; |
| 508 | u16 ips_enabled:1; |
| 509 | u16 reserved3:4; |
| 510 | u16 pc_feature_valid:1; |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 511 | } __packed; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 512 | |
Zhenyu Wang | 500a8cc | 2010-01-13 11:19:52 +0800 | [diff] [blame] | 513 | #define EDP_18BPP 0 |
| 514 | #define EDP_24BPP 1 |
| 515 | #define EDP_30BPP 2 |
| 516 | #define EDP_RATE_1_62 0 |
| 517 | #define EDP_RATE_2_7 1 |
| 518 | #define EDP_LANE_1 0 |
| 519 | #define EDP_LANE_2 1 |
| 520 | #define EDP_LANE_4 3 |
| 521 | #define EDP_PREEMPHASIS_NONE 0 |
| 522 | #define EDP_PREEMPHASIS_3_5dB 1 |
| 523 | #define EDP_PREEMPHASIS_6dB 2 |
| 524 | #define EDP_PREEMPHASIS_9_5dB 3 |
| 525 | #define EDP_VSWING_0_4V 0 |
| 526 | #define EDP_VSWING_0_6V 1 |
| 527 | #define EDP_VSWING_0_8V 2 |
| 528 | #define EDP_VSWING_1_2V 3 |
| 529 | |
| 530 | struct edp_power_seq { |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 531 | u16 t1_t3; |
| 532 | u16 t8; |
Zhenyu Wang | 500a8cc | 2010-01-13 11:19:52 +0800 | [diff] [blame] | 533 | u16 t9; |
| 534 | u16 t10; |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 535 | u16 t11_t12; |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 536 | } __packed; |
Zhenyu Wang | 500a8cc | 2010-01-13 11:19:52 +0800 | [diff] [blame] | 537 | |
| 538 | struct edp_link_params { |
| 539 | u8 rate:4; |
| 540 | u8 lanes:4; |
| 541 | u8 preemphasis:4; |
| 542 | u8 vswing:4; |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 543 | } __packed; |
Zhenyu Wang | 500a8cc | 2010-01-13 11:19:52 +0800 | [diff] [blame] | 544 | |
| 545 | struct bdb_edp { |
| 546 | struct edp_power_seq power_seqs[16]; |
| 547 | u32 color_depth; |
Zhenyu Wang | 500a8cc | 2010-01-13 11:19:52 +0800 | [diff] [blame] | 548 | struct edp_link_params link_params[16]; |
Rohit Jain | 96c0a2f | 2012-01-12 12:19:44 +0530 | [diff] [blame] | 549 | u32 sdrrs_msa_timing_delay; |
| 550 | |
| 551 | /* ith bit indicates enabled/disabled for (i+1)th panel */ |
| 552 | u16 edp_s3d_feature; |
| 553 | u16 edp_t3_optimization; |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 554 | } __packed; |
Zhenyu Wang | 500a8cc | 2010-01-13 11:19:52 +0800 | [diff] [blame] | 555 | |
Bryan Freed | 6d139a8 | 2010-10-14 09:14:51 +0100 | [diff] [blame] | 556 | void intel_setup_bios(struct drm_device *dev); |
Dan Carpenter | 0317c6c | 2012-06-27 12:10:30 +0300 | [diff] [blame] | 557 | int intel_parse_bios(struct drm_device *dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 558 | |
| 559 | /* |
| 560 | * Driver<->VBIOS interaction occurs through scratch bits in |
| 561 | * GR18 & SWF*. |
| 562 | */ |
| 563 | |
| 564 | /* GR18 bits are set on display switch and hotkey events */ |
| 565 | #define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */ |
| 566 | #define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */ |
| 567 | #define GR18_HK_NONE (0x0<<3) |
| 568 | #define GR18_HK_LFP_STRETCH (0x1<<3) |
| 569 | #define GR18_HK_TOGGLE_DISP (0x2<<3) |
| 570 | #define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */ |
| 571 | #define GR18_HK_POPUP_DISABLED (0x6<<3) |
| 572 | #define GR18_HK_POPUP_ENABLED (0x7<<3) |
| 573 | #define GR18_HK_PFIT (0x8<<3) |
| 574 | #define GR18_HK_APM_CHANGE (0xa<<3) |
| 575 | #define GR18_HK_MULTIPLE (0xc<<3) |
| 576 | #define GR18_USER_INT_EN (1<<2) |
| 577 | #define GR18_A0000_FLUSH_EN (1<<1) |
| 578 | #define GR18_SMM_EN (1<<0) |
| 579 | |
| 580 | /* Set by driver, cleared by VBIOS */ |
| 581 | #define SWF00_YRES_SHIFT 16 |
| 582 | #define SWF00_XRES_SHIFT 0 |
| 583 | #define SWF00_RES_MASK 0xffff |
| 584 | |
| 585 | /* Set by VBIOS at boot time and driver at runtime */ |
| 586 | #define SWF01_TV2_FORMAT_SHIFT 8 |
| 587 | #define SWF01_TV1_FORMAT_SHIFT 0 |
| 588 | #define SWF01_TV_FORMAT_MASK 0xffff |
| 589 | |
| 590 | #define SWF10_VBIOS_BLC_I2C_EN (1<<29) |
| 591 | #define SWF10_GTT_OVERRIDE_EN (1<<28) |
| 592 | #define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */ |
| 593 | #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24) |
| 594 | #define SWF10_OLD_TOGGLE 0x0 |
| 595 | #define SWF10_TOGGLE_LIST_1 0x1 |
| 596 | #define SWF10_TOGGLE_LIST_2 0x2 |
| 597 | #define SWF10_TOGGLE_LIST_3 0x3 |
| 598 | #define SWF10_TOGGLE_LIST_4 0x4 |
| 599 | #define SWF10_PANNING_EN (1<<23) |
| 600 | #define SWF10_DRIVER_LOADED (1<<22) |
| 601 | #define SWF10_EXTENDED_DESKTOP (1<<21) |
| 602 | #define SWF10_EXCLUSIVE_MODE (1<<20) |
| 603 | #define SWF10_OVERLAY_EN (1<<19) |
| 604 | #define SWF10_PLANEB_HOLDOFF (1<<18) |
| 605 | #define SWF10_PLANEA_HOLDOFF (1<<17) |
| 606 | #define SWF10_VGA_HOLDOFF (1<<16) |
| 607 | #define SWF10_ACTIVE_DISP_MASK 0xffff |
| 608 | #define SWF10_PIPEB_LFP2 (1<<15) |
| 609 | #define SWF10_PIPEB_EFP2 (1<<14) |
| 610 | #define SWF10_PIPEB_TV2 (1<<13) |
| 611 | #define SWF10_PIPEB_CRT2 (1<<12) |
| 612 | #define SWF10_PIPEB_LFP (1<<11) |
| 613 | #define SWF10_PIPEB_EFP (1<<10) |
| 614 | #define SWF10_PIPEB_TV (1<<9) |
| 615 | #define SWF10_PIPEB_CRT (1<<8) |
| 616 | #define SWF10_PIPEA_LFP2 (1<<7) |
| 617 | #define SWF10_PIPEA_EFP2 (1<<6) |
| 618 | #define SWF10_PIPEA_TV2 (1<<5) |
| 619 | #define SWF10_PIPEA_CRT2 (1<<4) |
| 620 | #define SWF10_PIPEA_LFP (1<<3) |
| 621 | #define SWF10_PIPEA_EFP (1<<2) |
| 622 | #define SWF10_PIPEA_TV (1<<1) |
| 623 | #define SWF10_PIPEA_CRT (1<<0) |
| 624 | |
| 625 | #define SWF11_MEMORY_SIZE_SHIFT 16 |
| 626 | #define SWF11_SV_TEST_EN (1<<15) |
| 627 | #define SWF11_IS_AGP (1<<14) |
| 628 | #define SWF11_DISPLAY_HOLDOFF (1<<13) |
| 629 | #define SWF11_DPMS_REDUCED (1<<12) |
| 630 | #define SWF11_IS_VBE_MODE (1<<11) |
| 631 | #define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */ |
| 632 | #define SWF11_DPMS_MASK 0x07 |
| 633 | #define SWF11_DPMS_OFF (1<<2) |
| 634 | #define SWF11_DPMS_SUSPEND (1<<1) |
| 635 | #define SWF11_DPMS_STANDBY (1<<0) |
| 636 | #define SWF11_DPMS_ON 0 |
| 637 | |
| 638 | #define SWF14_GFX_PFIT_EN (1<<31) |
| 639 | #define SWF14_TEXT_PFIT_EN (1<<30) |
| 640 | #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */ |
| 641 | #define SWF14_POPUP_EN (1<<28) |
| 642 | #define SWF14_DISPLAY_HOLDOFF (1<<27) |
| 643 | #define SWF14_DISP_DETECT_EN (1<<26) |
| 644 | #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */ |
| 645 | #define SWF14_DRIVER_STATUS (1<<24) |
| 646 | #define SWF14_OS_TYPE_WIN9X (1<<23) |
| 647 | #define SWF14_OS_TYPE_WINNT (1<<22) |
| 648 | /* 21:19 rsvd */ |
| 649 | #define SWF14_PM_TYPE_MASK 0x00070000 |
| 650 | #define SWF14_PM_ACPI_VIDEO (0x4 << 16) |
| 651 | #define SWF14_PM_ACPI (0x3 << 16) |
| 652 | #define SWF14_PM_APM_12 (0x2 << 16) |
| 653 | #define SWF14_PM_APM_11 (0x1 << 16) |
| 654 | #define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */ |
| 655 | /* if GR18 indicates a display switch */ |
| 656 | #define SWF14_DS_PIPEB_LFP2_EN (1<<15) |
| 657 | #define SWF14_DS_PIPEB_EFP2_EN (1<<14) |
| 658 | #define SWF14_DS_PIPEB_TV2_EN (1<<13) |
| 659 | #define SWF14_DS_PIPEB_CRT2_EN (1<<12) |
| 660 | #define SWF14_DS_PIPEB_LFP_EN (1<<11) |
| 661 | #define SWF14_DS_PIPEB_EFP_EN (1<<10) |
| 662 | #define SWF14_DS_PIPEB_TV_EN (1<<9) |
| 663 | #define SWF14_DS_PIPEB_CRT_EN (1<<8) |
| 664 | #define SWF14_DS_PIPEA_LFP2_EN (1<<7) |
| 665 | #define SWF14_DS_PIPEA_EFP2_EN (1<<6) |
| 666 | #define SWF14_DS_PIPEA_TV2_EN (1<<5) |
| 667 | #define SWF14_DS_PIPEA_CRT2_EN (1<<4) |
| 668 | #define SWF14_DS_PIPEA_LFP_EN (1<<3) |
| 669 | #define SWF14_DS_PIPEA_EFP_EN (1<<2) |
| 670 | #define SWF14_DS_PIPEA_TV_EN (1<<1) |
| 671 | #define SWF14_DS_PIPEA_CRT_EN (1<<0) |
| 672 | /* if GR18 indicates a panel fitting request */ |
| 673 | #define SWF14_PFIT_EN (1<<0) /* 0 means disable */ |
| 674 | /* if GR18 indicates an APM change request */ |
| 675 | #define SWF14_APM_HIBERNATE 0x4 |
| 676 | #define SWF14_APM_SUSPEND 0x3 |
| 677 | #define SWF14_APM_STANDBY 0x1 |
| 678 | #define SWF14_APM_RESTORE 0x0 |
| 679 | |
Zhao Yakui | 6363ee6 | 2009-11-24 09:48:44 +0800 | [diff] [blame] | 680 | /* Add the device class for LFP, TV, HDMI */ |
| 681 | #define DEVICE_TYPE_INT_LFP 0x1022 |
| 682 | #define DEVICE_TYPE_INT_TV 0x1009 |
| 683 | #define DEVICE_TYPE_HDMI 0x60D2 |
| 684 | #define DEVICE_TYPE_DP 0x68C6 |
| 685 | #define DEVICE_TYPE_eDP 0x78C6 |
| 686 | |
Ville Syrjälä | 78eb06c | 2013-11-01 20:32:07 +0200 | [diff] [blame] | 687 | #define DEVICE_TYPE_CLASS_EXTENSION (1 << 15) |
| 688 | #define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14) |
| 689 | #define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13) |
| 690 | #define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12) |
| 691 | #define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11) |
| 692 | #define DEVICE_TYPE_MIPI_OUTPUT (1 << 10) |
| 693 | #define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9) |
| 694 | #define DEVICE_TYPE_DUAL_CHANNEL (1 << 8) |
| 695 | #define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6) |
| 696 | #define DEVICE_TYPE_LVDS_SINGALING (1 << 5) |
| 697 | #define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4) |
| 698 | #define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3) |
| 699 | #define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2) |
| 700 | #define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1) |
| 701 | #define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0) |
| 702 | |
Ville Syrjälä | f02586d | 2013-11-01 20:32:08 +0200 | [diff] [blame] | 703 | /* |
| 704 | * Bits we care about when checking for DEVICE_TYPE_eDP |
| 705 | * Depending on the system, the other bits may or may not |
| 706 | * be set for eDP outputs. |
| 707 | */ |
| 708 | #define DEVICE_TYPE_eDP_BITS \ |
| 709 | (DEVICE_TYPE_INTERNAL_CONNECTOR | \ |
| 710 | DEVICE_TYPE_NOT_HDMI_OUTPUT | \ |
| 711 | DEVICE_TYPE_MIPI_OUTPUT | \ |
| 712 | DEVICE_TYPE_COMPOSITE_OUTPUT | \ |
| 713 | DEVICE_TYPE_DUAL_CHANNEL | \ |
| 714 | DEVICE_TYPE_LVDS_SINGALING | \ |
| 715 | DEVICE_TYPE_TMDS_DVI_SIGNALING | \ |
| 716 | DEVICE_TYPE_VIDEO_SIGNALING | \ |
| 717 | DEVICE_TYPE_DISPLAYPORT_OUTPUT | \ |
| 718 | DEVICE_TYPE_DIGITAL_OUTPUT | \ |
| 719 | DEVICE_TYPE_ANALOG_OUTPUT) |
| 720 | |
Zhao Yakui | 6363ee6 | 2009-11-24 09:48:44 +0800 | [diff] [blame] | 721 | /* define the DVO port for HDMI output type */ |
| 722 | #define DVO_B 1 |
| 723 | #define DVO_C 2 |
| 724 | #define DVO_D 3 |
| 725 | |
| 726 | /* define the PORT for DP output type */ |
| 727 | #define PORT_IDPB 7 |
| 728 | #define PORT_IDPC 8 |
| 729 | #define PORT_IDPD 9 |
| 730 | |
Paulo Zanoni | 6acab15 | 2013-09-12 17:06:24 -0300 | [diff] [blame] | 731 | /* Possible values for the "DVO Port" field for versions >= 155: */ |
| 732 | #define DVO_PORT_HDMIA 0 |
| 733 | #define DVO_PORT_HDMIB 1 |
| 734 | #define DVO_PORT_HDMIC 2 |
| 735 | #define DVO_PORT_HDMID 3 |
| 736 | #define DVO_PORT_LVDS 4 |
| 737 | #define DVO_PORT_TV 5 |
| 738 | #define DVO_PORT_CRT 6 |
| 739 | #define DVO_PORT_DPB 7 |
| 740 | #define DVO_PORT_DPC 8 |
| 741 | #define DVO_PORT_DPD 9 |
| 742 | #define DVO_PORT_DPA 10 |
| 743 | |
Shobhit Kumar | ea9a6ba | 2014-02-28 11:18:46 +0530 | [diff] [blame] | 744 | /* Block 52 contains MIPI Panel info |
| 745 | * 6 such enteries will there. Index into correct |
| 746 | * entery is based on the panel_index in #40 LFP |
| 747 | */ |
| 748 | #define MAX_MIPI_CONFIGURATIONS 6 |
| 749 | |
| 750 | #define MIPI_DSI_UNDEFINED_PANEL_ID 0 |
| 751 | #define MIPI_DSI_GENERIC_PANEL_ID 1 |
| 752 | |
| 753 | struct mipi_config { |
Shobhit Kumar | d17c544 | 2013-08-27 15:12:25 +0300 | [diff] [blame] | 754 | u16 panel_id; |
Shobhit Kumar | d17c544 | 2013-08-27 15:12:25 +0300 | [diff] [blame] | 755 | |
Shobhit Kumar | ea9a6ba | 2014-02-28 11:18:46 +0530 | [diff] [blame] | 756 | /* General Params */ |
| 757 | u32 enable_dithering:1; |
Shobhit Kumar | d17c544 | 2013-08-27 15:12:25 +0300 | [diff] [blame] | 758 | u32 rsvd1:1; |
Shobhit Kumar | ea9a6ba | 2014-02-28 11:18:46 +0530 | [diff] [blame] | 759 | u32 is_bridge:1; |
Shobhit Kumar | d17c544 | 2013-08-27 15:12:25 +0300 | [diff] [blame] | 760 | |
Shobhit Kumar | ea9a6ba | 2014-02-28 11:18:46 +0530 | [diff] [blame] | 761 | u32 panel_arch_type:2; |
| 762 | u32 is_cmd_mode:1; |
Shobhit Kumar | d17c544 | 2013-08-27 15:12:25 +0300 | [diff] [blame] | 763 | |
Shobhit Kumar | ea9a6ba | 2014-02-28 11:18:46 +0530 | [diff] [blame] | 764 | #define NON_BURST_SYNC_PULSE 0x1 |
| 765 | #define NON_BURST_SYNC_EVENTS 0x2 |
| 766 | #define BURST_MODE 0x3 |
| 767 | u32 video_transfer_mode:2; |
Shobhit Kumar | d17c544 | 2013-08-27 15:12:25 +0300 | [diff] [blame] | 768 | |
Shobhit Kumar | ea9a6ba | 2014-02-28 11:18:46 +0530 | [diff] [blame] | 769 | u32 cabc_supported:1; |
| 770 | u32 pwm_blc:1; |
| 771 | |
| 772 | /* Bit 13:10 */ |
| 773 | #define PIXEL_FORMAT_RGB565 0x1 |
| 774 | #define PIXEL_FORMAT_RGB666 0x2 |
| 775 | #define PIXEL_FORMAT_RGB666_LOOSELY_PACKED 0x3 |
| 776 | #define PIXEL_FORMAT_RGB888 0x4 |
| 777 | u32 videomode_color_format:4; |
| 778 | |
| 779 | /* Bit 15:14 */ |
| 780 | #define ENABLE_ROTATION_0 0x0 |
| 781 | #define ENABLE_ROTATION_90 0x1 |
| 782 | #define ENABLE_ROTATION_180 0x2 |
| 783 | #define ENABLE_ROTATION_270 0x3 |
| 784 | u32 rotation:2; |
| 785 | u32 bta_enabled:1; |
| 786 | u32 rsvd2:15; |
| 787 | |
| 788 | /* 2 byte Port Description */ |
| 789 | #define DUAL_LINK_NOT_SUPPORTED 0 |
| 790 | #define DUAL_LINK_FRONT_BACK 1 |
| 791 | #define DUAL_LINK_PIXEL_ALT 2 |
| 792 | u16 dual_link:2; |
| 793 | u16 lane_cnt:2; |
| 794 | u16 rsvd3:12; |
| 795 | |
| 796 | u16 rsvd4; |
| 797 | |
| 798 | u8 rsvd5[5]; |
| 799 | u32 dsi_ddr_clk; |
Shobhit Kumar | d17c544 | 2013-08-27 15:12:25 +0300 | [diff] [blame] | 800 | u32 bridge_ref_clk; |
Shobhit Kumar | d17c544 | 2013-08-27 15:12:25 +0300 | [diff] [blame] | 801 | |
Shobhit Kumar | ea9a6ba | 2014-02-28 11:18:46 +0530 | [diff] [blame] | 802 | #define BYTE_CLK_SEL_20MHZ 0 |
| 803 | #define BYTE_CLK_SEL_10MHZ 1 |
| 804 | #define BYTE_CLK_SEL_5MHZ 2 |
| 805 | u8 byte_clk_sel:2; |
| 806 | |
| 807 | u8 rsvd6:6; |
| 808 | |
| 809 | /* DPHY Flags */ |
| 810 | u16 dphy_param_valid:1; |
| 811 | u16 eot_pkt_disabled:1; |
| 812 | u16 enable_clk_stop:1; |
| 813 | u16 rsvd7:13; |
| 814 | |
| 815 | u32 hs_tx_timeout; |
| 816 | u32 lp_rx_timeout; |
| 817 | u32 turn_around_timeout; |
| 818 | u32 device_reset_timer; |
| 819 | u32 master_init_timer; |
| 820 | u32 dbi_bw_timer; |
| 821 | u32 lp_byte_clk_val; |
| 822 | |
| 823 | /* 4 byte Dphy Params */ |
| 824 | u32 prepare_cnt:6; |
| 825 | u32 rsvd8:2; |
Shobhit Kumar | d17c544 | 2013-08-27 15:12:25 +0300 | [diff] [blame] | 826 | u32 clk_zero_cnt:8; |
| 827 | u32 trail_cnt:5; |
Shobhit Kumar | ea9a6ba | 2014-02-28 11:18:46 +0530 | [diff] [blame] | 828 | u32 rsvd9:3; |
Shobhit Kumar | d17c544 | 2013-08-27 15:12:25 +0300 | [diff] [blame] | 829 | u32 exit_zero_cnt:6; |
Shobhit Kumar | ea9a6ba | 2014-02-28 11:18:46 +0530 | [diff] [blame] | 830 | u32 rsvd10:2; |
Shobhit Kumar | d17c544 | 2013-08-27 15:12:25 +0300 | [diff] [blame] | 831 | |
Shobhit Kumar | d17c544 | 2013-08-27 15:12:25 +0300 | [diff] [blame] | 832 | u32 clk_lane_switch_cnt; |
Shobhit Kumar | ea9a6ba | 2014-02-28 11:18:46 +0530 | [diff] [blame] | 833 | u32 hl_switch_cnt; |
| 834 | |
| 835 | u32 rsvd11[6]; |
| 836 | |
| 837 | /* timings based on dphy spec */ |
| 838 | u8 tclk_miss; |
| 839 | u8 tclk_post; |
| 840 | u8 rsvd12; |
| 841 | u8 tclk_pre; |
| 842 | u8 tclk_prepare; |
| 843 | u8 tclk_settle; |
| 844 | u8 tclk_term_enable; |
| 845 | u8 tclk_trail; |
| 846 | u16 tclk_prepare_clkzero; |
| 847 | u8 rsvd13; |
| 848 | u8 td_term_enable; |
| 849 | u8 teot; |
| 850 | u8 ths_exit; |
| 851 | u8 ths_prepare; |
| 852 | u16 ths_prepare_hszero; |
| 853 | u8 rsvd14; |
| 854 | u8 ths_settle; |
| 855 | u8 ths_skip; |
| 856 | u8 ths_trail; |
| 857 | u8 tinit; |
| 858 | u8 tlpx; |
| 859 | u8 rsvd15[3]; |
| 860 | |
| 861 | /* GPIOs */ |
| 862 | u8 panel_enable; |
| 863 | u8 bl_enable; |
| 864 | u8 pwm_enable; |
| 865 | u8 reset_r_n; |
| 866 | u8 pwr_down_r; |
| 867 | u8 stdby_r_n; |
| 868 | |
Jani Nikula | e445123 | 2013-12-02 11:26:09 -0200 | [diff] [blame] | 869 | } __packed; |
Shobhit Kumar | d17c544 | 2013-08-27 15:12:25 +0300 | [diff] [blame] | 870 | |
Shobhit Kumar | ea9a6ba | 2014-02-28 11:18:46 +0530 | [diff] [blame] | 871 | /* Block 52 contains MIPI configuration block |
| 872 | * 6 * bdb_mipi_config, followed by 6 pps data |
| 873 | * block below |
| 874 | * |
| 875 | * all delays has a unit of 100us |
| 876 | */ |
| 877 | struct mipi_pps_data { |
| 878 | u16 panel_on_delay; |
| 879 | u16 bl_enable_delay; |
| 880 | u16 bl_disable_delay; |
| 881 | u16 panel_off_delay; |
| 882 | u16 panel_power_cycle_delay; |
| 883 | }; |
| 884 | |
| 885 | struct bdb_mipi_config { |
| 886 | struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; |
| 887 | struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; |
| 888 | }; |
| 889 | |
| 890 | /* Block 53 contains MIPI sequences as needed by the panel |
| 891 | * for enabling it. This block can be variable in size and |
| 892 | * can be maximum of 6 blocks |
| 893 | */ |
| 894 | struct bdb_mipi_sequence { |
| 895 | u8 version; |
| 896 | u8 data[0]; |
| 897 | }; |
| 898 | |
Shobhit Kumar | d3b542f | 2014-04-14 11:00:34 +0530 | [diff] [blame^] | 899 | /* MIPI Sequnece Block definitions */ |
| 900 | enum mipi_seq { |
| 901 | MIPI_SEQ_UNDEFINED = 0, |
| 902 | MIPI_SEQ_ASSERT_RESET, |
| 903 | MIPI_SEQ_INIT_OTP, |
| 904 | MIPI_SEQ_DISPLAY_ON, |
| 905 | MIPI_SEQ_DISPLAY_OFF, |
| 906 | MIPI_SEQ_DEASSERT_RESET, |
| 907 | MIPI_SEQ_MAX |
| 908 | }; |
| 909 | |
| 910 | enum mipi_seq_element { |
| 911 | MIPI_SEQ_ELEM_UNDEFINED = 0, |
| 912 | MIPI_SEQ_ELEM_SEND_PKT, |
| 913 | MIPI_SEQ_ELEM_DELAY, |
| 914 | MIPI_SEQ_ELEM_GPIO, |
| 915 | MIPI_SEQ_ELEM_STATUS, |
| 916 | MIPI_SEQ_ELEM_MAX |
| 917 | }; |
| 918 | |
| 919 | enum mipi_gpio_pin_index { |
| 920 | MIPI_GPIO_UNDEFINED = 0, |
| 921 | MIPI_GPIO_PANEL_ENABLE, |
| 922 | MIPI_GPIO_BL_ENABLE, |
| 923 | MIPI_GPIO_PWM_ENABLE, |
| 924 | MIPI_GPIO_RESET_N, |
| 925 | MIPI_GPIO_PWR_DOWN_R, |
| 926 | MIPI_GPIO_STDBY_RST_N, |
| 927 | MIPI_GPIO_MAX |
| 928 | }; |
| 929 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 930 | #endif /* _I830_BIOS_H_ */ |