Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2009 VMware, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Michel Dänzer |
| 23 | */ |
| 24 | #include <drm/drmP.h> |
| 25 | #include <drm/radeon_drm.h> |
| 26 | #include "radeon_reg.h" |
| 27 | #include "radeon.h" |
| 28 | |
Alex Deucher | 009ee7a | 2012-06-04 18:45:15 -0400 | [diff] [blame] | 29 | #define RADEON_TEST_COPY_BLIT 1 |
| 30 | #define RADEON_TEST_COPY_DMA 0 |
| 31 | |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 32 | |
| 33 | /* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */ |
Alex Deucher | 009ee7a | 2012-06-04 18:45:15 -0400 | [diff] [blame] | 34 | static void radeon_do_test_moves(struct radeon_device *rdev, int flag) |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 35 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 36 | struct radeon_bo *vram_obj = NULL; |
| 37 | struct radeon_bo **gtt_obj = NULL; |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 38 | uint64_t gtt_addr, vram_addr; |
Dan Carpenter | 89cd67b | 2013-07-01 19:39:34 +0300 | [diff] [blame] | 39 | unsigned n, size; |
| 40 | int i, r, ring; |
Alex Deucher | 009ee7a | 2012-06-04 18:45:15 -0400 | [diff] [blame] | 41 | |
| 42 | switch (flag) { |
| 43 | case RADEON_TEST_COPY_DMA: |
| 44 | ring = radeon_copy_dma_ring_index(rdev); |
| 45 | break; |
| 46 | case RADEON_TEST_COPY_BLIT: |
| 47 | ring = radeon_copy_blit_ring_index(rdev); |
| 48 | break; |
| 49 | default: |
| 50 | DRM_ERROR("Unknown copy method\n"); |
| 51 | return; |
| 52 | } |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 53 | |
| 54 | size = 1024 * 1024; |
| 55 | |
| 56 | /* Number of tests = |
Michel Dänzer | 24cae9e | 2011-08-19 15:24:16 +0000 | [diff] [blame] | 57 | * (Total GTT - IB pool - writeback page - ring buffers) / test size |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 58 | */ |
Christian König | 7b1f248 | 2011-09-23 15:11:23 +0200 | [diff] [blame] | 59 | n = rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024; |
Christian König | bf85279 | 2011-10-13 13:19:22 +0200 | [diff] [blame] | 60 | for (i = 0; i < RADEON_NUM_RINGS; ++i) |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 61 | n -= rdev->ring[i].ring_size; |
Michel Dänzer | 24cae9e | 2011-08-19 15:24:16 +0000 | [diff] [blame] | 62 | if (rdev->wb.wb_obj) |
| 63 | n -= RADEON_GPU_PAGE_SIZE; |
| 64 | if (rdev->ih.ring_obj) |
| 65 | n -= rdev->ih.ring_size; |
| 66 | n /= size; |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 67 | |
| 68 | gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL); |
| 69 | if (!gtt_obj) { |
| 70 | DRM_ERROR("Failed to allocate %d pointers\n", n); |
| 71 | r = 1; |
| 72 | goto out_cleanup; |
| 73 | } |
| 74 | |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 75 | r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, |
Alex Deucher | 40f5cf9 | 2012-05-10 18:33:13 -0400 | [diff] [blame] | 76 | NULL, &vram_obj); |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 77 | if (r) { |
| 78 | DRM_ERROR("Failed to create VRAM object\n"); |
| 79 | goto out_cleanup; |
| 80 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 81 | r = radeon_bo_reserve(vram_obj, false); |
| 82 | if (unlikely(r != 0)) |
Maarten Lankhorst | 977c38d | 2013-06-27 13:48:26 +0200 | [diff] [blame] | 83 | goto out_unref; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 84 | r = radeon_bo_pin(vram_obj, RADEON_GEM_DOMAIN_VRAM, &vram_addr); |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 85 | if (r) { |
| 86 | DRM_ERROR("Failed to pin VRAM object\n"); |
Maarten Lankhorst | 977c38d | 2013-06-27 13:48:26 +0200 | [diff] [blame] | 87 | goto out_unres; |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 88 | } |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 89 | for (i = 0; i < n; i++) { |
| 90 | void *gtt_map, *vram_map; |
| 91 | void **gtt_start, **gtt_end; |
| 92 | void **vram_start, **vram_end; |
Maarten Lankhorst | 977c38d | 2013-06-27 13:48:26 +0200 | [diff] [blame] | 93 | struct radeon_fence *fence = NULL; |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 94 | |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 95 | r = radeon_bo_create(rdev, size, PAGE_SIZE, true, |
Alex Deucher | 40f5cf9 | 2012-05-10 18:33:13 -0400 | [diff] [blame] | 96 | RADEON_GEM_DOMAIN_GTT, NULL, gtt_obj + i); |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 97 | if (r) { |
| 98 | DRM_ERROR("Failed to create GTT object %d\n", i); |
Maarten Lankhorst | 977c38d | 2013-06-27 13:48:26 +0200 | [diff] [blame] | 99 | goto out_lclean; |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 100 | } |
| 101 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 102 | r = radeon_bo_reserve(gtt_obj[i], false); |
| 103 | if (unlikely(r != 0)) |
Maarten Lankhorst | 977c38d | 2013-06-27 13:48:26 +0200 | [diff] [blame] | 104 | goto out_lclean_unref; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 105 | r = radeon_bo_pin(gtt_obj[i], RADEON_GEM_DOMAIN_GTT, >t_addr); |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 106 | if (r) { |
| 107 | DRM_ERROR("Failed to pin GTT object %d\n", i); |
Maarten Lankhorst | 977c38d | 2013-06-27 13:48:26 +0200 | [diff] [blame] | 108 | goto out_lclean_unres; |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 109 | } |
| 110 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 111 | r = radeon_bo_kmap(gtt_obj[i], >t_map); |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 112 | if (r) { |
| 113 | DRM_ERROR("Failed to map GTT object %d\n", i); |
Maarten Lankhorst | 977c38d | 2013-06-27 13:48:26 +0200 | [diff] [blame] | 114 | goto out_lclean_unpin; |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 115 | } |
| 116 | |
| 117 | for (gtt_start = gtt_map, gtt_end = gtt_map + size; |
| 118 | gtt_start < gtt_end; |
| 119 | gtt_start++) |
| 120 | *gtt_start = gtt_start; |
| 121 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 122 | radeon_bo_kunmap(gtt_obj[i]); |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 123 | |
Alex Deucher | 009ee7a | 2012-06-04 18:45:15 -0400 | [diff] [blame] | 124 | if (ring == R600_RING_TYPE_DMA_INDEX) |
| 125 | r = radeon_copy_dma(rdev, gtt_addr, vram_addr, size / RADEON_GPU_PAGE_SIZE, &fence); |
| 126 | else |
| 127 | r = radeon_copy_blit(rdev, gtt_addr, vram_addr, size / RADEON_GPU_PAGE_SIZE, &fence); |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 128 | if (r) { |
| 129 | DRM_ERROR("Failed GTT->VRAM copy %d\n", i); |
Maarten Lankhorst | 977c38d | 2013-06-27 13:48:26 +0200 | [diff] [blame] | 130 | goto out_lclean_unpin; |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 131 | } |
| 132 | |
| 133 | r = radeon_fence_wait(fence, false); |
| 134 | if (r) { |
| 135 | DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i); |
Maarten Lankhorst | 977c38d | 2013-06-27 13:48:26 +0200 | [diff] [blame] | 136 | goto out_lclean_unpin; |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 137 | } |
| 138 | |
| 139 | radeon_fence_unref(&fence); |
| 140 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 141 | r = radeon_bo_kmap(vram_obj, &vram_map); |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 142 | if (r) { |
| 143 | DRM_ERROR("Failed to map VRAM object after copy %d\n", i); |
Maarten Lankhorst | 977c38d | 2013-06-27 13:48:26 +0200 | [diff] [blame] | 144 | goto out_lclean_unpin; |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 145 | } |
| 146 | |
| 147 | for (gtt_start = gtt_map, gtt_end = gtt_map + size, |
| 148 | vram_start = vram_map, vram_end = vram_map + size; |
| 149 | vram_start < vram_end; |
| 150 | gtt_start++, vram_start++) { |
| 151 | if (*vram_start != gtt_start) { |
| 152 | DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, " |
Michel Dänzer | 4fb1a35 | 2011-08-19 15:24:17 +0000 | [diff] [blame] | 153 | "expected 0x%p (GTT/VRAM offset " |
| 154 | "0x%16llx/0x%16llx)\n", |
| 155 | i, *vram_start, gtt_start, |
| 156 | (unsigned long long) |
| 157 | (gtt_addr - rdev->mc.gtt_start + |
| 158 | (void*)gtt_start - gtt_map), |
| 159 | (unsigned long long) |
| 160 | (vram_addr - rdev->mc.vram_start + |
| 161 | (void*)gtt_start - gtt_map)); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 162 | radeon_bo_kunmap(vram_obj); |
Maarten Lankhorst | 977c38d | 2013-06-27 13:48:26 +0200 | [diff] [blame] | 163 | goto out_lclean_unpin; |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 164 | } |
| 165 | *vram_start = vram_start; |
| 166 | } |
| 167 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 168 | radeon_bo_kunmap(vram_obj); |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 169 | |
Alex Deucher | 009ee7a | 2012-06-04 18:45:15 -0400 | [diff] [blame] | 170 | if (ring == R600_RING_TYPE_DMA_INDEX) |
| 171 | r = radeon_copy_dma(rdev, vram_addr, gtt_addr, size / RADEON_GPU_PAGE_SIZE, &fence); |
| 172 | else |
| 173 | r = radeon_copy_blit(rdev, vram_addr, gtt_addr, size / RADEON_GPU_PAGE_SIZE, &fence); |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 174 | if (r) { |
| 175 | DRM_ERROR("Failed VRAM->GTT copy %d\n", i); |
Maarten Lankhorst | 977c38d | 2013-06-27 13:48:26 +0200 | [diff] [blame] | 176 | goto out_lclean_unpin; |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 177 | } |
| 178 | |
| 179 | r = radeon_fence_wait(fence, false); |
| 180 | if (r) { |
| 181 | DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i); |
Maarten Lankhorst | 977c38d | 2013-06-27 13:48:26 +0200 | [diff] [blame] | 182 | goto out_lclean_unpin; |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 183 | } |
| 184 | |
| 185 | radeon_fence_unref(&fence); |
| 186 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 187 | r = radeon_bo_kmap(gtt_obj[i], >t_map); |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 188 | if (r) { |
| 189 | DRM_ERROR("Failed to map GTT object after copy %d\n", i); |
Maarten Lankhorst | 977c38d | 2013-06-27 13:48:26 +0200 | [diff] [blame] | 190 | goto out_lclean_unpin; |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 191 | } |
| 192 | |
| 193 | for (gtt_start = gtt_map, gtt_end = gtt_map + size, |
| 194 | vram_start = vram_map, vram_end = vram_map + size; |
| 195 | gtt_start < gtt_end; |
| 196 | gtt_start++, vram_start++) { |
| 197 | if (*gtt_start != vram_start) { |
| 198 | DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, " |
Michel Dänzer | 4fb1a35 | 2011-08-19 15:24:17 +0000 | [diff] [blame] | 199 | "expected 0x%p (VRAM/GTT offset " |
| 200 | "0x%16llx/0x%16llx)\n", |
| 201 | i, *gtt_start, vram_start, |
| 202 | (unsigned long long) |
| 203 | (vram_addr - rdev->mc.vram_start + |
| 204 | (void*)vram_start - vram_map), |
| 205 | (unsigned long long) |
| 206 | (gtt_addr - rdev->mc.gtt_start + |
| 207 | (void*)vram_start - vram_map)); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 208 | radeon_bo_kunmap(gtt_obj[i]); |
Maarten Lankhorst | 977c38d | 2013-06-27 13:48:26 +0200 | [diff] [blame] | 209 | goto out_lclean_unpin; |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 210 | } |
| 211 | } |
| 212 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 213 | radeon_bo_kunmap(gtt_obj[i]); |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 214 | |
| 215 | DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n", |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 216 | gtt_addr - rdev->mc.gtt_start); |
Maarten Lankhorst | 977c38d | 2013-06-27 13:48:26 +0200 | [diff] [blame] | 217 | continue; |
| 218 | |
| 219 | out_lclean_unpin: |
| 220 | radeon_bo_unpin(gtt_obj[i]); |
| 221 | out_lclean_unres: |
| 222 | radeon_bo_unreserve(gtt_obj[i]); |
| 223 | out_lclean_unref: |
| 224 | radeon_bo_unref(>t_obj[i]); |
| 225 | out_lclean: |
| 226 | for (--i; i >= 0; --i) { |
| 227 | radeon_bo_unpin(gtt_obj[i]); |
| 228 | radeon_bo_unreserve(gtt_obj[i]); |
| 229 | radeon_bo_unref(>t_obj[i]); |
| 230 | } |
| 231 | if (fence) |
| 232 | radeon_fence_unref(&fence); |
| 233 | break; |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 234 | } |
| 235 | |
Maarten Lankhorst | 977c38d | 2013-06-27 13:48:26 +0200 | [diff] [blame] | 236 | radeon_bo_unpin(vram_obj); |
| 237 | out_unres: |
| 238 | radeon_bo_unreserve(vram_obj); |
| 239 | out_unref: |
| 240 | radeon_bo_unref(&vram_obj); |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 241 | out_cleanup: |
Maarten Lankhorst | 977c38d | 2013-06-27 13:48:26 +0200 | [diff] [blame] | 242 | kfree(gtt_obj); |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 243 | if (r) { |
| 244 | printk(KERN_WARNING "Error while testing BO move.\n"); |
| 245 | } |
| 246 | } |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 247 | |
Alex Deucher | 009ee7a | 2012-06-04 18:45:15 -0400 | [diff] [blame] | 248 | void radeon_test_moves(struct radeon_device *rdev) |
| 249 | { |
| 250 | if (rdev->asic->copy.dma) |
| 251 | radeon_do_test_moves(rdev, RADEON_TEST_COPY_DMA); |
| 252 | if (rdev->asic->copy.blit) |
| 253 | radeon_do_test_moves(rdev, RADEON_TEST_COPY_BLIT); |
| 254 | } |
| 255 | |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 256 | static int radeon_test_create_and_emit_fence(struct radeon_device *rdev, |
| 257 | struct radeon_ring *ring, |
| 258 | struct radeon_fence **fence) |
| 259 | { |
| 260 | int r; |
| 261 | |
| 262 | if (ring->idx == R600_RING_TYPE_UVD_INDEX) { |
| 263 | r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL); |
| 264 | if (r) { |
| 265 | DRM_ERROR("Failed to get dummy create msg\n"); |
| 266 | return r; |
| 267 | } |
| 268 | |
| 269 | r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, fence); |
| 270 | if (r) { |
| 271 | DRM_ERROR("Failed to get dummy destroy msg\n"); |
| 272 | return r; |
| 273 | } |
| 274 | } else { |
| 275 | r = radeon_ring_lock(rdev, ring, 64); |
| 276 | if (r) { |
| 277 | DRM_ERROR("Failed to lock ring A %d\n", ring->idx); |
| 278 | return r; |
| 279 | } |
| 280 | radeon_fence_emit(rdev, fence, ring->idx); |
| 281 | radeon_ring_unlock_commit(rdev, ring); |
| 282 | } |
| 283 | return 0; |
| 284 | } |
| 285 | |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 286 | void radeon_test_ring_sync(struct radeon_device *rdev, |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 287 | struct radeon_ring *ringA, |
| 288 | struct radeon_ring *ringB) |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 289 | { |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 290 | struct radeon_fence *fence1 = NULL, *fence2 = NULL; |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 291 | struct radeon_semaphore *semaphore = NULL; |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 292 | int r; |
| 293 | |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 294 | r = radeon_semaphore_create(rdev, &semaphore); |
| 295 | if (r) { |
| 296 | DRM_ERROR("Failed to create semaphore\n"); |
| 297 | goto out_cleanup; |
| 298 | } |
| 299 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 300 | r = radeon_ring_lock(rdev, ringA, 64); |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 301 | if (r) { |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame] | 302 | DRM_ERROR("Failed to lock ring A %d\n", ringA->idx); |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 303 | goto out_cleanup; |
| 304 | } |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame] | 305 | radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore); |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 306 | radeon_ring_unlock_commit(rdev, ringA); |
| 307 | |
| 308 | r = radeon_test_create_and_emit_fence(rdev, ringA, &fence1); |
| 309 | if (r) |
| 310 | goto out_cleanup; |
| 311 | |
| 312 | r = radeon_ring_lock(rdev, ringA, 64); |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 313 | if (r) { |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 314 | DRM_ERROR("Failed to lock ring A %d\n", ringA->idx); |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 315 | goto out_cleanup; |
| 316 | } |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame] | 317 | radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 318 | radeon_ring_unlock_commit(rdev, ringA); |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 319 | |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 320 | r = radeon_test_create_and_emit_fence(rdev, ringA, &fence2); |
| 321 | if (r) |
| 322 | goto out_cleanup; |
| 323 | |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 324 | mdelay(1000); |
| 325 | |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 326 | if (radeon_fence_signaled(fence1)) { |
| 327 | DRM_ERROR("Fence 1 signaled without waiting for semaphore.\n"); |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 328 | goto out_cleanup; |
| 329 | } |
| 330 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 331 | r = radeon_ring_lock(rdev, ringB, 64); |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 332 | if (r) { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 333 | DRM_ERROR("Failed to lock ring B %p\n", ringB); |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 334 | goto out_cleanup; |
| 335 | } |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame] | 336 | radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 337 | radeon_ring_unlock_commit(rdev, ringB); |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 338 | |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 339 | r = radeon_fence_wait(fence1, false); |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 340 | if (r) { |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 341 | DRM_ERROR("Failed to wait for sync fence 1\n"); |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 342 | goto out_cleanup; |
| 343 | } |
| 344 | |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 345 | mdelay(1000); |
| 346 | |
| 347 | if (radeon_fence_signaled(fence2)) { |
| 348 | DRM_ERROR("Fence 2 signaled without waiting for semaphore.\n"); |
| 349 | goto out_cleanup; |
| 350 | } |
| 351 | |
| 352 | r = radeon_ring_lock(rdev, ringB, 64); |
| 353 | if (r) { |
| 354 | DRM_ERROR("Failed to lock ring B %p\n", ringB); |
| 355 | goto out_cleanup; |
| 356 | } |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame] | 357 | radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore); |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 358 | radeon_ring_unlock_commit(rdev, ringB); |
| 359 | |
| 360 | r = radeon_fence_wait(fence2, false); |
| 361 | if (r) { |
| 362 | DRM_ERROR("Failed to wait for sync fence 1\n"); |
| 363 | goto out_cleanup; |
| 364 | } |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 365 | |
| 366 | out_cleanup: |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 367 | radeon_semaphore_free(rdev, &semaphore, NULL); |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 368 | |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 369 | if (fence1) |
| 370 | radeon_fence_unref(&fence1); |
| 371 | |
| 372 | if (fence2) |
| 373 | radeon_fence_unref(&fence2); |
| 374 | |
| 375 | if (r) |
| 376 | printk(KERN_WARNING "Error while testing ring sync (%d).\n", r); |
| 377 | } |
| 378 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 379 | static void radeon_test_ring_sync2(struct radeon_device *rdev, |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 380 | struct radeon_ring *ringA, |
| 381 | struct radeon_ring *ringB, |
| 382 | struct radeon_ring *ringC) |
| 383 | { |
| 384 | struct radeon_fence *fenceA = NULL, *fenceB = NULL; |
| 385 | struct radeon_semaphore *semaphore = NULL; |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 386 | bool sigA, sigB; |
| 387 | int i, r; |
| 388 | |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 389 | r = radeon_semaphore_create(rdev, &semaphore); |
| 390 | if (r) { |
| 391 | DRM_ERROR("Failed to create semaphore\n"); |
| 392 | goto out_cleanup; |
| 393 | } |
| 394 | |
| 395 | r = radeon_ring_lock(rdev, ringA, 64); |
| 396 | if (r) { |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame] | 397 | DRM_ERROR("Failed to lock ring A %d\n", ringA->idx); |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 398 | goto out_cleanup; |
| 399 | } |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame] | 400 | radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore); |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 401 | radeon_ring_unlock_commit(rdev, ringA); |
| 402 | |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 403 | r = radeon_test_create_and_emit_fence(rdev, ringA, &fenceA); |
| 404 | if (r) |
| 405 | goto out_cleanup; |
| 406 | |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 407 | r = radeon_ring_lock(rdev, ringB, 64); |
| 408 | if (r) { |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame] | 409 | DRM_ERROR("Failed to lock ring B %d\n", ringB->idx); |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 410 | goto out_cleanup; |
| 411 | } |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame] | 412 | radeon_semaphore_emit_wait(rdev, ringB->idx, semaphore); |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 413 | radeon_ring_unlock_commit(rdev, ringB); |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 414 | r = radeon_test_create_and_emit_fence(rdev, ringB, &fenceB); |
| 415 | if (r) |
| 416 | goto out_cleanup; |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 417 | |
| 418 | mdelay(1000); |
| 419 | |
| 420 | if (radeon_fence_signaled(fenceA)) { |
| 421 | DRM_ERROR("Fence A signaled without waiting for semaphore.\n"); |
| 422 | goto out_cleanup; |
| 423 | } |
| 424 | if (radeon_fence_signaled(fenceB)) { |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 425 | DRM_ERROR("Fence B signaled without waiting for semaphore.\n"); |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 426 | goto out_cleanup; |
| 427 | } |
| 428 | |
| 429 | r = radeon_ring_lock(rdev, ringC, 64); |
| 430 | if (r) { |
| 431 | DRM_ERROR("Failed to lock ring B %p\n", ringC); |
| 432 | goto out_cleanup; |
| 433 | } |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame] | 434 | radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore); |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 435 | radeon_ring_unlock_commit(rdev, ringC); |
| 436 | |
| 437 | for (i = 0; i < 30; ++i) { |
| 438 | mdelay(100); |
| 439 | sigA = radeon_fence_signaled(fenceA); |
| 440 | sigB = radeon_fence_signaled(fenceB); |
| 441 | if (sigA || sigB) |
| 442 | break; |
| 443 | } |
| 444 | |
| 445 | if (!sigA && !sigB) { |
| 446 | DRM_ERROR("Neither fence A nor B has been signaled\n"); |
| 447 | goto out_cleanup; |
| 448 | } else if (sigA && sigB) { |
| 449 | DRM_ERROR("Both fence A and B has been signaled\n"); |
| 450 | goto out_cleanup; |
| 451 | } |
| 452 | |
| 453 | DRM_INFO("Fence %c was first signaled\n", sigA ? 'A' : 'B'); |
| 454 | |
| 455 | r = radeon_ring_lock(rdev, ringC, 64); |
| 456 | if (r) { |
| 457 | DRM_ERROR("Failed to lock ring B %p\n", ringC); |
| 458 | goto out_cleanup; |
| 459 | } |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame] | 460 | radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore); |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 461 | radeon_ring_unlock_commit(rdev, ringC); |
| 462 | |
| 463 | mdelay(1000); |
| 464 | |
| 465 | r = radeon_fence_wait(fenceA, false); |
| 466 | if (r) { |
| 467 | DRM_ERROR("Failed to wait for sync fence A\n"); |
| 468 | goto out_cleanup; |
| 469 | } |
| 470 | r = radeon_fence_wait(fenceB, false); |
| 471 | if (r) { |
| 472 | DRM_ERROR("Failed to wait for sync fence B\n"); |
| 473 | goto out_cleanup; |
| 474 | } |
| 475 | |
| 476 | out_cleanup: |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 477 | radeon_semaphore_free(rdev, &semaphore, NULL); |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 478 | |
| 479 | if (fenceA) |
| 480 | radeon_fence_unref(&fenceA); |
| 481 | |
| 482 | if (fenceB) |
| 483 | radeon_fence_unref(&fenceB); |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 484 | |
| 485 | if (r) |
| 486 | printk(KERN_WARNING "Error while testing ring sync (%d).\n", r); |
| 487 | } |
| 488 | |
| 489 | void radeon_test_syncing(struct radeon_device *rdev) |
| 490 | { |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 491 | int i, j, k; |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 492 | |
| 493 | for (i = 1; i < RADEON_NUM_RINGS; ++i) { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 494 | struct radeon_ring *ringA = &rdev->ring[i]; |
| 495 | if (!ringA->ready) |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 496 | continue; |
| 497 | |
| 498 | for (j = 0; j < i; ++j) { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 499 | struct radeon_ring *ringB = &rdev->ring[j]; |
| 500 | if (!ringB->ready) |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 501 | continue; |
| 502 | |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 503 | DRM_INFO("Testing syncing between rings %d and %d...\n", i, j); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 504 | radeon_test_ring_sync(rdev, ringA, ringB); |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 505 | |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 506 | DRM_INFO("Testing syncing between rings %d and %d...\n", j, i); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 507 | radeon_test_ring_sync(rdev, ringB, ringA); |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 508 | |
| 509 | for (k = 0; k < j; ++k) { |
| 510 | struct radeon_ring *ringC = &rdev->ring[k]; |
Alex Deucher | 1f2e124 | 2012-01-05 10:02:42 +0000 | [diff] [blame] | 511 | if (!ringC->ready) |
| 512 | continue; |
Christian König | ce95488 | 2011-11-17 15:22:44 +0100 | [diff] [blame] | 513 | |
| 514 | DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, j, k); |
| 515 | radeon_test_ring_sync2(rdev, ringA, ringB, ringC); |
| 516 | |
| 517 | DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, k, j); |
| 518 | radeon_test_ring_sync2(rdev, ringA, ringC, ringB); |
| 519 | |
| 520 | DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, i, k); |
| 521 | radeon_test_ring_sync2(rdev, ringB, ringA, ringC); |
| 522 | |
| 523 | DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, k, i); |
| 524 | radeon_test_ring_sync2(rdev, ringB, ringC, ringA); |
| 525 | |
| 526 | DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, i, j); |
| 527 | radeon_test_ring_sync2(rdev, ringC, ringA, ringB); |
| 528 | |
| 529 | DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, j, i); |
| 530 | radeon_test_ring_sync2(rdev, ringC, ringB, ringA); |
| 531 | } |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 532 | } |
| 533 | } |
| 534 | } |