Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 2 | * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * |
| 4 | * MIPS floating point support |
| 5 | * Copyright (C) 1994-2000 Algorithmics Ltd. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * |
| 7 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com |
| 8 | * Copyright (C) 2000 MIPS Technologies, Inc. |
| 9 | * |
| 10 | * This program is free software; you can distribute it and/or modify it |
| 11 | * under the terms of the GNU General Public License (Version 2) as |
| 12 | * published by the Free Software Foundation. |
| 13 | * |
| 14 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 17 | * for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License along |
| 20 | * with this program; if not, write to the Free Software Foundation, Inc., |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 21 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | * |
| 23 | * A complete emulator for MIPS coprocessor 1 instructions. This is |
| 24 | * required for #float(switch) or #float(trap), where it catches all |
| 25 | * COP1 instructions via the "CoProcessor Unusable" exception. |
| 26 | * |
| 27 | * More surprisingly it is also required for #float(ieee), to help out |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 28 | * the hardware FPU at the boundaries of the IEEE-754 representation |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | * (denormalised values, infinities, underflow, etc). It is made |
| 30 | * quite nasty because emulation of some non-COP1 instructions is |
| 31 | * required, e.g. in branch delay slots. |
| 32 | * |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 33 | * Note if you know that you won't have an FPU, then you'll get much |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | * better performance by compiling with -msoft-float! |
| 35 | */ |
| 36 | #include <linux/sched.h> |
Atsushi Nemoto | 83fd38c | 2007-07-07 23:21:49 +0900 | [diff] [blame] | 37 | #include <linux/debugfs.h> |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 38 | #include <linux/kconfig.h> |
Ralf Baechle | 85c51c5 | 2014-04-16 02:46:11 +0200 | [diff] [blame] | 39 | #include <linux/percpu-defs.h> |
Deng-Cheng Zhu | 7f788d2 | 2010-10-12 19:37:21 +0800 | [diff] [blame] | 40 | #include <linux/perf_event.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 41 | |
Ralf Baechle | cd8ee34 | 2014-04-16 02:09:53 +0200 | [diff] [blame] | 42 | #include <asm/branch.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | #include <asm/inst.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | #include <asm/ptrace.h> |
| 45 | #include <asm/signal.h> |
Ralf Baechle | cd8ee34 | 2014-04-16 02:09:53 +0200 | [diff] [blame] | 46 | #include <asm/uaccess.h> |
| 47 | |
| 48 | #include <asm/processor.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | #include <asm/fpu_emulator.h> |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 50 | #include <asm/fpu.h> |
Leonid Yegoshin | b0a668f | 2014-12-03 15:47:03 +0000 | [diff] [blame] | 51 | #include <asm/mips-r2-to-r6-emul.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 52 | |
| 53 | #include "ieee754.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 54 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | /* Function which emulates a floating point instruction. */ |
| 56 | |
Atsushi Nemoto | eae8907 | 2006-05-16 01:26:03 +0900 | [diff] [blame] | 57 | static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 58 | mips_instruction); |
| 59 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 60 | static int fpux_emu(struct pt_regs *, |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 61 | struct mips_fpu_struct *, mips_instruction, void *__user *); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 62 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 63 | /* Control registers */ |
| 64 | |
| 65 | #define FPCREG_RID 0 /* $0 = revision id */ |
| 66 | #define FPCREG_CSR 31 /* $31 = csr */ |
| 67 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 68 | /* convert condition code register number to csr bit */ |
Leonid Yegoshin | b0a668f | 2014-12-03 15:47:03 +0000 | [diff] [blame] | 69 | const unsigned int fpucondbit[8] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 70 | FPU_CSR_COND0, |
| 71 | FPU_CSR_COND1, |
| 72 | FPU_CSR_COND2, |
| 73 | FPU_CSR_COND3, |
| 74 | FPU_CSR_COND4, |
| 75 | FPU_CSR_COND5, |
| 76 | FPU_CSR_COND6, |
| 77 | FPU_CSR_COND7 |
| 78 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 79 | |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 80 | /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */ |
| 81 | static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; |
| 82 | static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; |
| 83 | static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; |
| 84 | static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; |
| 85 | |
| 86 | /* |
| 87 | * This functions translates a 32-bit microMIPS instruction |
| 88 | * into a 32-bit MIPS32 instruction. Returns 0 on success |
| 89 | * and SIGILL otherwise. |
| 90 | */ |
| 91 | static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) |
| 92 | { |
| 93 | union mips_instruction insn = *insn_ptr; |
| 94 | union mips_instruction mips32_insn = insn; |
| 95 | int func, fmt, op; |
| 96 | |
| 97 | switch (insn.mm_i_format.opcode) { |
| 98 | case mm_ldc132_op: |
| 99 | mips32_insn.mm_i_format.opcode = ldc1_op; |
| 100 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; |
| 101 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; |
| 102 | break; |
| 103 | case mm_lwc132_op: |
| 104 | mips32_insn.mm_i_format.opcode = lwc1_op; |
| 105 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; |
| 106 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; |
| 107 | break; |
| 108 | case mm_sdc132_op: |
| 109 | mips32_insn.mm_i_format.opcode = sdc1_op; |
| 110 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; |
| 111 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; |
| 112 | break; |
| 113 | case mm_swc132_op: |
| 114 | mips32_insn.mm_i_format.opcode = swc1_op; |
| 115 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; |
| 116 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; |
| 117 | break; |
| 118 | case mm_pool32i_op: |
| 119 | /* NOTE: offset is << by 1 if in microMIPS mode. */ |
| 120 | if ((insn.mm_i_format.rt == mm_bc1f_op) || |
| 121 | (insn.mm_i_format.rt == mm_bc1t_op)) { |
| 122 | mips32_insn.fb_format.opcode = cop1_op; |
| 123 | mips32_insn.fb_format.bc = bc_op; |
| 124 | mips32_insn.fb_format.flag = |
| 125 | (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; |
| 126 | } else |
| 127 | return SIGILL; |
| 128 | break; |
| 129 | case mm_pool32f_op: |
| 130 | switch (insn.mm_fp0_format.func) { |
| 131 | case mm_32f_01_op: |
| 132 | case mm_32f_11_op: |
| 133 | case mm_32f_02_op: |
| 134 | case mm_32f_12_op: |
| 135 | case mm_32f_41_op: |
| 136 | case mm_32f_51_op: |
| 137 | case mm_32f_42_op: |
| 138 | case mm_32f_52_op: |
| 139 | op = insn.mm_fp0_format.func; |
| 140 | if (op == mm_32f_01_op) |
| 141 | func = madd_s_op; |
| 142 | else if (op == mm_32f_11_op) |
| 143 | func = madd_d_op; |
| 144 | else if (op == mm_32f_02_op) |
| 145 | func = nmadd_s_op; |
| 146 | else if (op == mm_32f_12_op) |
| 147 | func = nmadd_d_op; |
| 148 | else if (op == mm_32f_41_op) |
| 149 | func = msub_s_op; |
| 150 | else if (op == mm_32f_51_op) |
| 151 | func = msub_d_op; |
| 152 | else if (op == mm_32f_42_op) |
| 153 | func = nmsub_s_op; |
| 154 | else |
| 155 | func = nmsub_d_op; |
| 156 | mips32_insn.fp6_format.opcode = cop1x_op; |
| 157 | mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; |
| 158 | mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; |
| 159 | mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; |
| 160 | mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; |
| 161 | mips32_insn.fp6_format.func = func; |
| 162 | break; |
| 163 | case mm_32f_10_op: |
| 164 | func = -1; /* Invalid */ |
| 165 | op = insn.mm_fp5_format.op & 0x7; |
| 166 | if (op == mm_ldxc1_op) |
| 167 | func = ldxc1_op; |
| 168 | else if (op == mm_sdxc1_op) |
| 169 | func = sdxc1_op; |
| 170 | else if (op == mm_lwxc1_op) |
| 171 | func = lwxc1_op; |
| 172 | else if (op == mm_swxc1_op) |
| 173 | func = swxc1_op; |
| 174 | |
| 175 | if (func != -1) { |
| 176 | mips32_insn.r_format.opcode = cop1x_op; |
| 177 | mips32_insn.r_format.rs = |
| 178 | insn.mm_fp5_format.base; |
| 179 | mips32_insn.r_format.rt = |
| 180 | insn.mm_fp5_format.index; |
| 181 | mips32_insn.r_format.rd = 0; |
| 182 | mips32_insn.r_format.re = insn.mm_fp5_format.fd; |
| 183 | mips32_insn.r_format.func = func; |
| 184 | } else |
| 185 | return SIGILL; |
| 186 | break; |
| 187 | case mm_32f_40_op: |
| 188 | op = -1; /* Invalid */ |
| 189 | if (insn.mm_fp2_format.op == mm_fmovt_op) |
| 190 | op = 1; |
| 191 | else if (insn.mm_fp2_format.op == mm_fmovf_op) |
| 192 | op = 0; |
| 193 | if (op != -1) { |
| 194 | mips32_insn.fp0_format.opcode = cop1_op; |
| 195 | mips32_insn.fp0_format.fmt = |
| 196 | sdps_format[insn.mm_fp2_format.fmt]; |
| 197 | mips32_insn.fp0_format.ft = |
| 198 | (insn.mm_fp2_format.cc<<2) + op; |
| 199 | mips32_insn.fp0_format.fs = |
| 200 | insn.mm_fp2_format.fs; |
| 201 | mips32_insn.fp0_format.fd = |
| 202 | insn.mm_fp2_format.fd; |
| 203 | mips32_insn.fp0_format.func = fmovc_op; |
| 204 | } else |
| 205 | return SIGILL; |
| 206 | break; |
| 207 | case mm_32f_60_op: |
| 208 | func = -1; /* Invalid */ |
| 209 | if (insn.mm_fp0_format.op == mm_fadd_op) |
| 210 | func = fadd_op; |
| 211 | else if (insn.mm_fp0_format.op == mm_fsub_op) |
| 212 | func = fsub_op; |
| 213 | else if (insn.mm_fp0_format.op == mm_fmul_op) |
| 214 | func = fmul_op; |
| 215 | else if (insn.mm_fp0_format.op == mm_fdiv_op) |
| 216 | func = fdiv_op; |
| 217 | if (func != -1) { |
| 218 | mips32_insn.fp0_format.opcode = cop1_op; |
| 219 | mips32_insn.fp0_format.fmt = |
| 220 | sdps_format[insn.mm_fp0_format.fmt]; |
| 221 | mips32_insn.fp0_format.ft = |
| 222 | insn.mm_fp0_format.ft; |
| 223 | mips32_insn.fp0_format.fs = |
| 224 | insn.mm_fp0_format.fs; |
| 225 | mips32_insn.fp0_format.fd = |
| 226 | insn.mm_fp0_format.fd; |
| 227 | mips32_insn.fp0_format.func = func; |
| 228 | } else |
| 229 | return SIGILL; |
| 230 | break; |
| 231 | case mm_32f_70_op: |
| 232 | func = -1; /* Invalid */ |
| 233 | if (insn.mm_fp0_format.op == mm_fmovn_op) |
| 234 | func = fmovn_op; |
| 235 | else if (insn.mm_fp0_format.op == mm_fmovz_op) |
| 236 | func = fmovz_op; |
| 237 | if (func != -1) { |
| 238 | mips32_insn.fp0_format.opcode = cop1_op; |
| 239 | mips32_insn.fp0_format.fmt = |
| 240 | sdps_format[insn.mm_fp0_format.fmt]; |
| 241 | mips32_insn.fp0_format.ft = |
| 242 | insn.mm_fp0_format.ft; |
| 243 | mips32_insn.fp0_format.fs = |
| 244 | insn.mm_fp0_format.fs; |
| 245 | mips32_insn.fp0_format.fd = |
| 246 | insn.mm_fp0_format.fd; |
| 247 | mips32_insn.fp0_format.func = func; |
| 248 | } else |
| 249 | return SIGILL; |
| 250 | break; |
| 251 | case mm_32f_73_op: /* POOL32FXF */ |
| 252 | switch (insn.mm_fp1_format.op) { |
| 253 | case mm_movf0_op: |
| 254 | case mm_movf1_op: |
| 255 | case mm_movt0_op: |
| 256 | case mm_movt1_op: |
| 257 | if ((insn.mm_fp1_format.op & 0x7f) == |
| 258 | mm_movf0_op) |
| 259 | op = 0; |
| 260 | else |
| 261 | op = 1; |
| 262 | mips32_insn.r_format.opcode = spec_op; |
| 263 | mips32_insn.r_format.rs = insn.mm_fp4_format.fs; |
| 264 | mips32_insn.r_format.rt = |
| 265 | (insn.mm_fp4_format.cc << 2) + op; |
| 266 | mips32_insn.r_format.rd = insn.mm_fp4_format.rt; |
| 267 | mips32_insn.r_format.re = 0; |
| 268 | mips32_insn.r_format.func = movc_op; |
| 269 | break; |
| 270 | case mm_fcvtd0_op: |
| 271 | case mm_fcvtd1_op: |
| 272 | case mm_fcvts0_op: |
| 273 | case mm_fcvts1_op: |
| 274 | if ((insn.mm_fp1_format.op & 0x7f) == |
| 275 | mm_fcvtd0_op) { |
| 276 | func = fcvtd_op; |
| 277 | fmt = swl_format[insn.mm_fp3_format.fmt]; |
| 278 | } else { |
| 279 | func = fcvts_op; |
| 280 | fmt = dwl_format[insn.mm_fp3_format.fmt]; |
| 281 | } |
| 282 | mips32_insn.fp0_format.opcode = cop1_op; |
| 283 | mips32_insn.fp0_format.fmt = fmt; |
| 284 | mips32_insn.fp0_format.ft = 0; |
| 285 | mips32_insn.fp0_format.fs = |
| 286 | insn.mm_fp3_format.fs; |
| 287 | mips32_insn.fp0_format.fd = |
| 288 | insn.mm_fp3_format.rt; |
| 289 | mips32_insn.fp0_format.func = func; |
| 290 | break; |
| 291 | case mm_fmov0_op: |
| 292 | case mm_fmov1_op: |
| 293 | case mm_fabs0_op: |
| 294 | case mm_fabs1_op: |
| 295 | case mm_fneg0_op: |
| 296 | case mm_fneg1_op: |
| 297 | if ((insn.mm_fp1_format.op & 0x7f) == |
| 298 | mm_fmov0_op) |
| 299 | func = fmov_op; |
| 300 | else if ((insn.mm_fp1_format.op & 0x7f) == |
| 301 | mm_fabs0_op) |
| 302 | func = fabs_op; |
| 303 | else |
| 304 | func = fneg_op; |
| 305 | mips32_insn.fp0_format.opcode = cop1_op; |
| 306 | mips32_insn.fp0_format.fmt = |
| 307 | sdps_format[insn.mm_fp3_format.fmt]; |
| 308 | mips32_insn.fp0_format.ft = 0; |
| 309 | mips32_insn.fp0_format.fs = |
| 310 | insn.mm_fp3_format.fs; |
| 311 | mips32_insn.fp0_format.fd = |
| 312 | insn.mm_fp3_format.rt; |
| 313 | mips32_insn.fp0_format.func = func; |
| 314 | break; |
| 315 | case mm_ffloorl_op: |
| 316 | case mm_ffloorw_op: |
| 317 | case mm_fceill_op: |
| 318 | case mm_fceilw_op: |
| 319 | case mm_ftruncl_op: |
| 320 | case mm_ftruncw_op: |
| 321 | case mm_froundl_op: |
| 322 | case mm_froundw_op: |
| 323 | case mm_fcvtl_op: |
| 324 | case mm_fcvtw_op: |
| 325 | if (insn.mm_fp1_format.op == mm_ffloorl_op) |
| 326 | func = ffloorl_op; |
| 327 | else if (insn.mm_fp1_format.op == mm_ffloorw_op) |
| 328 | func = ffloor_op; |
| 329 | else if (insn.mm_fp1_format.op == mm_fceill_op) |
| 330 | func = fceill_op; |
| 331 | else if (insn.mm_fp1_format.op == mm_fceilw_op) |
| 332 | func = fceil_op; |
| 333 | else if (insn.mm_fp1_format.op == mm_ftruncl_op) |
| 334 | func = ftruncl_op; |
| 335 | else if (insn.mm_fp1_format.op == mm_ftruncw_op) |
| 336 | func = ftrunc_op; |
| 337 | else if (insn.mm_fp1_format.op == mm_froundl_op) |
| 338 | func = froundl_op; |
| 339 | else if (insn.mm_fp1_format.op == mm_froundw_op) |
| 340 | func = fround_op; |
| 341 | else if (insn.mm_fp1_format.op == mm_fcvtl_op) |
| 342 | func = fcvtl_op; |
| 343 | else |
| 344 | func = fcvtw_op; |
| 345 | mips32_insn.fp0_format.opcode = cop1_op; |
| 346 | mips32_insn.fp0_format.fmt = |
| 347 | sd_format[insn.mm_fp1_format.fmt]; |
| 348 | mips32_insn.fp0_format.ft = 0; |
| 349 | mips32_insn.fp0_format.fs = |
| 350 | insn.mm_fp1_format.fs; |
| 351 | mips32_insn.fp0_format.fd = |
| 352 | insn.mm_fp1_format.rt; |
| 353 | mips32_insn.fp0_format.func = func; |
| 354 | break; |
| 355 | case mm_frsqrt_op: |
| 356 | case mm_fsqrt_op: |
| 357 | case mm_frecip_op: |
| 358 | if (insn.mm_fp1_format.op == mm_frsqrt_op) |
| 359 | func = frsqrt_op; |
| 360 | else if (insn.mm_fp1_format.op == mm_fsqrt_op) |
| 361 | func = fsqrt_op; |
| 362 | else |
| 363 | func = frecip_op; |
| 364 | mips32_insn.fp0_format.opcode = cop1_op; |
| 365 | mips32_insn.fp0_format.fmt = |
| 366 | sdps_format[insn.mm_fp1_format.fmt]; |
| 367 | mips32_insn.fp0_format.ft = 0; |
| 368 | mips32_insn.fp0_format.fs = |
| 369 | insn.mm_fp1_format.fs; |
| 370 | mips32_insn.fp0_format.fd = |
| 371 | insn.mm_fp1_format.rt; |
| 372 | mips32_insn.fp0_format.func = func; |
| 373 | break; |
| 374 | case mm_mfc1_op: |
| 375 | case mm_mtc1_op: |
| 376 | case mm_cfc1_op: |
| 377 | case mm_ctc1_op: |
Steven J. Hill | 9355e59 | 2013-11-07 12:48:29 +0000 | [diff] [blame] | 378 | case mm_mfhc1_op: |
| 379 | case mm_mthc1_op: |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 380 | if (insn.mm_fp1_format.op == mm_mfc1_op) |
| 381 | op = mfc_op; |
| 382 | else if (insn.mm_fp1_format.op == mm_mtc1_op) |
| 383 | op = mtc_op; |
| 384 | else if (insn.mm_fp1_format.op == mm_cfc1_op) |
| 385 | op = cfc_op; |
Steven J. Hill | 9355e59 | 2013-11-07 12:48:29 +0000 | [diff] [blame] | 386 | else if (insn.mm_fp1_format.op == mm_ctc1_op) |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 387 | op = ctc_op; |
Steven J. Hill | 9355e59 | 2013-11-07 12:48:29 +0000 | [diff] [blame] | 388 | else if (insn.mm_fp1_format.op == mm_mfhc1_op) |
| 389 | op = mfhc_op; |
| 390 | else |
| 391 | op = mthc_op; |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 392 | mips32_insn.fp1_format.opcode = cop1_op; |
| 393 | mips32_insn.fp1_format.op = op; |
| 394 | mips32_insn.fp1_format.rt = |
| 395 | insn.mm_fp1_format.rt; |
| 396 | mips32_insn.fp1_format.fs = |
| 397 | insn.mm_fp1_format.fs; |
| 398 | mips32_insn.fp1_format.fd = 0; |
| 399 | mips32_insn.fp1_format.func = 0; |
| 400 | break; |
| 401 | default: |
| 402 | return SIGILL; |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 403 | } |
| 404 | break; |
| 405 | case mm_32f_74_op: /* c.cond.fmt */ |
| 406 | mips32_insn.fp0_format.opcode = cop1_op; |
| 407 | mips32_insn.fp0_format.fmt = |
| 408 | sdps_format[insn.mm_fp4_format.fmt]; |
| 409 | mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; |
| 410 | mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; |
| 411 | mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2; |
| 412 | mips32_insn.fp0_format.func = |
| 413 | insn.mm_fp4_format.cond | MM_MIPS32_COND_FC; |
| 414 | break; |
| 415 | default: |
| 416 | return SIGILL; |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 417 | } |
| 418 | break; |
| 419 | default: |
| 420 | return SIGILL; |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 421 | } |
| 422 | |
| 423 | *insn_ptr = mips32_insn; |
| 424 | return 0; |
| 425 | } |
| 426 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 427 | /* |
| 428 | * Redundant with logic already in kernel/branch.c, |
| 429 | * embedded in compute_return_epc. At some point, |
| 430 | * a single subroutine should be used across both |
| 431 | * modules. |
| 432 | */ |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 433 | static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, |
| 434 | unsigned long *contpc) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 435 | { |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 436 | union mips_instruction insn = (union mips_instruction)dec_insn.insn; |
| 437 | unsigned int fcr31; |
| 438 | unsigned int bit = 0; |
| 439 | |
| 440 | switch (insn.i_format.opcode) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 441 | case spec_op: |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 442 | switch (insn.r_format.func) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 443 | case jalr_op: |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 444 | regs->regs[insn.r_format.rd] = |
| 445 | regs->cp0_epc + dec_insn.pc_inc + |
| 446 | dec_insn.next_pc_inc; |
| 447 | /* Fall through */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 448 | case jr_op: |
Markos Chandras | 5f9f41c | 2014-11-25 15:54:14 +0000 | [diff] [blame] | 449 | /* For R6, JR already emulated in jalr_op */ |
| 450 | if (NO_R6EMU && insn.r_format.opcode == jr_op) |
| 451 | break; |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 452 | *contpc = regs->regs[insn.r_format.rs]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 453 | return 1; |
| 454 | } |
| 455 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 456 | case bcond_op: |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 457 | switch (insn.i_format.rt) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 458 | case bltzal_op: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 459 | case bltzall_op: |
Markos Chandras | 319824e | 2014-11-25 16:02:23 +0000 | [diff] [blame] | 460 | if (NO_R6EMU && (insn.i_format.rs || |
| 461 | insn.i_format.rt == bltzall_op)) |
| 462 | break; |
| 463 | |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 464 | regs->regs[31] = regs->cp0_epc + |
| 465 | dec_insn.pc_inc + |
| 466 | dec_insn.next_pc_inc; |
| 467 | /* Fall through */ |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 468 | case bltzl_op: |
Markos Chandras | 319824e | 2014-11-25 16:02:23 +0000 | [diff] [blame] | 469 | if (NO_R6EMU) |
| 470 | break; |
| 471 | case bltz_op: |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 472 | if ((long)regs->regs[insn.i_format.rs] < 0) |
| 473 | *contpc = regs->cp0_epc + |
| 474 | dec_insn.pc_inc + |
| 475 | (insn.i_format.simmediate << 2); |
| 476 | else |
| 477 | *contpc = regs->cp0_epc + |
| 478 | dec_insn.pc_inc + |
| 479 | dec_insn.next_pc_inc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 480 | return 1; |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 481 | case bgezal_op: |
| 482 | case bgezall_op: |
Markos Chandras | 319824e | 2014-11-25 16:02:23 +0000 | [diff] [blame] | 483 | if (NO_R6EMU && (insn.i_format.rs || |
| 484 | insn.i_format.rt == bgezall_op)) |
| 485 | break; |
| 486 | |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 487 | regs->regs[31] = regs->cp0_epc + |
| 488 | dec_insn.pc_inc + |
| 489 | dec_insn.next_pc_inc; |
| 490 | /* Fall through */ |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 491 | case bgezl_op: |
Markos Chandras | 319824e | 2014-11-25 16:02:23 +0000 | [diff] [blame] | 492 | if (NO_R6EMU) |
| 493 | break; |
| 494 | case bgez_op: |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 495 | if ((long)regs->regs[insn.i_format.rs] >= 0) |
| 496 | *contpc = regs->cp0_epc + |
| 497 | dec_insn.pc_inc + |
| 498 | (insn.i_format.simmediate << 2); |
| 499 | else |
| 500 | *contpc = regs->cp0_epc + |
| 501 | dec_insn.pc_inc + |
| 502 | dec_insn.next_pc_inc; |
| 503 | return 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 504 | } |
| 505 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 506 | case jalx_op: |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 507 | set_isa16_mode(bit); |
| 508 | case jal_op: |
| 509 | regs->regs[31] = regs->cp0_epc + |
| 510 | dec_insn.pc_inc + |
| 511 | dec_insn.next_pc_inc; |
| 512 | /* Fall through */ |
| 513 | case j_op: |
| 514 | *contpc = regs->cp0_epc + dec_insn.pc_inc; |
| 515 | *contpc >>= 28; |
| 516 | *contpc <<= 28; |
| 517 | *contpc |= (insn.j_format.target << 2); |
| 518 | /* Set microMIPS mode bit: XOR for jalx. */ |
| 519 | *contpc ^= bit; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 520 | return 1; |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 521 | case beql_op: |
Markos Chandras | 319824e | 2014-11-25 16:02:23 +0000 | [diff] [blame] | 522 | if (NO_R6EMU) |
| 523 | break; |
| 524 | case beq_op: |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 525 | if (regs->regs[insn.i_format.rs] == |
| 526 | regs->regs[insn.i_format.rt]) |
| 527 | *contpc = regs->cp0_epc + |
| 528 | dec_insn.pc_inc + |
| 529 | (insn.i_format.simmediate << 2); |
| 530 | else |
| 531 | *contpc = regs->cp0_epc + |
| 532 | dec_insn.pc_inc + |
| 533 | dec_insn.next_pc_inc; |
| 534 | return 1; |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 535 | case bnel_op: |
Markos Chandras | 319824e | 2014-11-25 16:02:23 +0000 | [diff] [blame] | 536 | if (NO_R6EMU) |
| 537 | break; |
| 538 | case bne_op: |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 539 | if (regs->regs[insn.i_format.rs] != |
| 540 | regs->regs[insn.i_format.rt]) |
| 541 | *contpc = regs->cp0_epc + |
| 542 | dec_insn.pc_inc + |
| 543 | (insn.i_format.simmediate << 2); |
| 544 | else |
| 545 | *contpc = regs->cp0_epc + |
| 546 | dec_insn.pc_inc + |
| 547 | dec_insn.next_pc_inc; |
| 548 | return 1; |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 549 | case blezl_op: |
Markos Chandras | 319824e | 2014-11-25 16:02:23 +0000 | [diff] [blame] | 550 | if (NO_R6EMU) |
| 551 | break; |
| 552 | case blez_op: |
Markos Chandras | a8ff66f | 2014-11-26 12:57:54 +0000 | [diff] [blame] | 553 | |
| 554 | /* |
| 555 | * Compact branches for R6 for the |
| 556 | * blez and blezl opcodes. |
| 557 | * BLEZ | rs = 0 | rt != 0 == BLEZALC |
| 558 | * BLEZ | rs = rt != 0 == BGEZALC |
| 559 | * BLEZ | rs != 0 | rt != 0 == BGEUC |
| 560 | * BLEZL | rs = 0 | rt != 0 == BLEZC |
| 561 | * BLEZL | rs = rt != 0 == BGEZC |
| 562 | * BLEZL | rs != 0 | rt != 0 == BGEC |
| 563 | * |
| 564 | * For real BLEZ{,L}, rt is always 0. |
| 565 | */ |
| 566 | if (cpu_has_mips_r6 && insn.i_format.rt) { |
| 567 | if ((insn.i_format.opcode == blez_op) && |
| 568 | ((!insn.i_format.rs && insn.i_format.rt) || |
| 569 | (insn.i_format.rs == insn.i_format.rt))) |
| 570 | regs->regs[31] = regs->cp0_epc + |
| 571 | dec_insn.pc_inc; |
| 572 | *contpc = regs->cp0_epc + dec_insn.pc_inc + |
| 573 | dec_insn.next_pc_inc; |
| 574 | |
| 575 | return 1; |
| 576 | } |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 577 | if ((long)regs->regs[insn.i_format.rs] <= 0) |
| 578 | *contpc = regs->cp0_epc + |
| 579 | dec_insn.pc_inc + |
| 580 | (insn.i_format.simmediate << 2); |
| 581 | else |
| 582 | *contpc = regs->cp0_epc + |
| 583 | dec_insn.pc_inc + |
| 584 | dec_insn.next_pc_inc; |
| 585 | return 1; |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 586 | case bgtzl_op: |
Markos Chandras | 319824e | 2014-11-25 16:02:23 +0000 | [diff] [blame] | 587 | if (NO_R6EMU) |
| 588 | break; |
| 589 | case bgtz_op: |
Markos Chandras | f1b4406 | 2014-11-26 13:05:09 +0000 | [diff] [blame] | 590 | /* |
| 591 | * Compact branches for R6 for the |
| 592 | * bgtz and bgtzl opcodes. |
| 593 | * BGTZ | rs = 0 | rt != 0 == BGTZALC |
| 594 | * BGTZ | rs = rt != 0 == BLTZALC |
| 595 | * BGTZ | rs != 0 | rt != 0 == BLTUC |
| 596 | * BGTZL | rs = 0 | rt != 0 == BGTZC |
| 597 | * BGTZL | rs = rt != 0 == BLTZC |
| 598 | * BGTZL | rs != 0 | rt != 0 == BLTC |
| 599 | * |
| 600 | * *ZALC varint for BGTZ &&& rt != 0 |
| 601 | * For real GTZ{,L}, rt is always 0. |
| 602 | */ |
| 603 | if (cpu_has_mips_r6 && insn.i_format.rt) { |
| 604 | if ((insn.i_format.opcode == blez_op) && |
| 605 | ((!insn.i_format.rs && insn.i_format.rt) || |
| 606 | (insn.i_format.rs == insn.i_format.rt))) |
| 607 | regs->regs[31] = regs->cp0_epc + |
| 608 | dec_insn.pc_inc; |
| 609 | *contpc = regs->cp0_epc + dec_insn.pc_inc + |
| 610 | dec_insn.next_pc_inc; |
| 611 | |
| 612 | return 1; |
| 613 | } |
| 614 | |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 615 | if ((long)regs->regs[insn.i_format.rs] > 0) |
| 616 | *contpc = regs->cp0_epc + |
| 617 | dec_insn.pc_inc + |
| 618 | (insn.i_format.simmediate << 2); |
| 619 | else |
| 620 | *contpc = regs->cp0_epc + |
| 621 | dec_insn.pc_inc + |
| 622 | dec_insn.next_pc_inc; |
| 623 | return 1; |
Markos Chandras | c893ce3 | 2014-11-26 14:08:52 +0000 | [diff] [blame] | 624 | case cbcond0_op: |
Markos Chandras | 10d962d | 2014-11-26 15:03:54 +0000 | [diff] [blame] | 625 | case cbcond1_op: |
Markos Chandras | c893ce3 | 2014-11-26 14:08:52 +0000 | [diff] [blame] | 626 | if (!cpu_has_mips_r6) |
| 627 | break; |
| 628 | if (insn.i_format.rt && !insn.i_format.rs) |
| 629 | regs->regs[31] = regs->cp0_epc + 4; |
| 630 | *contpc = regs->cp0_epc + dec_insn.pc_inc + |
| 631 | dec_insn.next_pc_inc; |
| 632 | |
| 633 | return 1; |
David Daney | c26d421 | 2013-08-19 12:10:34 -0700 | [diff] [blame] | 634 | #ifdef CONFIG_CPU_CAVIUM_OCTEON |
| 635 | case lwc2_op: /* This is bbit0 on Octeon */ |
| 636 | if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) |
| 637 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); |
| 638 | else |
| 639 | *contpc = regs->cp0_epc + 8; |
| 640 | return 1; |
| 641 | case ldc2_op: /* This is bbit032 on Octeon */ |
| 642 | if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0) |
| 643 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); |
| 644 | else |
| 645 | *contpc = regs->cp0_epc + 8; |
| 646 | return 1; |
| 647 | case swc2_op: /* This is bbit1 on Octeon */ |
| 648 | if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) |
| 649 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); |
| 650 | else |
| 651 | *contpc = regs->cp0_epc + 8; |
| 652 | return 1; |
| 653 | case sdc2_op: /* This is bbit132 on Octeon */ |
| 654 | if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) |
| 655 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); |
| 656 | else |
| 657 | *contpc = regs->cp0_epc + 8; |
| 658 | return 1; |
Markos Chandras | 8467ca0 | 2014-11-26 13:56:51 +0000 | [diff] [blame] | 659 | #else |
| 660 | case bc6_op: |
| 661 | /* |
| 662 | * Only valid for MIPS R6 but we can still end up |
| 663 | * here from a broken userland so just tell emulator |
| 664 | * this is not a branch and let it break later on. |
| 665 | */ |
| 666 | if (!cpu_has_mips_r6) |
| 667 | break; |
| 668 | *contpc = regs->cp0_epc + dec_insn.pc_inc + |
| 669 | dec_insn.next_pc_inc; |
| 670 | |
| 671 | return 1; |
Markos Chandras | 84fef63 | 2014-11-26 15:43:11 +0000 | [diff] [blame] | 672 | case balc6_op: |
| 673 | if (!cpu_has_mips_r6) |
| 674 | break; |
| 675 | regs->regs[31] = regs->cp0_epc + 4; |
| 676 | *contpc = regs->cp0_epc + dec_insn.pc_inc + |
| 677 | dec_insn.next_pc_inc; |
| 678 | |
| 679 | return 1; |
Markos Chandras | 69b9a2f | 2014-11-27 09:32:25 +0000 | [diff] [blame] | 680 | case beqzcjic_op: |
| 681 | if (!cpu_has_mips_r6) |
| 682 | break; |
| 683 | *contpc = regs->cp0_epc + dec_insn.pc_inc + |
| 684 | dec_insn.next_pc_inc; |
| 685 | |
| 686 | return 1; |
Markos Chandras | 28d6f93 | 2015-01-08 11:55:20 +0000 | [diff] [blame] | 687 | case bnezcjialc_op: |
| 688 | if (!cpu_has_mips_r6) |
| 689 | break; |
| 690 | if (!insn.i_format.rs) |
| 691 | regs->regs[31] = regs->cp0_epc + 4; |
| 692 | *contpc = regs->cp0_epc + dec_insn.pc_inc + |
| 693 | dec_insn.next_pc_inc; |
| 694 | |
| 695 | return 1; |
David Daney | c26d421 | 2013-08-19 12:10:34 -0700 | [diff] [blame] | 696 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 697 | case cop0_op: |
| 698 | case cop1_op: |
Markos Chandras | c8a3458 | 2014-11-26 10:10:18 +0000 | [diff] [blame] | 699 | /* Need to check for R6 bc1nez and bc1eqz branches */ |
| 700 | if (cpu_has_mips_r6 && |
| 701 | ((insn.i_format.rs == bc1eqz_op) || |
| 702 | (insn.i_format.rs == bc1nez_op))) { |
| 703 | bit = 0; |
| 704 | switch (insn.i_format.rs) { |
| 705 | case bc1eqz_op: |
| 706 | if (get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1) |
| 707 | bit = 1; |
| 708 | break; |
| 709 | case bc1nez_op: |
| 710 | if (!(get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)) |
| 711 | bit = 1; |
| 712 | break; |
| 713 | } |
| 714 | if (bit) |
| 715 | *contpc = regs->cp0_epc + |
| 716 | dec_insn.pc_inc + |
| 717 | (insn.i_format.simmediate << 2); |
| 718 | else |
| 719 | *contpc = regs->cp0_epc + |
| 720 | dec_insn.pc_inc + |
| 721 | dec_insn.next_pc_inc; |
| 722 | |
| 723 | return 1; |
| 724 | } |
| 725 | /* R2/R6 compatible cop1 instruction. Fall through */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 726 | case cop2_op: |
| 727 | case cop1x_op: |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 728 | if (insn.i_format.rs == bc_op) { |
| 729 | preempt_disable(); |
| 730 | if (is_fpu_owner()) |
Manuel Lauss | 842dfc1 | 2014-11-07 14:13:54 +0100 | [diff] [blame] | 731 | fcr31 = read_32bit_cp1_register(CP1_STATUS); |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 732 | else |
| 733 | fcr31 = current->thread.fpu.fcr31; |
| 734 | preempt_enable(); |
| 735 | |
| 736 | bit = (insn.i_format.rt >> 2); |
| 737 | bit += (bit != 0); |
| 738 | bit += 23; |
| 739 | switch (insn.i_format.rt & 3) { |
| 740 | case 0: /* bc1f */ |
| 741 | case 2: /* bc1fl */ |
| 742 | if (~fcr31 & (1 << bit)) |
| 743 | *contpc = regs->cp0_epc + |
| 744 | dec_insn.pc_inc + |
| 745 | (insn.i_format.simmediate << 2); |
| 746 | else |
| 747 | *contpc = regs->cp0_epc + |
| 748 | dec_insn.pc_inc + |
| 749 | dec_insn.next_pc_inc; |
| 750 | return 1; |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 751 | case 1: /* bc1t */ |
| 752 | case 3: /* bc1tl */ |
| 753 | if (fcr31 & (1 << bit)) |
| 754 | *contpc = regs->cp0_epc + |
| 755 | dec_insn.pc_inc + |
| 756 | (insn.i_format.simmediate << 2); |
| 757 | else |
| 758 | *contpc = regs->cp0_epc + |
| 759 | dec_insn.pc_inc + |
| 760 | dec_insn.next_pc_inc; |
| 761 | return 1; |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 762 | } |
| 763 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 764 | break; |
| 765 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 766 | return 0; |
| 767 | } |
| 768 | |
| 769 | /* |
| 770 | * In the Linux kernel, we support selection of FPR format on the |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 771 | * basis of the Status.FR bit. If an FPU is not present, the FR bit |
David Daney | da0bac3 | 2009-11-02 11:33:46 -0800 | [diff] [blame] | 772 | * is hardwired to zero, which would imply a 32-bit FPU even for |
Paul Burton | 597ce17 | 2013-11-22 13:12:07 +0000 | [diff] [blame] | 773 | * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS. |
Ralf Baechle | 51d943f | 2012-08-15 19:42:19 +0200 | [diff] [blame] | 774 | * FPU emu is slow and bulky and optimizing this function offers fairly |
| 775 | * sizeable benefits so we try to be clever and make this function return |
| 776 | * a constant whenever possible, that is on 64-bit kernels without O32 |
Paul Burton | 597ce17 | 2013-11-22 13:12:07 +0000 | [diff] [blame] | 777 | * compatibility enabled and on 32-bit without 64-bit FPU support. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 778 | */ |
David Daney | da0bac3 | 2009-11-02 11:33:46 -0800 | [diff] [blame] | 779 | static inline int cop1_64bit(struct pt_regs *xcp) |
| 780 | { |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 781 | if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32)) |
| 782 | return 1; |
| 783 | else if (config_enabled(CONFIG_32BIT) && |
| 784 | !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT)) |
| 785 | return 0; |
| 786 | |
Paul Burton | 597ce17 | 2013-11-22 13:12:07 +0000 | [diff] [blame] | 787 | return !test_thread_flag(TIF_32BIT_FPREGS); |
David Daney | da0bac3 | 2009-11-02 11:33:46 -0800 | [diff] [blame] | 788 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 789 | |
Paul Burton | 4227a2d | 2014-09-11 08:30:20 +0100 | [diff] [blame] | 790 | static inline bool hybrid_fprs(void) |
| 791 | { |
| 792 | return test_thread_flag(TIF_HYBRID_FPREGS); |
| 793 | } |
| 794 | |
Ralf Baechle | 47fa0c0 | 2014-04-16 11:00:12 +0200 | [diff] [blame] | 795 | #define SIFROMREG(si, x) \ |
| 796 | do { \ |
Paul Burton | 4227a2d | 2014-09-11 08:30:20 +0100 | [diff] [blame] | 797 | if (cop1_64bit(xcp) && !hybrid_fprs()) \ |
Paul Burton | c8c0da6 | 2014-09-24 10:45:37 +0100 | [diff] [blame] | 798 | (si) = (int)get_fpr32(&ctx->fpr[x], 0); \ |
Paul Burton | bbd426f | 2014-02-13 11:26:41 +0000 | [diff] [blame] | 799 | else \ |
Paul Burton | c8c0da6 | 2014-09-24 10:45:37 +0100 | [diff] [blame] | 800 | (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \ |
Paul Burton | bbd426f | 2014-02-13 11:26:41 +0000 | [diff] [blame] | 801 | } while (0) |
David Daney | da0bac3 | 2009-11-02 11:33:46 -0800 | [diff] [blame] | 802 | |
Ralf Baechle | 47fa0c0 | 2014-04-16 11:00:12 +0200 | [diff] [blame] | 803 | #define SITOREG(si, x) \ |
| 804 | do { \ |
Paul Burton | 4227a2d | 2014-09-11 08:30:20 +0100 | [diff] [blame] | 805 | if (cop1_64bit(xcp) && !hybrid_fprs()) { \ |
Paul Burton | ef1c47a | 2014-01-27 17:14:47 +0000 | [diff] [blame] | 806 | unsigned i; \ |
Paul Burton | bbd426f | 2014-02-13 11:26:41 +0000 | [diff] [blame] | 807 | set_fpr32(&ctx->fpr[x], 0, si); \ |
Paul Burton | ef1c47a | 2014-01-27 17:14:47 +0000 | [diff] [blame] | 808 | for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ |
| 809 | set_fpr32(&ctx->fpr[x], i, 0); \ |
| 810 | } else { \ |
Paul Burton | bbd426f | 2014-02-13 11:26:41 +0000 | [diff] [blame] | 811 | set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \ |
Paul Burton | ef1c47a | 2014-01-27 17:14:47 +0000 | [diff] [blame] | 812 | } \ |
Paul Burton | bbd426f | 2014-02-13 11:26:41 +0000 | [diff] [blame] | 813 | } while (0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 814 | |
Paul Burton | c8c0da6 | 2014-09-24 10:45:37 +0100 | [diff] [blame] | 815 | #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1)) |
Paul Burton | ef1c47a | 2014-01-27 17:14:47 +0000 | [diff] [blame] | 816 | |
Ralf Baechle | 47fa0c0 | 2014-04-16 11:00:12 +0200 | [diff] [blame] | 817 | #define SITOHREG(si, x) \ |
| 818 | do { \ |
Paul Burton | ef1c47a | 2014-01-27 17:14:47 +0000 | [diff] [blame] | 819 | unsigned i; \ |
| 820 | set_fpr32(&ctx->fpr[x], 1, si); \ |
| 821 | for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ |
| 822 | set_fpr32(&ctx->fpr[x], i, 0); \ |
| 823 | } while (0) |
Leonid Yegoshin | 1ac94400 | 2013-11-07 12:48:28 +0000 | [diff] [blame] | 824 | |
Ralf Baechle | 47fa0c0 | 2014-04-16 11:00:12 +0200 | [diff] [blame] | 825 | #define DIFROMREG(di, x) \ |
Paul Burton | bbd426f | 2014-02-13 11:26:41 +0000 | [diff] [blame] | 826 | ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0)) |
| 827 | |
Ralf Baechle | 47fa0c0 | 2014-04-16 11:00:12 +0200 | [diff] [blame] | 828 | #define DITOREG(di, x) \ |
| 829 | do { \ |
Paul Burton | ef1c47a | 2014-01-27 17:14:47 +0000 | [diff] [blame] | 830 | unsigned fpr, i; \ |
| 831 | fpr = (x) & ~(cop1_64bit(xcp) == 0); \ |
| 832 | set_fpr64(&ctx->fpr[fpr], 0, di); \ |
| 833 | for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \ |
| 834 | set_fpr64(&ctx->fpr[fpr], i, 0); \ |
| 835 | } while (0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 836 | |
Ralf Baechle | 21a151d | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 837 | #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) |
| 838 | #define SPTOREG(sp, x) SITOREG((sp).bits, x) |
| 839 | #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) |
| 840 | #define DPTOREG(dp, x) DITOREG((dp).bits, x) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 841 | |
| 842 | /* |
| 843 | * Emulate the single floating point instruction pointed at by EPC. |
| 844 | * Two instructions if the instruction is in a branch delay slot. |
| 845 | */ |
| 846 | |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 847 | static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 848 | struct mm_decoded_insn dec_insn, void *__user *fault_addr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 849 | { |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 850 | unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 851 | unsigned int cond, cbit; |
| 852 | mips_instruction ir; |
| 853 | int likely, pc_inc; |
| 854 | u32 __user *wva; |
| 855 | u64 __user *dva; |
| 856 | u32 value; |
| 857 | u32 wval; |
| 858 | u64 dval; |
| 859 | int sig; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 860 | |
Ralf Baechle | 70e4c23 | 2014-04-30 11:09:44 +0200 | [diff] [blame] | 861 | /* |
| 862 | * These are giving gcc a gentle hint about what to expect in |
| 863 | * dec_inst in order to do better optimization. |
| 864 | */ |
| 865 | if (!cpu_has_mmips && dec_insn.micro_mips_mode) |
| 866 | unreachable(); |
| 867 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 868 | /* XXX NEC Vr54xx bug workaround */ |
Ralf Baechle | e7e9cae | 2014-04-16 01:59:03 +0200 | [diff] [blame] | 869 | if (delay_slot(xcp)) { |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 870 | if (dec_insn.micro_mips_mode) { |
| 871 | if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) |
Ralf Baechle | e7e9cae | 2014-04-16 01:59:03 +0200 | [diff] [blame] | 872 | clear_delay_slot(xcp); |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 873 | } else { |
| 874 | if (!isBranchInstr(xcp, dec_insn, &contpc)) |
Ralf Baechle | e7e9cae | 2014-04-16 01:59:03 +0200 | [diff] [blame] | 875 | clear_delay_slot(xcp); |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 876 | } |
| 877 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 878 | |
Ralf Baechle | e7e9cae | 2014-04-16 01:59:03 +0200 | [diff] [blame] | 879 | if (delay_slot(xcp)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 880 | /* |
| 881 | * The instruction to be emulated is in a branch delay slot |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 882 | * which means that we have to emulate the branch instruction |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 883 | * BEFORE we do the cop1 instruction. |
| 884 | * |
| 885 | * This branch could be a COP1 branch, but in that case we |
| 886 | * would have had a trap for that instruction, and would not |
| 887 | * come through this route. |
| 888 | * |
| 889 | * Linux MIPS branch emulator operates on context, updating the |
| 890 | * cp0_epc. |
| 891 | */ |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 892 | ir = dec_insn.next_insn; /* process delay slot instr */ |
| 893 | pc_inc = dec_insn.next_pc_inc; |
Ralf Baechle | 333d1f6 | 2005-02-28 17:55:57 +0000 | [diff] [blame] | 894 | } else { |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 895 | ir = dec_insn.insn; /* process current instr */ |
| 896 | pc_inc = dec_insn.pc_inc; |
| 897 | } |
| 898 | |
| 899 | /* |
| 900 | * Since microMIPS FPU instructios are a subset of MIPS32 FPU |
| 901 | * instructions, we want to convert microMIPS FPU instructions |
| 902 | * into MIPS32 instructions so that we could reuse all of the |
| 903 | * FPU emulation code. |
| 904 | * |
| 905 | * NOTE: We cannot do this for branch instructions since they |
| 906 | * are not a subset. Example: Cannot emulate a 16-bit |
| 907 | * aligned target address with a MIPS32 instruction. |
| 908 | */ |
| 909 | if (dec_insn.micro_mips_mode) { |
| 910 | /* |
| 911 | * If next instruction is a 16-bit instruction, then it |
| 912 | * it cannot be a FPU instruction. This could happen |
| 913 | * since we can be called for non-FPU instructions. |
| 914 | */ |
| 915 | if ((pc_inc == 2) || |
| 916 | (microMIPS32_to_MIPS32((union mips_instruction *)&ir) |
| 917 | == SIGILL)) |
| 918 | return SIGILL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 919 | } |
| 920 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 921 | emul: |
Peter Zijlstra | a8b0ca1 | 2011-06-27 14:41:57 +0200 | [diff] [blame] | 922 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 923 | MIPS_FPU_EMU_INC_STATS(emulated); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 924 | switch (MIPSInst_OPCODE(ir)) { |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 925 | case ldc1_op: |
| 926 | dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + |
| 927 | MIPSInst_SIMM(ir)); |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 928 | MIPS_FPU_EMU_INC_STATS(loads); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 929 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 930 | if (!access_ok(VERIFY_READ, dva, sizeof(u64))) { |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 931 | MIPS_FPU_EMU_INC_STATS(errors); |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 932 | *fault_addr = dva; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 933 | return SIGBUS; |
| 934 | } |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 935 | if (__get_user(dval, dva)) { |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 936 | MIPS_FPU_EMU_INC_STATS(errors); |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 937 | *fault_addr = dva; |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 938 | return SIGSEGV; |
| 939 | } |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 940 | DITOREG(dval, MIPSInst_RT(ir)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 941 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 942 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 943 | case sdc1_op: |
| 944 | dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + |
| 945 | MIPSInst_SIMM(ir)); |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 946 | MIPS_FPU_EMU_INC_STATS(stores); |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 947 | DIFROMREG(dval, MIPSInst_RT(ir)); |
| 948 | if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) { |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 949 | MIPS_FPU_EMU_INC_STATS(errors); |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 950 | *fault_addr = dva; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 951 | return SIGBUS; |
| 952 | } |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 953 | if (__put_user(dval, dva)) { |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 954 | MIPS_FPU_EMU_INC_STATS(errors); |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 955 | *fault_addr = dva; |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 956 | return SIGSEGV; |
| 957 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 958 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 959 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 960 | case lwc1_op: |
| 961 | wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + |
| 962 | MIPSInst_SIMM(ir)); |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 963 | MIPS_FPU_EMU_INC_STATS(loads); |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 964 | if (!access_ok(VERIFY_READ, wva, sizeof(u32))) { |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 965 | MIPS_FPU_EMU_INC_STATS(errors); |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 966 | *fault_addr = wva; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 967 | return SIGBUS; |
| 968 | } |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 969 | if (__get_user(wval, wva)) { |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 970 | MIPS_FPU_EMU_INC_STATS(errors); |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 971 | *fault_addr = wva; |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 972 | return SIGSEGV; |
| 973 | } |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 974 | SITOREG(wval, MIPSInst_RT(ir)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 975 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 976 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 977 | case swc1_op: |
| 978 | wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + |
| 979 | MIPSInst_SIMM(ir)); |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 980 | MIPS_FPU_EMU_INC_STATS(stores); |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 981 | SIFROMREG(wval, MIPSInst_RT(ir)); |
| 982 | if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) { |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 983 | MIPS_FPU_EMU_INC_STATS(errors); |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 984 | *fault_addr = wva; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 985 | return SIGBUS; |
| 986 | } |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 987 | if (__put_user(wval, wva)) { |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 988 | MIPS_FPU_EMU_INC_STATS(errors); |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 989 | *fault_addr = wva; |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 990 | return SIGSEGV; |
| 991 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 992 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 993 | |
| 994 | case cop1_op: |
| 995 | switch (MIPSInst_RS(ir)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 996 | case dmfc_op: |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 997 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
| 998 | return SIGILL; |
| 999 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1000 | /* copregister fs -> gpr[rt] */ |
| 1001 | if (MIPSInst_RT(ir) != 0) { |
| 1002 | DIFROMREG(xcp->regs[MIPSInst_RT(ir)], |
| 1003 | MIPSInst_RD(ir)); |
| 1004 | } |
| 1005 | break; |
| 1006 | |
| 1007 | case dmtc_op: |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1008 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
| 1009 | return SIGILL; |
| 1010 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1011 | /* copregister fs <- rt */ |
| 1012 | DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); |
| 1013 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1014 | |
Leonid Yegoshin | 1ac94400 | 2013-11-07 12:48:28 +0000 | [diff] [blame] | 1015 | case mfhc_op: |
| 1016 | if (!cpu_has_mips_r2) |
| 1017 | goto sigill; |
| 1018 | |
| 1019 | /* copregister rd -> gpr[rt] */ |
| 1020 | if (MIPSInst_RT(ir) != 0) { |
| 1021 | SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], |
| 1022 | MIPSInst_RD(ir)); |
| 1023 | } |
| 1024 | break; |
| 1025 | |
| 1026 | case mthc_op: |
| 1027 | if (!cpu_has_mips_r2) |
| 1028 | goto sigill; |
| 1029 | |
| 1030 | /* copregister rd <- gpr[rt] */ |
| 1031 | SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); |
| 1032 | break; |
| 1033 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1034 | case mfc_op: |
| 1035 | /* copregister rd -> gpr[rt] */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1036 | if (MIPSInst_RT(ir) != 0) { |
| 1037 | SIFROMREG(xcp->regs[MIPSInst_RT(ir)], |
| 1038 | MIPSInst_RD(ir)); |
| 1039 | } |
| 1040 | break; |
| 1041 | |
| 1042 | case mtc_op: |
| 1043 | /* copregister rd <- rt */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1044 | SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); |
| 1045 | break; |
| 1046 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1047 | case cfc_op: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1048 | /* cop control register rd -> gpr[rt] */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1049 | if (MIPSInst_RD(ir) == FPCREG_CSR) { |
| 1050 | value = ctx->fcr31; |
Ralf Baechle | 92df0f8 | 2014-04-19 14:03:37 +0200 | [diff] [blame] | 1051 | pr_debug("%p gpr[%d]<-csr=%08x\n", |
| 1052 | (void *) (xcp->cp0_epc), |
| 1053 | MIPSInst_RT(ir), value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1054 | } |
| 1055 | else if (MIPSInst_RD(ir) == FPCREG_RID) |
| 1056 | value = 0; |
| 1057 | else |
| 1058 | value = 0; |
| 1059 | if (MIPSInst_RT(ir)) |
| 1060 | xcp->regs[MIPSInst_RT(ir)] = value; |
| 1061 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1062 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1063 | case ctc_op: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1064 | /* copregister rd <- rt */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1065 | if (MIPSInst_RT(ir) == 0) |
| 1066 | value = 0; |
| 1067 | else |
| 1068 | value = xcp->regs[MIPSInst_RT(ir)]; |
| 1069 | |
| 1070 | /* we only have one writable control reg |
| 1071 | */ |
| 1072 | if (MIPSInst_RD(ir) == FPCREG_CSR) { |
Ralf Baechle | 92df0f8 | 2014-04-19 14:03:37 +0200 | [diff] [blame] | 1073 | pr_debug("%p gpr[%d]->csr=%08x\n", |
| 1074 | (void *) (xcp->cp0_epc), |
| 1075 | MIPSInst_RT(ir), value); |
Shane McDonald | 95e8f63 | 2010-05-06 23:26:57 -0600 | [diff] [blame] | 1076 | |
Maciej W. Rozycki | 2cfcf8a | 2015-04-03 23:24:56 +0100 | [diff] [blame] | 1077 | /* Don't write reserved bits. */ |
| 1078 | ctx->fcr31 = value & ~FPU_CSR_RSVD; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1079 | } |
| 1080 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { |
| 1081 | return SIGFPE; |
| 1082 | } |
| 1083 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1084 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1085 | case bc_op: |
Ralf Baechle | e7e9cae | 2014-04-16 01:59:03 +0200 | [diff] [blame] | 1086 | if (delay_slot(xcp)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1087 | return SIGILL; |
| 1088 | |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1089 | if (cpu_has_mips_4_5_r) |
| 1090 | cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; |
| 1091 | else |
| 1092 | cbit = FPU_CSR_COND; |
| 1093 | cond = ctx->fcr31 & cbit; |
| 1094 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1095 | likely = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1096 | switch (MIPSInst_RT(ir) & 3) { |
| 1097 | case bcfl_op: |
| 1098 | likely = 1; |
| 1099 | case bcf_op: |
| 1100 | cond = !cond; |
| 1101 | break; |
| 1102 | case bctl_op: |
| 1103 | likely = 1; |
| 1104 | case bct_op: |
| 1105 | break; |
| 1106 | default: |
| 1107 | /* thats an illegal instruction */ |
| 1108 | return SIGILL; |
| 1109 | } |
| 1110 | |
Ralf Baechle | e7e9cae | 2014-04-16 01:59:03 +0200 | [diff] [blame] | 1111 | set_delay_slot(xcp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1112 | if (cond) { |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1113 | /* |
| 1114 | * Branch taken: emulate dslot instruction |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1115 | */ |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 1116 | xcp->cp0_epc += dec_insn.pc_inc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1117 | |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 1118 | contpc = MIPSInst_SIMM(ir); |
| 1119 | ir = dec_insn.next_insn; |
| 1120 | if (dec_insn.micro_mips_mode) { |
| 1121 | contpc = (xcp->cp0_epc + (contpc << 1)); |
| 1122 | |
| 1123 | /* If 16-bit instruction, not FPU. */ |
| 1124 | if ((dec_insn.next_pc_inc == 2) || |
| 1125 | (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { |
| 1126 | |
| 1127 | /* |
| 1128 | * Since this instruction will |
| 1129 | * be put on the stack with |
| 1130 | * 32-bit words, get around |
| 1131 | * this problem by putting a |
| 1132 | * NOP16 as the second one. |
| 1133 | */ |
| 1134 | if (dec_insn.next_pc_inc == 2) |
| 1135 | ir = (ir & (~0xffff)) | MM_NOP16; |
| 1136 | |
| 1137 | /* |
| 1138 | * Single step the non-CP1 |
| 1139 | * instruction in the dslot. |
| 1140 | */ |
| 1141 | return mips_dsemul(xcp, ir, contpc); |
| 1142 | } |
| 1143 | } else |
| 1144 | contpc = (xcp->cp0_epc + (contpc << 2)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1145 | |
| 1146 | switch (MIPSInst_OPCODE(ir)) { |
| 1147 | case lwc1_op: |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1148 | goto emul; |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1149 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1150 | case swc1_op: |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1151 | goto emul; |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1152 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1153 | case ldc1_op: |
| 1154 | case sdc1_op: |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1155 | if (cpu_has_mips_2_3_4_5 || |
| 1156 | cpu_has_mips64) |
| 1157 | goto emul; |
| 1158 | |
| 1159 | return SIGILL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1160 | goto emul; |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1161 | |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1162 | case cop1_op: |
| 1163 | goto emul; |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1164 | |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1165 | case cop1x_op: |
Markos Chandras | a5466d7 | 2014-10-21 10:21:54 +0100 | [diff] [blame] | 1166 | if (cpu_has_mips_4_5 || cpu_has_mips64 || cpu_has_mips32r2) |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1167 | /* its one of ours */ |
| 1168 | goto emul; |
| 1169 | |
| 1170 | return SIGILL; |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1171 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1172 | case spec_op: |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1173 | if (!cpu_has_mips_4_5_r) |
| 1174 | return SIGILL; |
| 1175 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1176 | if (MIPSInst_FUNC(ir) == movc_op) |
| 1177 | goto emul; |
| 1178 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1179 | } |
| 1180 | |
| 1181 | /* |
| 1182 | * Single step the non-cp1 |
| 1183 | * instruction in the dslot |
| 1184 | */ |
Atsushi Nemoto | e70dfc1 | 2007-07-13 23:02:29 +0900 | [diff] [blame] | 1185 | return mips_dsemul(xcp, ir, contpc); |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1186 | } else if (likely) { /* branch not taken */ |
Maciej W. Rozycki | 5d77cf2 | 2015-04-03 23:24:24 +0100 | [diff] [blame] | 1187 | /* |
| 1188 | * branch likely nullifies |
| 1189 | * dslot if not taken |
| 1190 | */ |
| 1191 | xcp->cp0_epc += dec_insn.pc_inc; |
| 1192 | contpc += dec_insn.pc_inc; |
| 1193 | /* |
| 1194 | * else continue & execute |
| 1195 | * dslot as normal insn |
| 1196 | */ |
| 1197 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1198 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1199 | |
| 1200 | default: |
| 1201 | if (!(MIPSInst_RS(ir) & 0x10)) |
| 1202 | return SIGILL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1203 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1204 | /* a real fpu computation instruction */ |
| 1205 | if ((sig = fpu_emu(xcp, ctx, ir))) |
| 1206 | return sig; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1207 | } |
| 1208 | break; |
| 1209 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1210 | case cop1x_op: |
Markos Chandras | a5466d7 | 2014-10-21 10:21:54 +0100 | [diff] [blame] | 1211 | if (!cpu_has_mips_4_5 && !cpu_has_mips64 && !cpu_has_mips32r2) |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1212 | return SIGILL; |
| 1213 | |
| 1214 | sig = fpux_emu(xcp, ctx, ir, fault_addr); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1215 | if (sig) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1216 | return sig; |
| 1217 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1218 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1219 | case spec_op: |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1220 | if (!cpu_has_mips_4_5_r) |
| 1221 | return SIGILL; |
| 1222 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1223 | if (MIPSInst_FUNC(ir) != movc_op) |
| 1224 | return SIGILL; |
| 1225 | cond = fpucondbit[MIPSInst_RT(ir) >> 2]; |
| 1226 | if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) |
| 1227 | xcp->regs[MIPSInst_RD(ir)] = |
| 1228 | xcp->regs[MIPSInst_RS(ir)]; |
| 1229 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1230 | default: |
Leonid Yegoshin | 1ac94400 | 2013-11-07 12:48:28 +0000 | [diff] [blame] | 1231 | sigill: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1232 | return SIGILL; |
| 1233 | } |
| 1234 | |
| 1235 | /* we did it !! */ |
Atsushi Nemoto | e70dfc1 | 2007-07-13 23:02:29 +0900 | [diff] [blame] | 1236 | xcp->cp0_epc = contpc; |
Ralf Baechle | e7e9cae | 2014-04-16 01:59:03 +0200 | [diff] [blame] | 1237 | clear_delay_slot(xcp); |
Ralf Baechle | 333d1f6 | 2005-02-28 17:55:57 +0000 | [diff] [blame] | 1238 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1239 | return 0; |
| 1240 | } |
| 1241 | |
| 1242 | /* |
| 1243 | * Conversion table from MIPS compare ops 48-63 |
| 1244 | * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); |
| 1245 | */ |
| 1246 | static const unsigned char cmptab[8] = { |
| 1247 | 0, /* cmp_0 (sig) cmp_sf */ |
| 1248 | IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ |
| 1249 | IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ |
| 1250 | IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ |
| 1251 | IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ |
| 1252 | IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ |
| 1253 | IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ |
| 1254 | IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ |
| 1255 | }; |
| 1256 | |
| 1257 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1258 | /* |
| 1259 | * Additional MIPS4 instructions |
| 1260 | */ |
| 1261 | |
Ralf Baechle | 47fa0c0 | 2014-04-16 11:00:12 +0200 | [diff] [blame] | 1262 | #define DEF3OP(name, p, f1, f2, f3) \ |
| 1263 | static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \ |
| 1264 | union ieee754##p s, union ieee754##p t) \ |
| 1265 | { \ |
| 1266 | struct _ieee754_csr ieee754_csr_save; \ |
| 1267 | s = f1(s, t); \ |
| 1268 | ieee754_csr_save = ieee754_csr; \ |
| 1269 | s = f2(s, r); \ |
| 1270 | ieee754_csr_save.cx |= ieee754_csr.cx; \ |
| 1271 | ieee754_csr_save.sx |= ieee754_csr.sx; \ |
| 1272 | s = f3(s); \ |
| 1273 | ieee754_csr.cx |= ieee754_csr_save.cx; \ |
| 1274 | ieee754_csr.sx |= ieee754_csr_save.sx; \ |
| 1275 | return s; \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1276 | } |
| 1277 | |
Ralf Baechle | 2209bcb | 2014-04-16 01:31:11 +0200 | [diff] [blame] | 1278 | static union ieee754dp fpemu_dp_recip(union ieee754dp d) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1279 | { |
| 1280 | return ieee754dp_div(ieee754dp_one(0), d); |
| 1281 | } |
| 1282 | |
Ralf Baechle | 2209bcb | 2014-04-16 01:31:11 +0200 | [diff] [blame] | 1283 | static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1284 | { |
| 1285 | return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); |
| 1286 | } |
| 1287 | |
Ralf Baechle | 2209bcb | 2014-04-16 01:31:11 +0200 | [diff] [blame] | 1288 | static union ieee754sp fpemu_sp_recip(union ieee754sp s) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1289 | { |
| 1290 | return ieee754sp_div(ieee754sp_one(0), s); |
| 1291 | } |
| 1292 | |
Ralf Baechle | 2209bcb | 2014-04-16 01:31:11 +0200 | [diff] [blame] | 1293 | static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1294 | { |
| 1295 | return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); |
| 1296 | } |
| 1297 | |
Ralf Baechle | 21a151d | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1298 | DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); |
| 1299 | DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1300 | DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); |
| 1301 | DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); |
Ralf Baechle | 21a151d | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1302 | DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); |
| 1303 | DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1304 | DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); |
| 1305 | DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); |
| 1306 | |
Atsushi Nemoto | eae8907 | 2006-05-16 01:26:03 +0900 | [diff] [blame] | 1307 | static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1308 | mips_instruction ir, void *__user *fault_addr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1309 | { |
| 1310 | unsigned rcsr = 0; /* resulting csr */ |
| 1311 | |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1312 | MIPS_FPU_EMU_INC_STATS(cp1xops); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1313 | |
| 1314 | switch (MIPSInst_FMA_FFMT(ir)) { |
| 1315 | case s_fmt:{ /* 0 */ |
| 1316 | |
Ralf Baechle | 2209bcb | 2014-04-16 01:31:11 +0200 | [diff] [blame] | 1317 | union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp); |
| 1318 | union ieee754sp fd, fr, fs, ft; |
Ralf Baechle | 3fccc01 | 2005-10-23 13:58:21 +0100 | [diff] [blame] | 1319 | u32 __user *va; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1320 | u32 val; |
| 1321 | |
| 1322 | switch (MIPSInst_FUNC(ir)) { |
| 1323 | case lwxc1_op: |
Ralf Baechle | 3fccc01 | 2005-10-23 13:58:21 +0100 | [diff] [blame] | 1324 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1325 | xcp->regs[MIPSInst_FT(ir)]); |
| 1326 | |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1327 | MIPS_FPU_EMU_INC_STATS(loads); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1328 | if (!access_ok(VERIFY_READ, va, sizeof(u32))) { |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1329 | MIPS_FPU_EMU_INC_STATS(errors); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1330 | *fault_addr = va; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1331 | return SIGBUS; |
| 1332 | } |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1333 | if (__get_user(val, va)) { |
| 1334 | MIPS_FPU_EMU_INC_STATS(errors); |
| 1335 | *fault_addr = va; |
| 1336 | return SIGSEGV; |
| 1337 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1338 | SITOREG(val, MIPSInst_FD(ir)); |
| 1339 | break; |
| 1340 | |
| 1341 | case swxc1_op: |
Ralf Baechle | 3fccc01 | 2005-10-23 13:58:21 +0100 | [diff] [blame] | 1342 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1343 | xcp->regs[MIPSInst_FT(ir)]); |
| 1344 | |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1345 | MIPS_FPU_EMU_INC_STATS(stores); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1346 | |
| 1347 | SIFROMREG(val, MIPSInst_FS(ir)); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1348 | if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { |
| 1349 | MIPS_FPU_EMU_INC_STATS(errors); |
| 1350 | *fault_addr = va; |
| 1351 | return SIGBUS; |
| 1352 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1353 | if (put_user(val, va)) { |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1354 | MIPS_FPU_EMU_INC_STATS(errors); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1355 | *fault_addr = va; |
| 1356 | return SIGSEGV; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1357 | } |
| 1358 | break; |
| 1359 | |
| 1360 | case madd_s_op: |
| 1361 | handler = fpemu_sp_madd; |
| 1362 | goto scoptop; |
| 1363 | case msub_s_op: |
| 1364 | handler = fpemu_sp_msub; |
| 1365 | goto scoptop; |
| 1366 | case nmadd_s_op: |
| 1367 | handler = fpemu_sp_nmadd; |
| 1368 | goto scoptop; |
| 1369 | case nmsub_s_op: |
| 1370 | handler = fpemu_sp_nmsub; |
| 1371 | goto scoptop; |
| 1372 | |
| 1373 | scoptop: |
| 1374 | SPFROMREG(fr, MIPSInst_FR(ir)); |
| 1375 | SPFROMREG(fs, MIPSInst_FS(ir)); |
| 1376 | SPFROMREG(ft, MIPSInst_FT(ir)); |
| 1377 | fd = (*handler) (fr, fs, ft); |
| 1378 | SPTOREG(fd, MIPSInst_FD(ir)); |
| 1379 | |
| 1380 | copcsr: |
Deng-Cheng Zhu | c410352 | 2014-05-29 12:26:45 -0700 | [diff] [blame] | 1381 | if (ieee754_cxtest(IEEE754_INEXACT)) { |
| 1382 | MIPS_FPU_EMU_INC_STATS(ieee754_inexact); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1383 | rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; |
Deng-Cheng Zhu | c410352 | 2014-05-29 12:26:45 -0700 | [diff] [blame] | 1384 | } |
| 1385 | if (ieee754_cxtest(IEEE754_UNDERFLOW)) { |
| 1386 | MIPS_FPU_EMU_INC_STATS(ieee754_underflow); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1387 | rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; |
Deng-Cheng Zhu | c410352 | 2014-05-29 12:26:45 -0700 | [diff] [blame] | 1388 | } |
| 1389 | if (ieee754_cxtest(IEEE754_OVERFLOW)) { |
| 1390 | MIPS_FPU_EMU_INC_STATS(ieee754_overflow); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1391 | rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; |
Deng-Cheng Zhu | c410352 | 2014-05-29 12:26:45 -0700 | [diff] [blame] | 1392 | } |
| 1393 | if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { |
| 1394 | MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1395 | rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; |
Deng-Cheng Zhu | c410352 | 2014-05-29 12:26:45 -0700 | [diff] [blame] | 1396 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1397 | |
| 1398 | ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1399 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1400 | /*printk ("SIGFPE: FPU csr = %08x\n", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1401 | ctx->fcr31); */ |
| 1402 | return SIGFPE; |
| 1403 | } |
| 1404 | |
| 1405 | break; |
| 1406 | |
| 1407 | default: |
| 1408 | return SIGILL; |
| 1409 | } |
| 1410 | break; |
| 1411 | } |
| 1412 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1413 | case d_fmt:{ /* 1 */ |
Ralf Baechle | 2209bcb | 2014-04-16 01:31:11 +0200 | [diff] [blame] | 1414 | union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp); |
| 1415 | union ieee754dp fd, fr, fs, ft; |
Ralf Baechle | 3fccc01 | 2005-10-23 13:58:21 +0100 | [diff] [blame] | 1416 | u64 __user *va; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1417 | u64 val; |
| 1418 | |
| 1419 | switch (MIPSInst_FUNC(ir)) { |
| 1420 | case ldxc1_op: |
Ralf Baechle | 3fccc01 | 2005-10-23 13:58:21 +0100 | [diff] [blame] | 1421 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1422 | xcp->regs[MIPSInst_FT(ir)]); |
| 1423 | |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1424 | MIPS_FPU_EMU_INC_STATS(loads); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1425 | if (!access_ok(VERIFY_READ, va, sizeof(u64))) { |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1426 | MIPS_FPU_EMU_INC_STATS(errors); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1427 | *fault_addr = va; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1428 | return SIGBUS; |
| 1429 | } |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1430 | if (__get_user(val, va)) { |
| 1431 | MIPS_FPU_EMU_INC_STATS(errors); |
| 1432 | *fault_addr = va; |
| 1433 | return SIGSEGV; |
| 1434 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1435 | DITOREG(val, MIPSInst_FD(ir)); |
| 1436 | break; |
| 1437 | |
| 1438 | case sdxc1_op: |
Ralf Baechle | 3fccc01 | 2005-10-23 13:58:21 +0100 | [diff] [blame] | 1439 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1440 | xcp->regs[MIPSInst_FT(ir)]); |
| 1441 | |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1442 | MIPS_FPU_EMU_INC_STATS(stores); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1443 | DIFROMREG(val, MIPSInst_FS(ir)); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1444 | if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1445 | MIPS_FPU_EMU_INC_STATS(errors); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1446 | *fault_addr = va; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1447 | return SIGBUS; |
| 1448 | } |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1449 | if (__put_user(val, va)) { |
| 1450 | MIPS_FPU_EMU_INC_STATS(errors); |
| 1451 | *fault_addr = va; |
| 1452 | return SIGSEGV; |
| 1453 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1454 | break; |
| 1455 | |
| 1456 | case madd_d_op: |
| 1457 | handler = fpemu_dp_madd; |
| 1458 | goto dcoptop; |
| 1459 | case msub_d_op: |
| 1460 | handler = fpemu_dp_msub; |
| 1461 | goto dcoptop; |
| 1462 | case nmadd_d_op: |
| 1463 | handler = fpemu_dp_nmadd; |
| 1464 | goto dcoptop; |
| 1465 | case nmsub_d_op: |
| 1466 | handler = fpemu_dp_nmsub; |
| 1467 | goto dcoptop; |
| 1468 | |
| 1469 | dcoptop: |
| 1470 | DPFROMREG(fr, MIPSInst_FR(ir)); |
| 1471 | DPFROMREG(fs, MIPSInst_FS(ir)); |
| 1472 | DPFROMREG(ft, MIPSInst_FT(ir)); |
| 1473 | fd = (*handler) (fr, fs, ft); |
| 1474 | DPTOREG(fd, MIPSInst_FD(ir)); |
| 1475 | goto copcsr; |
| 1476 | |
| 1477 | default: |
| 1478 | return SIGILL; |
| 1479 | } |
| 1480 | break; |
| 1481 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1482 | |
Deng-Cheng Zhu | 51061b8 | 2014-03-06 17:05:27 -0800 | [diff] [blame] | 1483 | case 0x3: |
| 1484 | if (MIPSInst_FUNC(ir) != pfetch_op) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1485 | return SIGILL; |
Deng-Cheng Zhu | 51061b8 | 2014-03-06 17:05:27 -0800 | [diff] [blame] | 1486 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1487 | /* ignore prefx operation */ |
| 1488 | break; |
| 1489 | |
| 1490 | default: |
| 1491 | return SIGILL; |
| 1492 | } |
| 1493 | |
| 1494 | return 0; |
| 1495 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1496 | |
| 1497 | |
| 1498 | |
| 1499 | /* |
| 1500 | * Emulate a single COP1 arithmetic instruction. |
| 1501 | */ |
Atsushi Nemoto | eae8907 | 2006-05-16 01:26:03 +0900 | [diff] [blame] | 1502 | static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1503 | mips_instruction ir) |
| 1504 | { |
| 1505 | int rfmt; /* resulting format */ |
| 1506 | unsigned rcsr = 0; /* resulting csr */ |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1507 | unsigned int oldrm; |
| 1508 | unsigned int cbit; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1509 | unsigned cond; |
| 1510 | union { |
Ralf Baechle | 2209bcb | 2014-04-16 01:31:11 +0200 | [diff] [blame] | 1511 | union ieee754dp d; |
| 1512 | union ieee754sp s; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1513 | int w; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1514 | s64 l; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1515 | } rv; /* resulting value */ |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1516 | u64 bits; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1517 | |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1518 | MIPS_FPU_EMU_INC_STATS(cp1ops); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1519 | switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1520 | case s_fmt: { /* 0 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1521 | union { |
Ralf Baechle | 2209bcb | 2014-04-16 01:31:11 +0200 | [diff] [blame] | 1522 | union ieee754sp(*b) (union ieee754sp, union ieee754sp); |
| 1523 | union ieee754sp(*u) (union ieee754sp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1524 | } handler; |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1525 | union ieee754sp fs, ft; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1526 | |
| 1527 | switch (MIPSInst_FUNC(ir)) { |
| 1528 | /* binary ops */ |
| 1529 | case fadd_op: |
| 1530 | handler.b = ieee754sp_add; |
| 1531 | goto scopbop; |
| 1532 | case fsub_op: |
| 1533 | handler.b = ieee754sp_sub; |
| 1534 | goto scopbop; |
| 1535 | case fmul_op: |
| 1536 | handler.b = ieee754sp_mul; |
| 1537 | goto scopbop; |
| 1538 | case fdiv_op: |
| 1539 | handler.b = ieee754sp_div; |
| 1540 | goto scopbop; |
| 1541 | |
| 1542 | /* unary ops */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1543 | case fsqrt_op: |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1544 | if (!cpu_has_mips_4_5_r) |
| 1545 | return SIGILL; |
| 1546 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1547 | handler.u = ieee754sp_sqrt; |
| 1548 | goto scopuop; |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1549 | |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1550 | /* |
| 1551 | * Note that on some MIPS IV implementations such as the |
| 1552 | * R5000 and R8000 the FSQRT and FRECIP instructions do not |
| 1553 | * achieve full IEEE-754 accuracy - however this emulator does. |
| 1554 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1555 | case frsqrt_op: |
Markos Chandras | e0d32f33 | 2015-01-15 10:11:17 +0000 | [diff] [blame] | 1556 | if (!cpu_has_mips_4_5_r2_r6) |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1557 | return SIGILL; |
| 1558 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1559 | handler.u = fpemu_sp_rsqrt; |
| 1560 | goto scopuop; |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1561 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1562 | case frecip_op: |
Markos Chandras | e0d32f33 | 2015-01-15 10:11:17 +0000 | [diff] [blame] | 1563 | if (!cpu_has_mips_4_5_r2_r6) |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1564 | return SIGILL; |
| 1565 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1566 | handler.u = fpemu_sp_recip; |
| 1567 | goto scopuop; |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1568 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1569 | case fmovc_op: |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1570 | if (!cpu_has_mips_4_5_r) |
| 1571 | return SIGILL; |
| 1572 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1573 | cond = fpucondbit[MIPSInst_FT(ir) >> 2]; |
| 1574 | if (((ctx->fcr31 & cond) != 0) != |
| 1575 | ((MIPSInst_FT(ir) & 1) != 0)) |
| 1576 | return 0; |
| 1577 | SPFROMREG(rv.s, MIPSInst_FS(ir)); |
| 1578 | break; |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1579 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1580 | case fmovz_op: |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1581 | if (!cpu_has_mips_4_5_r) |
| 1582 | return SIGILL; |
| 1583 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1584 | if (xcp->regs[MIPSInst_FT(ir)] != 0) |
| 1585 | return 0; |
| 1586 | SPFROMREG(rv.s, MIPSInst_FS(ir)); |
| 1587 | break; |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1588 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1589 | case fmovn_op: |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1590 | if (!cpu_has_mips_4_5_r) |
| 1591 | return SIGILL; |
| 1592 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1593 | if (xcp->regs[MIPSInst_FT(ir)] == 0) |
| 1594 | return 0; |
| 1595 | SPFROMREG(rv.s, MIPSInst_FS(ir)); |
| 1596 | break; |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1597 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1598 | case fabs_op: |
| 1599 | handler.u = ieee754sp_abs; |
| 1600 | goto scopuop; |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1601 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1602 | case fneg_op: |
| 1603 | handler.u = ieee754sp_neg; |
| 1604 | goto scopuop; |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1605 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1606 | case fmov_op: |
| 1607 | /* an easy one */ |
| 1608 | SPFROMREG(rv.s, MIPSInst_FS(ir)); |
| 1609 | goto copcsr; |
| 1610 | |
| 1611 | /* binary op on handler */ |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1612 | scopbop: |
| 1613 | SPFROMREG(fs, MIPSInst_FS(ir)); |
| 1614 | SPFROMREG(ft, MIPSInst_FT(ir)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1615 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1616 | rv.s = (*handler.b) (fs, ft); |
| 1617 | goto copcsr; |
| 1618 | scopuop: |
| 1619 | SPFROMREG(fs, MIPSInst_FS(ir)); |
| 1620 | rv.s = (*handler.u) (fs); |
| 1621 | goto copcsr; |
| 1622 | copcsr: |
Deng-Cheng Zhu | c410352 | 2014-05-29 12:26:45 -0700 | [diff] [blame] | 1623 | if (ieee754_cxtest(IEEE754_INEXACT)) { |
| 1624 | MIPS_FPU_EMU_INC_STATS(ieee754_inexact); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1625 | rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; |
Deng-Cheng Zhu | c410352 | 2014-05-29 12:26:45 -0700 | [diff] [blame] | 1626 | } |
| 1627 | if (ieee754_cxtest(IEEE754_UNDERFLOW)) { |
| 1628 | MIPS_FPU_EMU_INC_STATS(ieee754_underflow); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1629 | rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; |
Deng-Cheng Zhu | c410352 | 2014-05-29 12:26:45 -0700 | [diff] [blame] | 1630 | } |
| 1631 | if (ieee754_cxtest(IEEE754_OVERFLOW)) { |
| 1632 | MIPS_FPU_EMU_INC_STATS(ieee754_overflow); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1633 | rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; |
Deng-Cheng Zhu | c410352 | 2014-05-29 12:26:45 -0700 | [diff] [blame] | 1634 | } |
| 1635 | if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) { |
| 1636 | MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1637 | rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; |
Deng-Cheng Zhu | c410352 | 2014-05-29 12:26:45 -0700 | [diff] [blame] | 1638 | } |
| 1639 | if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { |
| 1640 | MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1641 | rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; |
Deng-Cheng Zhu | c410352 | 2014-05-29 12:26:45 -0700 | [diff] [blame] | 1642 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1643 | break; |
| 1644 | |
| 1645 | /* unary conv ops */ |
| 1646 | case fcvts_op: |
| 1647 | return SIGILL; /* not defined */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1648 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1649 | case fcvtd_op: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1650 | SPFROMREG(fs, MIPSInst_FS(ir)); |
| 1651 | rv.d = ieee754dp_fsp(fs); |
| 1652 | rfmt = d_fmt; |
| 1653 | goto copcsr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1654 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1655 | case fcvtw_op: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1656 | SPFROMREG(fs, MIPSInst_FS(ir)); |
| 1657 | rv.w = ieee754sp_tint(fs); |
| 1658 | rfmt = w_fmt; |
| 1659 | goto copcsr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1660 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1661 | case fround_op: |
| 1662 | case ftrunc_op: |
| 1663 | case fceil_op: |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1664 | case ffloor_op: |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1665 | if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64) |
| 1666 | return SIGILL; |
| 1667 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1668 | oldrm = ieee754_csr.rm; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1669 | SPFROMREG(fs, MIPSInst_FS(ir)); |
Maciej W. Rozycki | 2cfcf8a | 2015-04-03 23:24:56 +0100 | [diff] [blame] | 1670 | ieee754_csr.rm = MIPSInst_FUNC(ir); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1671 | rv.w = ieee754sp_tint(fs); |
| 1672 | ieee754_csr.rm = oldrm; |
| 1673 | rfmt = w_fmt; |
| 1674 | goto copcsr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1675 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1676 | case fcvtl_op: |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1677 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
| 1678 | return SIGILL; |
| 1679 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1680 | SPFROMREG(fs, MIPSInst_FS(ir)); |
| 1681 | rv.l = ieee754sp_tlong(fs); |
| 1682 | rfmt = l_fmt; |
| 1683 | goto copcsr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1684 | |
| 1685 | case froundl_op: |
| 1686 | case ftruncl_op: |
| 1687 | case fceill_op: |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1688 | case ffloorl_op: |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1689 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
| 1690 | return SIGILL; |
| 1691 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1692 | oldrm = ieee754_csr.rm; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1693 | SPFROMREG(fs, MIPSInst_FS(ir)); |
Maciej W. Rozycki | 2cfcf8a | 2015-04-03 23:24:56 +0100 | [diff] [blame] | 1694 | ieee754_csr.rm = MIPSInst_FUNC(ir); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1695 | rv.l = ieee754sp_tlong(fs); |
| 1696 | ieee754_csr.rm = oldrm; |
| 1697 | rfmt = l_fmt; |
| 1698 | goto copcsr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1699 | |
| 1700 | default: |
| 1701 | if (MIPSInst_FUNC(ir) >= fcmp_op) { |
| 1702 | unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; |
Ralf Baechle | 2209bcb | 2014-04-16 01:31:11 +0200 | [diff] [blame] | 1703 | union ieee754sp fs, ft; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1704 | |
| 1705 | SPFROMREG(fs, MIPSInst_FS(ir)); |
| 1706 | SPFROMREG(ft, MIPSInst_FT(ir)); |
| 1707 | rv.w = ieee754sp_cmp(fs, ft, |
| 1708 | cmptab[cmpop & 0x7], cmpop & 0x8); |
| 1709 | rfmt = -1; |
| 1710 | if ((cmpop & 0x8) && ieee754_cxtest |
| 1711 | (IEEE754_INVALID_OPERATION)) |
| 1712 | rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; |
| 1713 | else |
| 1714 | goto copcsr; |
| 1715 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1716 | } else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1717 | return SIGILL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1718 | break; |
| 1719 | } |
| 1720 | break; |
| 1721 | } |
| 1722 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1723 | case d_fmt: { |
| 1724 | union ieee754dp fs, ft; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1725 | union { |
Ralf Baechle | 2209bcb | 2014-04-16 01:31:11 +0200 | [diff] [blame] | 1726 | union ieee754dp(*b) (union ieee754dp, union ieee754dp); |
| 1727 | union ieee754dp(*u) (union ieee754dp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1728 | } handler; |
| 1729 | |
| 1730 | switch (MIPSInst_FUNC(ir)) { |
| 1731 | /* binary ops */ |
| 1732 | case fadd_op: |
| 1733 | handler.b = ieee754dp_add; |
| 1734 | goto dcopbop; |
| 1735 | case fsub_op: |
| 1736 | handler.b = ieee754dp_sub; |
| 1737 | goto dcopbop; |
| 1738 | case fmul_op: |
| 1739 | handler.b = ieee754dp_mul; |
| 1740 | goto dcopbop; |
| 1741 | case fdiv_op: |
| 1742 | handler.b = ieee754dp_div; |
| 1743 | goto dcopbop; |
| 1744 | |
| 1745 | /* unary ops */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1746 | case fsqrt_op: |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1747 | if (!cpu_has_mips_2_3_4_5_r) |
| 1748 | return SIGILL; |
| 1749 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1750 | handler.u = ieee754dp_sqrt; |
| 1751 | goto dcopuop; |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1752 | /* |
| 1753 | * Note that on some MIPS IV implementations such as the |
| 1754 | * R5000 and R8000 the FSQRT and FRECIP instructions do not |
| 1755 | * achieve full IEEE-754 accuracy - however this emulator does. |
| 1756 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1757 | case frsqrt_op: |
Markos Chandras | e0d32f33 | 2015-01-15 10:11:17 +0000 | [diff] [blame] | 1758 | if (!cpu_has_mips_4_5_r2_r6) |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1759 | return SIGILL; |
| 1760 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1761 | handler.u = fpemu_dp_rsqrt; |
| 1762 | goto dcopuop; |
| 1763 | case frecip_op: |
Markos Chandras | e0d32f33 | 2015-01-15 10:11:17 +0000 | [diff] [blame] | 1764 | if (!cpu_has_mips_4_5_r2_r6) |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1765 | return SIGILL; |
| 1766 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1767 | handler.u = fpemu_dp_recip; |
| 1768 | goto dcopuop; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1769 | case fmovc_op: |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1770 | if (!cpu_has_mips_4_5_r) |
| 1771 | return SIGILL; |
| 1772 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1773 | cond = fpucondbit[MIPSInst_FT(ir) >> 2]; |
| 1774 | if (((ctx->fcr31 & cond) != 0) != |
| 1775 | ((MIPSInst_FT(ir) & 1) != 0)) |
| 1776 | return 0; |
| 1777 | DPFROMREG(rv.d, MIPSInst_FS(ir)); |
| 1778 | break; |
| 1779 | case fmovz_op: |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1780 | if (!cpu_has_mips_4_5_r) |
| 1781 | return SIGILL; |
| 1782 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1783 | if (xcp->regs[MIPSInst_FT(ir)] != 0) |
| 1784 | return 0; |
| 1785 | DPFROMREG(rv.d, MIPSInst_FS(ir)); |
| 1786 | break; |
| 1787 | case fmovn_op: |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1788 | if (!cpu_has_mips_4_5_r) |
| 1789 | return SIGILL; |
| 1790 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1791 | if (xcp->regs[MIPSInst_FT(ir)] == 0) |
| 1792 | return 0; |
| 1793 | DPFROMREG(rv.d, MIPSInst_FS(ir)); |
| 1794 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1795 | case fabs_op: |
| 1796 | handler.u = ieee754dp_abs; |
| 1797 | goto dcopuop; |
| 1798 | |
| 1799 | case fneg_op: |
| 1800 | handler.u = ieee754dp_neg; |
| 1801 | goto dcopuop; |
| 1802 | |
| 1803 | case fmov_op: |
| 1804 | /* an easy one */ |
| 1805 | DPFROMREG(rv.d, MIPSInst_FS(ir)); |
| 1806 | goto copcsr; |
| 1807 | |
| 1808 | /* binary op on handler */ |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1809 | dcopbop: |
| 1810 | DPFROMREG(fs, MIPSInst_FS(ir)); |
| 1811 | DPFROMREG(ft, MIPSInst_FT(ir)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1812 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1813 | rv.d = (*handler.b) (fs, ft); |
| 1814 | goto copcsr; |
| 1815 | dcopuop: |
| 1816 | DPFROMREG(fs, MIPSInst_FS(ir)); |
| 1817 | rv.d = (*handler.u) (fs); |
| 1818 | goto copcsr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1819 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1820 | /* |
| 1821 | * unary conv ops |
| 1822 | */ |
| 1823 | case fcvts_op: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1824 | DPFROMREG(fs, MIPSInst_FS(ir)); |
| 1825 | rv.s = ieee754sp_fdp(fs); |
| 1826 | rfmt = s_fmt; |
| 1827 | goto copcsr; |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1828 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1829 | case fcvtd_op: |
| 1830 | return SIGILL; /* not defined */ |
| 1831 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1832 | case fcvtw_op: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1833 | DPFROMREG(fs, MIPSInst_FS(ir)); |
| 1834 | rv.w = ieee754dp_tint(fs); /* wrong */ |
| 1835 | rfmt = w_fmt; |
| 1836 | goto copcsr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1837 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1838 | case fround_op: |
| 1839 | case ftrunc_op: |
| 1840 | case fceil_op: |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1841 | case ffloor_op: |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1842 | if (!cpu_has_mips_2_3_4_5_r) |
| 1843 | return SIGILL; |
| 1844 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1845 | oldrm = ieee754_csr.rm; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1846 | DPFROMREG(fs, MIPSInst_FS(ir)); |
Maciej W. Rozycki | 2cfcf8a | 2015-04-03 23:24:56 +0100 | [diff] [blame] | 1847 | ieee754_csr.rm = MIPSInst_FUNC(ir); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1848 | rv.w = ieee754dp_tint(fs); |
| 1849 | ieee754_csr.rm = oldrm; |
| 1850 | rfmt = w_fmt; |
| 1851 | goto copcsr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1852 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1853 | case fcvtl_op: |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1854 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
| 1855 | return SIGILL; |
| 1856 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1857 | DPFROMREG(fs, MIPSInst_FS(ir)); |
| 1858 | rv.l = ieee754dp_tlong(fs); |
| 1859 | rfmt = l_fmt; |
| 1860 | goto copcsr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1861 | |
| 1862 | case froundl_op: |
| 1863 | case ftruncl_op: |
| 1864 | case fceill_op: |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1865 | case ffloorl_op: |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1866 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
| 1867 | return SIGILL; |
| 1868 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1869 | oldrm = ieee754_csr.rm; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1870 | DPFROMREG(fs, MIPSInst_FS(ir)); |
Maciej W. Rozycki | 2cfcf8a | 2015-04-03 23:24:56 +0100 | [diff] [blame] | 1871 | ieee754_csr.rm = MIPSInst_FUNC(ir); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1872 | rv.l = ieee754dp_tlong(fs); |
| 1873 | ieee754_csr.rm = oldrm; |
| 1874 | rfmt = l_fmt; |
| 1875 | goto copcsr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1876 | |
| 1877 | default: |
| 1878 | if (MIPSInst_FUNC(ir) >= fcmp_op) { |
| 1879 | unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; |
Ralf Baechle | 2209bcb | 2014-04-16 01:31:11 +0200 | [diff] [blame] | 1880 | union ieee754dp fs, ft; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1881 | |
| 1882 | DPFROMREG(fs, MIPSInst_FS(ir)); |
| 1883 | DPFROMREG(ft, MIPSInst_FT(ir)); |
| 1884 | rv.w = ieee754dp_cmp(fs, ft, |
| 1885 | cmptab[cmpop & 0x7], cmpop & 0x8); |
| 1886 | rfmt = -1; |
| 1887 | if ((cmpop & 0x8) |
| 1888 | && |
| 1889 | ieee754_cxtest |
| 1890 | (IEEE754_INVALID_OPERATION)) |
| 1891 | rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; |
| 1892 | else |
| 1893 | goto copcsr; |
| 1894 | |
| 1895 | } |
| 1896 | else { |
| 1897 | return SIGILL; |
| 1898 | } |
| 1899 | break; |
| 1900 | } |
| 1901 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1902 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1903 | case w_fmt: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1904 | switch (MIPSInst_FUNC(ir)) { |
| 1905 | case fcvts_op: |
| 1906 | /* convert word to single precision real */ |
| 1907 | SPFROMREG(fs, MIPSInst_FS(ir)); |
| 1908 | rv.s = ieee754sp_fint(fs.bits); |
| 1909 | rfmt = s_fmt; |
| 1910 | goto copcsr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1911 | case fcvtd_op: |
| 1912 | /* convert word to double precision real */ |
| 1913 | SPFROMREG(fs, MIPSInst_FS(ir)); |
| 1914 | rv.d = ieee754dp_fint(fs.bits); |
| 1915 | rfmt = d_fmt; |
| 1916 | goto copcsr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1917 | default: |
| 1918 | return SIGILL; |
| 1919 | } |
| 1920 | break; |
| 1921 | } |
| 1922 | |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1923 | case l_fmt: |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1924 | |
| 1925 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
| 1926 | return SIGILL; |
| 1927 | |
Paul Burton | bbd426f | 2014-02-13 11:26:41 +0000 | [diff] [blame] | 1928 | DIFROMREG(bits, MIPSInst_FS(ir)); |
| 1929 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1930 | switch (MIPSInst_FUNC(ir)) { |
| 1931 | case fcvts_op: |
| 1932 | /* convert long to single precision real */ |
Paul Burton | bbd426f | 2014-02-13 11:26:41 +0000 | [diff] [blame] | 1933 | rv.s = ieee754sp_flong(bits); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1934 | rfmt = s_fmt; |
| 1935 | goto copcsr; |
| 1936 | case fcvtd_op: |
| 1937 | /* convert long to double precision real */ |
Paul Burton | bbd426f | 2014-02-13 11:26:41 +0000 | [diff] [blame] | 1938 | rv.d = ieee754dp_flong(bits); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1939 | rfmt = d_fmt; |
| 1940 | goto copcsr; |
| 1941 | default: |
| 1942 | return SIGILL; |
| 1943 | } |
| 1944 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1945 | |
| 1946 | default: |
| 1947 | return SIGILL; |
| 1948 | } |
| 1949 | |
| 1950 | /* |
| 1951 | * Update the fpu CSR register for this operation. |
| 1952 | * If an exception is required, generate a tidy SIGFPE exception, |
| 1953 | * without updating the result register. |
| 1954 | * Note: cause exception bits do not accumulate, they are rewritten |
| 1955 | * for each op; only the flag/sticky bits accumulate. |
| 1956 | */ |
| 1957 | ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; |
| 1958 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 1959 | /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1960 | return SIGFPE; |
| 1961 | } |
| 1962 | |
| 1963 | /* |
| 1964 | * Now we can safely write the result back to the register file. |
| 1965 | */ |
| 1966 | switch (rfmt) { |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1967 | case -1: |
| 1968 | |
| 1969 | if (cpu_has_mips_4_5_r) |
Rob Kendrick | c3b9b94 | 2014-07-23 10:03:58 +0100 | [diff] [blame] | 1970 | cbit = fpucondbit[MIPSInst_FD(ir) >> 2]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1971 | else |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1972 | cbit = FPU_CSR_COND; |
| 1973 | if (rv.w) |
| 1974 | ctx->fcr31 |= cbit; |
| 1975 | else |
| 1976 | ctx->fcr31 &= ~cbit; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1977 | break; |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1978 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1979 | case d_fmt: |
| 1980 | DPTOREG(rv.d, MIPSInst_FD(ir)); |
| 1981 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1982 | case s_fmt: |
| 1983 | SPTOREG(rv.s, MIPSInst_FD(ir)); |
| 1984 | break; |
| 1985 | case w_fmt: |
| 1986 | SITOREG(rv.w, MIPSInst_FD(ir)); |
| 1987 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1988 | case l_fmt: |
Ralf Baechle | 08a0790 | 2014-04-19 13:11:37 +0200 | [diff] [blame] | 1989 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
| 1990 | return SIGILL; |
| 1991 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1992 | DITOREG(rv.l, MIPSInst_FD(ir)); |
| 1993 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1994 | default: |
| 1995 | return SIGILL; |
| 1996 | } |
| 1997 | |
| 1998 | return 0; |
| 1999 | } |
| 2000 | |
Atsushi Nemoto | e04582b | 2006-10-09 00:10:01 +0900 | [diff] [blame] | 2001 | int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 2002 | int has_fpu, void *__user *fault_addr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2003 | { |
Ralf Baechle | 333d1f6 | 2005-02-28 17:55:57 +0000 | [diff] [blame] | 2004 | unsigned long oldepc, prevepc; |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 2005 | struct mm_decoded_insn dec_insn; |
| 2006 | u16 instr[4]; |
| 2007 | u16 *instr_ptr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2008 | int sig = 0; |
| 2009 | |
| 2010 | oldepc = xcp->cp0_epc; |
| 2011 | do { |
| 2012 | prevepc = xcp->cp0_epc; |
| 2013 | |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 2014 | if (get_isa16_mode(prevepc) && cpu_has_mmips) { |
| 2015 | /* |
| 2016 | * Get next 2 microMIPS instructions and convert them |
| 2017 | * into 32-bit instructions. |
| 2018 | */ |
| 2019 | if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || |
| 2020 | (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || |
| 2021 | (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || |
| 2022 | (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { |
| 2023 | MIPS_FPU_EMU_INC_STATS(errors); |
| 2024 | return SIGBUS; |
| 2025 | } |
| 2026 | instr_ptr = instr; |
| 2027 | |
| 2028 | /* Get first instruction. */ |
| 2029 | if (mm_insn_16bit(*instr_ptr)) { |
| 2030 | /* Duplicate the half-word. */ |
| 2031 | dec_insn.insn = (*instr_ptr << 16) | |
| 2032 | (*instr_ptr); |
| 2033 | /* 16-bit instruction. */ |
| 2034 | dec_insn.pc_inc = 2; |
| 2035 | instr_ptr += 1; |
| 2036 | } else { |
| 2037 | dec_insn.insn = (*instr_ptr << 16) | |
| 2038 | *(instr_ptr+1); |
| 2039 | /* 32-bit instruction. */ |
| 2040 | dec_insn.pc_inc = 4; |
| 2041 | instr_ptr += 2; |
| 2042 | } |
| 2043 | /* Get second instruction. */ |
| 2044 | if (mm_insn_16bit(*instr_ptr)) { |
| 2045 | /* Duplicate the half-word. */ |
| 2046 | dec_insn.next_insn = (*instr_ptr << 16) | |
| 2047 | (*instr_ptr); |
| 2048 | /* 16-bit instruction. */ |
| 2049 | dec_insn.next_pc_inc = 2; |
| 2050 | } else { |
| 2051 | dec_insn.next_insn = (*instr_ptr << 16) | |
| 2052 | *(instr_ptr+1); |
| 2053 | /* 32-bit instruction. */ |
| 2054 | dec_insn.next_pc_inc = 4; |
| 2055 | } |
| 2056 | dec_insn.micro_mips_mode = 1; |
| 2057 | } else { |
| 2058 | if ((get_user(dec_insn.insn, |
| 2059 | (mips_instruction __user *) xcp->cp0_epc)) || |
| 2060 | (get_user(dec_insn.next_insn, |
| 2061 | (mips_instruction __user *)(xcp->cp0_epc+4)))) { |
| 2062 | MIPS_FPU_EMU_INC_STATS(errors); |
| 2063 | return SIGBUS; |
| 2064 | } |
| 2065 | dec_insn.pc_inc = 4; |
| 2066 | dec_insn.next_pc_inc = 4; |
| 2067 | dec_insn.micro_mips_mode = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2068 | } |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 2069 | |
| 2070 | if ((dec_insn.insn == 0) || |
| 2071 | ((dec_insn.pc_inc == 2) && |
| 2072 | ((dec_insn.insn & 0xffff) == MM_NOP16))) |
| 2073 | xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2074 | else { |
Ralf Baechle | cd21dfc | 2005-04-28 13:39:10 +0000 | [diff] [blame] | 2075 | /* |
Maciej W. Rozycki | 2cfcf8a | 2015-04-03 23:24:56 +0100 | [diff] [blame] | 2076 | * The 'ieee754_csr' is an alias of ctx->fcr31. |
| 2077 | * No need to copy ctx->fcr31 to ieee754_csr. |
Ralf Baechle | cd21dfc | 2005-04-28 13:39:10 +0000 | [diff] [blame] | 2078 | */ |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 2079 | sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2080 | } |
| 2081 | |
Atsushi Nemoto | e04582b | 2006-10-09 00:10:01 +0900 | [diff] [blame] | 2082 | if (has_fpu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2083 | break; |
| 2084 | if (sig) |
| 2085 | break; |
| 2086 | |
| 2087 | cond_resched(); |
| 2088 | } while (xcp->cp0_epc > prevepc); |
| 2089 | |
| 2090 | /* SIGILL indicates a non-fpu instruction */ |
| 2091 | if (sig == SIGILL && xcp->cp0_epc != oldepc) |
Ralf Baechle | 3f7cac4 | 2014-04-26 01:49:14 +0200 | [diff] [blame] | 2092 | /* but if EPC has advanced, then ignore it */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2093 | sig = 0; |
| 2094 | |
| 2095 | return sig; |
| 2096 | } |