Raviteja Tamatam | e97849a | 2017-09-12 20:25:50 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include "dsi-panel-sim-video.dtsi" |
| 14 | #include "dsi-panel-sim-cmd.dtsi" |
| 15 | #include "dsi-panel-sim-dsc375-cmd.dtsi" |
| 16 | #include "dsi-panel-sim-dualmipi-video.dtsi" |
| 17 | #include "dsi-panel-sim-dualmipi-cmd.dtsi" |
| 18 | #include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" |
| 19 | #include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi" |
| 20 | #include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi" |
| 21 | #include "dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi" |
| 22 | #include "dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi" |
Rashi Bindra | 5f52b4e | 2017-09-26 18:17:06 +0530 | [diff] [blame] | 23 | #include "dsi-panel-nt35597-dualmipi-wqxga-video.dtsi" |
| 24 | #include "dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi" |
| 25 | #include "dsi-panel-nt35695b-truly-fhd-video.dtsi" |
| 26 | #include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi" |
| 27 | #include "dsi-panel-rm67195-amoled-fhd-cmd.dtsi" |
Raviteja Tamatam | e97849a | 2017-09-12 20:25:50 +0530 | [diff] [blame] | 28 | #include <dt-bindings/clock/mdss-10nm-pll-clk.h> |
| 29 | |
| 30 | &soc { |
| 31 | dsi_panel_pwr_supply: dsi_panel_pwr_supply { |
| 32 | #address-cells = <1>; |
| 33 | #size-cells = <0>; |
| 34 | |
| 35 | qcom,panel-supply-entry@0 { |
| 36 | reg = <0>; |
| 37 | qcom,supply-name = "vddio"; |
| 38 | qcom,supply-min-voltage = <1800000>; |
| 39 | qcom,supply-max-voltage = <1800000>; |
| 40 | qcom,supply-enable-load = <62000>; |
| 41 | qcom,supply-disable-load = <80>; |
| 42 | qcom,supply-post-on-sleep = <20>; |
| 43 | }; |
| 44 | |
| 45 | qcom,panel-supply-entry@1 { |
| 46 | reg = <1>; |
| 47 | qcom,supply-name = "lab"; |
| 48 | qcom,supply-min-voltage = <4600000>; |
| 49 | qcom,supply-max-voltage = <6000000>; |
| 50 | qcom,supply-enable-load = <100000>; |
| 51 | qcom,supply-disable-load = <100>; |
| 52 | }; |
| 53 | |
| 54 | qcom,panel-supply-entry@2 { |
| 55 | reg = <2>; |
| 56 | qcom,supply-name = "ibb"; |
| 57 | qcom,supply-min-voltage = <4600000>; |
| 58 | qcom,supply-max-voltage = <6000000>; |
| 59 | qcom,supply-enable-load = <100000>; |
| 60 | qcom,supply-disable-load = <100>; |
| 61 | qcom,supply-post-on-sleep = <20>; |
| 62 | }; |
| 63 | }; |
| 64 | |
| 65 | dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { |
| 66 | #address-cells = <1>; |
| 67 | #size-cells = <0>; |
| 68 | |
| 69 | qcom,panel-supply-entry@0 { |
| 70 | reg = <0>; |
| 71 | qcom,supply-name = "vddio"; |
| 72 | qcom,supply-min-voltage = <1800000>; |
| 73 | qcom,supply-max-voltage = <1800000>; |
| 74 | qcom,supply-enable-load = <62000>; |
| 75 | qcom,supply-disable-load = <80>; |
| 76 | qcom,supply-post-on-sleep = <20>; |
| 77 | }; |
| 78 | }; |
| 79 | |
| 80 | dsi_panel_pwr_supply_vdd_no_labibb: dsi_panel_pwr_supply_vdd_no_labibb { |
| 81 | #address-cells = <1>; |
| 82 | #size-cells = <0>; |
| 83 | |
| 84 | qcom,panel-supply-entry@0 { |
| 85 | reg = <0>; |
| 86 | qcom,supply-name = "vddio"; |
| 87 | qcom,supply-min-voltage = <1800000>; |
| 88 | qcom,supply-max-voltage = <1800000>; |
| 89 | qcom,supply-enable-load = <62000>; |
| 90 | qcom,supply-disable-load = <80>; |
| 91 | qcom,supply-post-on-sleep = <20>; |
| 92 | }; |
| 93 | |
| 94 | qcom,panel-supply-entry@1 { |
| 95 | reg = <1>; |
| 96 | qcom,supply-name = "vdd"; |
| 97 | qcom,supply-min-voltage = <3000000>; |
| 98 | qcom,supply-max-voltage = <3000000>; |
| 99 | qcom,supply-enable-load = <857000>; |
| 100 | qcom,supply-disable-load = <0>; |
| 101 | qcom,supply-post-on-sleep = <0>; |
| 102 | }; |
| 103 | }; |
| 104 | |
Rashi Bindra | 5f52b4e | 2017-09-26 18:17:06 +0530 | [diff] [blame] | 105 | dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled { |
| 106 | #address-cells = <1>; |
| 107 | #size-cells = <0>; |
| 108 | |
| 109 | qcom,panel-supply-entry@0 { |
| 110 | reg = <0>; |
Vishnuvardhan Prodduturi | d5fb080 | 2017-11-08 14:49:31 +0530 | [diff] [blame^] | 111 | qcom,supply-name = "vddio"; |
Rashi Bindra | 5f52b4e | 2017-09-26 18:17:06 +0530 | [diff] [blame] | 112 | qcom,supply-min-voltage = <1800000>; |
Vishnuvardhan Prodduturi | d5fb080 | 2017-11-08 14:49:31 +0530 | [diff] [blame^] | 113 | qcom,supply-max-voltage = <1800000>; |
Rashi Bindra | 5f52b4e | 2017-09-26 18:17:06 +0530 | [diff] [blame] | 114 | qcom,supply-enable-load = <32000>; |
| 115 | qcom,supply-disable-load = <80>; |
| 116 | }; |
| 117 | |
| 118 | qcom,panel-supply-entry@1 { |
| 119 | reg = <1>; |
| 120 | qcom,supply-name = "vdda-3p3"; |
| 121 | qcom,supply-min-voltage = <3300000>; |
| 122 | qcom,supply-max-voltage = <3300000>; |
| 123 | qcom,supply-enable-load = <13200>; |
| 124 | qcom,supply-disable-load = <80>; |
| 125 | }; |
| 126 | |
| 127 | qcom,panel-supply-entry@2 { |
| 128 | reg = <2>; |
| 129 | qcom,supply-name = "lab"; |
| 130 | qcom,supply-min-voltage = <4600000>; |
| 131 | qcom,supply-max-voltage = <6100000>; |
| 132 | qcom,supply-enable-load = <100000>; |
| 133 | qcom,supply-disable-load = <100>; |
| 134 | }; |
| 135 | |
| 136 | qcom,panel-supply-entry@3 { |
| 137 | reg = <3>; |
| 138 | qcom,supply-name = "ibb"; |
| 139 | qcom,supply-min-voltage = <4000000>; |
| 140 | qcom,supply-max-voltage = <6300000>; |
| 141 | qcom,supply-enable-load = <100000>; |
| 142 | qcom,supply-disable-load = <100>; |
| 143 | }; |
| 144 | |
| 145 | qcom,panel-supply-entry@4 { |
| 146 | reg = <4>; |
| 147 | qcom,supply-name = "oledb"; |
| 148 | qcom,supply-min-voltage = <5000000>; |
| 149 | qcom,supply-max-voltage = <8100000>; |
| 150 | qcom,supply-enable-load = <100000>; |
| 151 | qcom,supply-disable-load = <100>; |
| 152 | }; |
| 153 | }; |
| 154 | |
Raviteja Tamatam | e97849a | 2017-09-12 20:25:50 +0530 | [diff] [blame] | 155 | dsi_dual_nt35597_truly_video_display: qcom,dsi-display@0 { |
| 156 | compatible = "qcom,dsi-display"; |
| 157 | label = "dsi_dual_nt35597_truly_video_display"; |
| 158 | qcom,display-type = "primary"; |
| 159 | |
| 160 | qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; |
| 161 | qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; |
| 162 | clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| 163 | <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| 164 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 165 | |
| 166 | pinctrl-names = "panel_active", "panel_suspend"; |
| 167 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 168 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 169 | qcom,platform-reset-gpio = <&tlmm 75 0>; |
| 170 | qcom,panel-mode-gpio = <&tlmm 76 0>; |
| 171 | |
| 172 | qcom,dsi-panel = <&dsi_dual_nt35597_truly_video>; |
| 173 | vddio-supply = <&pm660_l11>; |
| 174 | lab-supply = <&lcdb_ldo_vreg>; |
| 175 | ibb-supply = <&lcdb_ncp_vreg>; |
| 176 | }; |
| 177 | |
| 178 | dsi_dual_nt35597_truly_cmd_display: qcom,dsi-display@1 { |
| 179 | compatible = "qcom,dsi-display"; |
| 180 | label = "dsi_dual_nt35597_truly_cmd_display"; |
| 181 | qcom,display-type = "primary"; |
| 182 | |
| 183 | qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; |
| 184 | qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; |
| 185 | clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| 186 | <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| 187 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 188 | |
| 189 | pinctrl-names = "panel_active", "panel_suspend"; |
| 190 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 191 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 192 | qcom,platform-te-gpio = <&tlmm 10 0>; |
| 193 | qcom,platform-reset-gpio = <&tlmm 75 0>; |
| 194 | qcom,panel-mode-gpio = <&tlmm 76 0>; |
| 195 | |
| 196 | qcom,dsi-panel = <&dsi_dual_nt35597_truly_cmd>; |
| 197 | vddio-supply = <&pm660_l11>; |
| 198 | lab-supply = <&lcdb_ldo_vreg>; |
| 199 | ibb-supply = <&lcdb_ncp_vreg>; |
| 200 | }; |
| 201 | |
| 202 | dsi_nt35597_truly_dsc_cmd_display: qcom,dsi-display@2 { |
| 203 | compatible = "qcom,dsi-display"; |
| 204 | label = "dsi_nt35597_truly_dsc_cmd_display"; |
| 205 | qcom,display-type = "primary"; |
| 206 | |
| 207 | qcom,dsi-ctrl = <&mdss_dsi1>; |
| 208 | qcom,dsi-phy = <&mdss_dsi_phy1>; |
| 209 | clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, |
| 210 | <&mdss_dsi1_pll PCLK_MUX_1_CLK>; |
| 211 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 212 | |
| 213 | pinctrl-names = "panel_active", "panel_suspend"; |
| 214 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 215 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 216 | qcom,platform-te-gpio = <&tlmm 10 0>; |
| 217 | qcom,platform-reset-gpio = <&tlmm 75 0>; |
| 218 | qcom,panel-mode-gpio = <&tlmm 76 0>; |
| 219 | |
| 220 | qcom,dsi-panel = <&dsi_nt35597_truly_dsc_cmd>; |
| 221 | vddio-supply = <&pm660_l11>; |
| 222 | lab-supply = <&lcdb_ldo_vreg>; |
| 223 | ibb-supply = <&lcdb_ncp_vreg>; |
| 224 | }; |
| 225 | |
| 226 | dsi_nt35597_truly_dsc_video_display: qcom,dsi-display@3 { |
| 227 | compatible = "qcom,dsi-display"; |
| 228 | label = "dsi_nt35597_truly_dsc_video_display"; |
| 229 | qcom,display-type = "primary"; |
| 230 | |
| 231 | qcom,dsi-ctrl = <&mdss_dsi1>; |
| 232 | qcom,dsi-phy = <&mdss_dsi_phy1>; |
| 233 | clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, |
| 234 | <&mdss_dsi1_pll PCLK_MUX_1_CLK>; |
| 235 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 236 | |
| 237 | pinctrl-names = "panel_active", "panel_suspend"; |
| 238 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 239 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 240 | qcom,platform-te-gpio = <&tlmm 10 0>; |
| 241 | qcom,platform-reset-gpio = <&tlmm 75 0>; |
| 242 | qcom,panel-mode-gpio = <&tlmm 76 0>; |
| 243 | |
| 244 | qcom,dsi-panel = <&dsi_nt35597_truly_dsc_video>; |
| 245 | vddio-supply = <&pm660_l11>; |
| 246 | lab-supply = <&lcdb_ldo_vreg>; |
| 247 | ibb-supply = <&lcdb_ncp_vreg>; |
| 248 | }; |
| 249 | |
| 250 | dsi_sim_vid_display: qcom,dsi-display@4 { |
| 251 | compatible = "qcom,dsi-display"; |
| 252 | label = "dsi_sim_vid_display"; |
| 253 | qcom,display-type = "primary"; |
| 254 | |
| 255 | qcom,dsi-ctrl = <&mdss_dsi0>; |
| 256 | qcom,dsi-phy = <&mdss_dsi_phy0>; |
| 257 | clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| 258 | <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| 259 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 260 | |
| 261 | pinctrl-names = "panel_active", "panel_suspend"; |
| 262 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 263 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 264 | |
| 265 | qcom,dsi-panel = <&dsi_sim_vid>; |
| 266 | }; |
| 267 | |
| 268 | dsi_dual_sim_vid_display: qcom,dsi-display@5 { |
| 269 | compatible = "qcom,dsi-display"; |
| 270 | label = "dsi_dual_sim_vid_display"; |
| 271 | qcom,display-type = "primary"; |
| 272 | |
| 273 | qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; |
| 274 | qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; |
| 275 | clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| 276 | <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| 277 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 278 | |
| 279 | pinctrl-names = "panel_active", "panel_suspend"; |
| 280 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 281 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 282 | |
| 283 | qcom,dsi-panel = <&dsi_dual_sim_vid>; |
| 284 | }; |
| 285 | |
| 286 | dsi_sim_cmd_display: qcom,dsi-display@6 { |
| 287 | compatible = "qcom,dsi-display"; |
| 288 | label = "dsi_sim_cmd_display"; |
| 289 | qcom,display-type = "primary"; |
| 290 | |
| 291 | qcom,dsi-ctrl = <&mdss_dsi0>; |
| 292 | qcom,dsi-phy = <&mdss_dsi_phy0>; |
| 293 | clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| 294 | <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| 295 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 296 | |
| 297 | pinctrl-names = "panel_active", "panel_suspend"; |
| 298 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 299 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 300 | |
| 301 | qcom,dsi-panel = <&dsi_sim_cmd>; |
| 302 | }; |
| 303 | |
| 304 | dsi_dual_sim_cmd_display: qcom,dsi-display@7 { |
| 305 | compatible = "qcom,dsi-display"; |
| 306 | label = "dsi_dual_sim_cmd_display"; |
| 307 | qcom,display-type = "primary"; |
| 308 | |
| 309 | qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; |
| 310 | qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; |
| 311 | clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| 312 | <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| 313 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 314 | |
| 315 | pinctrl-names = "panel_active", "panel_suspend"; |
| 316 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 317 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 318 | |
| 319 | qcom,dsi-panel = <&dsi_dual_sim_cmd>; |
| 320 | }; |
| 321 | |
| 322 | dsi_sim_dsc_375_cmd_display: qcom,dsi-display@8 { |
| 323 | compatible = "qcom,dsi-display"; |
| 324 | label = "dsi_sim_dsc_375_cmd_display"; |
| 325 | qcom,display-type = "primary"; |
| 326 | |
| 327 | qcom,dsi-ctrl = <&mdss_dsi0>; |
| 328 | qcom,dsi-phy = <&mdss_dsi_phy0>; |
| 329 | clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| 330 | <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| 331 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 332 | |
| 333 | pinctrl-names = "panel_active", "panel_suspend"; |
| 334 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 335 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 336 | |
| 337 | qcom,dsi-panel = <&dsi_sim_dsc_375_cmd>; |
| 338 | }; |
| 339 | |
| 340 | dsi_dual_sim_dsc_375_cmd_display: qcom,dsi-display@9 { |
| 341 | compatible = "qcom,dsi-display"; |
| 342 | label = "dsi_dual_sim_dsc_375_cmd_display"; |
| 343 | qcom,display-type = "primary"; |
| 344 | |
| 345 | qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; |
| 346 | qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; |
| 347 | clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| 348 | <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| 349 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 350 | |
| 351 | pinctrl-names = "panel_active", "panel_suspend"; |
| 352 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 353 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 354 | |
| 355 | qcom,dsi-panel = <&dsi_dual_sim_dsc_375_cmd>; |
| 356 | }; |
| 357 | |
Rashi Bindra | 5f52b4e | 2017-09-26 18:17:06 +0530 | [diff] [blame] | 358 | dsi_dual_nt35597_video_display: qcom,dsi-display@10 { |
| 359 | compatible = "qcom,dsi-display"; |
| 360 | label = "dsi_dual_nt35597_video_display"; |
| 361 | qcom,display-type = "primary"; |
| 362 | |
| 363 | qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; |
| 364 | qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; |
| 365 | clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| 366 | <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| 367 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 368 | |
| 369 | pinctrl-names = "panel_active", "panel_suspend"; |
| 370 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 371 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 372 | qcom,platform-reset-gpio = <&tlmm 75 0>; |
| 373 | qcom,panel-mode-gpio = <&tlmm 76 0>; |
| 374 | |
| 375 | qcom,dsi-panel = <&dsi_dual_nt35597_video>; |
| 376 | vddio-supply = <&pm660_l11>; |
| 377 | lab-supply = <&lcdb_ldo_vreg>; |
| 378 | ibb-supply = <&lcdb_ncp_vreg>; |
| 379 | }; |
| 380 | |
| 381 | dsi_dual_nt35597_cmd_display: qcom,dsi-display@11 { |
| 382 | compatible = "qcom,dsi-display"; |
| 383 | label = "dsi_dual_nt35597_cmd_display"; |
| 384 | qcom,display-type = "primary"; |
| 385 | |
| 386 | qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; |
| 387 | qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; |
| 388 | clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| 389 | <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| 390 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 391 | |
| 392 | pinctrl-names = "panel_active", "panel_suspend"; |
| 393 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 394 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 395 | qcom,platform-reset-gpio = <&tlmm 75 0>; |
| 396 | qcom,panel-mode-gpio = <&tlmm 76 0>; |
| 397 | |
| 398 | qcom,dsi-panel = <&dsi_dual_nt35597_cmd>; |
| 399 | vddio-supply = <&pm660_l11>; |
| 400 | lab-supply = <&lcdb_ldo_vreg>; |
| 401 | ibb-supply = <&lcdb_ncp_vreg>; |
| 402 | }; |
| 403 | |
| 404 | dsi_rm67195_amoled_fhd_cmd_display: qcom,dsi-display@12 { |
| 405 | compatible = "qcom,dsi-display"; |
| 406 | label = "dsi_rm67195_amoled_fhd_cmd_display"; |
| 407 | qcom,display-type = "primary"; |
| 408 | |
| 409 | qcom,dsi-ctrl = <&mdss_dsi0>; |
| 410 | qcom,dsi-phy = <&mdss_dsi_phy0>; |
| 411 | clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| 412 | <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| 413 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 414 | |
| 415 | pinctrl-names = "panel_active", "panel_suspend"; |
| 416 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 417 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 418 | qcom,platform-te-gpio = <&tlmm 10 0>; |
| 419 | qcom,platform-reset-gpio = <&tlmm 75 0>; |
| 420 | |
| 421 | qcom,dsi-panel = <&dsi_rm67195_amoled_fhd_cmd>; |
| 422 | vddio-supply = <&pm660_l11>; |
Vishnuvardhan Prodduturi | d5fb080 | 2017-11-08 14:49:31 +0530 | [diff] [blame^] | 423 | vdda-3p3-supply = <&pm660l_l6>; |
| 424 | lab-supply = <&lab_regulator>; |
| 425 | ibb-supply = <&ibb_regulator>; |
| 426 | oledb-supply = <&pm660a_oledb>; |
Rashi Bindra | 5f52b4e | 2017-09-26 18:17:06 +0530 | [diff] [blame] | 427 | }; |
| 428 | |
| 429 | dsi_nt35695b_truly_fhd_video_display: qcom,dsi-display@13 { |
| 430 | compatible = "qcom,dsi-display"; |
| 431 | label = "dsi_nt35695b_truly_fhd_video_display"; |
| 432 | qcom,display-type = "primary"; |
| 433 | |
| 434 | qcom,dsi-ctrl = <&mdss_dsi0>; |
| 435 | qcom,dsi-phy = <&mdss_dsi_phy0>; |
| 436 | clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| 437 | <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| 438 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 439 | |
| 440 | pinctrl-names = "panel_active", "panel_suspend"; |
| 441 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 442 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 443 | qcom,platform-reset-gpio = <&tlmm 75 0>; |
| 444 | |
| 445 | qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_video>; |
| 446 | vddio-supply = <&pm660_l11>; |
| 447 | lab-supply = <&lcdb_ldo_vreg>; |
| 448 | ibb-supply = <&lcdb_ncp_vreg>; |
| 449 | }; |
| 450 | |
| 451 | dsi_nt35695b_truly_fhd_cmd_display: qcom,dsi-display@14 { |
| 452 | compatible = "qcom,dsi-display"; |
| 453 | label = "dsi_nt35695b_truly_fhd_cmd_display"; |
| 454 | qcom,display-type = "primary"; |
| 455 | |
| 456 | qcom,dsi-ctrl = <&mdss_dsi0>; |
| 457 | qcom,dsi-phy = <&mdss_dsi_phy0>; |
| 458 | clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| 459 | <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| 460 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 461 | |
| 462 | pinctrl-names = "panel_active", "panel_suspend"; |
| 463 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 464 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 465 | qcom,platform-te-gpio = <&tlmm 10 0>; |
| 466 | qcom,platform-reset-gpio = <&tlmm 75 0>; |
| 467 | |
| 468 | qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_cmd>; |
| 469 | vddio-supply = <&pm660_l11>; |
| 470 | lab-supply = <&lcdb_ldo_vreg>; |
| 471 | ibb-supply = <&lcdb_ncp_vreg>; |
| 472 | }; |
| 473 | |
Raviteja Tamatam | e97849a | 2017-09-12 20:25:50 +0530 | [diff] [blame] | 474 | sde_wb: qcom,wb-display@0 { |
| 475 | compatible = "qcom,wb-display"; |
| 476 | cell-index = <0>; |
| 477 | label = "wb_display"; |
| 478 | }; |
| 479 | |
| 480 | ext_disp: qcom,msm-ext-disp { |
| 481 | compatible = "qcom,msm-ext-disp"; |
Raviteja Tamatam | e97849a | 2017-09-12 20:25:50 +0530 | [diff] [blame] | 482 | |
| 483 | ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { |
| 484 | compatible = "qcom,msm-ext-disp-audio-codec-rx"; |
| 485 | }; |
| 486 | }; |
Raviteja Tamatam | e97849a | 2017-09-12 20:25:50 +0530 | [diff] [blame] | 487 | }; |
| 488 | |
| 489 | &sde_dp { |
Padmanabhan Komanduru | f3838e4 | 2017-10-20 12:50:47 +0530 | [diff] [blame] | 490 | qcom,dp-usbpd-detection = <&pm660_pdphy>; |
| 491 | qcom,ext-disp = <&ext_disp>; |
| 492 | |
Raviteja Tamatam | e97849a | 2017-09-12 20:25:50 +0530 | [diff] [blame] | 493 | pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; |
| 494 | pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>; |
| 495 | pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>; |
| 496 | qcom,aux-en-gpio = <&tlmm 50 0>; |
| 497 | qcom,aux-sel-gpio = <&tlmm 40 0>; |
| 498 | qcom,usbplug-cc-gpio = <&tlmm 38 0>; |
| 499 | }; |
| 500 | |
| 501 | &mdss_mdp { |
Padmanabhan Komanduru | d03f38f | 2017-10-10 15:34:41 +0530 | [diff] [blame] | 502 | connectors = <&sde_rscc &sde_wb &sde_dp>; |
Raviteja Tamatam | e97849a | 2017-09-12 20:25:50 +0530 | [diff] [blame] | 503 | }; |
| 504 | |
| 505 | &dsi_dual_nt35597_truly_video { |
| 506 | qcom,mdss-dsi-t-clk-post = <0x0D>; |
| 507 | qcom,mdss-dsi-t-clk-pre = <0x2D>; |
| 508 | qcom,mdss-dsi-display-timings { |
| 509 | timing@0{ |
| 510 | qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 |
| 511 | 07 05 03 04 00]; |
| 512 | qcom,display-topology = <2 0 2>, |
| 513 | <1 0 2>; |
| 514 | qcom,default-topology-index = <0>; |
| 515 | }; |
| 516 | }; |
| 517 | }; |
| 518 | |
| 519 | &dsi_dual_nt35597_truly_cmd { |
| 520 | qcom,mdss-dsi-t-clk-post = <0x0D>; |
| 521 | qcom,mdss-dsi-t-clk-pre = <0x2D>; |
| 522 | qcom,mdss-dsi-display-timings { |
| 523 | timing@0{ |
| 524 | qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 |
| 525 | 07 05 03 04 00]; |
| 526 | qcom,display-topology = <2 0 2>, |
| 527 | <1 0 2>; |
| 528 | qcom,default-topology-index = <0>; |
| 529 | }; |
| 530 | }; |
| 531 | }; |
| 532 | |
| 533 | &dsi_nt35597_truly_dsc_cmd { |
| 534 | qcom,mdss-dsi-t-clk-post = <0x0b>; |
| 535 | qcom,mdss-dsi-t-clk-pre = <0x23>; |
| 536 | qcom,mdss-dsi-display-timings { |
| 537 | timing@0{ |
| 538 | qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05 |
| 539 | 05 03 03 04 00]; |
| 540 | qcom,display-topology = <1 1 1>, |
| 541 | <2 2 1>, /* dsc merge */ |
| 542 | <2 1 1>; /* 3d mux */ |
| 543 | qcom,default-topology-index = <1>; |
| 544 | }; |
| 545 | }; |
| 546 | }; |
| 547 | |
| 548 | &dsi_nt35597_truly_dsc_video { |
| 549 | qcom,mdss-dsi-t-clk-post = <0x0b>; |
| 550 | qcom,mdss-dsi-t-clk-pre = <0x23>; |
| 551 | qcom,mdss-dsi-display-timings { |
| 552 | timing@0{ |
| 553 | qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05 |
| 554 | 04 03 03 04 00]; |
| 555 | qcom,display-topology = <1 1 1>, |
| 556 | <2 2 1>, /* dsc merge */ |
| 557 | <2 1 1>; /* 3d mux */ |
| 558 | qcom,default-topology-index = <1>; |
| 559 | }; |
| 560 | }; |
| 561 | }; |
| 562 | |
| 563 | &dsi_sim_vid { |
| 564 | qcom,mdss-dsi-t-clk-post = <0x0d>; |
| 565 | qcom,mdss-dsi-t-clk-pre = <0x2d>; |
| 566 | qcom,mdss-dsi-display-timings { |
| 567 | timing@0{ |
| 568 | qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 |
| 569 | 07 05 03 04 00]; |
| 570 | qcom,display-topology = <1 0 1>, |
| 571 | <2 0 1>; |
| 572 | qcom,default-topology-index = <0>; |
| 573 | }; |
| 574 | }; |
| 575 | }; |
| 576 | |
| 577 | &dsi_dual_sim_vid { |
| 578 | qcom,mdss-dsi-t-clk-post = <0x0d>; |
| 579 | qcom,mdss-dsi-t-clk-pre = <0x2d>; |
| 580 | qcom,mdss-dsi-display-timings { |
| 581 | timing@0{ |
| 582 | qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 |
| 583 | 07 05 03 04 00]; |
| 584 | qcom,display-topology = <2 0 2>, |
| 585 | <1 0 2>; |
| 586 | qcom,default-topology-index = <0>; |
| 587 | }; |
| 588 | }; |
| 589 | }; |
| 590 | |
| 591 | &dsi_sim_cmd { |
| 592 | qcom,mdss-dsi-t-clk-post = <0x0d>; |
| 593 | qcom,mdss-dsi-t-clk-pre = <0x2d>; |
| 594 | qcom,mdss-dsi-display-timings { |
| 595 | timing@0{ |
| 596 | qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 |
| 597 | 07 05 03 04 00]; |
| 598 | qcom,display-topology = <1 0 1>, |
| 599 | <2 0 1>; |
| 600 | qcom,default-topology-index = <0>; |
| 601 | }; |
| 602 | }; |
| 603 | }; |
| 604 | |
| 605 | &dsi_dual_sim_cmd { |
| 606 | qcom,mdss-dsi-t-clk-post = <0x0d>; |
| 607 | qcom,mdss-dsi-t-clk-pre = <0x2d>; |
| 608 | qcom,mdss-dsi-display-timings { |
| 609 | timing@0{ |
| 610 | qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09 |
| 611 | 09 06 03 04 00]; |
| 612 | qcom,display-topology = <2 0 2>; |
| 613 | qcom,default-topology-index = <0>; |
| 614 | }; |
| 615 | timing@1{ |
| 616 | qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 |
| 617 | 07 05 03 04 00]; |
| 618 | qcom,display-topology = <2 0 2>, |
| 619 | <1 0 2>; |
| 620 | qcom,default-topology-index = <0>; |
| 621 | }; |
| 622 | timing@2{ |
| 623 | qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06 |
| 624 | 06 04 03 04 00]; |
| 625 | qcom,display-topology = <2 0 2>; |
| 626 | qcom,default-topology-index = <0>; |
| 627 | }; |
| 628 | }; |
| 629 | }; |
| 630 | |
| 631 | &dsi_sim_dsc_375_cmd { |
| 632 | qcom,mdss-dsi-t-clk-post = <0x0d>; |
| 633 | qcom,mdss-dsi-t-clk-pre = <0x2d>; |
| 634 | qcom,mdss-dsi-display-timings { |
| 635 | timing@0 { /* 1080p */ |
| 636 | qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07 |
| 637 | 07 04 03 04 00]; |
| 638 | qcom,display-topology = <1 1 1>; |
| 639 | qcom,default-topology-index = <0>; |
| 640 | }; |
| 641 | timing@1 { /* qhd */ |
| 642 | qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05 |
| 643 | 05 03 03 04 00]; |
| 644 | qcom,display-topology = <1 1 1>, |
| 645 | <2 2 1>, /* dsc merge */ |
| 646 | <2 1 1>; /* 3d mux */ |
| 647 | qcom,default-topology-index = <0>; |
| 648 | }; |
| 649 | }; |
| 650 | }; |
| 651 | |
| 652 | &dsi_dual_sim_dsc_375_cmd { |
| 653 | qcom,mdss-dsi-t-clk-post = <0x0d>; |
| 654 | qcom,mdss-dsi-t-clk-pre = <0x2d>; |
| 655 | qcom,mdss-dsi-display-timings { |
| 656 | timing@0 { /* qhd */ |
| 657 | qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 |
| 658 | 07 05 03 04 00]; |
| 659 | qcom,display-topology = <2 2 2>; |
| 660 | qcom,default-topology-index = <0>; |
| 661 | }; |
| 662 | timing@1 { /* 4k */ |
| 663 | qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06 |
| 664 | 06 04 03 04 00]; |
| 665 | qcom,display-topology = <2 2 2>; |
| 666 | qcom,default-topology-index = <0>; |
| 667 | }; |
| 668 | }; |
| 669 | }; |
Rashi Bindra | 5f52b4e | 2017-09-26 18:17:06 +0530 | [diff] [blame] | 670 | |
| 671 | &dsi_dual_nt35597_video { |
| 672 | qcom,mdss-dsi-t-clk-post = <0x0d>; |
| 673 | qcom,mdss-dsi-t-clk-pre = <0x2d>; |
| 674 | qcom,mdss-dsi-display-timings { |
| 675 | timing@0 { |
| 676 | qcom,mdss-dsi-panel-timings = [00 1c 08 07 23 22 07 07 |
| 677 | 05 03 04 00]; |
| 678 | qcom,display-topology = <2 0 2>, |
| 679 | <1 0 2>; |
| 680 | qcom,default-topology-index = <0>; |
| 681 | }; |
| 682 | }; |
| 683 | }; |
| 684 | |
| 685 | &dsi_dual_nt35597_cmd { |
| 686 | qcom,mdss-dsi-t-clk-post = <0x0d>; |
| 687 | qcom,mdss-dsi-t-clk-pre = <0x2d>; |
| 688 | qcom,mdss-dsi-display-timings { |
| 689 | timing@0 { |
| 690 | qcom,mdss-dsi-panel-timings = [00 1c 08 07 23 22 07 07 |
| 691 | 05 03 04 00]; |
| 692 | qcom,display-topology = <2 0 2>, |
| 693 | <1 0 2>; |
| 694 | qcom,default-topology-index = <0>; |
| 695 | }; |
| 696 | }; |
| 697 | }; |
| 698 | |
| 699 | &dsi_rm67195_amoled_fhd_cmd { |
| 700 | qcom,mdss-dsi-t-clk-post = <0x07>; |
| 701 | qcom,mdss-dsi-t-clk-pre = <0x1c>; |
| 702 | qcom,mdss-dsi-display-timings { |
| 703 | timing@0 { |
| 704 | qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c |
| 705 | 05 07 05 03 04 00]; |
| 706 | qcom,display-topology = <1 0 1>; |
| 707 | qcom,default-topology-index = <0>; |
| 708 | }; |
| 709 | }; |
| 710 | }; |
| 711 | |
| 712 | &dsi_nt35695b_truly_fhd_video { |
| 713 | qcom,mdss-dsi-t-clk-post = <0x07>; |
| 714 | qcom,mdss-dsi-t-clk-pre = <0x1c>; |
| 715 | qcom,mdss-dsi-display-timings { |
| 716 | timing@0 { |
| 717 | qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c |
| 718 | 05 07 05 03 04 00]; |
| 719 | qcom,display-topology = <1 0 1>; |
| 720 | qcom,default-topology-index = <0>; |
| 721 | }; |
| 722 | }; |
| 723 | }; |
| 724 | |
| 725 | &dsi_nt35695b_truly_fhd_cmd { |
| 726 | qcom,mdss-dsi-t-clk-post = <0x07>; |
| 727 | qcom,mdss-dsi-t-clk-pre = <0x1c>; |
| 728 | qcom,mdss-dsi-display-timings { |
| 729 | timing@0 { |
| 730 | qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c |
| 731 | 05 07 05 03 04 00]; |
| 732 | qcom,display-topology = <1 0 1>; |
| 733 | qcom,default-topology-index = <0>; |
| 734 | }; |
| 735 | }; |
| 736 | }; |