Michael Hennerich | 6c536e4 | 2010-05-24 14:33:14 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Driver for the Analog Devices digital potentiometers |
| 3 | * |
| 4 | * Copyright (C) 2010 Michael Hennerich, Analog Devices Inc. |
| 5 | * |
| 6 | * Licensed under the GPL-2 or later. |
| 7 | */ |
| 8 | |
| 9 | #ifndef _AD_DPOT_H_ |
| 10 | #define _AD_DPOT_H_ |
| 11 | |
| 12 | #include <linux/types.h> |
| 13 | |
| 14 | #define DPOT_CONF(features, wipers, max_pos, uid) \ |
| 15 | (((features) << 18) | (((wipers) & 0xFF) << 10) | \ |
| 16 | ((max_pos & 0xF) << 6) | (uid & 0x3F)) |
| 17 | |
Michael Hennerich | 59592d0 | 2010-05-24 14:33:16 -0700 | [diff] [blame] | 18 | #define DPOT_UID(conf) (conf & 0x3F) |
| 19 | #define DPOT_MAX_POS(conf) ((conf >> 6) & 0xF) |
| 20 | #define DPOT_WIPERS(conf) ((conf >> 10) & 0xFF) |
| 21 | #define DPOT_FEAT(conf) (conf >> 18) |
Michael Hennerich | 6c536e4 | 2010-05-24 14:33:14 -0700 | [diff] [blame] | 22 | |
Michael Hennerich | 59592d0 | 2010-05-24 14:33:16 -0700 | [diff] [blame] | 23 | #define BRDAC0 (1 << 0) |
| 24 | #define BRDAC1 (1 << 1) |
| 25 | #define BRDAC2 (1 << 2) |
| 26 | #define BRDAC3 (1 << 3) |
| 27 | #define BRDAC4 (1 << 4) |
| 28 | #define BRDAC5 (1 << 5) |
| 29 | #define MAX_RDACS 6 |
Michael Hennerich | 6c536e4 | 2010-05-24 14:33:14 -0700 | [diff] [blame] | 30 | |
| 31 | #define F_CMD_INC (1 << 0) /* Features INC/DEC ALL, 6dB */ |
| 32 | #define F_CMD_EEP (1 << 1) /* Features EEPROM */ |
Michael Hennerich | e3ae68476 | 2010-05-24 14:33:15 -0700 | [diff] [blame] | 33 | #define F_CMD_OTP (1 << 2) /* Features OTP */ |
| 34 | #define F_CMD_TOL (1 << 3) /* RDACS feature Tolerance REG */ |
| 35 | #define F_RDACS_RW (1 << 4) /* RDACS are Read/Write */ |
| 36 | #define F_RDACS_WONLY (1 << 5) /* RDACS are Write only */ |
| 37 | #define F_AD_APPDATA (1 << 6) /* RDAC Address append to data */ |
| 38 | #define F_SPI_8BIT (1 << 7) /* All SPI XFERS are 8-bit */ |
| 39 | #define F_SPI_16BIT (1 << 8) /* All SPI XFERS are 16-bit */ |
| 40 | #define F_SPI_24BIT (1 << 9) /* All SPI XFERS are 24-bit */ |
Michael Hennerich | 6c536e4 | 2010-05-24 14:33:14 -0700 | [diff] [blame] | 41 | |
| 42 | #define F_RDACS_RW_TOL (F_RDACS_RW | F_CMD_EEP | F_CMD_TOL) |
| 43 | #define F_RDACS_RW_EEP (F_RDACS_RW | F_CMD_EEP) |
| 44 | #define F_SPI (F_SPI_8BIT | F_SPI_16BIT | F_SPI_24BIT) |
| 45 | |
| 46 | enum dpot_devid { |
| 47 | AD5258_ID = DPOT_CONF(F_RDACS_RW_TOL, BRDAC0, 6, 0), /* I2C */ |
| 48 | AD5259_ID = DPOT_CONF(F_RDACS_RW_TOL, BRDAC0, 8, 1), |
| 49 | AD5251_ID = DPOT_CONF(F_RDACS_RW_TOL | F_CMD_INC, |
steven miao | 4b068de | 2010-10-26 14:22:37 -0700 | [diff] [blame] | 50 | BRDAC1 | BRDAC3, 6, 2), |
Michael Hennerich | 6c536e4 | 2010-05-24 14:33:14 -0700 | [diff] [blame] | 51 | AD5252_ID = DPOT_CONF(F_RDACS_RW_TOL | F_CMD_INC, |
steven miao | 4b068de | 2010-10-26 14:22:37 -0700 | [diff] [blame] | 52 | BRDAC1 | BRDAC3, 8, 3), |
Michael Hennerich | 6c536e4 | 2010-05-24 14:33:14 -0700 | [diff] [blame] | 53 | AD5253_ID = DPOT_CONF(F_RDACS_RW_TOL | F_CMD_INC, |
| 54 | BRDAC0 | BRDAC1 | BRDAC2 | BRDAC3, 6, 4), |
| 55 | AD5254_ID = DPOT_CONF(F_RDACS_RW_TOL | F_CMD_INC, |
| 56 | BRDAC0 | BRDAC1 | BRDAC2 | BRDAC3, 8, 5), |
| 57 | AD5255_ID = DPOT_CONF(F_RDACS_RW_TOL | F_CMD_INC, |
| 58 | BRDAC0 | BRDAC1 | BRDAC2, 9, 6), |
| 59 | AD5160_ID = DPOT_CONF(F_RDACS_WONLY | F_AD_APPDATA | F_SPI_8BIT, |
| 60 | BRDAC0, 8, 7), /* SPI */ |
| 61 | AD5161_ID = DPOT_CONF(F_RDACS_WONLY | F_AD_APPDATA | F_SPI_8BIT, |
| 62 | BRDAC0, 8, 8), |
| 63 | AD5162_ID = DPOT_CONF(F_RDACS_WONLY | F_AD_APPDATA | F_SPI_16BIT, |
| 64 | BRDAC0 | BRDAC1, 8, 9), |
| 65 | AD5165_ID = DPOT_CONF(F_RDACS_WONLY | F_AD_APPDATA | F_SPI_8BIT, |
| 66 | BRDAC0, 8, 10), |
| 67 | AD5200_ID = DPOT_CONF(F_RDACS_WONLY | F_AD_APPDATA | F_SPI_8BIT, |
| 68 | BRDAC0, 8, 11), |
| 69 | AD5201_ID = DPOT_CONF(F_RDACS_WONLY | F_AD_APPDATA | F_SPI_8BIT, |
| 70 | BRDAC0, 5, 12), |
| 71 | AD5203_ID = DPOT_CONF(F_RDACS_WONLY | F_AD_APPDATA | F_SPI_8BIT, |
| 72 | BRDAC0 | BRDAC1 | BRDAC2 | BRDAC3, 6, 13), |
| 73 | AD5204_ID = DPOT_CONF(F_RDACS_WONLY | F_AD_APPDATA | F_SPI_16BIT, |
| 74 | BRDAC0 | BRDAC1 | BRDAC2 | BRDAC3, 8, 14), |
| 75 | AD5206_ID = DPOT_CONF(F_RDACS_WONLY | F_AD_APPDATA | F_SPI_16BIT, |
| 76 | BRDAC0 | BRDAC1 | BRDAC2 | BRDAC3 | BRDAC4 | BRDAC5, |
| 77 | 8, 15), |
| 78 | AD5207_ID = DPOT_CONF(F_RDACS_WONLY | F_AD_APPDATA | F_SPI_16BIT, |
| 79 | BRDAC0 | BRDAC1, 8, 16), |
| 80 | AD5231_ID = DPOT_CONF(F_RDACS_RW_EEP | F_CMD_INC | F_SPI_24BIT, |
| 81 | BRDAC0, 10, 17), |
| 82 | AD5232_ID = DPOT_CONF(F_RDACS_RW_EEP | F_CMD_INC | F_SPI_16BIT, |
| 83 | BRDAC0 | BRDAC1, 8, 18), |
| 84 | AD5233_ID = DPOT_CONF(F_RDACS_RW_EEP | F_CMD_INC | F_SPI_16BIT, |
| 85 | BRDAC0 | BRDAC1 | BRDAC2 | BRDAC3, 6, 19), |
| 86 | AD5235_ID = DPOT_CONF(F_RDACS_RW_EEP | F_CMD_INC | F_SPI_24BIT, |
| 87 | BRDAC0 | BRDAC1, 10, 20), |
| 88 | AD5260_ID = DPOT_CONF(F_RDACS_WONLY | F_AD_APPDATA | F_SPI_8BIT, |
| 89 | BRDAC0, 8, 21), |
| 90 | AD5262_ID = DPOT_CONF(F_RDACS_WONLY | F_AD_APPDATA | F_SPI_16BIT, |
| 91 | BRDAC0 | BRDAC1, 8, 22), |
| 92 | AD5263_ID = DPOT_CONF(F_RDACS_WONLY | F_AD_APPDATA | F_SPI_16BIT, |
| 93 | BRDAC0 | BRDAC1 | BRDAC2 | BRDAC3, 8, 23), |
| 94 | AD5290_ID = DPOT_CONF(F_RDACS_WONLY | F_AD_APPDATA | F_SPI_8BIT, |
| 95 | BRDAC0, 8, 24), |
Michael Hennerich | a4bd394 | 2010-10-26 14:22:36 -0700 | [diff] [blame] | 96 | AD5291_ID = DPOT_CONF(F_RDACS_RW | F_SPI_16BIT | F_CMD_OTP, |
| 97 | BRDAC0, 8, 25), |
| 98 | AD5292_ID = DPOT_CONF(F_RDACS_RW | F_SPI_16BIT | F_CMD_OTP, |
| 99 | BRDAC0, 10, 26), |
Michael Hennerich | 6c536e4 | 2010-05-24 14:33:14 -0700 | [diff] [blame] | 100 | AD5293_ID = DPOT_CONF(F_RDACS_RW | F_SPI_16BIT, BRDAC0, 10, 27), |
| 101 | AD7376_ID = DPOT_CONF(F_RDACS_WONLY | F_AD_APPDATA | F_SPI_8BIT, |
| 102 | BRDAC0, 7, 28), |
| 103 | AD8400_ID = DPOT_CONF(F_RDACS_WONLY | F_AD_APPDATA | F_SPI_8BIT, |
| 104 | BRDAC0, 8, 29), |
| 105 | AD8402_ID = DPOT_CONF(F_RDACS_WONLY | F_AD_APPDATA | F_SPI_16BIT, |
| 106 | BRDAC0 | BRDAC1, 8, 30), |
| 107 | AD8403_ID = DPOT_CONF(F_RDACS_WONLY | F_AD_APPDATA | F_SPI_16BIT, |
| 108 | BRDAC0 | BRDAC1 | BRDAC2, 8, 31), |
| 109 | ADN2850_ID = DPOT_CONF(F_RDACS_RW_EEP | F_CMD_INC | F_SPI_24BIT, |
| 110 | BRDAC0 | BRDAC1, 10, 32), |
Michael Hennerich | e3ae68476 | 2010-05-24 14:33:15 -0700 | [diff] [blame] | 111 | AD5241_ID = DPOT_CONF(F_RDACS_RW, BRDAC0, 8, 33), |
| 112 | AD5242_ID = DPOT_CONF(F_RDACS_RW, BRDAC0 | BRDAC1, 8, 34), |
| 113 | AD5243_ID = DPOT_CONF(F_RDACS_RW, BRDAC0 | BRDAC1, 8, 35), |
| 114 | AD5245_ID = DPOT_CONF(F_RDACS_RW, BRDAC0, 8, 36), |
| 115 | AD5246_ID = DPOT_CONF(F_RDACS_RW, BRDAC0, 7, 37), |
| 116 | AD5247_ID = DPOT_CONF(F_RDACS_RW, BRDAC0, 7, 38), |
| 117 | AD5248_ID = DPOT_CONF(F_RDACS_RW, BRDAC0 | BRDAC1, 8, 39), |
Michael Hennerich | c74cba6 | 2010-05-24 14:33:15 -0700 | [diff] [blame] | 118 | AD5280_ID = DPOT_CONF(F_RDACS_RW, BRDAC0, 8, 40), |
| 119 | AD5282_ID = DPOT_CONF(F_RDACS_RW, BRDAC0 | BRDAC1, 8, 41), |
| 120 | ADN2860_ID = DPOT_CONF(F_RDACS_RW_TOL | F_CMD_INC, |
| 121 | BRDAC0 | BRDAC1 | BRDAC2, 9, 42), |
Michael Hennerich | 59592d0 | 2010-05-24 14:33:16 -0700 | [diff] [blame] | 122 | AD5273_ID = DPOT_CONF(F_RDACS_RW | F_CMD_OTP, BRDAC0, 6, 43), |
| 123 | AD5171_ID = DPOT_CONF(F_RDACS_RW | F_CMD_OTP, BRDAC0, 6, 44), |
| 124 | AD5170_ID = DPOT_CONF(F_RDACS_RW | F_CMD_OTP, BRDAC0, 8, 45), |
| 125 | AD5172_ID = DPOT_CONF(F_RDACS_RW | F_CMD_OTP, BRDAC0 | BRDAC1, 8, 46), |
| 126 | AD5173_ID = DPOT_CONF(F_RDACS_RW | F_CMD_OTP, BRDAC0 | BRDAC1, 8, 47), |
Michael Hennerich | a4bd394 | 2010-10-26 14:22:36 -0700 | [diff] [blame] | 127 | AD5270_ID = DPOT_CONF(F_RDACS_RW | F_CMD_OTP | F_SPI_16BIT, |
| 128 | BRDAC0, 10, 48), |
| 129 | AD5271_ID = DPOT_CONF(F_RDACS_RW | F_CMD_OTP | F_SPI_16BIT, |
| 130 | BRDAC0, 8, 49), |
| 131 | AD5272_ID = DPOT_CONF(F_RDACS_RW | F_CMD_OTP, BRDAC0, 10, 50), |
| 132 | AD5274_ID = DPOT_CONF(F_RDACS_RW | F_CMD_OTP, BRDAC0, 8, 51), |
Michael Hennerich | 6c536e4 | 2010-05-24 14:33:14 -0700 | [diff] [blame] | 133 | }; |
| 134 | |
| 135 | #define DPOT_RDAC0 0 |
| 136 | #define DPOT_RDAC1 1 |
| 137 | #define DPOT_RDAC2 2 |
| 138 | #define DPOT_RDAC3 3 |
| 139 | #define DPOT_RDAC4 4 |
| 140 | #define DPOT_RDAC5 5 |
| 141 | |
| 142 | #define DPOT_RDAC_MASK 0x1F |
| 143 | |
| 144 | #define DPOT_REG_TOL 0x18 |
| 145 | #define DPOT_TOL_RDAC0 (DPOT_REG_TOL | DPOT_RDAC0) |
| 146 | #define DPOT_TOL_RDAC1 (DPOT_REG_TOL | DPOT_RDAC1) |
| 147 | #define DPOT_TOL_RDAC2 (DPOT_REG_TOL | DPOT_RDAC2) |
| 148 | #define DPOT_TOL_RDAC3 (DPOT_REG_TOL | DPOT_RDAC3) |
| 149 | #define DPOT_TOL_RDAC4 (DPOT_REG_TOL | DPOT_RDAC4) |
| 150 | #define DPOT_TOL_RDAC5 (DPOT_REG_TOL | DPOT_RDAC5) |
| 151 | |
| 152 | /* RDAC-to-EEPROM Interface Commands */ |
Michael Hennerich | 59592d0 | 2010-05-24 14:33:16 -0700 | [diff] [blame] | 153 | #define DPOT_ADDR_RDAC (0x0 << 5) |
| 154 | #define DPOT_ADDR_EEPROM (0x1 << 5) |
| 155 | #define DPOT_ADDR_OTP (0x1 << 6) |
| 156 | #define DPOT_ADDR_CMD (0x1 << 7) |
| 157 | #define DPOT_ADDR_OTP_EN (0x1 << 9) |
Michael Hennerich | 6c536e4 | 2010-05-24 14:33:14 -0700 | [diff] [blame] | 158 | |
| 159 | #define DPOT_DEC_ALL_6DB (DPOT_ADDR_CMD | (0x4 << 3)) |
| 160 | #define DPOT_INC_ALL_6DB (DPOT_ADDR_CMD | (0x9 << 3)) |
| 161 | #define DPOT_DEC_ALL (DPOT_ADDR_CMD | (0x6 << 3)) |
| 162 | #define DPOT_INC_ALL (DPOT_ADDR_CMD | (0xB << 3)) |
| 163 | |
| 164 | #define DPOT_SPI_RDAC 0xB0 |
| 165 | #define DPOT_SPI_EEPROM 0x30 |
| 166 | #define DPOT_SPI_READ_RDAC 0xA0 |
| 167 | #define DPOT_SPI_READ_EEPROM 0x90 |
| 168 | #define DPOT_SPI_DEC_ALL_6DB 0x50 |
| 169 | #define DPOT_SPI_INC_ALL_6DB 0xD0 |
| 170 | #define DPOT_SPI_DEC_ALL 0x70 |
| 171 | #define DPOT_SPI_INC_ALL 0xF0 |
| 172 | |
| 173 | /* AD5291/2/3 use special commands */ |
| 174 | #define DPOT_AD5291_RDAC 0x01 |
| 175 | #define DPOT_AD5291_READ_RDAC 0x02 |
Michael Hennerich | a4bd394 | 2010-10-26 14:22:36 -0700 | [diff] [blame] | 176 | #define DPOT_AD5291_STORE_XTPM 0x03 |
| 177 | #define DPOT_AD5291_CTRLREG 0x06 |
| 178 | #define DPOT_AD5291_UNLOCK_CMD 0x03 |
Michael Hennerich | 6c536e4 | 2010-05-24 14:33:14 -0700 | [diff] [blame] | 179 | |
Michael Hennerich | a4bd394 | 2010-10-26 14:22:36 -0700 | [diff] [blame] | 180 | /* AD5270/1/2/4 use special commands */ |
| 181 | #define DPOT_AD5270_1_2_4_RDAC 0x01 |
| 182 | #define DPOT_AD5270_1_2_4_READ_RDAC 0x02 |
| 183 | #define DPOT_AD5270_1_2_4_STORE_XTPM 0x03 |
| 184 | #define DPOT_AD5270_1_2_4_CTRLREG 0x07 |
| 185 | #define DPOT_AD5270_1_2_4_UNLOCK_CMD 0x03 |
Michael Hennerich | e3ae68476 | 2010-05-24 14:33:15 -0700 | [diff] [blame] | 186 | |
Michael Hennerich | 5f400cf | 2010-10-26 14:22:35 -0700 | [diff] [blame] | 187 | #define DPOT_AD5282_RDAC_AB 0x80 |
Michael Hennerich | a4bd394 | 2010-10-26 14:22:36 -0700 | [diff] [blame] | 188 | |
Michael Hennerich | 59592d0 | 2010-05-24 14:33:16 -0700 | [diff] [blame] | 189 | #define DPOT_AD5273_FUSE 0x80 |
Michael Hennerich | 5f400cf | 2010-10-26 14:22:35 -0700 | [diff] [blame] | 190 | #define DPOT_AD5170_2_3_FUSE 0x20 |
| 191 | #define DPOT_AD5170_2_3_OW 0x08 |
| 192 | #define DPOT_AD5172_3_A0 0x08 |
| 193 | #define DPOT_AD5170_2FUSE 0x80 |
Michael Hennerich | 59592d0 | 2010-05-24 14:33:16 -0700 | [diff] [blame] | 194 | |
Michael Hennerich | 6c536e4 | 2010-05-24 14:33:14 -0700 | [diff] [blame] | 195 | struct dpot_data; |
| 196 | |
| 197 | struct ad_dpot_bus_ops { |
| 198 | int (*read_d8) (void *client); |
| 199 | int (*read_r8d8) (void *client, u8 reg); |
| 200 | int (*read_r8d16) (void *client, u8 reg); |
| 201 | int (*write_d8) (void *client, u8 val); |
| 202 | int (*write_r8d8) (void *client, u8 reg, u8 val); |
| 203 | int (*write_r8d16) (void *client, u8 reg, u16 val); |
| 204 | }; |
| 205 | |
| 206 | struct ad_dpot_bus_data { |
| 207 | void *client; |
| 208 | const struct ad_dpot_bus_ops *bops; |
| 209 | }; |
| 210 | |
| 211 | struct ad_dpot_id { |
| 212 | char *name; |
| 213 | unsigned long devid; |
| 214 | }; |
| 215 | |
| 216 | int ad_dpot_probe(struct device *dev, struct ad_dpot_bus_data *bdata, const struct ad_dpot_id *id); |
| 217 | int ad_dpot_remove(struct device *dev); |
| 218 | |
| 219 | #endif |